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1/*
2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#include <drm/drm_of.h>
19
20#include "msm_drv.h"
21#include "msm_debugfs.h"
22#include "msm_fence.h"
23#include "msm_gpu.h"
24#include "msm_kms.h"
25
26
27/*
28 * MSM driver version:
29 * - 1.0.0 - initial interface
30 * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers
31 * - 1.2.0 - adds explicit fence support for submit ioctl
32 */
33#define MSM_VERSION_MAJOR 1
34#define MSM_VERSION_MINOR 2
35#define MSM_VERSION_PATCHLEVEL 0
36
37static void msm_fb_output_poll_changed(struct drm_device *dev)
38{
39 struct msm_drm_private *priv = dev->dev_private;
40 if (priv->fbdev)
41 drm_fb_helper_hotplug_event(priv->fbdev);
42}
43
44static const struct drm_mode_config_funcs mode_config_funcs = {
45 .fb_create = msm_framebuffer_create,
46 .output_poll_changed = msm_fb_output_poll_changed,
47 .atomic_check = msm_atomic_check,
48 .atomic_commit = msm_atomic_commit,
49 .atomic_state_alloc = msm_atomic_state_alloc,
50 .atomic_state_clear = msm_atomic_state_clear,
51 .atomic_state_free = msm_atomic_state_free,
52};
53
54int msm_register_address_space(struct drm_device *dev,
55 struct msm_gem_address_space *aspace)
56{
57 struct msm_drm_private *priv = dev->dev_private;
58 int idx = priv->num_aspaces++;
59
60 if (WARN_ON(idx >= ARRAY_SIZE(priv->aspace)))
61 return -EINVAL;
62
63 priv->aspace[idx] = aspace;
64
65 return idx;
66}
67
68#ifdef CONFIG_DRM_MSM_REGISTER_LOGGING
69static bool reglog = false;
70MODULE_PARM_DESC(reglog, "Enable register read/write logging");
71module_param(reglog, bool, 0600);
72#else
73#define reglog 0
74#endif
75
76#ifdef CONFIG_DRM_FBDEV_EMULATION
77static bool fbdev = true;
78MODULE_PARM_DESC(fbdev, "Enable fbdev compat layer");
79module_param(fbdev, bool, 0600);
80#endif
81
82static char *vram = "16m";
83MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU)");
84module_param(vram, charp, 0);
85
86bool dumpstate = false;
87MODULE_PARM_DESC(dumpstate, "Dump KMS state on errors");
88module_param(dumpstate, bool, 0600);
89
90/*
91 * Util/helpers:
92 */
93
94void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
95 const char *dbgname)
96{
97 struct resource *res;
98 unsigned long size;
99 void __iomem *ptr;
100
101 if (name)
102 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
103 else
104 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
105
106 if (!res) {
107 dev_err(&pdev->dev, "failed to get memory resource: %s\n", name);
108 return ERR_PTR(-EINVAL);
109 }
110
111 size = resource_size(res);
112
113 ptr = devm_ioremap_nocache(&pdev->dev, res->start, size);
114 if (!ptr) {
115 dev_err(&pdev->dev, "failed to ioremap: %s\n", name);
116 return ERR_PTR(-ENOMEM);
117 }
118
119 if (reglog)
120 printk(KERN_DEBUG "IO:region %s %p %08lx\n", dbgname, ptr, size);
121
122 return ptr;
123}
124
125void msm_writel(u32 data, void __iomem *addr)
126{
127 if (reglog)
128 printk(KERN_DEBUG "IO:W %p %08x\n", addr, data);
129 writel(data, addr);
130}
131
132u32 msm_readl(const void __iomem *addr)
133{
134 u32 val = readl(addr);
135 if (reglog)
136 printk(KERN_ERR "IO:R %p %08x\n", addr, val);
137 return val;
138}
139
140struct vblank_event {
141 struct list_head node;
142 int crtc_id;
143 bool enable;
144};
145
146static void vblank_ctrl_worker(struct work_struct *work)
147{
148 struct msm_vblank_ctrl *vbl_ctrl = container_of(work,
149 struct msm_vblank_ctrl, work);
150 struct msm_drm_private *priv = container_of(vbl_ctrl,
151 struct msm_drm_private, vblank_ctrl);
152 struct msm_kms *kms = priv->kms;
153 struct vblank_event *vbl_ev, *tmp;
154 unsigned long flags;
155
156 spin_lock_irqsave(&vbl_ctrl->lock, flags);
157 list_for_each_entry_safe(vbl_ev, tmp, &vbl_ctrl->event_list, node) {
158 list_del(&vbl_ev->node);
159 spin_unlock_irqrestore(&vbl_ctrl->lock, flags);
160
161 if (vbl_ev->enable)
162 kms->funcs->enable_vblank(kms,
163 priv->crtcs[vbl_ev->crtc_id]);
164 else
165 kms->funcs->disable_vblank(kms,
166 priv->crtcs[vbl_ev->crtc_id]);
167
168 kfree(vbl_ev);
169
170 spin_lock_irqsave(&vbl_ctrl->lock, flags);
171 }
172
173 spin_unlock_irqrestore(&vbl_ctrl->lock, flags);
174}
175
176static int vblank_ctrl_queue_work(struct msm_drm_private *priv,
177 int crtc_id, bool enable)
178{
179 struct msm_vblank_ctrl *vbl_ctrl = &priv->vblank_ctrl;
180 struct vblank_event *vbl_ev;
181 unsigned long flags;
182
183 vbl_ev = kzalloc(sizeof(*vbl_ev), GFP_ATOMIC);
184 if (!vbl_ev)
185 return -ENOMEM;
186
187 vbl_ev->crtc_id = crtc_id;
188 vbl_ev->enable = enable;
189
190 spin_lock_irqsave(&vbl_ctrl->lock, flags);
191 list_add_tail(&vbl_ev->node, &vbl_ctrl->event_list);
192 spin_unlock_irqrestore(&vbl_ctrl->lock, flags);
193
194 queue_work(priv->wq, &vbl_ctrl->work);
195
196 return 0;
197}
198
199static int msm_drm_uninit(struct device *dev)
200{
201 struct platform_device *pdev = to_platform_device(dev);
202 struct drm_device *ddev = platform_get_drvdata(pdev);
203 struct msm_drm_private *priv = ddev->dev_private;
204 struct msm_kms *kms = priv->kms;
205 struct msm_gpu *gpu = priv->gpu;
206 struct msm_vblank_ctrl *vbl_ctrl = &priv->vblank_ctrl;
207 struct vblank_event *vbl_ev, *tmp;
208
209 /* We must cancel and cleanup any pending vblank enable/disable
210 * work before drm_irq_uninstall() to avoid work re-enabling an
211 * irq after uninstall has disabled it.
212 */
213 cancel_work_sync(&vbl_ctrl->work);
214 list_for_each_entry_safe(vbl_ev, tmp, &vbl_ctrl->event_list, node) {
215 list_del(&vbl_ev->node);
216 kfree(vbl_ev);
217 }
218
219 msm_gem_shrinker_cleanup(ddev);
220
221 drm_kms_helper_poll_fini(ddev);
222
223 drm_dev_unregister(ddev);
224
225#ifdef CONFIG_DRM_FBDEV_EMULATION
226 if (fbdev && priv->fbdev)
227 msm_fbdev_free(ddev);
228#endif
229 drm_mode_config_cleanup(ddev);
230
231 pm_runtime_get_sync(dev);
232 drm_irq_uninstall(ddev);
233 pm_runtime_put_sync(dev);
234
235 flush_workqueue(priv->wq);
236 destroy_workqueue(priv->wq);
237
238 flush_workqueue(priv->atomic_wq);
239 destroy_workqueue(priv->atomic_wq);
240
241 if (kms && kms->funcs)
242 kms->funcs->destroy(kms);
243
244 if (gpu) {
245 mutex_lock(&ddev->struct_mutex);
246 gpu->funcs->pm_suspend(gpu);
247 mutex_unlock(&ddev->struct_mutex);
248 gpu->funcs->destroy(gpu);
249 }
250
251 if (priv->vram.paddr) {
252 unsigned long attrs = DMA_ATTR_NO_KERNEL_MAPPING;
253 drm_mm_takedown(&priv->vram.mm);
254 dma_free_attrs(dev, priv->vram.size, NULL,
255 priv->vram.paddr, attrs);
256 }
257
258 component_unbind_all(dev, ddev);
259
260 msm_mdss_destroy(ddev);
261
262 ddev->dev_private = NULL;
263 drm_dev_unref(ddev);
264
265 kfree(priv);
266
267 return 0;
268}
269
270static int get_mdp_ver(struct platform_device *pdev)
271{
272 struct device *dev = &pdev->dev;
273
274 return (int) (unsigned long) of_device_get_match_data(dev);
275}
276
277#include <linux/of_address.h>
278
279static int msm_init_vram(struct drm_device *dev)
280{
281 struct msm_drm_private *priv = dev->dev_private;
282 struct device_node *node;
283 unsigned long size = 0;
284 int ret = 0;
285
286 /* In the device-tree world, we could have a 'memory-region'
287 * phandle, which gives us a link to our "vram". Allocating
288 * is all nicely abstracted behind the dma api, but we need
289 * to know the entire size to allocate it all in one go. There
290 * are two cases:
291 * 1) device with no IOMMU, in which case we need exclusive
292 * access to a VRAM carveout big enough for all gpu
293 * buffers
294 * 2) device with IOMMU, but where the bootloader puts up
295 * a splash screen. In this case, the VRAM carveout
296 * need only be large enough for fbdev fb. But we need
297 * exclusive access to the buffer to avoid the kernel
298 * using those pages for other purposes (which appears
299 * as corruption on screen before we have a chance to
300 * load and do initial modeset)
301 */
302
303 node = of_parse_phandle(dev->dev->of_node, "memory-region", 0);
304 if (node) {
305 struct resource r;
306 ret = of_address_to_resource(node, 0, &r);
307 of_node_put(node);
308 if (ret)
309 return ret;
310 size = r.end - r.start;
311 DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start);
312
313 /* if we have no IOMMU, then we need to use carveout allocator.
314 * Grab the entire CMA chunk carved out in early startup in
315 * mach-msm:
316 */
317 } else if (!iommu_present(&platform_bus_type)) {
318 DRM_INFO("using %s VRAM carveout\n", vram);
319 size = memparse(vram, NULL);
320 }
321
322 if (size) {
323 unsigned long attrs = 0;
324 void *p;
325
326 priv->vram.size = size;
327
328 drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1);
329
330 attrs |= DMA_ATTR_NO_KERNEL_MAPPING;
331 attrs |= DMA_ATTR_WRITE_COMBINE;
332
333 /* note that for no-kernel-mapping, the vaddr returned
334 * is bogus, but non-null if allocation succeeded:
335 */
336 p = dma_alloc_attrs(dev->dev, size,
337 &priv->vram.paddr, GFP_KERNEL, attrs);
338 if (!p) {
339 dev_err(dev->dev, "failed to allocate VRAM\n");
340 priv->vram.paddr = 0;
341 return -ENOMEM;
342 }
343
344 dev_info(dev->dev, "VRAM: %08x->%08x\n",
345 (uint32_t)priv->vram.paddr,
346 (uint32_t)(priv->vram.paddr + size));
347 }
348
349 return ret;
350}
351
352static int msm_drm_init(struct device *dev, struct drm_driver *drv)
353{
354 struct platform_device *pdev = to_platform_device(dev);
355 struct drm_device *ddev;
356 struct msm_drm_private *priv;
357 struct msm_kms *kms;
358 int ret;
359
360 ddev = drm_dev_alloc(drv, dev);
361 if (IS_ERR(ddev)) {
362 dev_err(dev, "failed to allocate drm_device\n");
363 return PTR_ERR(ddev);
364 }
365
366 platform_set_drvdata(pdev, ddev);
367 ddev->platformdev = pdev;
368
369 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
370 if (!priv) {
371 drm_dev_unref(ddev);
372 return -ENOMEM;
373 }
374
375 ddev->dev_private = priv;
376 priv->dev = ddev;
377
378 ret = msm_mdss_init(ddev);
379 if (ret) {
380 kfree(priv);
381 drm_dev_unref(ddev);
382 return ret;
383 }
384
385 priv->wq = alloc_ordered_workqueue("msm", 0);
386 priv->atomic_wq = alloc_ordered_workqueue("msm:atomic", 0);
387 init_waitqueue_head(&priv->pending_crtcs_event);
388
389 INIT_LIST_HEAD(&priv->inactive_list);
390 INIT_LIST_HEAD(&priv->vblank_ctrl.event_list);
391 INIT_WORK(&priv->vblank_ctrl.work, vblank_ctrl_worker);
392 spin_lock_init(&priv->vblank_ctrl.lock);
393
394 drm_mode_config_init(ddev);
395
396 /* Bind all our sub-components: */
397 ret = component_bind_all(dev, ddev);
398 if (ret) {
399 msm_mdss_destroy(ddev);
400 kfree(priv);
401 drm_dev_unref(ddev);
402 return ret;
403 }
404
405 ret = msm_init_vram(ddev);
406 if (ret)
407 goto fail;
408
409 msm_gem_shrinker_init(ddev);
410
411 switch (get_mdp_ver(pdev)) {
412 case 4:
413 kms = mdp4_kms_init(ddev);
414 priv->kms = kms;
415 break;
416 case 5:
417 kms = mdp5_kms_init(ddev);
418 break;
419 default:
420 kms = ERR_PTR(-ENODEV);
421 break;
422 }
423
424 if (IS_ERR(kms)) {
425 /*
426 * NOTE: once we have GPU support, having no kms should not
427 * be considered fatal.. ideally we would still support gpu
428 * and (for example) use dmabuf/prime to share buffers with
429 * imx drm driver on iMX5
430 */
431 dev_err(dev, "failed to load kms\n");
432 ret = PTR_ERR(kms);
433 goto fail;
434 }
435
436 if (kms) {
437 ret = kms->funcs->hw_init(kms);
438 if (ret) {
439 dev_err(dev, "kms hw init failed: %d\n", ret);
440 goto fail;
441 }
442 }
443
444 ddev->mode_config.funcs = &mode_config_funcs;
445
446 ret = drm_vblank_init(ddev, priv->num_crtcs);
447 if (ret < 0) {
448 dev_err(dev, "failed to initialize vblank\n");
449 goto fail;
450 }
451
452 if (kms) {
453 pm_runtime_get_sync(dev);
454 ret = drm_irq_install(ddev, kms->irq);
455 pm_runtime_put_sync(dev);
456 if (ret < 0) {
457 dev_err(dev, "failed to install IRQ handler\n");
458 goto fail;
459 }
460 }
461
462 ret = drm_dev_register(ddev, 0);
463 if (ret)
464 goto fail;
465
466 drm_mode_config_reset(ddev);
467
468#ifdef CONFIG_DRM_FBDEV_EMULATION
469 if (fbdev)
470 priv->fbdev = msm_fbdev_init(ddev);
471#endif
472
473 ret = msm_debugfs_late_init(ddev);
474 if (ret)
475 goto fail;
476
477 drm_kms_helper_poll_init(ddev);
478
479 return 0;
480
481fail:
482 msm_drm_uninit(dev);
483 return ret;
484}
485
486/*
487 * DRM operations:
488 */
489
490static void load_gpu(struct drm_device *dev)
491{
492 static DEFINE_MUTEX(init_lock);
493 struct msm_drm_private *priv = dev->dev_private;
494
495 mutex_lock(&init_lock);
496
497 if (!priv->gpu)
498 priv->gpu = adreno_load_gpu(dev);
499
500 mutex_unlock(&init_lock);
501}
502
503static int msm_open(struct drm_device *dev, struct drm_file *file)
504{
505 struct msm_file_private *ctx;
506
507 /* For now, load gpu on open.. to avoid the requirement of having
508 * firmware in the initrd.
509 */
510 load_gpu(dev);
511
512 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
513 if (!ctx)
514 return -ENOMEM;
515
516 file->driver_priv = ctx;
517
518 return 0;
519}
520
521static void msm_preclose(struct drm_device *dev, struct drm_file *file)
522{
523 struct msm_drm_private *priv = dev->dev_private;
524 struct msm_file_private *ctx = file->driver_priv;
525
526 mutex_lock(&dev->struct_mutex);
527 if (ctx == priv->lastctx)
528 priv->lastctx = NULL;
529 mutex_unlock(&dev->struct_mutex);
530
531 kfree(ctx);
532}
533
534static void msm_lastclose(struct drm_device *dev)
535{
536 struct msm_drm_private *priv = dev->dev_private;
537 if (priv->fbdev)
538 drm_fb_helper_restore_fbdev_mode_unlocked(priv->fbdev);
539}
540
541static irqreturn_t msm_irq(int irq, void *arg)
542{
543 struct drm_device *dev = arg;
544 struct msm_drm_private *priv = dev->dev_private;
545 struct msm_kms *kms = priv->kms;
546 BUG_ON(!kms);
547 return kms->funcs->irq(kms);
548}
549
550static void msm_irq_preinstall(struct drm_device *dev)
551{
552 struct msm_drm_private *priv = dev->dev_private;
553 struct msm_kms *kms = priv->kms;
554 BUG_ON(!kms);
555 kms->funcs->irq_preinstall(kms);
556}
557
558static int msm_irq_postinstall(struct drm_device *dev)
559{
560 struct msm_drm_private *priv = dev->dev_private;
561 struct msm_kms *kms = priv->kms;
562 BUG_ON(!kms);
563 return kms->funcs->irq_postinstall(kms);
564}
565
566static void msm_irq_uninstall(struct drm_device *dev)
567{
568 struct msm_drm_private *priv = dev->dev_private;
569 struct msm_kms *kms = priv->kms;
570 BUG_ON(!kms);
571 kms->funcs->irq_uninstall(kms);
572}
573
574static int msm_enable_vblank(struct drm_device *dev, unsigned int pipe)
575{
576 struct msm_drm_private *priv = dev->dev_private;
577 struct msm_kms *kms = priv->kms;
578 if (!kms)
579 return -ENXIO;
580 DBG("dev=%p, crtc=%u", dev, pipe);
581 return vblank_ctrl_queue_work(priv, pipe, true);
582}
583
584static void msm_disable_vblank(struct drm_device *dev, unsigned int pipe)
585{
586 struct msm_drm_private *priv = dev->dev_private;
587 struct msm_kms *kms = priv->kms;
588 if (!kms)
589 return;
590 DBG("dev=%p, crtc=%u", dev, pipe);
591 vblank_ctrl_queue_work(priv, pipe, false);
592}
593
594/*
595 * DRM ioctls:
596 */
597
598static int msm_ioctl_get_param(struct drm_device *dev, void *data,
599 struct drm_file *file)
600{
601 struct msm_drm_private *priv = dev->dev_private;
602 struct drm_msm_param *args = data;
603 struct msm_gpu *gpu;
604
605 /* for now, we just have 3d pipe.. eventually this would need to
606 * be more clever to dispatch to appropriate gpu module:
607 */
608 if (args->pipe != MSM_PIPE_3D0)
609 return -EINVAL;
610
611 gpu = priv->gpu;
612
613 if (!gpu)
614 return -ENXIO;
615
616 return gpu->funcs->get_param(gpu, args->param, &args->value);
617}
618
619static int msm_ioctl_gem_new(struct drm_device *dev, void *data,
620 struct drm_file *file)
621{
622 struct drm_msm_gem_new *args = data;
623
624 if (args->flags & ~MSM_BO_FLAGS) {
625 DRM_ERROR("invalid flags: %08x\n", args->flags);
626 return -EINVAL;
627 }
628
629 return msm_gem_new_handle(dev, file, args->size,
630 args->flags, &args->handle);
631}
632
633static inline ktime_t to_ktime(struct drm_msm_timespec timeout)
634{
635 return ktime_set(timeout.tv_sec, timeout.tv_nsec);
636}
637
638static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
639 struct drm_file *file)
640{
641 struct drm_msm_gem_cpu_prep *args = data;
642 struct drm_gem_object *obj;
643 ktime_t timeout = to_ktime(args->timeout);
644 int ret;
645
646 if (args->op & ~MSM_PREP_FLAGS) {
647 DRM_ERROR("invalid op: %08x\n", args->op);
648 return -EINVAL;
649 }
650
651 obj = drm_gem_object_lookup(file, args->handle);
652 if (!obj)
653 return -ENOENT;
654
655 ret = msm_gem_cpu_prep(obj, args->op, &timeout);
656
657 drm_gem_object_unreference_unlocked(obj);
658
659 return ret;
660}
661
662static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
663 struct drm_file *file)
664{
665 struct drm_msm_gem_cpu_fini *args = data;
666 struct drm_gem_object *obj;
667 int ret;
668
669 obj = drm_gem_object_lookup(file, args->handle);
670 if (!obj)
671 return -ENOENT;
672
673 ret = msm_gem_cpu_fini(obj);
674
675 drm_gem_object_unreference_unlocked(obj);
676
677 return ret;
678}
679
680static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
681 struct drm_file *file)
682{
683 struct drm_msm_gem_info *args = data;
684 struct drm_gem_object *obj;
685 int ret = 0;
686
687 if (args->pad)
688 return -EINVAL;
689
690 obj = drm_gem_object_lookup(file, args->handle);
691 if (!obj)
692 return -ENOENT;
693
694 args->offset = msm_gem_mmap_offset(obj);
695
696 drm_gem_object_unreference_unlocked(obj);
697
698 return ret;
699}
700
701static int msm_ioctl_wait_fence(struct drm_device *dev, void *data,
702 struct drm_file *file)
703{
704 struct msm_drm_private *priv = dev->dev_private;
705 struct drm_msm_wait_fence *args = data;
706 ktime_t timeout = to_ktime(args->timeout);
707
708 if (args->pad) {
709 DRM_ERROR("invalid pad: %08x\n", args->pad);
710 return -EINVAL;
711 }
712
713 if (!priv->gpu)
714 return 0;
715
716 return msm_wait_fence(priv->gpu->fctx, args->fence, &timeout, true);
717}
718
719static int msm_ioctl_gem_madvise(struct drm_device *dev, void *data,
720 struct drm_file *file)
721{
722 struct drm_msm_gem_madvise *args = data;
723 struct drm_gem_object *obj;
724 int ret;
725
726 switch (args->madv) {
727 case MSM_MADV_DONTNEED:
728 case MSM_MADV_WILLNEED:
729 break;
730 default:
731 return -EINVAL;
732 }
733
734 ret = mutex_lock_interruptible(&dev->struct_mutex);
735 if (ret)
736 return ret;
737
738 obj = drm_gem_object_lookup(file, args->handle);
739 if (!obj) {
740 ret = -ENOENT;
741 goto unlock;
742 }
743
744 ret = msm_gem_madvise(obj, args->madv);
745 if (ret >= 0) {
746 args->retained = ret;
747 ret = 0;
748 }
749
750 drm_gem_object_unreference(obj);
751
752unlock:
753 mutex_unlock(&dev->struct_mutex);
754 return ret;
755}
756
757static const struct drm_ioctl_desc msm_ioctls[] = {
758 DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_AUTH|DRM_RENDER_ALLOW),
759 DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_AUTH|DRM_RENDER_ALLOW),
760 DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_AUTH|DRM_RENDER_ALLOW),
761 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_AUTH|DRM_RENDER_ALLOW),
762 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_AUTH|DRM_RENDER_ALLOW),
763 DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_AUTH|DRM_RENDER_ALLOW),
764 DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_AUTH|DRM_RENDER_ALLOW),
765 DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE, msm_ioctl_gem_madvise, DRM_AUTH|DRM_RENDER_ALLOW),
766};
767
768static const struct vm_operations_struct vm_ops = {
769 .fault = msm_gem_fault,
770 .open = drm_gem_vm_open,
771 .close = drm_gem_vm_close,
772};
773
774static const struct file_operations fops = {
775 .owner = THIS_MODULE,
776 .open = drm_open,
777 .release = drm_release,
778 .unlocked_ioctl = drm_ioctl,
779 .compat_ioctl = drm_compat_ioctl,
780 .poll = drm_poll,
781 .read = drm_read,
782 .llseek = no_llseek,
783 .mmap = msm_gem_mmap,
784};
785
786static struct drm_driver msm_driver = {
787 .driver_features = DRIVER_HAVE_IRQ |
788 DRIVER_GEM |
789 DRIVER_PRIME |
790 DRIVER_RENDER |
791 DRIVER_ATOMIC |
792 DRIVER_MODESET,
793 .open = msm_open,
794 .preclose = msm_preclose,
795 .lastclose = msm_lastclose,
796 .irq_handler = msm_irq,
797 .irq_preinstall = msm_irq_preinstall,
798 .irq_postinstall = msm_irq_postinstall,
799 .irq_uninstall = msm_irq_uninstall,
800 .get_vblank_counter = drm_vblank_no_hw_counter,
801 .enable_vblank = msm_enable_vblank,
802 .disable_vblank = msm_disable_vblank,
803 .gem_free_object = msm_gem_free_object,
804 .gem_vm_ops = &vm_ops,
805 .dumb_create = msm_gem_dumb_create,
806 .dumb_map_offset = msm_gem_dumb_map_offset,
807 .dumb_destroy = drm_gem_dumb_destroy,
808 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
809 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
810 .gem_prime_export = drm_gem_prime_export,
811 .gem_prime_import = drm_gem_prime_import,
812 .gem_prime_pin = msm_gem_prime_pin,
813 .gem_prime_unpin = msm_gem_prime_unpin,
814 .gem_prime_get_sg_table = msm_gem_prime_get_sg_table,
815 .gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
816 .gem_prime_vmap = msm_gem_prime_vmap,
817 .gem_prime_vunmap = msm_gem_prime_vunmap,
818 .gem_prime_mmap = msm_gem_prime_mmap,
819#ifdef CONFIG_DEBUG_FS
820 .debugfs_init = msm_debugfs_init,
821 .debugfs_cleanup = msm_debugfs_cleanup,
822#endif
823 .ioctls = msm_ioctls,
824 .num_ioctls = DRM_MSM_NUM_IOCTLS,
825 .fops = &fops,
826 .name = "msm",
827 .desc = "MSM Snapdragon DRM",
828 .date = "20130625",
829 .major = MSM_VERSION_MAJOR,
830 .minor = MSM_VERSION_MINOR,
831 .patchlevel = MSM_VERSION_PATCHLEVEL,
832};
833
834#ifdef CONFIG_PM_SLEEP
835static int msm_pm_suspend(struct device *dev)
836{
837 struct drm_device *ddev = dev_get_drvdata(dev);
838
839 drm_kms_helper_poll_disable(ddev);
840
841 return 0;
842}
843
844static int msm_pm_resume(struct device *dev)
845{
846 struct drm_device *ddev = dev_get_drvdata(dev);
847
848 drm_kms_helper_poll_enable(ddev);
849
850 return 0;
851}
852#endif
853
854static const struct dev_pm_ops msm_pm_ops = {
855 SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume)
856};
857
858/*
859 * Componentized driver support:
860 */
861
862/*
863 * NOTE: duplication of the same code as exynos or imx (or probably any other).
864 * so probably some room for some helpers
865 */
866static int compare_of(struct device *dev, void *data)
867{
868 return dev->of_node == data;
869}
870
871/*
872 * Identify what components need to be added by parsing what remote-endpoints
873 * our MDP output ports are connected to. In the case of LVDS on MDP4, there
874 * is no external component that we need to add since LVDS is within MDP4
875 * itself.
876 */
877static int add_components_mdp(struct device *mdp_dev,
878 struct component_match **matchptr)
879{
880 struct device_node *np = mdp_dev->of_node;
881 struct device_node *ep_node;
882 struct device *master_dev;
883
884 /*
885 * on MDP4 based platforms, the MDP platform device is the component
886 * master that adds other display interface components to itself.
887 *
888 * on MDP5 based platforms, the MDSS platform device is the component
889 * master that adds MDP5 and other display interface components to
890 * itself.
891 */
892 if (of_device_is_compatible(np, "qcom,mdp4"))
893 master_dev = mdp_dev;
894 else
895 master_dev = mdp_dev->parent;
896
897 for_each_endpoint_of_node(np, ep_node) {
898 struct device_node *intf;
899 struct of_endpoint ep;
900 int ret;
901
902 ret = of_graph_parse_endpoint(ep_node, &ep);
903 if (ret) {
904 dev_err(mdp_dev, "unable to parse port endpoint\n");
905 of_node_put(ep_node);
906 return ret;
907 }
908
909 /*
910 * The LCDC/LVDS port on MDP4 is a speacial case where the
911 * remote-endpoint isn't a component that we need to add
912 */
913 if (of_device_is_compatible(np, "qcom,mdp4") &&
914 ep.port == 0)
915 continue;
916
917 /*
918 * It's okay if some of the ports don't have a remote endpoint
919 * specified. It just means that the port isn't connected to
920 * any external interface.
921 */
922 intf = of_graph_get_remote_port_parent(ep_node);
923 if (!intf)
924 continue;
925
926 drm_of_component_match_add(master_dev, matchptr, compare_of,
927 intf);
928 of_node_put(intf);
929 }
930
931 return 0;
932}
933
934static int compare_name_mdp(struct device *dev, void *data)
935{
936 return (strstr(dev_name(dev), "mdp") != NULL);
937}
938
939static int add_display_components(struct device *dev,
940 struct component_match **matchptr)
941{
942 struct device *mdp_dev;
943 int ret;
944
945 /*
946 * MDP5 based devices don't have a flat hierarchy. There is a top level
947 * parent: MDSS, and children: MDP5, DSI, HDMI, eDP etc. Populate the
948 * children devices, find the MDP5 node, and then add the interfaces
949 * to our components list.
950 */
951 if (of_device_is_compatible(dev->of_node, "qcom,mdss")) {
952 ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
953 if (ret) {
954 dev_err(dev, "failed to populate children devices\n");
955 return ret;
956 }
957
958 mdp_dev = device_find_child(dev, NULL, compare_name_mdp);
959 if (!mdp_dev) {
960 dev_err(dev, "failed to find MDSS MDP node\n");
961 of_platform_depopulate(dev);
962 return -ENODEV;
963 }
964
965 put_device(mdp_dev);
966
967 /* add the MDP component itself */
968 drm_of_component_match_add(dev, matchptr, compare_of,
969 mdp_dev->of_node);
970 } else {
971 /* MDP4 */
972 mdp_dev = dev;
973 }
974
975 ret = add_components_mdp(mdp_dev, matchptr);
976 if (ret)
977 of_platform_depopulate(dev);
978
979 return ret;
980}
981
982/*
983 * We don't know what's the best binding to link the gpu with the drm device.
984 * Fow now, we just hunt for all the possible gpus that we support, and add them
985 * as components.
986 */
987static const struct of_device_id msm_gpu_match[] = {
988 { .compatible = "qcom,adreno-3xx" },
989 { .compatible = "qcom,kgsl-3d0" },
990 { },
991};
992
993static int add_gpu_components(struct device *dev,
994 struct component_match **matchptr)
995{
996 struct device_node *np;
997
998 np = of_find_matching_node(NULL, msm_gpu_match);
999 if (!np)
1000 return 0;
1001
1002 drm_of_component_match_add(dev, matchptr, compare_of, np);
1003
1004 of_node_put(np);
1005
1006 return 0;
1007}
1008
1009static int msm_drm_bind(struct device *dev)
1010{
1011 return msm_drm_init(dev, &msm_driver);
1012}
1013
1014static void msm_drm_unbind(struct device *dev)
1015{
1016 msm_drm_uninit(dev);
1017}
1018
1019static const struct component_master_ops msm_drm_ops = {
1020 .bind = msm_drm_bind,
1021 .unbind = msm_drm_unbind,
1022};
1023
1024/*
1025 * Platform driver:
1026 */
1027
1028static int msm_pdev_probe(struct platform_device *pdev)
1029{
1030 struct component_match *match = NULL;
1031 int ret;
1032
1033 ret = add_display_components(&pdev->dev, &match);
1034 if (ret)
1035 return ret;
1036
1037 ret = add_gpu_components(&pdev->dev, &match);
1038 if (ret)
1039 return ret;
1040
1041 /* on all devices that I am aware of, iommu's which can map
1042 * any address the cpu can see are used:
1043 */
1044 ret = dma_set_mask_and_coherent(&pdev->dev, ~0);
1045 if (ret)
1046 return ret;
1047
1048 return component_master_add_with_match(&pdev->dev, &msm_drm_ops, match);
1049}
1050
1051static int msm_pdev_remove(struct platform_device *pdev)
1052{
1053 component_master_del(&pdev->dev, &msm_drm_ops);
1054 of_platform_depopulate(&pdev->dev);
1055
1056 return 0;
1057}
1058
1059static const struct of_device_id dt_match[] = {
1060 { .compatible = "qcom,mdp4", .data = (void *)4 }, /* MDP4 */
1061 { .compatible = "qcom,mdss", .data = (void *)5 }, /* MDP5 MDSS */
1062 {}
1063};
1064MODULE_DEVICE_TABLE(of, dt_match);
1065
1066static struct platform_driver msm_platform_driver = {
1067 .probe = msm_pdev_probe,
1068 .remove = msm_pdev_remove,
1069 .driver = {
1070 .name = "msm",
1071 .of_match_table = dt_match,
1072 .pm = &msm_pm_ops,
1073 },
1074};
1075
1076static int __init msm_drm_register(void)
1077{
1078 DBG("init");
1079 msm_mdp_register();
1080 msm_dsi_register();
1081 msm_edp_register();
1082 msm_hdmi_register();
1083 adreno_register();
1084 return platform_driver_register(&msm_platform_driver);
1085}
1086
1087static void __exit msm_drm_unregister(void)
1088{
1089 DBG("fini");
1090 platform_driver_unregister(&msm_platform_driver);
1091 msm_hdmi_unregister();
1092 adreno_unregister();
1093 msm_edp_unregister();
1094 msm_dsi_unregister();
1095 msm_mdp_unregister();
1096}
1097
1098module_init(msm_drm_register);
1099module_exit(msm_drm_unregister);
1100
1101MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1102MODULE_DESCRIPTION("MSM DRM Driver");
1103MODULE_LICENSE("GPL");