Loading...
Note: File does not exist in v3.1.
1/* Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
2 *
3 * derived from imx-hdmi.c(renamed to bridge/dw_hdmi.c now)
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9#include <linux/module.h>
10#include <linux/platform_device.h>
11#include <linux/component.h>
12#include <linux/mfd/syscon.h>
13#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
14#include <drm/bridge/dw_hdmi.h>
15#include <video/imx-ipu-v3.h>
16#include <linux/regmap.h>
17#include <drm/drm_of.h>
18#include <drm/drmP.h>
19#include <drm/drm_crtc_helper.h>
20#include <drm/drm_edid.h>
21#include <drm/drm_encoder_slave.h>
22
23#include "imx-drm.h"
24
25struct imx_hdmi {
26 struct device *dev;
27 struct drm_encoder encoder;
28 struct regmap *regmap;
29};
30
31static inline struct imx_hdmi *enc_to_imx_hdmi(struct drm_encoder *e)
32{
33 return container_of(e, struct imx_hdmi, encoder);
34}
35
36static const struct dw_hdmi_mpll_config imx_mpll_cfg[] = {
37 {
38 45250000, {
39 { 0x01e0, 0x0000 },
40 { 0x21e1, 0x0000 },
41 { 0x41e2, 0x0000 }
42 },
43 }, {
44 92500000, {
45 { 0x0140, 0x0005 },
46 { 0x2141, 0x0005 },
47 { 0x4142, 0x0005 },
48 },
49 }, {
50 148500000, {
51 { 0x00a0, 0x000a },
52 { 0x20a1, 0x000a },
53 { 0x40a2, 0x000a },
54 },
55 }, {
56 216000000, {
57 { 0x00a0, 0x000a },
58 { 0x2001, 0x000f },
59 { 0x4002, 0x000f },
60 },
61 }, {
62 ~0UL, {
63 { 0x0000, 0x0000 },
64 { 0x0000, 0x0000 },
65 { 0x0000, 0x0000 },
66 },
67 }
68};
69
70static const struct dw_hdmi_curr_ctrl imx_cur_ctr[] = {
71 /* pixelclk bpp8 bpp10 bpp12 */
72 {
73 54000000, { 0x091c, 0x091c, 0x06dc },
74 }, {
75 58400000, { 0x091c, 0x06dc, 0x06dc },
76 }, {
77 72000000, { 0x06dc, 0x06dc, 0x091c },
78 }, {
79 74250000, { 0x06dc, 0x0b5c, 0x091c },
80 }, {
81 118800000, { 0x091c, 0x091c, 0x06dc },
82 }, {
83 216000000, { 0x06dc, 0x0b5c, 0x091c },
84 }, {
85 ~0UL, { 0x0000, 0x0000, 0x0000 },
86 },
87};
88
89/*
90 * Resistance term 133Ohm Cfg
91 * PREEMP config 0.00
92 * TX/CK level 10
93 */
94static const struct dw_hdmi_phy_config imx_phy_config[] = {
95 /*pixelclk symbol term vlev */
96 { 216000000, 0x800d, 0x0005, 0x01ad},
97 { ~0UL, 0x0000, 0x0000, 0x0000}
98};
99
100static int dw_hdmi_imx_parse_dt(struct imx_hdmi *hdmi)
101{
102 struct device_node *np = hdmi->dev->of_node;
103
104 hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "gpr");
105 if (IS_ERR(hdmi->regmap)) {
106 dev_err(hdmi->dev, "Unable to get gpr\n");
107 return PTR_ERR(hdmi->regmap);
108 }
109
110 return 0;
111}
112
113static void dw_hdmi_imx_encoder_disable(struct drm_encoder *encoder)
114{
115}
116
117static void dw_hdmi_imx_encoder_enable(struct drm_encoder *encoder)
118{
119 struct imx_hdmi *hdmi = enc_to_imx_hdmi(encoder);
120 int mux = drm_of_encoder_active_port_id(hdmi->dev->of_node, encoder);
121
122 regmap_update_bits(hdmi->regmap, IOMUXC_GPR3,
123 IMX6Q_GPR3_HDMI_MUX_CTL_MASK,
124 mux << IMX6Q_GPR3_HDMI_MUX_CTL_SHIFT);
125}
126
127static int dw_hdmi_imx_atomic_check(struct drm_encoder *encoder,
128 struct drm_crtc_state *crtc_state,
129 struct drm_connector_state *conn_state)
130{
131 struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);
132
133 imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
134 imx_crtc_state->di_hsync_pin = 2;
135 imx_crtc_state->di_vsync_pin = 3;
136
137 return 0;
138}
139
140static const struct drm_encoder_helper_funcs dw_hdmi_imx_encoder_helper_funcs = {
141 .enable = dw_hdmi_imx_encoder_enable,
142 .disable = dw_hdmi_imx_encoder_disable,
143 .atomic_check = dw_hdmi_imx_atomic_check,
144};
145
146static const struct drm_encoder_funcs dw_hdmi_imx_encoder_funcs = {
147 .destroy = drm_encoder_cleanup,
148};
149
150static enum drm_mode_status imx6q_hdmi_mode_valid(struct drm_connector *con,
151 struct drm_display_mode *mode)
152{
153 if (mode->clock < 13500)
154 return MODE_CLOCK_LOW;
155 /* FIXME: Hardware is capable of 266MHz, but setup data is missing. */
156 if (mode->clock > 216000)
157 return MODE_CLOCK_HIGH;
158
159 return MODE_OK;
160}
161
162static enum drm_mode_status imx6dl_hdmi_mode_valid(struct drm_connector *con,
163 struct drm_display_mode *mode)
164{
165 if (mode->clock < 13500)
166 return MODE_CLOCK_LOW;
167 /* FIXME: Hardware is capable of 270MHz, but setup data is missing. */
168 if (mode->clock > 216000)
169 return MODE_CLOCK_HIGH;
170
171 return MODE_OK;
172}
173
174static struct dw_hdmi_plat_data imx6q_hdmi_drv_data = {
175 .mpll_cfg = imx_mpll_cfg,
176 .cur_ctr = imx_cur_ctr,
177 .phy_config = imx_phy_config,
178 .dev_type = IMX6Q_HDMI,
179 .mode_valid = imx6q_hdmi_mode_valid,
180};
181
182static struct dw_hdmi_plat_data imx6dl_hdmi_drv_data = {
183 .mpll_cfg = imx_mpll_cfg,
184 .cur_ctr = imx_cur_ctr,
185 .phy_config = imx_phy_config,
186 .dev_type = IMX6DL_HDMI,
187 .mode_valid = imx6dl_hdmi_mode_valid,
188};
189
190static const struct of_device_id dw_hdmi_imx_dt_ids[] = {
191 { .compatible = "fsl,imx6q-hdmi",
192 .data = &imx6q_hdmi_drv_data
193 }, {
194 .compatible = "fsl,imx6dl-hdmi",
195 .data = &imx6dl_hdmi_drv_data
196 },
197 {},
198};
199MODULE_DEVICE_TABLE(of, dw_hdmi_imx_dt_ids);
200
201static int dw_hdmi_imx_bind(struct device *dev, struct device *master,
202 void *data)
203{
204 struct platform_device *pdev = to_platform_device(dev);
205 const struct dw_hdmi_plat_data *plat_data;
206 const struct of_device_id *match;
207 struct drm_device *drm = data;
208 struct drm_encoder *encoder;
209 struct imx_hdmi *hdmi;
210 struct resource *iores;
211 int irq;
212 int ret;
213
214 if (!pdev->dev.of_node)
215 return -ENODEV;
216
217 hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
218 if (!hdmi)
219 return -ENOMEM;
220
221 match = of_match_node(dw_hdmi_imx_dt_ids, pdev->dev.of_node);
222 plat_data = match->data;
223 hdmi->dev = &pdev->dev;
224 encoder = &hdmi->encoder;
225
226 irq = platform_get_irq(pdev, 0);
227 if (irq < 0)
228 return irq;
229
230 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
231 if (!iores)
232 return -ENXIO;
233
234 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
235 /*
236 * If we failed to find the CRTC(s) which this encoder is
237 * supposed to be connected to, it's because the CRTC has
238 * not been registered yet. Defer probing, and hope that
239 * the required CRTC is added later.
240 */
241 if (encoder->possible_crtcs == 0)
242 return -EPROBE_DEFER;
243
244 ret = dw_hdmi_imx_parse_dt(hdmi);
245 if (ret < 0)
246 return ret;
247
248 drm_encoder_helper_add(encoder, &dw_hdmi_imx_encoder_helper_funcs);
249 drm_encoder_init(drm, encoder, &dw_hdmi_imx_encoder_funcs,
250 DRM_MODE_ENCODER_TMDS, NULL);
251
252 ret = dw_hdmi_bind(dev, master, data, encoder, iores, irq, plat_data);
253
254 /*
255 * If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(),
256 * which would have called the encoder cleanup. Do it manually.
257 */
258 if (ret)
259 drm_encoder_cleanup(encoder);
260
261 return ret;
262}
263
264static void dw_hdmi_imx_unbind(struct device *dev, struct device *master,
265 void *data)
266{
267 return dw_hdmi_unbind(dev, master, data);
268}
269
270static const struct component_ops dw_hdmi_imx_ops = {
271 .bind = dw_hdmi_imx_bind,
272 .unbind = dw_hdmi_imx_unbind,
273};
274
275static int dw_hdmi_imx_probe(struct platform_device *pdev)
276{
277 return component_add(&pdev->dev, &dw_hdmi_imx_ops);
278}
279
280static int dw_hdmi_imx_remove(struct platform_device *pdev)
281{
282 component_del(&pdev->dev, &dw_hdmi_imx_ops);
283
284 return 0;
285}
286
287static struct platform_driver dw_hdmi_imx_platform_driver = {
288 .probe = dw_hdmi_imx_probe,
289 .remove = dw_hdmi_imx_remove,
290 .driver = {
291 .name = "dwhdmi-imx",
292 .of_match_table = dw_hdmi_imx_dt_ids,
293 },
294};
295
296module_platform_driver(dw_hdmi_imx_platform_driver);
297
298MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
299MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
300MODULE_DESCRIPTION("IMX6 Specific DW-HDMI Driver Extension");
301MODULE_LICENSE("GPL");
302MODULE_ALIAS("platform:dwhdmi-imx");