1/*
  2 * Copyright © 2014 Intel Corporation
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice (including the next
 12 * paragraph) shall be included in all copies or substantial portions of the
 13 * Software.
 14 *
 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 21 * IN THE SOFTWARE.
 22 *
 23 */
 24#include <linux/firmware.h>
 25#include "i915_drv.h"
 26#include "i915_reg.h"
 27
 28/**
 29 * DOC: csr support for dmc
 30 *
 31 * Display Context Save and Restore (CSR) firmware support added from gen9
 32 * onwards to drive newly added DMC (Display microcontroller) in display
 33 * engine to save and restore the state of display engine when it enter into
 34 * low-power state and comes back to normal.
 35 */
 36
 37#define I915_CSR_KBL "i915/kbl_dmc_ver1_01.bin"
 38MODULE_FIRMWARE(I915_CSR_KBL);
 39#define KBL_CSR_VERSION_REQUIRED	CSR_VERSION(1, 1)
 40
 41#define I915_CSR_SKL "i915/skl_dmc_ver1_26.bin"
 42MODULE_FIRMWARE(I915_CSR_SKL);
 43#define SKL_CSR_VERSION_REQUIRED	CSR_VERSION(1, 26)
 44
 45#define I915_CSR_BXT "i915/bxt_dmc_ver1_07.bin"
 46MODULE_FIRMWARE(I915_CSR_BXT);
 47#define BXT_CSR_VERSION_REQUIRED	CSR_VERSION(1, 7)
 48
 49#define FIRMWARE_URL  "https://01.org/linuxgraphics/intel-linux-graphics-firmwares"
 50
 51
 52
 53
 54#define CSR_MAX_FW_SIZE			0x2FFF
 55#define CSR_DEFAULT_FW_OFFSET		0xFFFFFFFF
 56
 57struct intel_css_header {
 58	/* 0x09 for DMC */
 59	uint32_t module_type;
 60
 61	/* Includes the DMC specific header in dwords */
 62	uint32_t header_len;
 63
 64	/* always value would be 0x10000 */
 65	uint32_t header_ver;
 66
 67	/* Not used */
 68	uint32_t module_id;
 69
 70	/* Not used */
 71	uint32_t module_vendor;
 72
 73	/* in YYYYMMDD format */
 74	uint32_t date;
 75
 76	/* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
 77	uint32_t size;
 78
 79	/* Not used */
 80	uint32_t key_size;
 81
 82	/* Not used */
 83	uint32_t modulus_size;
 84
 85	/* Not used */
 86	uint32_t exponent_size;
 87
 88	/* Not used */
 89	uint32_t reserved1[12];
 90
 91	/* Major Minor */
 92	uint32_t version;
 93
 94	/* Not used */
 95	uint32_t reserved2[8];
 96
 97	/* Not used */
 98	uint32_t kernel_header_info;
 99} __packed;
100
101struct intel_fw_info {
102	uint16_t reserved1;
103
104	/* Stepping (A, B, C, ..., *). * is a wildcard */
105	char stepping;
106
107	/* Sub-stepping (0, 1, ..., *). * is a wildcard */
108	char substepping;
109
110	uint32_t offset;
111	uint32_t reserved2;
112} __packed;
113
114struct intel_package_header {
115	/* DMC container header length in dwords */
116	unsigned char header_len;
117
118	/* always value would be 0x01 */
119	unsigned char header_ver;
120
121	unsigned char reserved[10];
122
123	/* Number of valid entries in the FWInfo array below */
124	uint32_t num_entries;
125
126	struct intel_fw_info fw_info[20];
127} __packed;
128
129struct intel_dmc_header {
130	/* always value would be 0x40403E3E */
131	uint32_t signature;
132
133	/* DMC binary header length */
134	unsigned char header_len;
135
136	/* 0x01 */
137	unsigned char header_ver;
138
139	/* Reserved */
140	uint16_t dmcc_ver;
141
142	/* Major, Minor */
143	uint32_t	project;
144
145	/* Firmware program size (excluding header) in dwords */
146	uint32_t	fw_size;
147
148	/* Major Minor version */
149	uint32_t fw_version;
150
151	/* Number of valid MMIO cycles present. */
152	uint32_t mmio_count;
153
154	/* MMIO address */
155	uint32_t mmioaddr[8];
156
157	/* MMIO data */
158	uint32_t mmiodata[8];
159
160	/* FW filename  */
161	unsigned char dfile[32];
162
163	uint32_t reserved1[2];
164} __packed;
165
166struct stepping_info {
167	char stepping;
168	char substepping;
169};
170
171static const struct stepping_info skl_stepping_info[] = {
172	{'A', '0'}, {'B', '0'}, {'C', '0'},
173	{'D', '0'}, {'E', '0'}, {'F', '0'},
174	{'G', '0'}, {'H', '0'}, {'I', '0'},
175	{'J', '0'}, {'K', '0'}
176};
177
178static const struct stepping_info bxt_stepping_info[] = {
179	{'A', '0'}, {'A', '1'}, {'A', '2'},
180	{'B', '0'}, {'B', '1'}, {'B', '2'}
181};
182
183static const struct stepping_info no_stepping_info = { '*', '*' };
184
185static const struct stepping_info *
186intel_get_stepping_info(struct drm_i915_private *dev_priv)
187{
188	const struct stepping_info *si;
189	unsigned int size;
190
191	if (IS_SKYLAKE(dev_priv)) {
192		size = ARRAY_SIZE(skl_stepping_info);
193		si = skl_stepping_info;
194	} else if (IS_BROXTON(dev_priv)) {
195		size = ARRAY_SIZE(bxt_stepping_info);
196		si = bxt_stepping_info;
197	} else {
198		size = 0;
199	}
200
201	if (INTEL_REVID(dev_priv) < size)
202		return si + INTEL_REVID(dev_priv);
203
204	return &no_stepping_info;
205}
206
207static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
208{
209	uint32_t val, mask;
210
211	mask = DC_STATE_DEBUG_MASK_MEMORY_UP;
212
213	if (IS_BROXTON(dev_priv))
214		mask |= DC_STATE_DEBUG_MASK_CORES;
215
216	/* The below bit doesn't need to be cleared ever afterwards */
217	val = I915_READ(DC_STATE_DEBUG);
218	if ((val & mask) != mask) {
219		val |= mask;
220		I915_WRITE(DC_STATE_DEBUG, val);
221		POSTING_READ(DC_STATE_DEBUG);
222	}
223}
224
225/**
226 * intel_csr_load_program() - write the firmware from memory to register.
227 * @dev_priv: i915 drm device.
228 *
229 * CSR firmware is read from a .bin file and kept in internal memory one time.
230 * Everytime display comes back from low power state this function is called to
231 * copy the firmware from internal memory to registers.
232 */
233void intel_csr_load_program(struct drm_i915_private *dev_priv)
234{
235	u32 *payload = dev_priv->csr.dmc_payload;
236	uint32_t i, fw_size;
237
238	if (!IS_GEN9(dev_priv)) {
239		DRM_ERROR("No CSR support available for this platform\n");
240		return;
241	}
242
243	if (!dev_priv->csr.dmc_payload) {
244		DRM_ERROR("Tried to program CSR with empty payload\n");
245		return;
246	}
247
248	fw_size = dev_priv->csr.dmc_fw_size;
249	for (i = 0; i < fw_size; i++)
250		I915_WRITE(CSR_PROGRAM(i), payload[i]);
251
252	for (i = 0; i < dev_priv->csr.mmio_count; i++) {
253		I915_WRITE(dev_priv->csr.mmioaddr[i],
254			   dev_priv->csr.mmiodata[i]);
255	}
256
257	dev_priv->csr.dc_state = 0;
258
259	gen9_set_dc_state_debugmask(dev_priv);
260}
261
262static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv,
263			      const struct firmware *fw)
264{
265	struct intel_css_header *css_header;
266	struct intel_package_header *package_header;
267	struct intel_dmc_header *dmc_header;
268	struct intel_csr *csr = &dev_priv->csr;
269	const struct stepping_info *si = intel_get_stepping_info(dev_priv);
270	uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes;
271	uint32_t i;
272	uint32_t *dmc_payload;
273	uint32_t required_version;
274
275	if (!fw)
276		return NULL;
277
278	/* Extract CSS Header information*/
279	css_header = (struct intel_css_header *)fw->data;
280	if (sizeof(struct intel_css_header) !=
281	    (css_header->header_len * 4)) {
282		DRM_ERROR("Firmware has wrong CSS header length %u bytes\n",
283			  (css_header->header_len * 4));
284		return NULL;
285	}
286
287	csr->version = css_header->version;
288
289	if (IS_KABYLAKE(dev_priv)) {
290		required_version = KBL_CSR_VERSION_REQUIRED;
291	} else if (IS_SKYLAKE(dev_priv)) {
292		required_version = SKL_CSR_VERSION_REQUIRED;
293	} else if (IS_BROXTON(dev_priv)) {
294		required_version = BXT_CSR_VERSION_REQUIRED;
295	} else {
296		MISSING_CASE(INTEL_REVID(dev_priv));
297		required_version = 0;
298	}
299
300	if (csr->version != required_version) {
301		DRM_INFO("Refusing to load DMC firmware v%u.%u,"
302			 " please use v%u.%u [" FIRMWARE_URL "].\n",
303			 CSR_VERSION_MAJOR(csr->version),
304			 CSR_VERSION_MINOR(csr->version),
305			 CSR_VERSION_MAJOR(required_version),
306			 CSR_VERSION_MINOR(required_version));
307		return NULL;
308	}
309
310	readcount += sizeof(struct intel_css_header);
311
312	/* Extract Package Header information*/
313	package_header = (struct intel_package_header *)
314		&fw->data[readcount];
315	if (sizeof(struct intel_package_header) !=
316	    (package_header->header_len * 4)) {
317		DRM_ERROR("Firmware has wrong package header length %u bytes\n",
318			  (package_header->header_len * 4));
319		return NULL;
320	}
321	readcount += sizeof(struct intel_package_header);
322
323	/* Search for dmc_offset to find firware binary. */
324	for (i = 0; i < package_header->num_entries; i++) {
325		if (package_header->fw_info[i].substepping == '*' &&
326		    si->stepping == package_header->fw_info[i].stepping) {
327			dmc_offset = package_header->fw_info[i].offset;
328			break;
329		} else if (si->stepping == package_header->fw_info[i].stepping &&
330			   si->substepping == package_header->fw_info[i].substepping) {
331			dmc_offset = package_header->fw_info[i].offset;
332			break;
333		} else if (package_header->fw_info[i].stepping == '*' &&
334			   package_header->fw_info[i].substepping == '*')
335			dmc_offset = package_header->fw_info[i].offset;
336	}
337	if (dmc_offset == CSR_DEFAULT_FW_OFFSET) {
338		DRM_ERROR("Firmware not supported for %c stepping\n",
339			  si->stepping);
340		return NULL;
341	}
342	readcount += dmc_offset;
343
344	/* Extract dmc_header information. */
345	dmc_header = (struct intel_dmc_header *)&fw->data[readcount];
346	if (sizeof(struct intel_dmc_header) != (dmc_header->header_len)) {
347		DRM_ERROR("Firmware has wrong dmc header length %u bytes\n",
348			  (dmc_header->header_len));
349		return NULL;
350	}
351	readcount += sizeof(struct intel_dmc_header);
352
353	/* Cache the dmc header info. */
354	if (dmc_header->mmio_count > ARRAY_SIZE(csr->mmioaddr)) {
355		DRM_ERROR("Firmware has wrong mmio count %u\n",
356			  dmc_header->mmio_count);
357		return NULL;
358	}
359	csr->mmio_count = dmc_header->mmio_count;
360	for (i = 0; i < dmc_header->mmio_count; i++) {
361		if (dmc_header->mmioaddr[i] < CSR_MMIO_START_RANGE ||
362		    dmc_header->mmioaddr[i] > CSR_MMIO_END_RANGE) {
363			DRM_ERROR(" Firmware has wrong mmio address 0x%x\n",
364				  dmc_header->mmioaddr[i]);
365			return NULL;
366		}
367		csr->mmioaddr[i] = _MMIO(dmc_header->mmioaddr[i]);
368		csr->mmiodata[i] = dmc_header->mmiodata[i];
369	}
370
371	/* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
372	nbytes = dmc_header->fw_size * 4;
373	if (nbytes > CSR_MAX_FW_SIZE) {
374		DRM_ERROR("CSR firmware too big (%u) bytes\n", nbytes);
375		return NULL;
376	}
377	csr->dmc_fw_size = dmc_header->fw_size;
378
379	dmc_payload = kmalloc(nbytes, GFP_KERNEL);
380	if (!dmc_payload) {
381		DRM_ERROR("Memory allocation failed for dmc payload\n");
382		return NULL;
383	}
384
385	return memcpy(dmc_payload, &fw->data[readcount], nbytes);
386}
387
388static void csr_load_work_fn(struct work_struct *work)
389{
390	struct drm_i915_private *dev_priv;
391	struct intel_csr *csr;
392	const struct firmware *fw;
393	int ret;
394
395	dev_priv = container_of(work, typeof(*dev_priv), csr.work);
396	csr = &dev_priv->csr;
397
398	ret = request_firmware(&fw, dev_priv->csr.fw_path,
399			       &dev_priv->drm.pdev->dev);
400	if (fw)
401		dev_priv->csr.dmc_payload = parse_csr_fw(dev_priv, fw);
402
403	if (dev_priv->csr.dmc_payload) {
404		intel_csr_load_program(dev_priv);
405
406		intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
407
408		DRM_INFO("Finished loading %s (v%u.%u)\n",
409			 dev_priv->csr.fw_path,
410			 CSR_VERSION_MAJOR(csr->version),
411			 CSR_VERSION_MINOR(csr->version));
412	} else {
413		dev_notice(dev_priv->drm.dev,
414			   "Failed to load DMC firmware"
415			   " [" FIRMWARE_URL "],"
416			   " disabling runtime power management.\n");
417	}
418
419	release_firmware(fw);
420}
421
422/**
423 * intel_csr_ucode_init() - initialize the firmware loading.
424 * @dev_priv: i915 drm device.
425 *
426 * This function is called at the time of loading the display driver to read
427 * firmware from a .bin file and copied into a internal memory.
428 */
429void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
430{
431	struct intel_csr *csr = &dev_priv->csr;
432
433	INIT_WORK(&dev_priv->csr.work, csr_load_work_fn);
434
435	if (!HAS_CSR(dev_priv))
436		return;
437
438	if (IS_KABYLAKE(dev_priv))
439		csr->fw_path = I915_CSR_KBL;
440	else if (IS_SKYLAKE(dev_priv))
441		csr->fw_path = I915_CSR_SKL;
442	else if (IS_BROXTON(dev_priv))
443		csr->fw_path = I915_CSR_BXT;
444	else {
445		DRM_ERROR("Unexpected: no known CSR firmware for platform\n");
446		return;
447	}
448
449	DRM_DEBUG_KMS("Loading %s\n", csr->fw_path);
450
451	/*
452	 * Obtain a runtime pm reference, until CSR is loaded,
453	 * to avoid entering runtime-suspend.
454	 */
455	intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
456
457	schedule_work(&dev_priv->csr.work);
458}
459
460/**
461 * intel_csr_ucode_suspend() - prepare CSR firmware before system suspend
462 * @dev_priv: i915 drm device
463 *
464 * Prepare the DMC firmware before entering system suspend. This includes
465 * flushing pending work items and releasing any resources acquired during
466 * init.
467 */
468void intel_csr_ucode_suspend(struct drm_i915_private *dev_priv)
469{
470	if (!HAS_CSR(dev_priv))
471		return;
472
473	flush_work(&dev_priv->csr.work);
474
475	/* Drop the reference held in case DMC isn't loaded. */
476	if (!dev_priv->csr.dmc_payload)
477		intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
478}
479
480/**
481 * intel_csr_ucode_resume() - init CSR firmware during system resume
482 * @dev_priv: i915 drm device
483 *
484 * Reinitialize the DMC firmware during system resume, reacquiring any
485 * resources released in intel_csr_ucode_suspend().
486 */
487void intel_csr_ucode_resume(struct drm_i915_private *dev_priv)
488{
489	if (!HAS_CSR(dev_priv))
490		return;
491
492	/*
493	 * Reacquire the reference to keep RPM disabled in case DMC isn't
494	 * loaded.
495	 */
496	if (!dev_priv->csr.dmc_payload)
497		intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
498}
499
500/**
501 * intel_csr_ucode_fini() - unload the CSR firmware.
502 * @dev_priv: i915 drm device.
503 *
504 * Firmmware unloading includes freeing the internal memory and reset the
505 * firmware loading status.
506 */
507void intel_csr_ucode_fini(struct drm_i915_private *dev_priv)
508{
509	if (!HAS_CSR(dev_priv))
510		return;
511
512	intel_csr_ucode_suspend(dev_priv);
513
514	kfree(dev_priv->csr.dmc_payload);
515}