Loading...
Note: File does not exist in v3.1.
1/*
2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3 * VA Linux Systems Inc., Fremont, California.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Original Authors:
25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane
26 *
27 * Kernel port Author: Dave Airlie
28 */
29
30#ifndef AMDGPU_MODE_H
31#define AMDGPU_MODE_H
32
33#include <drm/drm_crtc.h>
34#include <drm/drm_edid.h>
35#include <drm/drm_dp_helper.h>
36#include <drm/drm_fixed.h>
37#include <drm/drm_crtc_helper.h>
38#include <drm/drm_fb_helper.h>
39#include <drm/drm_plane_helper.h>
40#include <linux/i2c.h>
41#include <linux/i2c-algo-bit.h>
42#include <linux/hrtimer.h>
43#include "amdgpu_irq.h"
44
45struct amdgpu_bo;
46struct amdgpu_device;
47struct amdgpu_encoder;
48struct amdgpu_router;
49struct amdgpu_hpd;
50
51#define to_amdgpu_crtc(x) container_of(x, struct amdgpu_crtc, base)
52#define to_amdgpu_connector(x) container_of(x, struct amdgpu_connector, base)
53#define to_amdgpu_encoder(x) container_of(x, struct amdgpu_encoder, base)
54#define to_amdgpu_framebuffer(x) container_of(x, struct amdgpu_framebuffer, base)
55
56#define AMDGPU_MAX_HPD_PINS 6
57#define AMDGPU_MAX_CRTCS 6
58#define AMDGPU_MAX_AFMT_BLOCKS 9
59
60enum amdgpu_rmx_type {
61 RMX_OFF,
62 RMX_FULL,
63 RMX_CENTER,
64 RMX_ASPECT
65};
66
67enum amdgpu_underscan_type {
68 UNDERSCAN_OFF,
69 UNDERSCAN_ON,
70 UNDERSCAN_AUTO,
71};
72
73#define AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS 50
74#define AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS 10
75
76enum amdgpu_hpd_id {
77 AMDGPU_HPD_1 = 0,
78 AMDGPU_HPD_2,
79 AMDGPU_HPD_3,
80 AMDGPU_HPD_4,
81 AMDGPU_HPD_5,
82 AMDGPU_HPD_6,
83 AMDGPU_HPD_LAST,
84 AMDGPU_HPD_NONE = 0xff,
85};
86
87enum amdgpu_crtc_irq {
88 AMDGPU_CRTC_IRQ_VBLANK1 = 0,
89 AMDGPU_CRTC_IRQ_VBLANK2,
90 AMDGPU_CRTC_IRQ_VBLANK3,
91 AMDGPU_CRTC_IRQ_VBLANK4,
92 AMDGPU_CRTC_IRQ_VBLANK5,
93 AMDGPU_CRTC_IRQ_VBLANK6,
94 AMDGPU_CRTC_IRQ_VLINE1,
95 AMDGPU_CRTC_IRQ_VLINE2,
96 AMDGPU_CRTC_IRQ_VLINE3,
97 AMDGPU_CRTC_IRQ_VLINE4,
98 AMDGPU_CRTC_IRQ_VLINE5,
99 AMDGPU_CRTC_IRQ_VLINE6,
100 AMDGPU_CRTC_IRQ_LAST,
101 AMDGPU_CRTC_IRQ_NONE = 0xff
102};
103
104enum amdgpu_pageflip_irq {
105 AMDGPU_PAGEFLIP_IRQ_D1 = 0,
106 AMDGPU_PAGEFLIP_IRQ_D2,
107 AMDGPU_PAGEFLIP_IRQ_D3,
108 AMDGPU_PAGEFLIP_IRQ_D4,
109 AMDGPU_PAGEFLIP_IRQ_D5,
110 AMDGPU_PAGEFLIP_IRQ_D6,
111 AMDGPU_PAGEFLIP_IRQ_LAST,
112 AMDGPU_PAGEFLIP_IRQ_NONE = 0xff
113};
114
115enum amdgpu_flip_status {
116 AMDGPU_FLIP_NONE,
117 AMDGPU_FLIP_PENDING,
118 AMDGPU_FLIP_SUBMITTED
119};
120
121#define AMDGPU_MAX_I2C_BUS 16
122
123/* amdgpu gpio-based i2c
124 * 1. "mask" reg and bits
125 * grabs the gpio pins for software use
126 * 0=not held 1=held
127 * 2. "a" reg and bits
128 * output pin value
129 * 0=low 1=high
130 * 3. "en" reg and bits
131 * sets the pin direction
132 * 0=input 1=output
133 * 4. "y" reg and bits
134 * input pin value
135 * 0=low 1=high
136 */
137struct amdgpu_i2c_bus_rec {
138 bool valid;
139 /* id used by atom */
140 uint8_t i2c_id;
141 /* id used by atom */
142 enum amdgpu_hpd_id hpd;
143 /* can be used with hw i2c engine */
144 bool hw_capable;
145 /* uses multi-media i2c engine */
146 bool mm_i2c;
147 /* regs and bits */
148 uint32_t mask_clk_reg;
149 uint32_t mask_data_reg;
150 uint32_t a_clk_reg;
151 uint32_t a_data_reg;
152 uint32_t en_clk_reg;
153 uint32_t en_data_reg;
154 uint32_t y_clk_reg;
155 uint32_t y_data_reg;
156 uint32_t mask_clk_mask;
157 uint32_t mask_data_mask;
158 uint32_t a_clk_mask;
159 uint32_t a_data_mask;
160 uint32_t en_clk_mask;
161 uint32_t en_data_mask;
162 uint32_t y_clk_mask;
163 uint32_t y_data_mask;
164};
165
166#define AMDGPU_MAX_BIOS_CONNECTOR 16
167
168/* pll flags */
169#define AMDGPU_PLL_USE_BIOS_DIVS (1 << 0)
170#define AMDGPU_PLL_NO_ODD_POST_DIV (1 << 1)
171#define AMDGPU_PLL_USE_REF_DIV (1 << 2)
172#define AMDGPU_PLL_LEGACY (1 << 3)
173#define AMDGPU_PLL_PREFER_LOW_REF_DIV (1 << 4)
174#define AMDGPU_PLL_PREFER_HIGH_REF_DIV (1 << 5)
175#define AMDGPU_PLL_PREFER_LOW_FB_DIV (1 << 6)
176#define AMDGPU_PLL_PREFER_HIGH_FB_DIV (1 << 7)
177#define AMDGPU_PLL_PREFER_LOW_POST_DIV (1 << 8)
178#define AMDGPU_PLL_PREFER_HIGH_POST_DIV (1 << 9)
179#define AMDGPU_PLL_USE_FRAC_FB_DIV (1 << 10)
180#define AMDGPU_PLL_PREFER_CLOSEST_LOWER (1 << 11)
181#define AMDGPU_PLL_USE_POST_DIV (1 << 12)
182#define AMDGPU_PLL_IS_LCD (1 << 13)
183#define AMDGPU_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
184
185struct amdgpu_pll {
186 /* reference frequency */
187 uint32_t reference_freq;
188
189 /* fixed dividers */
190 uint32_t reference_div;
191 uint32_t post_div;
192
193 /* pll in/out limits */
194 uint32_t pll_in_min;
195 uint32_t pll_in_max;
196 uint32_t pll_out_min;
197 uint32_t pll_out_max;
198 uint32_t lcd_pll_out_min;
199 uint32_t lcd_pll_out_max;
200 uint32_t best_vco;
201
202 /* divider limits */
203 uint32_t min_ref_div;
204 uint32_t max_ref_div;
205 uint32_t min_post_div;
206 uint32_t max_post_div;
207 uint32_t min_feedback_div;
208 uint32_t max_feedback_div;
209 uint32_t min_frac_feedback_div;
210 uint32_t max_frac_feedback_div;
211
212 /* flags for the current clock */
213 uint32_t flags;
214
215 /* pll id */
216 uint32_t id;
217};
218
219struct amdgpu_i2c_chan {
220 struct i2c_adapter adapter;
221 struct drm_device *dev;
222 struct i2c_algo_bit_data bit;
223 struct amdgpu_i2c_bus_rec rec;
224 struct drm_dp_aux aux;
225 bool has_aux;
226 struct mutex mutex;
227};
228
229struct amdgpu_fbdev;
230
231struct amdgpu_afmt {
232 bool enabled;
233 int offset;
234 bool last_buffer_filled_status;
235 int id;
236 struct amdgpu_audio_pin *pin;
237};
238
239/*
240 * Audio
241 */
242struct amdgpu_audio_pin {
243 int channels;
244 int rate;
245 int bits_per_sample;
246 u8 status_bits;
247 u8 category_code;
248 u32 offset;
249 bool connected;
250 u32 id;
251};
252
253struct amdgpu_audio {
254 bool enabled;
255 struct amdgpu_audio_pin pin[AMDGPU_MAX_AFMT_BLOCKS];
256 int num_pins;
257};
258
259struct amdgpu_mode_mc_save {
260 u32 vga_render_control;
261 u32 vga_hdp_control;
262 bool crtc_enabled[AMDGPU_MAX_CRTCS];
263};
264
265struct amdgpu_display_funcs {
266 /* vga render */
267 void (*set_vga_render_state)(struct amdgpu_device *adev, bool render);
268 /* display watermarks */
269 void (*bandwidth_update)(struct amdgpu_device *adev);
270 /* get frame count */
271 u32 (*vblank_get_counter)(struct amdgpu_device *adev, int crtc);
272 /* wait for vblank */
273 void (*vblank_wait)(struct amdgpu_device *adev, int crtc);
274 /* set backlight level */
275 void (*backlight_set_level)(struct amdgpu_encoder *amdgpu_encoder,
276 u8 level);
277 /* get backlight level */
278 u8 (*backlight_get_level)(struct amdgpu_encoder *amdgpu_encoder);
279 /* hotplug detect */
280 bool (*hpd_sense)(struct amdgpu_device *adev, enum amdgpu_hpd_id hpd);
281 void (*hpd_set_polarity)(struct amdgpu_device *adev,
282 enum amdgpu_hpd_id hpd);
283 u32 (*hpd_get_gpio_reg)(struct amdgpu_device *adev);
284 /* pageflipping */
285 void (*page_flip)(struct amdgpu_device *adev,
286 int crtc_id, u64 crtc_base, bool async);
287 int (*page_flip_get_scanoutpos)(struct amdgpu_device *adev, int crtc,
288 u32 *vbl, u32 *position);
289 /* display topology setup */
290 void (*add_encoder)(struct amdgpu_device *adev,
291 uint32_t encoder_enum,
292 uint32_t supported_device,
293 u16 caps);
294 void (*add_connector)(struct amdgpu_device *adev,
295 uint32_t connector_id,
296 uint32_t supported_device,
297 int connector_type,
298 struct amdgpu_i2c_bus_rec *i2c_bus,
299 uint16_t connector_object_id,
300 struct amdgpu_hpd *hpd,
301 struct amdgpu_router *router);
302 void (*stop_mc_access)(struct amdgpu_device *adev,
303 struct amdgpu_mode_mc_save *save);
304 void (*resume_mc_access)(struct amdgpu_device *adev,
305 struct amdgpu_mode_mc_save *save);
306};
307
308struct amdgpu_mode_info {
309 struct atom_context *atom_context;
310 struct card_info *atom_card_info;
311 bool mode_config_initialized;
312 struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS];
313 struct amdgpu_afmt *afmt[AMDGPU_MAX_AFMT_BLOCKS];
314 /* DVI-I properties */
315 struct drm_property *coherent_mode_property;
316 /* DAC enable load detect */
317 struct drm_property *load_detect_property;
318 /* underscan */
319 struct drm_property *underscan_property;
320 struct drm_property *underscan_hborder_property;
321 struct drm_property *underscan_vborder_property;
322 /* audio */
323 struct drm_property *audio_property;
324 /* FMT dithering */
325 struct drm_property *dither_property;
326 /* hardcoded DFP edid from BIOS */
327 struct edid *bios_hardcoded_edid;
328 int bios_hardcoded_edid_size;
329
330 /* pointer to fbdev info structure */
331 struct amdgpu_fbdev *rfbdev;
332 /* firmware flags */
333 u16 firmware_flags;
334 /* pointer to backlight encoder */
335 struct amdgpu_encoder *bl_encoder;
336 struct amdgpu_audio audio; /* audio stuff */
337 int num_crtc; /* number of crtcs */
338 int num_hpd; /* number of hpd pins */
339 int num_dig; /* number of dig blocks */
340 int disp_priority;
341 const struct amdgpu_display_funcs *funcs;
342};
343
344#define AMDGPU_MAX_BL_LEVEL 0xFF
345
346#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
347
348struct amdgpu_backlight_privdata {
349 struct amdgpu_encoder *encoder;
350 uint8_t negative;
351};
352
353#endif
354
355struct amdgpu_atom_ss {
356 uint16_t percentage;
357 uint16_t percentage_divider;
358 uint8_t type;
359 uint16_t step;
360 uint8_t delay;
361 uint8_t range;
362 uint8_t refdiv;
363 /* asic_ss */
364 uint16_t rate;
365 uint16_t amount;
366};
367
368struct amdgpu_crtc {
369 struct drm_crtc base;
370 int crtc_id;
371 u16 lut_r[256], lut_g[256], lut_b[256];
372 bool enabled;
373 bool can_tile;
374 uint32_t crtc_offset;
375 struct drm_gem_object *cursor_bo;
376 uint64_t cursor_addr;
377 int cursor_x;
378 int cursor_y;
379 int cursor_hot_x;
380 int cursor_hot_y;
381 int cursor_width;
382 int cursor_height;
383 int max_cursor_width;
384 int max_cursor_height;
385 enum amdgpu_rmx_type rmx_type;
386 u8 h_border;
387 u8 v_border;
388 fixed20_12 vsc;
389 fixed20_12 hsc;
390 struct drm_display_mode native_mode;
391 u32 pll_id;
392 /* page flipping */
393 struct amdgpu_flip_work *pflip_works;
394 enum amdgpu_flip_status pflip_status;
395 int deferred_flip_completion;
396 /* pll sharing */
397 struct amdgpu_atom_ss ss;
398 bool ss_enabled;
399 u32 adjusted_clock;
400 int bpc;
401 u32 pll_reference_div;
402 u32 pll_post_div;
403 u32 pll_flags;
404 struct drm_encoder *encoder;
405 struct drm_connector *connector;
406 /* for dpm */
407 u32 line_time;
408 u32 wm_low;
409 u32 wm_high;
410 u32 lb_vblank_lead_lines;
411 struct drm_display_mode hw_mode;
412 /* for virtual dce */
413 struct hrtimer vblank_timer;
414 enum amdgpu_interrupt_state vsync_timer_enabled;
415};
416
417struct amdgpu_encoder_atom_dig {
418 bool linkb;
419 /* atom dig */
420 bool coherent_mode;
421 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
422 /* atom lvds/edp */
423 uint32_t lcd_misc;
424 uint16_t panel_pwr_delay;
425 uint32_t lcd_ss_id;
426 /* panel mode */
427 struct drm_display_mode native_mode;
428 struct backlight_device *bl_dev;
429 int dpms_mode;
430 uint8_t backlight_level;
431 int panel_mode;
432 struct amdgpu_afmt *afmt;
433};
434
435struct amdgpu_encoder {
436 struct drm_encoder base;
437 uint32_t encoder_enum;
438 uint32_t encoder_id;
439 uint32_t devices;
440 uint32_t active_device;
441 uint32_t flags;
442 uint32_t pixel_clock;
443 enum amdgpu_rmx_type rmx_type;
444 enum amdgpu_underscan_type underscan_type;
445 uint32_t underscan_hborder;
446 uint32_t underscan_vborder;
447 struct drm_display_mode native_mode;
448 void *enc_priv;
449 int audio_polling_active;
450 bool is_ext_encoder;
451 u16 caps;
452};
453
454struct amdgpu_connector_atom_dig {
455 /* displayport */
456 u8 dpcd[DP_RECEIVER_CAP_SIZE];
457 u8 dp_sink_type;
458 int dp_clock;
459 int dp_lane_count;
460 bool edp_on;
461};
462
463struct amdgpu_gpio_rec {
464 bool valid;
465 u8 id;
466 u32 reg;
467 u32 mask;
468 u32 shift;
469};
470
471struct amdgpu_hpd {
472 enum amdgpu_hpd_id hpd;
473 u8 plugged_state;
474 struct amdgpu_gpio_rec gpio;
475};
476
477struct amdgpu_router {
478 u32 router_id;
479 struct amdgpu_i2c_bus_rec i2c_info;
480 u8 i2c_addr;
481 /* i2c mux */
482 bool ddc_valid;
483 u8 ddc_mux_type;
484 u8 ddc_mux_control_pin;
485 u8 ddc_mux_state;
486 /* clock/data mux */
487 bool cd_valid;
488 u8 cd_mux_type;
489 u8 cd_mux_control_pin;
490 u8 cd_mux_state;
491};
492
493enum amdgpu_connector_audio {
494 AMDGPU_AUDIO_DISABLE = 0,
495 AMDGPU_AUDIO_ENABLE = 1,
496 AMDGPU_AUDIO_AUTO = 2
497};
498
499enum amdgpu_connector_dither {
500 AMDGPU_FMT_DITHER_DISABLE = 0,
501 AMDGPU_FMT_DITHER_ENABLE = 1,
502};
503
504struct amdgpu_connector {
505 struct drm_connector base;
506 uint32_t connector_id;
507 uint32_t devices;
508 struct amdgpu_i2c_chan *ddc_bus;
509 /* some systems have an hdmi and vga port with a shared ddc line */
510 bool shared_ddc;
511 bool use_digital;
512 /* we need to mind the EDID between detect
513 and get modes due to analog/digital/tvencoder */
514 struct edid *edid;
515 void *con_priv;
516 bool dac_load_detect;
517 bool detected_by_load; /* if the connection status was determined by load */
518 uint16_t connector_object_id;
519 struct amdgpu_hpd hpd;
520 struct amdgpu_router router;
521 struct amdgpu_i2c_chan *router_bus;
522 enum amdgpu_connector_audio audio;
523 enum amdgpu_connector_dither dither;
524 unsigned pixelclock_for_modeset;
525};
526
527struct amdgpu_framebuffer {
528 struct drm_framebuffer base;
529 struct drm_gem_object *obj;
530};
531
532#define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
533 ((em) == ATOM_ENCODER_MODE_DP_MST))
534
535/* Driver internal use only flags of amdgpu_get_crtc_scanoutpos() */
536#define USE_REAL_VBLANKSTART (1 << 30)
537#define GET_DISTANCE_TO_VBLANKSTART (1 << 31)
538
539void amdgpu_link_encoder_connector(struct drm_device *dev);
540
541struct drm_connector *
542amdgpu_get_connector_for_encoder(struct drm_encoder *encoder);
543struct drm_connector *
544amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder);
545bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder,
546 u32 pixel_clock);
547
548u16 amdgpu_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
549struct drm_encoder *amdgpu_get_external_encoder(struct drm_encoder *encoder);
550
551bool amdgpu_ddc_probe(struct amdgpu_connector *amdgpu_connector, bool use_aux);
552
553void amdgpu_encoder_set_active_device(struct drm_encoder *encoder);
554
555int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
556 unsigned int flags, int *vpos, int *hpos,
557 ktime_t *stime, ktime_t *etime,
558 const struct drm_display_mode *mode);
559
560int amdgpu_framebuffer_init(struct drm_device *dev,
561 struct amdgpu_framebuffer *rfb,
562 const struct drm_mode_fb_cmd2 *mode_cmd,
563 struct drm_gem_object *obj);
564
565int amdgpufb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
566
567void amdgpu_enc_destroy(struct drm_encoder *encoder);
568void amdgpu_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
569bool amdgpu_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
570 const struct drm_display_mode *mode,
571 struct drm_display_mode *adjusted_mode);
572void amdgpu_panel_mode_fixup(struct drm_encoder *encoder,
573 struct drm_display_mode *adjusted_mode);
574int amdgpu_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc);
575
576/* fbdev layer */
577int amdgpu_fbdev_init(struct amdgpu_device *adev);
578void amdgpu_fbdev_fini(struct amdgpu_device *adev);
579void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state);
580int amdgpu_fbdev_total_size(struct amdgpu_device *adev);
581bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj);
582void amdgpu_fbdev_restore_mode(struct amdgpu_device *adev);
583
584void amdgpu_fb_output_poll_changed(struct amdgpu_device *adev);
585
586
587int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int bpp, bool tiled);
588
589/* amdgpu_display.c */
590void amdgpu_print_display_setup(struct drm_device *dev);
591int amdgpu_modeset_create_props(struct amdgpu_device *adev);
592int amdgpu_crtc_set_config(struct drm_mode_set *set);
593int amdgpu_crtc_page_flip_target(struct drm_crtc *crtc,
594 struct drm_framebuffer *fb,
595 struct drm_pending_vblank_event *event,
596 uint32_t page_flip_flags, uint32_t target);
597extern const struct drm_mode_config_funcs amdgpu_mode_funcs;
598
599#endif