1/*
  2 * Support for the GPIO/IRQ expander chips present on several HTC phones.
  3 * These are implemented in CPLD chips present on the board.
  4 *
  5 * Copyright (c) 2007 Kevin O'Connor <kevin@koconnor.net>
  6 * Copyright (c) 2007 Philipp Zabel <philipp.zabel@gmail.com>
  7 *
  8 * This file may be distributed under the terms of the GNU GPL license.
  9 */
 10
 11#include <linux/kernel.h>
 12#include <linux/errno.h>
 13#include <linux/interrupt.h>
 14#include <linux/irq.h>
 15#include <linux/io.h>
 16#include <linux/spinlock.h>
 17#include <linux/platform_data/gpio-htc-egpio.h>
 18#include <linux/platform_device.h>
 19#include <linux/slab.h>
 20#include <linux/init.h>
 21
 22struct egpio_chip {
 23	int              reg_start;
 24	int              cached_values;
 25	unsigned long    is_out;
 26	struct device    *dev;
 27	struct gpio_chip chip;
 28};
 29
 30struct egpio_info {
 31	spinlock_t        lock;
 32
 33	/* iomem info */
 34	void __iomem      *base_addr;
 35	int               bus_shift;	/* byte shift */
 36	int               reg_shift;	/* bit shift */
 37	int               reg_mask;
 38
 39	/* irq info */
 40	int               ack_register;
 41	int               ack_write;
 42	u16               irqs_enabled;
 43	uint              irq_start;
 44	int               nirqs;
 45	uint              chained_irq;
 46
 47	/* egpio info */
 48	struct egpio_chip *chip;
 49	int               nchips;
 50};
 51
 52static inline void egpio_writew(u16 value, struct egpio_info *ei, int reg)
 53{
 54	writew(value, ei->base_addr + (reg << ei->bus_shift));
 55}
 56
 57static inline u16 egpio_readw(struct egpio_info *ei, int reg)
 58{
 59	return readw(ei->base_addr + (reg << ei->bus_shift));
 60}
 61
 62/*
 63 * IRQs
 64 */
 65
 66static inline void ack_irqs(struct egpio_info *ei)
 67{
 68	egpio_writew(ei->ack_write, ei, ei->ack_register);
 69	pr_debug("EGPIO ack - write %x to base+%x\n",
 70			ei->ack_write, ei->ack_register << ei->bus_shift);
 71}
 72
 73static void egpio_ack(struct irq_data *data)
 74{
 75}
 76
 77/* There does not appear to be a way to proactively mask interrupts
 78 * on the egpio chip itself.  So, we simply ignore interrupts that
 79 * aren't desired. */
 80static void egpio_mask(struct irq_data *data)
 81{
 82	struct egpio_info *ei = irq_data_get_irq_chip_data(data);
 83	ei->irqs_enabled &= ~(1 << (data->irq - ei->irq_start));
 84	pr_debug("EGPIO mask %d %04x\n", data->irq, ei->irqs_enabled);
 85}
 86
 87static void egpio_unmask(struct irq_data *data)
 88{
 89	struct egpio_info *ei = irq_data_get_irq_chip_data(data);
 90	ei->irqs_enabled |= 1 << (data->irq - ei->irq_start);
 91	pr_debug("EGPIO unmask %d %04x\n", data->irq, ei->irqs_enabled);
 92}
 93
 94static struct irq_chip egpio_muxed_chip = {
 95	.name		= "htc-egpio",
 96	.irq_ack	= egpio_ack,
 97	.irq_mask	= egpio_mask,
 98	.irq_unmask	= egpio_unmask,
 99};
100
101static void egpio_handler(struct irq_desc *desc)
102{
103	struct egpio_info *ei = irq_desc_get_handler_data(desc);
104	int irqpin;
105
106	/* Read current pins. */
107	unsigned long readval = egpio_readw(ei, ei->ack_register);
108	pr_debug("IRQ reg: %x\n", (unsigned int)readval);
109	/* Ack/unmask interrupts. */
110	ack_irqs(ei);
111	/* Process all set pins. */
112	readval &= ei->irqs_enabled;
113	for_each_set_bit(irqpin, &readval, ei->nirqs) {
114		/* Run irq handler */
115		pr_debug("got IRQ %d\n", irqpin);
116		generic_handle_irq(ei->irq_start + irqpin);
117	}
118}
119
120int htc_egpio_get_wakeup_irq(struct device *dev)
121{
122	struct egpio_info *ei = dev_get_drvdata(dev);
123
124	/* Read current pins. */
125	u16 readval = egpio_readw(ei, ei->ack_register);
126	/* Ack/unmask interrupts. */
127	ack_irqs(ei);
128	/* Return first set pin. */
129	readval &= ei->irqs_enabled;
130	return ei->irq_start + ffs(readval) - 1;
131}
132EXPORT_SYMBOL(htc_egpio_get_wakeup_irq);
133
134static inline int egpio_pos(struct egpio_info *ei, int bit)
135{
136	return bit >> ei->reg_shift;
137}
138
139static inline int egpio_bit(struct egpio_info *ei, int bit)
140{
141	return 1 << (bit & ((1 << ei->reg_shift)-1));
142}
143
144/*
145 * Input pins
146 */
147
148static int egpio_get(struct gpio_chip *chip, unsigned offset)
149{
150	struct egpio_chip *egpio;
151	struct egpio_info *ei;
152	unsigned           bit;
153	int                reg;
154	int                value;
155
156	pr_debug("egpio_get_value(%d)\n", chip->base + offset);
157
158	egpio = gpiochip_get_data(chip);
159	ei    = dev_get_drvdata(egpio->dev);
160	bit   = egpio_bit(ei, offset);
161	reg   = egpio->reg_start + egpio_pos(ei, offset);
162
163	if (test_bit(offset, &egpio->is_out)) {
164		return !!(egpio->cached_values & (1 << offset));
165	} else {
166		value = egpio_readw(ei, reg);
167		pr_debug("readw(%p + %x) = %x\n",
168			 ei->base_addr, reg << ei->bus_shift, value);
169		return !!(value & bit);
170	}
171}
172
173static int egpio_direction_input(struct gpio_chip *chip, unsigned offset)
174{
175	struct egpio_chip *egpio;
176
177	egpio = gpiochip_get_data(chip);
178	return test_bit(offset, &egpio->is_out) ? -EINVAL : 0;
179}
180
181
182/*
183 * Output pins
184 */
185
186static void egpio_set(struct gpio_chip *chip, unsigned offset, int value)
187{
188	unsigned long     flag;
189	struct egpio_chip *egpio;
190	struct egpio_info *ei;
191	unsigned          bit;
192	int               pos;
193	int               reg;
194	int               shift;
195
196	pr_debug("egpio_set(%s, %d(%d), %d)\n",
197			chip->label, offset, offset+chip->base, value);
198
199	egpio = gpiochip_get_data(chip);
200	ei    = dev_get_drvdata(egpio->dev);
201	bit   = egpio_bit(ei, offset);
202	pos   = egpio_pos(ei, offset);
203	reg   = egpio->reg_start + pos;
204	shift = pos << ei->reg_shift;
205
206	pr_debug("egpio %s: reg %d = 0x%04x\n", value ? "set" : "clear",
207			reg, (egpio->cached_values >> shift) & ei->reg_mask);
208
209	spin_lock_irqsave(&ei->lock, flag);
210	if (value)
211		egpio->cached_values |= (1 << offset);
212	else
213		egpio->cached_values &= ~(1 << offset);
214	egpio_writew((egpio->cached_values >> shift) & ei->reg_mask, ei, reg);
215	spin_unlock_irqrestore(&ei->lock, flag);
216}
217
218static int egpio_direction_output(struct gpio_chip *chip,
219					unsigned offset, int value)
220{
221	struct egpio_chip *egpio;
222
223	egpio = gpiochip_get_data(chip);
224	if (test_bit(offset, &egpio->is_out)) {
225		egpio_set(chip, offset, value);
226		return 0;
227	} else {
228		return -EINVAL;
229	}
230}
231
232static int egpio_get_direction(struct gpio_chip *chip, unsigned offset)
233{
234	struct egpio_chip *egpio;
235
236	egpio = gpiochip_get_data(chip);
237
238	return !test_bit(offset, &egpio->is_out);
239}
240
241static void egpio_write_cache(struct egpio_info *ei)
242{
243	int               i;
244	struct egpio_chip *egpio;
245	int               shift;
246
247	for (i = 0; i < ei->nchips; i++) {
248		egpio = &(ei->chip[i]);
249		if (!egpio->is_out)
250			continue;
251
252		for (shift = 0; shift < egpio->chip.ngpio;
253				shift += (1<<ei->reg_shift)) {
254
255			int reg = egpio->reg_start + egpio_pos(ei, shift);
256
257			if (!((egpio->is_out >> shift) & ei->reg_mask))
258				continue;
259
260			pr_debug("EGPIO: setting %x to %x, was %x\n", reg,
261				(egpio->cached_values >> shift) & ei->reg_mask,
262				egpio_readw(ei, reg));
263
264			egpio_writew((egpio->cached_values >> shift)
265					& ei->reg_mask, ei, reg);
266		}
267	}
268}
269
270
271/*
272 * Setup
273 */
274
275static int __init egpio_probe(struct platform_device *pdev)
276{
277	struct htc_egpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
278	struct resource   *res;
279	struct egpio_info *ei;
280	struct gpio_chip  *chip;
281	unsigned int      irq, irq_end;
282	int               i;
283	int               ret;
284
285	/* Initialize ei data structure. */
286	ei = devm_kzalloc(&pdev->dev, sizeof(*ei), GFP_KERNEL);
287	if (!ei)
288		return -ENOMEM;
289
290	spin_lock_init(&ei->lock);
291
292	/* Find chained irq */
293	ret = -EINVAL;
294	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
295	if (res)
296		ei->chained_irq = res->start;
297
298	/* Map egpio chip into virtual address space. */
299	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
300	if (!res)
301		goto fail;
302	ei->base_addr = devm_ioremap_nocache(&pdev->dev, res->start,
303					     resource_size(res));
304	if (!ei->base_addr)
305		goto fail;
306	pr_debug("EGPIO phys=%08x virt=%p\n", (u32)res->start, ei->base_addr);
307
308	if ((pdata->bus_width != 16) && (pdata->bus_width != 32))
309		goto fail;
310	ei->bus_shift = fls(pdata->bus_width - 1) - 3;
311	pr_debug("bus_shift = %d\n", ei->bus_shift);
312
313	if ((pdata->reg_width != 8) && (pdata->reg_width != 16))
314		goto fail;
315	ei->reg_shift = fls(pdata->reg_width - 1);
316	pr_debug("reg_shift = %d\n", ei->reg_shift);
317
318	ei->reg_mask = (1 << pdata->reg_width) - 1;
319
320	platform_set_drvdata(pdev, ei);
321
322	ei->nchips = pdata->num_chips;
323	ei->chip = devm_kzalloc(&pdev->dev,
324				sizeof(struct egpio_chip) * ei->nchips,
325				GFP_KERNEL);
326	if (!ei->chip) {
327		ret = -ENOMEM;
328		goto fail;
329	}
330	for (i = 0; i < ei->nchips; i++) {
331		ei->chip[i].reg_start = pdata->chip[i].reg_start;
332		ei->chip[i].cached_values = pdata->chip[i].initial_values;
333		ei->chip[i].is_out = pdata->chip[i].direction;
334		ei->chip[i].dev = &(pdev->dev);
335		chip = &(ei->chip[i].chip);
336		chip->label           = "htc-egpio";
337		chip->parent          = &pdev->dev;
338		chip->owner           = THIS_MODULE;
339		chip->get             = egpio_get;
340		chip->set             = egpio_set;
341		chip->direction_input = egpio_direction_input;
342		chip->direction_output = egpio_direction_output;
343		chip->get_direction   = egpio_get_direction;
344		chip->base            = pdata->chip[i].gpio_base;
345		chip->ngpio           = pdata->chip[i].num_gpios;
346
347		gpiochip_add_data(chip, &ei->chip[i]);
348	}
349
350	/* Set initial pin values */
351	egpio_write_cache(ei);
352
353	ei->irq_start = pdata->irq_base;
354	ei->nirqs = pdata->num_irqs;
355	ei->ack_register = pdata->ack_register;
356
357	if (ei->chained_irq) {
358		/* Setup irq handlers */
359		ei->ack_write = 0xFFFF;
360		if (pdata->invert_acks)
361			ei->ack_write = 0;
362		irq_end = ei->irq_start + ei->nirqs;
363		for (irq = ei->irq_start; irq < irq_end; irq++) {
364			irq_set_chip_and_handler(irq, &egpio_muxed_chip,
365						 handle_simple_irq);
366			irq_set_chip_data(irq, ei);
367			irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
368		}
369		irq_set_irq_type(ei->chained_irq, IRQ_TYPE_EDGE_RISING);
370		irq_set_chained_handler_and_data(ei->chained_irq,
371						 egpio_handler, ei);
372		ack_irqs(ei);
373
374		device_init_wakeup(&pdev->dev, 1);
375	}
376
377	return 0;
378
379fail:
380	printk(KERN_ERR "EGPIO failed to setup\n");
381	return ret;
382}
383
384#ifdef CONFIG_PM
385static int egpio_suspend(struct platform_device *pdev, pm_message_t state)
386{
387	struct egpio_info *ei = platform_get_drvdata(pdev);
388
389	if (ei->chained_irq && device_may_wakeup(&pdev->dev))
390		enable_irq_wake(ei->chained_irq);
391	return 0;
392}
393
394static int egpio_resume(struct platform_device *pdev)
395{
396	struct egpio_info *ei = platform_get_drvdata(pdev);
397
398	if (ei->chained_irq && device_may_wakeup(&pdev->dev))
399		disable_irq_wake(ei->chained_irq);
400
401	/* Update registers from the cache, in case
402	   the CPLD was powered off during suspend */
403	egpio_write_cache(ei);
404	return 0;
405}
406#else
407#define egpio_suspend NULL
408#define egpio_resume NULL
409#endif
410
411
412static struct platform_driver egpio_driver = {
413	.driver = {
414		.name = "htc-egpio",
415		.suppress_bind_attrs = true,
416	},
417	.suspend      = egpio_suspend,
418	.resume       = egpio_resume,
419};
420
421static int __init egpio_init(void)
422{
423	return platform_driver_probe(&egpio_driver, egpio_probe);
424}
425/* start early for dependencies */
426subsys_initcall(egpio_init);