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1/*
2 * Copyright (C) 2002 - 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>
3 * and Markus Demleitner <msdemlei@cl.uni-heidelberg.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This driver adds basic cpufreq support for SMU & 970FX based G5 Macs,
10 * that is iMac G5 and latest single CPU desktop.
11 */
12
13#undef DEBUG
14
15#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
16
17#include <linux/module.h>
18#include <linux/types.h>
19#include <linux/errno.h>
20#include <linux/kernel.h>
21#include <linux/delay.h>
22#include <linux/sched.h>
23#include <linux/cpufreq.h>
24#include <linux/init.h>
25#include <linux/completion.h>
26#include <linux/mutex.h>
27#include <linux/of_device.h>
28#include <asm/prom.h>
29#include <asm/machdep.h>
30#include <asm/irq.h>
31#include <asm/sections.h>
32#include <asm/cputable.h>
33#include <asm/time.h>
34#include <asm/smu.h>
35#include <asm/pmac_pfunc.h>
36
37#define DBG(fmt...) pr_debug(fmt)
38
39/* see 970FX user manual */
40
41#define SCOM_PCR 0x0aa001 /* PCR scom addr */
42
43#define PCR_HILO_SELECT 0x80000000U /* 1 = PCR, 0 = PCRH */
44#define PCR_SPEED_FULL 0x00000000U /* 1:1 speed value */
45#define PCR_SPEED_HALF 0x00020000U /* 1:2 speed value */
46#define PCR_SPEED_QUARTER 0x00040000U /* 1:4 speed value */
47#define PCR_SPEED_MASK 0x000e0000U /* speed mask */
48#define PCR_SPEED_SHIFT 17
49#define PCR_FREQ_REQ_VALID 0x00010000U /* freq request valid */
50#define PCR_VOLT_REQ_VALID 0x00008000U /* volt request valid */
51#define PCR_TARGET_TIME_MASK 0x00006000U /* target time */
52#define PCR_STATLAT_MASK 0x00001f00U /* STATLAT value */
53#define PCR_SNOOPLAT_MASK 0x000000f0U /* SNOOPLAT value */
54#define PCR_SNOOPACC_MASK 0x0000000fU /* SNOOPACC value */
55
56#define SCOM_PSR 0x408001 /* PSR scom addr */
57/* warning: PSR is a 64 bits register */
58#define PSR_CMD_RECEIVED 0x2000000000000000U /* command received */
59#define PSR_CMD_COMPLETED 0x1000000000000000U /* command completed */
60#define PSR_CUR_SPEED_MASK 0x0300000000000000U /* current speed */
61#define PSR_CUR_SPEED_SHIFT (56)
62
63/*
64 * The G5 only supports two frequencies (Quarter speed is not supported)
65 */
66#define CPUFREQ_HIGH 0
67#define CPUFREQ_LOW 1
68
69static struct cpufreq_frequency_table g5_cpu_freqs[] = {
70 {0, CPUFREQ_HIGH, 0},
71 {0, CPUFREQ_LOW, 0},
72 {0, 0, CPUFREQ_TABLE_END},
73};
74
75/* Power mode data is an array of the 32 bits PCR values to use for
76 * the various frequencies, retrieved from the device-tree
77 */
78static int g5_pmode_cur;
79
80static void (*g5_switch_volt)(int speed_mode);
81static int (*g5_switch_freq)(int speed_mode);
82static int (*g5_query_freq)(void);
83
84static unsigned long transition_latency;
85
86#ifdef CONFIG_PMAC_SMU
87
88static const u32 *g5_pmode_data;
89static int g5_pmode_max;
90
91static struct smu_sdbp_fvt *g5_fvt_table; /* table of op. points */
92static int g5_fvt_count; /* number of op. points */
93static int g5_fvt_cur; /* current op. point */
94
95/*
96 * SMU based voltage switching for Neo2 platforms
97 */
98
99static void g5_smu_switch_volt(int speed_mode)
100{
101 struct smu_simple_cmd cmd;
102
103 DECLARE_COMPLETION_ONSTACK(comp);
104 smu_queue_simple(&cmd, SMU_CMD_POWER_COMMAND, 8, smu_done_complete,
105 &comp, 'V', 'S', 'L', 'E', 'W',
106 0xff, g5_fvt_cur+1, speed_mode);
107 wait_for_completion(&comp);
108}
109
110/*
111 * Platform function based voltage/vdnap switching for Neo2
112 */
113
114static struct pmf_function *pfunc_set_vdnap0;
115static struct pmf_function *pfunc_vdnap0_complete;
116
117static void g5_vdnap_switch_volt(int speed_mode)
118{
119 struct pmf_args args;
120 u32 slew, done = 0;
121 unsigned long timeout;
122
123 slew = (speed_mode == CPUFREQ_LOW) ? 1 : 0;
124 args.count = 1;
125 args.u[0].p = &slew;
126
127 pmf_call_one(pfunc_set_vdnap0, &args);
128
129 /* It's an irq GPIO so we should be able to just block here,
130 * I'll do that later after I've properly tested the IRQ code for
131 * platform functions
132 */
133 timeout = jiffies + HZ/10;
134 while(!time_after(jiffies, timeout)) {
135 args.count = 1;
136 args.u[0].p = &done;
137 pmf_call_one(pfunc_vdnap0_complete, &args);
138 if (done)
139 break;
140 usleep_range(1000, 1000);
141 }
142 if (done == 0)
143 pr_warn("Timeout in clock slewing !\n");
144}
145
146
147/*
148 * SCOM based frequency switching for 970FX rev3
149 */
150static int g5_scom_switch_freq(int speed_mode)
151{
152 unsigned long flags;
153 int to;
154
155 /* If frequency is going up, first ramp up the voltage */
156 if (speed_mode < g5_pmode_cur)
157 g5_switch_volt(speed_mode);
158
159 local_irq_save(flags);
160
161 /* Clear PCR high */
162 scom970_write(SCOM_PCR, 0);
163 /* Clear PCR low */
164 scom970_write(SCOM_PCR, PCR_HILO_SELECT | 0);
165 /* Set PCR low */
166 scom970_write(SCOM_PCR, PCR_HILO_SELECT |
167 g5_pmode_data[speed_mode]);
168
169 /* Wait for completion */
170 for (to = 0; to < 10; to++) {
171 unsigned long psr = scom970_read(SCOM_PSR);
172
173 if ((psr & PSR_CMD_RECEIVED) == 0 &&
174 (((psr >> PSR_CUR_SPEED_SHIFT) ^
175 (g5_pmode_data[speed_mode] >> PCR_SPEED_SHIFT)) & 0x3)
176 == 0)
177 break;
178 if (psr & PSR_CMD_COMPLETED)
179 break;
180 udelay(100);
181 }
182
183 local_irq_restore(flags);
184
185 /* If frequency is going down, last ramp the voltage */
186 if (speed_mode > g5_pmode_cur)
187 g5_switch_volt(speed_mode);
188
189 g5_pmode_cur = speed_mode;
190 ppc_proc_freq = g5_cpu_freqs[speed_mode].frequency * 1000ul;
191
192 return 0;
193}
194
195static int g5_scom_query_freq(void)
196{
197 unsigned long psr = scom970_read(SCOM_PSR);
198 int i;
199
200 for (i = 0; i <= g5_pmode_max; i++)
201 if ((((psr >> PSR_CUR_SPEED_SHIFT) ^
202 (g5_pmode_data[i] >> PCR_SPEED_SHIFT)) & 0x3) == 0)
203 break;
204 return i;
205}
206
207/*
208 * Fake voltage switching for platforms with missing support
209 */
210
211static void g5_dummy_switch_volt(int speed_mode)
212{
213}
214
215#endif /* CONFIG_PMAC_SMU */
216
217/*
218 * Platform function based voltage switching for PowerMac7,2 & 7,3
219 */
220
221static struct pmf_function *pfunc_cpu0_volt_high;
222static struct pmf_function *pfunc_cpu0_volt_low;
223static struct pmf_function *pfunc_cpu1_volt_high;
224static struct pmf_function *pfunc_cpu1_volt_low;
225
226static void g5_pfunc_switch_volt(int speed_mode)
227{
228 if (speed_mode == CPUFREQ_HIGH) {
229 if (pfunc_cpu0_volt_high)
230 pmf_call_one(pfunc_cpu0_volt_high, NULL);
231 if (pfunc_cpu1_volt_high)
232 pmf_call_one(pfunc_cpu1_volt_high, NULL);
233 } else {
234 if (pfunc_cpu0_volt_low)
235 pmf_call_one(pfunc_cpu0_volt_low, NULL);
236 if (pfunc_cpu1_volt_low)
237 pmf_call_one(pfunc_cpu1_volt_low, NULL);
238 }
239 usleep_range(10000, 10000); /* should be faster , to fix */
240}
241
242/*
243 * Platform function based frequency switching for PowerMac7,2 & 7,3
244 */
245
246static struct pmf_function *pfunc_cpu_setfreq_high;
247static struct pmf_function *pfunc_cpu_setfreq_low;
248static struct pmf_function *pfunc_cpu_getfreq;
249static struct pmf_function *pfunc_slewing_done;
250
251static int g5_pfunc_switch_freq(int speed_mode)
252{
253 struct pmf_args args;
254 u32 done = 0;
255 unsigned long timeout;
256 int rc;
257
258 DBG("g5_pfunc_switch_freq(%d)\n", speed_mode);
259
260 /* If frequency is going up, first ramp up the voltage */
261 if (speed_mode < g5_pmode_cur)
262 g5_switch_volt(speed_mode);
263
264 /* Do it */
265 if (speed_mode == CPUFREQ_HIGH)
266 rc = pmf_call_one(pfunc_cpu_setfreq_high, NULL);
267 else
268 rc = pmf_call_one(pfunc_cpu_setfreq_low, NULL);
269
270 if (rc)
271 pr_warn("pfunc switch error %d\n", rc);
272
273 /* It's an irq GPIO so we should be able to just block here,
274 * I'll do that later after I've properly tested the IRQ code for
275 * platform functions
276 */
277 timeout = jiffies + HZ/10;
278 while(!time_after(jiffies, timeout)) {
279 args.count = 1;
280 args.u[0].p = &done;
281 pmf_call_one(pfunc_slewing_done, &args);
282 if (done)
283 break;
284 usleep_range(500, 500);
285 }
286 if (done == 0)
287 pr_warn("Timeout in clock slewing !\n");
288
289 /* If frequency is going down, last ramp the voltage */
290 if (speed_mode > g5_pmode_cur)
291 g5_switch_volt(speed_mode);
292
293 g5_pmode_cur = speed_mode;
294 ppc_proc_freq = g5_cpu_freqs[speed_mode].frequency * 1000ul;
295
296 return 0;
297}
298
299static int g5_pfunc_query_freq(void)
300{
301 struct pmf_args args;
302 u32 val = 0;
303
304 args.count = 1;
305 args.u[0].p = &val;
306 pmf_call_one(pfunc_cpu_getfreq, &args);
307 return val ? CPUFREQ_HIGH : CPUFREQ_LOW;
308}
309
310
311/*
312 * Common interface to the cpufreq core
313 */
314
315static int g5_cpufreq_target(struct cpufreq_policy *policy, unsigned int index)
316{
317 return g5_switch_freq(index);
318}
319
320static unsigned int g5_cpufreq_get_speed(unsigned int cpu)
321{
322 return g5_cpu_freqs[g5_pmode_cur].frequency;
323}
324
325static int g5_cpufreq_cpu_init(struct cpufreq_policy *policy)
326{
327 return cpufreq_generic_init(policy, g5_cpu_freqs, transition_latency);
328}
329
330static struct cpufreq_driver g5_cpufreq_driver = {
331 .name = "powermac",
332 .flags = CPUFREQ_CONST_LOOPS,
333 .init = g5_cpufreq_cpu_init,
334 .verify = cpufreq_generic_frequency_table_verify,
335 .target_index = g5_cpufreq_target,
336 .get = g5_cpufreq_get_speed,
337 .attr = cpufreq_generic_attr,
338};
339
340
341#ifdef CONFIG_PMAC_SMU
342
343static int __init g5_neo2_cpufreq_init(struct device_node *cpunode)
344{
345 unsigned int psize, ssize;
346 unsigned long max_freq;
347 char *freq_method, *volt_method;
348 const u32 *valp;
349 u32 pvr_hi;
350 int use_volts_vdnap = 0;
351 int use_volts_smu = 0;
352 int rc = -ENODEV;
353
354 /* Check supported platforms */
355 if (of_machine_is_compatible("PowerMac8,1") ||
356 of_machine_is_compatible("PowerMac8,2") ||
357 of_machine_is_compatible("PowerMac9,1") ||
358 of_machine_is_compatible("PowerMac12,1"))
359 use_volts_smu = 1;
360 else if (of_machine_is_compatible("PowerMac11,2"))
361 use_volts_vdnap = 1;
362 else
363 return -ENODEV;
364
365 /* Check 970FX for now */
366 valp = of_get_property(cpunode, "cpu-version", NULL);
367 if (!valp) {
368 DBG("No cpu-version property !\n");
369 goto bail_noprops;
370 }
371 pvr_hi = (*valp) >> 16;
372 if (pvr_hi != 0x3c && pvr_hi != 0x44) {
373 pr_err("Unsupported CPU version\n");
374 goto bail_noprops;
375 }
376
377 /* Look for the powertune data in the device-tree */
378 g5_pmode_data = of_get_property(cpunode, "power-mode-data",&psize);
379 if (!g5_pmode_data) {
380 DBG("No power-mode-data !\n");
381 goto bail_noprops;
382 }
383 g5_pmode_max = psize / sizeof(u32) - 1;
384
385 if (use_volts_smu) {
386 const struct smu_sdbp_header *shdr;
387
388 /* Look for the FVT table */
389 shdr = smu_get_sdb_partition(SMU_SDB_FVT_ID, NULL);
390 if (!shdr)
391 goto bail_noprops;
392 g5_fvt_table = (struct smu_sdbp_fvt *)&shdr[1];
393 ssize = (shdr->len * sizeof(u32)) - sizeof(*shdr);
394 g5_fvt_count = ssize / sizeof(*g5_fvt_table);
395 g5_fvt_cur = 0;
396
397 /* Sanity checking */
398 if (g5_fvt_count < 1 || g5_pmode_max < 1)
399 goto bail_noprops;
400
401 g5_switch_volt = g5_smu_switch_volt;
402 volt_method = "SMU";
403 } else if (use_volts_vdnap) {
404 struct device_node *root;
405
406 root = of_find_node_by_path("/");
407 if (root == NULL) {
408 pr_err("Can't find root of device tree\n");
409 goto bail_noprops;
410 }
411 pfunc_set_vdnap0 = pmf_find_function(root, "set-vdnap0");
412 pfunc_vdnap0_complete =
413 pmf_find_function(root, "slewing-done");
414 if (pfunc_set_vdnap0 == NULL ||
415 pfunc_vdnap0_complete == NULL) {
416 pr_err("Can't find required platform function\n");
417 goto bail_noprops;
418 }
419
420 g5_switch_volt = g5_vdnap_switch_volt;
421 volt_method = "GPIO";
422 } else {
423 g5_switch_volt = g5_dummy_switch_volt;
424 volt_method = "none";
425 }
426
427 /*
428 * From what I see, clock-frequency is always the maximal frequency.
429 * The current driver can not slew sysclk yet, so we really only deal
430 * with powertune steps for now. We also only implement full freq and
431 * half freq in this version. So far, I haven't yet seen a machine
432 * supporting anything else.
433 */
434 valp = of_get_property(cpunode, "clock-frequency", NULL);
435 if (!valp)
436 return -ENODEV;
437 max_freq = (*valp)/1000;
438 g5_cpu_freqs[0].frequency = max_freq;
439 g5_cpu_freqs[1].frequency = max_freq/2;
440
441 /* Set callbacks */
442 transition_latency = 12000;
443 g5_switch_freq = g5_scom_switch_freq;
444 g5_query_freq = g5_scom_query_freq;
445 freq_method = "SCOM";
446
447 /* Force apply current frequency to make sure everything is in
448 * sync (voltage is right for example). Firmware may leave us with
449 * a strange setting ...
450 */
451 g5_switch_volt(CPUFREQ_HIGH);
452 msleep(10);
453 g5_pmode_cur = -1;
454 g5_switch_freq(g5_query_freq());
455
456 pr_info("Registering G5 CPU frequency driver\n");
457 pr_info("Frequency method: %s, Voltage method: %s\n",
458 freq_method, volt_method);
459 pr_info("Low: %d Mhz, High: %d Mhz, Cur: %d MHz\n",
460 g5_cpu_freqs[1].frequency/1000,
461 g5_cpu_freqs[0].frequency/1000,
462 g5_cpu_freqs[g5_pmode_cur].frequency/1000);
463
464 rc = cpufreq_register_driver(&g5_cpufreq_driver);
465
466 /* We keep the CPU node on hold... hopefully, Apple G5 don't have
467 * hotplug CPU with a dynamic device-tree ...
468 */
469 return rc;
470
471 bail_noprops:
472 of_node_put(cpunode);
473
474 return rc;
475}
476
477#endif /* CONFIG_PMAC_SMU */
478
479
480static int __init g5_pm72_cpufreq_init(struct device_node *cpunode)
481{
482 struct device_node *cpuid = NULL, *hwclock = NULL;
483 const u8 *eeprom = NULL;
484 const u32 *valp;
485 u64 max_freq, min_freq, ih, il;
486 int has_volt = 1, rc = 0;
487
488 DBG("cpufreq: Initializing for PowerMac7,2, PowerMac7,3 and"
489 " RackMac3,1...\n");
490
491 /* Lookup the cpuid eeprom node */
492 cpuid = of_find_node_by_path("/u3@0,f8000000/i2c@f8001000/cpuid@a0");
493 if (cpuid != NULL)
494 eeprom = of_get_property(cpuid, "cpuid", NULL);
495 if (eeprom == NULL) {
496 pr_err("Can't find cpuid EEPROM !\n");
497 rc = -ENODEV;
498 goto bail;
499 }
500
501 /* Lookup the i2c hwclock */
502 for_each_node_by_name(hwclock, "i2c-hwclock") {
503 const char *loc = of_get_property(hwclock,
504 "hwctrl-location", NULL);
505 if (loc == NULL)
506 continue;
507 if (strcmp(loc, "CPU CLOCK"))
508 continue;
509 if (!of_get_property(hwclock, "platform-get-frequency", NULL))
510 continue;
511 break;
512 }
513 if (hwclock == NULL) {
514 pr_err("Can't find i2c clock chip !\n");
515 rc = -ENODEV;
516 goto bail;
517 }
518
519 DBG("cpufreq: i2c clock chip found: %s\n", hwclock->full_name);
520
521 /* Now get all the platform functions */
522 pfunc_cpu_getfreq =
523 pmf_find_function(hwclock, "get-frequency");
524 pfunc_cpu_setfreq_high =
525 pmf_find_function(hwclock, "set-frequency-high");
526 pfunc_cpu_setfreq_low =
527 pmf_find_function(hwclock, "set-frequency-low");
528 pfunc_slewing_done =
529 pmf_find_function(hwclock, "slewing-done");
530 pfunc_cpu0_volt_high =
531 pmf_find_function(hwclock, "set-voltage-high-0");
532 pfunc_cpu0_volt_low =
533 pmf_find_function(hwclock, "set-voltage-low-0");
534 pfunc_cpu1_volt_high =
535 pmf_find_function(hwclock, "set-voltage-high-1");
536 pfunc_cpu1_volt_low =
537 pmf_find_function(hwclock, "set-voltage-low-1");
538
539 /* Check we have minimum requirements */
540 if (pfunc_cpu_getfreq == NULL || pfunc_cpu_setfreq_high == NULL ||
541 pfunc_cpu_setfreq_low == NULL || pfunc_slewing_done == NULL) {
542 pr_err("Can't find platform functions !\n");
543 rc = -ENODEV;
544 goto bail;
545 }
546
547 /* Check that we have complete sets */
548 if (pfunc_cpu0_volt_high == NULL || pfunc_cpu0_volt_low == NULL) {
549 pmf_put_function(pfunc_cpu0_volt_high);
550 pmf_put_function(pfunc_cpu0_volt_low);
551 pfunc_cpu0_volt_high = pfunc_cpu0_volt_low = NULL;
552 has_volt = 0;
553 }
554 if (!has_volt ||
555 pfunc_cpu1_volt_high == NULL || pfunc_cpu1_volt_low == NULL) {
556 pmf_put_function(pfunc_cpu1_volt_high);
557 pmf_put_function(pfunc_cpu1_volt_low);
558 pfunc_cpu1_volt_high = pfunc_cpu1_volt_low = NULL;
559 }
560
561 /* Note: The device tree also contains a "platform-set-values"
562 * function for which I haven't quite figured out the usage. It
563 * might have to be called on init and/or wakeup, I'm not too sure
564 * but things seem to work fine without it so far ...
565 */
566
567 /* Get max frequency from device-tree */
568 valp = of_get_property(cpunode, "clock-frequency", NULL);
569 if (!valp) {
570 pr_err("Can't find CPU frequency !\n");
571 rc = -ENODEV;
572 goto bail;
573 }
574
575 max_freq = (*valp)/1000;
576
577 /* Now calculate reduced frequency by using the cpuid input freq
578 * ratio. This requires 64 bits math unless we are willing to lose
579 * some precision
580 */
581 ih = *((u32 *)(eeprom + 0x10));
582 il = *((u32 *)(eeprom + 0x20));
583
584 /* Check for machines with no useful settings */
585 if (il == ih) {
586 pr_warn("No low frequency mode available on this model !\n");
587 rc = -ENODEV;
588 goto bail;
589 }
590
591 min_freq = 0;
592 if (ih != 0 && il != 0)
593 min_freq = (max_freq * il) / ih;
594
595 /* Sanity check */
596 if (min_freq >= max_freq || min_freq < 1000) {
597 pr_err("Can't calculate low frequency !\n");
598 rc = -ENXIO;
599 goto bail;
600 }
601 g5_cpu_freqs[0].frequency = max_freq;
602 g5_cpu_freqs[1].frequency = min_freq;
603
604 /* Based on a measurement on Xserve G5, rounded up. */
605 transition_latency = 10 * NSEC_PER_MSEC;
606
607 /* Set callbacks */
608 g5_switch_volt = g5_pfunc_switch_volt;
609 g5_switch_freq = g5_pfunc_switch_freq;
610 g5_query_freq = g5_pfunc_query_freq;
611
612 /* Force apply current frequency to make sure everything is in
613 * sync (voltage is right for example). Firmware may leave us with
614 * a strange setting ...
615 */
616 g5_switch_volt(CPUFREQ_HIGH);
617 msleep(10);
618 g5_pmode_cur = -1;
619 g5_switch_freq(g5_query_freq());
620
621 pr_info("Registering G5 CPU frequency driver\n");
622 pr_info("Frequency method: i2c/pfunc, Voltage method: %s\n",
623 has_volt ? "i2c/pfunc" : "none");
624 pr_info("Low: %d Mhz, High: %d Mhz, Cur: %d MHz\n",
625 g5_cpu_freqs[1].frequency/1000,
626 g5_cpu_freqs[0].frequency/1000,
627 g5_cpu_freqs[g5_pmode_cur].frequency/1000);
628
629 rc = cpufreq_register_driver(&g5_cpufreq_driver);
630 bail:
631 if (rc != 0) {
632 pmf_put_function(pfunc_cpu_getfreq);
633 pmf_put_function(pfunc_cpu_setfreq_high);
634 pmf_put_function(pfunc_cpu_setfreq_low);
635 pmf_put_function(pfunc_slewing_done);
636 pmf_put_function(pfunc_cpu0_volt_high);
637 pmf_put_function(pfunc_cpu0_volt_low);
638 pmf_put_function(pfunc_cpu1_volt_high);
639 pmf_put_function(pfunc_cpu1_volt_low);
640 }
641 of_node_put(hwclock);
642 of_node_put(cpuid);
643 of_node_put(cpunode);
644
645 return rc;
646}
647
648static int __init g5_cpufreq_init(void)
649{
650 struct device_node *cpunode;
651 int rc = 0;
652
653 /* Get first CPU node */
654 cpunode = of_cpu_device_node_get(0);
655 if (cpunode == NULL) {
656 pr_err("Can't find any CPU node\n");
657 return -ENODEV;
658 }
659
660 if (of_machine_is_compatible("PowerMac7,2") ||
661 of_machine_is_compatible("PowerMac7,3") ||
662 of_machine_is_compatible("RackMac3,1"))
663 rc = g5_pm72_cpufreq_init(cpunode);
664#ifdef CONFIG_PMAC_SMU
665 else
666 rc = g5_neo2_cpufreq_init(cpunode);
667#endif /* CONFIG_PMAC_SMU */
668
669 return rc;
670}
671
672module_init(g5_cpufreq_init);
673
674
675MODULE_LICENSE("GPL");