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1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Parts of this file are based on Ralink's 2.6.21 BSP
7 *
8 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
9 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
10 * Copyright (C) 2013 John Crispin <john@phrozen.org>
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/module.h>
16
17#include <asm/mipsregs.h>
18#include <asm/mach-ralink/ralink_regs.h>
19#include <asm/mach-ralink/rt305x.h>
20#include <asm/mach-ralink/pinmux.h>
21
22#include "common.h"
23
24static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
25static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
26static struct rt2880_pmx_func uartf_func[] = {
27 FUNC("uartf", RT305X_GPIO_MODE_UARTF, 7, 8),
28 FUNC("pcm uartf", RT305X_GPIO_MODE_PCM_UARTF, 7, 8),
29 FUNC("pcm i2s", RT305X_GPIO_MODE_PCM_I2S, 7, 8),
30 FUNC("i2s uartf", RT305X_GPIO_MODE_I2S_UARTF, 7, 8),
31 FUNC("pcm gpio", RT305X_GPIO_MODE_PCM_GPIO, 11, 4),
32 FUNC("gpio uartf", RT305X_GPIO_MODE_GPIO_UARTF, 7, 4),
33 FUNC("gpio i2s", RT305X_GPIO_MODE_GPIO_I2S, 7, 4),
34};
35static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) };
36static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
37static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
38static struct rt2880_pmx_func rt5350_led_func[] = { FUNC("led", 0, 22, 5) };
39static struct rt2880_pmx_func rt5350_cs1_func[] = {
40 FUNC("spi_cs1", 0, 27, 1),
41 FUNC("wdg_cs1", 1, 27, 1),
42};
43static struct rt2880_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) };
44static struct rt2880_pmx_func rt3352_rgmii_func[] = {
45 FUNC("rgmii", 0, 24, 12)
46};
47static struct rt2880_pmx_func rgmii_func[] = { FUNC("rgmii", 0, 40, 12) };
48static struct rt2880_pmx_func rt3352_lna_func[] = { FUNC("lna", 0, 36, 2) };
49static struct rt2880_pmx_func rt3352_pa_func[] = { FUNC("pa", 0, 38, 2) };
50static struct rt2880_pmx_func rt3352_led_func[] = { FUNC("led", 0, 40, 5) };
51
52static struct rt2880_pmx_group rt3050_pinmux_data[] = {
53 GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
54 GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
55 GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
56 RT305X_GPIO_MODE_UART0_SHIFT),
57 GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
58 GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
59 GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO),
60 GRP("rgmii", rgmii_func, 1, RT305X_GPIO_MODE_RGMII),
61 GRP("sdram", sdram_func, 1, RT305X_GPIO_MODE_SDRAM),
62 { 0 }
63};
64
65static struct rt2880_pmx_group rt3352_pinmux_data[] = {
66 GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
67 GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
68 GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
69 RT305X_GPIO_MODE_UART0_SHIFT),
70 GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
71 GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
72 GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO),
73 GRP("rgmii", rt3352_rgmii_func, 1, RT305X_GPIO_MODE_RGMII),
74 GRP("lna", rt3352_lna_func, 1, RT3352_GPIO_MODE_LNA),
75 GRP("pa", rt3352_pa_func, 1, RT3352_GPIO_MODE_PA),
76 GRP("led", rt3352_led_func, 1, RT5350_GPIO_MODE_PHY_LED),
77 { 0 }
78};
79
80static struct rt2880_pmx_group rt5350_pinmux_data[] = {
81 GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
82 GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
83 GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
84 RT305X_GPIO_MODE_UART0_SHIFT),
85 GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
86 GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
87 GRP("led", rt5350_led_func, 1, RT5350_GPIO_MODE_PHY_LED),
88 GRP("spi_cs1", rt5350_cs1_func, 2, RT5350_GPIO_MODE_SPI_CS1),
89 { 0 }
90};
91
92static unsigned long rt5350_get_mem_size(void)
93{
94 void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
95 unsigned long ret;
96 u32 t;
97
98 t = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG);
99 t = (t >> RT5350_SYSCFG0_DRAM_SIZE_SHIFT) &
100 RT5350_SYSCFG0_DRAM_SIZE_MASK;
101
102 switch (t) {
103 case RT5350_SYSCFG0_DRAM_SIZE_2M:
104 ret = 2;
105 break;
106 case RT5350_SYSCFG0_DRAM_SIZE_8M:
107 ret = 8;
108 break;
109 case RT5350_SYSCFG0_DRAM_SIZE_16M:
110 ret = 16;
111 break;
112 case RT5350_SYSCFG0_DRAM_SIZE_32M:
113 ret = 32;
114 break;
115 case RT5350_SYSCFG0_DRAM_SIZE_64M:
116 ret = 64;
117 break;
118 default:
119 panic("rt5350: invalid DRAM size: %u", t);
120 break;
121 }
122
123 return ret;
124}
125
126void __init ralink_clk_init(void)
127{
128 unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate;
129 unsigned long wmac_rate = 40000000;
130
131 u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
132
133 if (soc_is_rt305x() || soc_is_rt3350()) {
134 t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) &
135 RT305X_SYSCFG_CPUCLK_MASK;
136 switch (t) {
137 case RT305X_SYSCFG_CPUCLK_LOW:
138 cpu_rate = 320000000;
139 break;
140 case RT305X_SYSCFG_CPUCLK_HIGH:
141 cpu_rate = 384000000;
142 break;
143 }
144 sys_rate = uart_rate = wdt_rate = cpu_rate / 3;
145 } else if (soc_is_rt3352()) {
146 t = (t >> RT3352_SYSCFG0_CPUCLK_SHIFT) &
147 RT3352_SYSCFG0_CPUCLK_MASK;
148 switch (t) {
149 case RT3352_SYSCFG0_CPUCLK_LOW:
150 cpu_rate = 384000000;
151 break;
152 case RT3352_SYSCFG0_CPUCLK_HIGH:
153 cpu_rate = 400000000;
154 break;
155 }
156 sys_rate = wdt_rate = cpu_rate / 3;
157 uart_rate = 40000000;
158 } else if (soc_is_rt5350()) {
159 t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) &
160 RT5350_SYSCFG0_CPUCLK_MASK;
161 switch (t) {
162 case RT5350_SYSCFG0_CPUCLK_360:
163 cpu_rate = 360000000;
164 sys_rate = cpu_rate / 3;
165 break;
166 case RT5350_SYSCFG0_CPUCLK_320:
167 cpu_rate = 320000000;
168 sys_rate = cpu_rate / 4;
169 break;
170 case RT5350_SYSCFG0_CPUCLK_300:
171 cpu_rate = 300000000;
172 sys_rate = cpu_rate / 3;
173 break;
174 default:
175 BUG();
176 }
177 uart_rate = 40000000;
178 wdt_rate = sys_rate;
179 } else {
180 BUG();
181 }
182
183 if (soc_is_rt3352() || soc_is_rt5350()) {
184 u32 val = rt_sysc_r32(RT3352_SYSC_REG_SYSCFG0);
185
186 if (!(val & RT3352_CLKCFG0_XTAL_SEL))
187 wmac_rate = 20000000;
188 }
189
190 ralink_clk_add("cpu", cpu_rate);
191 ralink_clk_add("sys", sys_rate);
192 ralink_clk_add("10000b00.spi", sys_rate);
193 ralink_clk_add("10000b40.spi", sys_rate);
194 ralink_clk_add("10000100.timer", wdt_rate);
195 ralink_clk_add("10000120.watchdog", wdt_rate);
196 ralink_clk_add("10000500.uart", uart_rate);
197 ralink_clk_add("10000c00.uartlite", uart_rate);
198 ralink_clk_add("10100000.ethernet", sys_rate);
199 ralink_clk_add("10180000.wmac", wmac_rate);
200}
201
202void __init ralink_of_remap(void)
203{
204 rt_sysc_membase = plat_of_remap_node("ralink,rt3050-sysc");
205 rt_memc_membase = plat_of_remap_node("ralink,rt3050-memc");
206
207 if (!rt_sysc_membase || !rt_memc_membase)
208 panic("Failed to remap core resources");
209}
210
211void prom_soc_init(struct ralink_soc_info *soc_info)
212{
213 void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
214 unsigned char *name;
215 u32 n0;
216 u32 n1;
217 u32 id;
218
219 n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
220 n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
221
222 if (n0 == RT3052_CHIP_NAME0 && n1 == RT3052_CHIP_NAME1) {
223 unsigned long icache_sets;
224
225 icache_sets = (read_c0_config1() >> 22) & 7;
226 if (icache_sets == 1) {
227 ralink_soc = RT305X_SOC_RT3050;
228 name = "RT3050";
229 soc_info->compatible = "ralink,rt3050-soc";
230 } else {
231 ralink_soc = RT305X_SOC_RT3052;
232 name = "RT3052";
233 soc_info->compatible = "ralink,rt3052-soc";
234 }
235 } else if (n0 == RT3350_CHIP_NAME0 && n1 == RT3350_CHIP_NAME1) {
236 ralink_soc = RT305X_SOC_RT3350;
237 name = "RT3350";
238 soc_info->compatible = "ralink,rt3350-soc";
239 } else if (n0 == RT3352_CHIP_NAME0 && n1 == RT3352_CHIP_NAME1) {
240 ralink_soc = RT305X_SOC_RT3352;
241 name = "RT3352";
242 soc_info->compatible = "ralink,rt3352-soc";
243 } else if (n0 == RT5350_CHIP_NAME0 && n1 == RT5350_CHIP_NAME1) {
244 ralink_soc = RT305X_SOC_RT5350;
245 name = "RT5350";
246 soc_info->compatible = "ralink,rt5350-soc";
247 } else {
248 panic("rt305x: unknown SoC, n0:%08x n1:%08x", n0, n1);
249 }
250
251 id = __raw_readl(sysc + SYSC_REG_CHIP_ID);
252
253 snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
254 "Ralink %s id:%u rev:%u",
255 name,
256 (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
257 (id & CHIP_ID_REV_MASK));
258
259 soc_info->mem_base = RT305X_SDRAM_BASE;
260 if (soc_is_rt5350()) {
261 soc_info->mem_size = rt5350_get_mem_size();
262 rt2880_pinmux_data = rt5350_pinmux_data;
263 } else if (soc_is_rt305x() || soc_is_rt3350()) {
264 soc_info->mem_size_min = RT305X_MEM_SIZE_MIN;
265 soc_info->mem_size_max = RT305X_MEM_SIZE_MAX;
266 rt2880_pinmux_data = rt3050_pinmux_data;
267 } else if (soc_is_rt3352()) {
268 soc_info->mem_size_min = RT3352_MEM_SIZE_MIN;
269 soc_info->mem_size_max = RT3352_MEM_SIZE_MAX;
270 rt2880_pinmux_data = rt3352_pinmux_data;
271 }
272}