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1/*
2 * include/asm-mips/i8259.h
3 *
4 * i8259A interrupt definitions.
5 *
6 * Copyright (C) 2003 Maciej W. Rozycki
7 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14#ifndef _ASM_I8259_H
15#define _ASM_I8259_H
16
17#include <linux/compiler.h>
18#include <linux/spinlock.h>
19
20#include <asm/io.h>
21#include <irq.h>
22
23/* i8259A PIC registers */
24#define PIC_MASTER_CMD 0x20
25#define PIC_MASTER_IMR 0x21
26#define PIC_MASTER_ISR PIC_MASTER_CMD
27#define PIC_MASTER_POLL PIC_MASTER_ISR
28#define PIC_MASTER_OCW3 PIC_MASTER_ISR
29#define PIC_SLAVE_CMD 0xa0
30#define PIC_SLAVE_IMR 0xa1
31
32/* i8259A PIC related value */
33#define PIC_CASCADE_IR 2
34#define MASTER_ICW4_DEFAULT 0x01
35#define SLAVE_ICW4_DEFAULT 0x01
36#define PIC_ICW4_AEOI 2
37
38extern raw_spinlock_t i8259A_lock;
39
40extern int i8259A_irq_pending(unsigned int irq);
41extern void make_8259A_irq(unsigned int irq);
42
43extern void init_i8259_irqs(void);
44
45/*
46 * Do the traditional i8259 interrupt polling thing. This is for the few
47 * cases where no better interrupt acknowledge method is available and we
48 * absolutely must touch the i8259.
49 */
50static inline int i8259_irq(void)
51{
52 int irq;
53
54 raw_spin_lock(&i8259A_lock);
55
56 /* Perform an interrupt acknowledge cycle on controller 1. */
57 outb(0x0C, PIC_MASTER_CMD); /* prepare for poll */
58 irq = inb(PIC_MASTER_CMD) & 7;
59 if (irq == PIC_CASCADE_IR) {
60 /*
61 * Interrupt is cascaded so perform interrupt
62 * acknowledge on controller 2.
63 */
64 outb(0x0C, PIC_SLAVE_CMD); /* prepare for poll */
65 irq = (inb(PIC_SLAVE_CMD) & 7) + 8;
66 }
67
68 if (unlikely(irq == 7)) {
69 /*
70 * This may be a spurious interrupt.
71 *
72 * Read the interrupt status register (ISR). If the most
73 * significant bit is not set then there is no valid
74 * interrupt.
75 */
76 outb(0x0B, PIC_MASTER_ISR); /* ISR register */
77 if(~inb(PIC_MASTER_ISR) & 0x80)
78 irq = -1;
79 }
80
81 raw_spin_unlock(&i8259A_lock);
82
83 return likely(irq >= 0) ? irq + I8259A_IRQ_BASE : irq;
84}
85
86#endif /* _ASM_I8259_H */
1/*
2 * include/asm-mips/i8259.h
3 *
4 * i8259A interrupt definitions.
5 *
6 * Copyright (C) 2003 Maciej W. Rozycki
7 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14#ifndef _ASM_I8259_H
15#define _ASM_I8259_H
16
17#include <linux/compiler.h>
18#include <linux/spinlock.h>
19
20#include <asm/io.h>
21#include <irq.h>
22
23/* i8259A PIC registers */
24#define PIC_MASTER_CMD 0x20
25#define PIC_MASTER_IMR 0x21
26#define PIC_MASTER_ISR PIC_MASTER_CMD
27#define PIC_MASTER_POLL PIC_MASTER_ISR
28#define PIC_MASTER_OCW3 PIC_MASTER_ISR
29#define PIC_SLAVE_CMD 0xa0
30#define PIC_SLAVE_IMR 0xa1
31
32/* i8259A PIC related value */
33#define PIC_CASCADE_IR 2
34#define MASTER_ICW4_DEFAULT 0x01
35#define SLAVE_ICW4_DEFAULT 0x01
36#define PIC_ICW4_AEOI 2
37
38extern raw_spinlock_t i8259A_lock;
39
40extern void make_8259A_irq(unsigned int irq);
41
42extern void init_i8259_irqs(void);
43extern int i8259_of_init(struct device_node *node, struct device_node *parent);
44
45/**
46 * i8159_set_poll() - Override the i8259 polling function
47 * @poll: pointer to platform-specific polling function
48 *
49 * Call this to override the generic i8259 polling function, which directly
50 * accesses i8259 registers, with a platform specific one which may be faster
51 * in cases where hardware provides a more optimal means of polling for an
52 * interrupt.
53 */
54extern void i8259_set_poll(int (*poll)(void));
55
56/*
57 * Do the traditional i8259 interrupt polling thing. This is for the few
58 * cases where no better interrupt acknowledge method is available and we
59 * absolutely must touch the i8259.
60 */
61static inline int i8259_irq(void)
62{
63 int irq;
64
65 raw_spin_lock(&i8259A_lock);
66
67 /* Perform an interrupt acknowledge cycle on controller 1. */
68 outb(0x0C, PIC_MASTER_CMD); /* prepare for poll */
69 irq = inb(PIC_MASTER_CMD) & 7;
70 if (irq == PIC_CASCADE_IR) {
71 /*
72 * Interrupt is cascaded so perform interrupt
73 * acknowledge on controller 2.
74 */
75 outb(0x0C, PIC_SLAVE_CMD); /* prepare for poll */
76 irq = (inb(PIC_SLAVE_CMD) & 7) + 8;
77 }
78
79 if (unlikely(irq == 7)) {
80 /*
81 * This may be a spurious interrupt.
82 *
83 * Read the interrupt status register (ISR). If the most
84 * significant bit is not set then there is no valid
85 * interrupt.
86 */
87 outb(0x0B, PIC_MASTER_ISR); /* ISR register */
88 if(~inb(PIC_MASTER_ISR) & 0x80)
89 irq = -1;
90 }
91
92 raw_spin_unlock(&i8259A_lock);
93
94 return likely(irq >= 0) ? irq + I8259A_IRQ_BASE : irq;
95}
96
97#endif /* _ASM_I8259_H */