1/*
 2 * Common defines for v7m cpus
 3 */
 4#define V7M_SCS_ICTR			IOMEM(0xe000e004)
 5#define V7M_SCS_ICTR_INTLINESNUM_MASK		0x0000000f
 6
 7#define BASEADDR_V7M_SCB		IOMEM(0xe000ed00)
 8
 9#define V7M_SCB_CPUID			0x00
10
11#define V7M_SCB_ICSR			0x04
12#define V7M_SCB_ICSR_PENDSVSET			(1 << 28)
13#define V7M_SCB_ICSR_PENDSVCLR			(1 << 27)
14#define V7M_SCB_ICSR_RETTOBASE			(1 << 11)
15
16#define V7M_SCB_VTOR			0x08
17
18#define V7M_SCB_AIRCR			0x0c
19#define V7M_SCB_AIRCR_VECTKEY			(0x05fa << 16)
20#define V7M_SCB_AIRCR_SYSRESETREQ		(1 << 2)
21
22#define V7M_SCB_SCR			0x10
23#define V7M_SCB_SCR_SLEEPDEEP			(1 << 2)
24
25#define V7M_SCB_CCR			0x14
26#define V7M_SCB_CCR_STKALIGN			(1 << 9)
27#define V7M_SCB_CCR_DC				(1 << 16)
28#define V7M_SCB_CCR_IC				(1 << 17)
29#define V7M_SCB_CCR_BP				(1 << 18)
30
31#define V7M_SCB_SHPR2			0x1c
32#define V7M_SCB_SHPR3			0x20
33
34#define V7M_SCB_SHCSR			0x24
35#define V7M_SCB_SHCSR_USGFAULTENA		(1 << 18)
36#define V7M_SCB_SHCSR_BUSFAULTENA		(1 << 17)
37#define V7M_SCB_SHCSR_MEMFAULTENA		(1 << 16)
38
39#define V7M_xPSR_FRAMEPTRALIGN			0x00000200
40#define V7M_xPSR_EXCEPTIONNO			0x000001ff
41
42/*
43 * When branching to an address that has bits [31:28] == 0xf an exception return
44 * occurs. Bits [27:5] are reserved (SBOP). If the processor implements the FP
45 * extension Bit [4] defines if the exception frame has space allocated for FP
46 * state information, SBOP otherwise. Bit [3] defines the mode that is returned
47 * to (0 -> handler mode; 1 -> thread mode). Bit [2] defines which sp is used
48 * (0 -> msp; 1 -> psp). Bits [1:0] are fixed to 0b01.
49 */
50#define EXC_RET_STACK_MASK			0x00000004
51#define EXC_RET_THREADMODE_PROCESSSTACK		0xfffffffd
52
53/* Cache related definitions */
54
55#define	V7M_SCB_CLIDR		0x78	/* Cache Level ID register */
56#define	V7M_SCB_CTR		0x7c	/* Cache Type register */
57#define	V7M_SCB_CCSIDR		0x80	/* Cache size ID register */
58#define	V7M_SCB_CSSELR		0x84	/* Cache size selection register */
59
60/* Cache opeartions */
61#define	V7M_SCB_ICIALLU		0x250	/* I-cache invalidate all to PoU */
62#define	V7M_SCB_ICIMVAU		0x258	/* I-cache invalidate by MVA to PoU */
63#define	V7M_SCB_DCIMVAC		0x25c	/* D-cache invalidate by MVA to PoC */
64#define	V7M_SCB_DCISW		0x260	/* D-cache invalidate by set-way */
65#define	V7M_SCB_DCCMVAU		0x264	/* D-cache clean by MVA to PoU */
66#define	V7M_SCB_DCCMVAC		0x268	/* D-cache clean by MVA to PoC */
67#define	V7M_SCB_DCCSW		0x26c	/* D-cache clean by set-way */
68#define	V7M_SCB_DCCIMVAC	0x270	/* D-cache clean and invalidate by MVA to PoC */
69#define	V7M_SCB_DCCISW		0x274	/* D-cache clean and invalidate by set-way */
70#define	V7M_SCB_BPIALL		0x278	/* D-cache clean and invalidate by set-way */
71
72#ifndef __ASSEMBLY__
73
74enum reboot_mode;
75
76void armv7m_restart(enum reboot_mode mode, const char *cmd);
77
78#endif /* __ASSEMBLY__ */