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1/*
2 * Copyright (C) 2005-2006 by Texas Instruments
3 *
4 * This file is part of the Inventra Controller Driver for Linux.
5 *
6 * The Inventra Controller Driver for Linux is free software; you
7 * can redistribute it and/or modify it under the terms of the GNU
8 * General Public License version 2 as published by the Free Software
9 * Foundation.
10 *
11 * The Inventra Controller Driver for Linux is distributed in
12 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
13 * without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 * License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with The Inventra Controller Driver for Linux ; if not,
19 * write to the Free Software Foundation, Inc., 59 Temple Place,
20 * Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24#include <linux/module.h>
25#include <linux/kernel.h>
26#include <linux/sched.h>
27#include <linux/init.h>
28#include <linux/list.h>
29#include <linux/delay.h>
30#include <linux/clk.h>
31#include <linux/io.h>
32#include <linux/gpio.h>
33#include <linux/platform_device.h>
34#include <linux/dma-mapping.h>
35
36#include <mach/hardware.h>
37#include <mach/memory.h>
38#include <mach/gpio.h>
39#include <mach/cputype.h>
40
41#include <asm/mach-types.h>
42
43#include "musb_core.h"
44
45#ifdef CONFIG_MACH_DAVINCI_EVM
46#define GPIO_nVBUS_DRV 160
47#endif
48
49#include "davinci.h"
50#include "cppi_dma.h"
51
52
53#define USB_PHY_CTRL IO_ADDRESS(USBPHY_CTL_PADDR)
54#define DM355_DEEPSLEEP IO_ADDRESS(DM355_DEEPSLEEP_PADDR)
55
56struct davinci_glue {
57 struct device *dev;
58 struct platform_device *musb;
59 struct clk *clk;
60};
61
62/* REVISIT (PM) we should be able to keep the PHY in low power mode most
63 * of the time (24 MHZ oscillator and PLL off, etc) by setting POWER.D0
64 * and, when in host mode, autosuspending idle root ports... PHYPLLON
65 * (overriding SUSPENDM?) then likely needs to stay off.
66 */
67
68static inline void phy_on(void)
69{
70 u32 phy_ctrl = __raw_readl(USB_PHY_CTRL);
71
72 /* power everything up; start the on-chip PHY and its PLL */
73 phy_ctrl &= ~(USBPHY_OSCPDWN | USBPHY_OTGPDWN | USBPHY_PHYPDWN);
74 phy_ctrl |= USBPHY_SESNDEN | USBPHY_VBDTCTEN | USBPHY_PHYPLLON;
75 __raw_writel(phy_ctrl, USB_PHY_CTRL);
76
77 /* wait for PLL to lock before proceeding */
78 while ((__raw_readl(USB_PHY_CTRL) & USBPHY_PHYCLKGD) == 0)
79 cpu_relax();
80}
81
82static inline void phy_off(void)
83{
84 u32 phy_ctrl = __raw_readl(USB_PHY_CTRL);
85
86 /* powerdown the on-chip PHY, its PLL, and the OTG block */
87 phy_ctrl &= ~(USBPHY_SESNDEN | USBPHY_VBDTCTEN | USBPHY_PHYPLLON);
88 phy_ctrl |= USBPHY_OSCPDWN | USBPHY_OTGPDWN | USBPHY_PHYPDWN;
89 __raw_writel(phy_ctrl, USB_PHY_CTRL);
90}
91
92static int dma_off = 1;
93
94static void davinci_musb_enable(struct musb *musb)
95{
96 u32 tmp, old, val;
97
98 /* workaround: setup irqs through both register sets */
99 tmp = (musb->epmask & DAVINCI_USB_TX_ENDPTS_MASK)
100 << DAVINCI_USB_TXINT_SHIFT;
101 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
102 old = tmp;
103 tmp = (musb->epmask & (0xfffe & DAVINCI_USB_RX_ENDPTS_MASK))
104 << DAVINCI_USB_RXINT_SHIFT;
105 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
106 tmp |= old;
107
108 val = ~MUSB_INTR_SOF;
109 tmp |= ((val & 0x01ff) << DAVINCI_USB_USBINT_SHIFT);
110 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
111
112 if (is_dma_capable() && !dma_off)
113 printk(KERN_WARNING "%s %s: dma not reactivated\n",
114 __FILE__, __func__);
115 else
116 dma_off = 0;
117
118 /* force a DRVVBUS irq so we can start polling for ID change */
119 if (is_otg_enabled(musb))
120 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG,
121 DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT);
122}
123
124/*
125 * Disable the HDRC and flush interrupts
126 */
127static void davinci_musb_disable(struct musb *musb)
128{
129 /* because we don't set CTRLR.UINT, "important" to:
130 * - not read/write INTRUSB/INTRUSBE
131 * - (except during initial setup, as workaround)
132 * - use INTSETR/INTCLRR instead
133 */
134 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_CLR_REG,
135 DAVINCI_USB_USBINT_MASK
136 | DAVINCI_USB_TXINT_MASK
137 | DAVINCI_USB_RXINT_MASK);
138 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
139 musb_writel(musb->ctrl_base, DAVINCI_USB_EOI_REG, 0);
140
141 if (is_dma_capable() && !dma_off)
142 WARNING("dma still active\n");
143}
144
145
146#define portstate(stmt) stmt
147
148/*
149 * VBUS SWITCHING IS BOARD-SPECIFIC ... at least for the DM6446 EVM,
150 * which doesn't wire DRVVBUS to the FET that switches it. Unclear
151 * if that's a problem with the DM6446 chip or just with that board.
152 *
153 * In either case, the DM355 EVM automates DRVVBUS the normal way,
154 * when J10 is out, and TI documents it as handling OTG.
155 */
156
157#ifdef CONFIG_MACH_DAVINCI_EVM
158
159static int vbus_state = -1;
160
161/* I2C operations are always synchronous, and require a task context.
162 * With unloaded systems, using the shared workqueue seems to suffice
163 * to satisfy the 100msec A_WAIT_VRISE timeout...
164 */
165static void evm_deferred_drvvbus(struct work_struct *ignored)
166{
167 gpio_set_value_cansleep(GPIO_nVBUS_DRV, vbus_state);
168 vbus_state = !vbus_state;
169}
170
171#endif /* EVM */
172
173static void davinci_musb_source_power(struct musb *musb, int is_on, int immediate)
174{
175#ifdef CONFIG_MACH_DAVINCI_EVM
176 if (is_on)
177 is_on = 1;
178
179 if (vbus_state == is_on)
180 return;
181 vbus_state = !is_on; /* 0/1 vs "-1 == unknown/init" */
182
183 if (machine_is_davinci_evm()) {
184 static DECLARE_WORK(evm_vbus_work, evm_deferred_drvvbus);
185
186 if (immediate)
187 gpio_set_value_cansleep(GPIO_nVBUS_DRV, vbus_state);
188 else
189 schedule_work(&evm_vbus_work);
190 }
191 if (immediate)
192 vbus_state = is_on;
193#endif
194}
195
196static void davinci_musb_set_vbus(struct musb *musb, int is_on)
197{
198 WARN_ON(is_on && is_peripheral_active(musb));
199 davinci_musb_source_power(musb, is_on, 0);
200}
201
202
203#define POLL_SECONDS 2
204
205static struct timer_list otg_workaround;
206
207static void otg_timer(unsigned long _musb)
208{
209 struct musb *musb = (void *)_musb;
210 void __iomem *mregs = musb->mregs;
211 u8 devctl;
212 unsigned long flags;
213
214 /* We poll because DaVinci's won't expose several OTG-critical
215 * status change events (from the transceiver) otherwise.
216 */
217 devctl = musb_readb(mregs, MUSB_DEVCTL);
218 dev_dbg(musb->controller, "poll devctl %02x (%s)\n", devctl,
219 otg_state_string(musb->xceiv->state));
220
221 spin_lock_irqsave(&musb->lock, flags);
222 switch (musb->xceiv->state) {
223 case OTG_STATE_A_WAIT_VFALL:
224 /* Wait till VBUS falls below SessionEnd (~0.2V); the 1.3 RTL
225 * seems to mis-handle session "start" otherwise (or in our
226 * case "recover"), in routine "VBUS was valid by the time
227 * VBUSERR got reported during enumeration" cases.
228 */
229 if (devctl & MUSB_DEVCTL_VBUS) {
230 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
231 break;
232 }
233 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
234 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG,
235 MUSB_INTR_VBUSERROR << DAVINCI_USB_USBINT_SHIFT);
236 break;
237 case OTG_STATE_B_IDLE:
238 if (!is_peripheral_enabled(musb))
239 break;
240
241 /* There's no ID-changed IRQ, so we have no good way to tell
242 * when to switch to the A-Default state machine (by setting
243 * the DEVCTL.SESSION flag).
244 *
245 * Workaround: whenever we're in B_IDLE, try setting the
246 * session flag every few seconds. If it works, ID was
247 * grounded and we're now in the A-Default state machine.
248 *
249 * NOTE setting the session flag is _supposed_ to trigger
250 * SRP, but clearly it doesn't.
251 */
252 musb_writeb(mregs, MUSB_DEVCTL,
253 devctl | MUSB_DEVCTL_SESSION);
254 devctl = musb_readb(mregs, MUSB_DEVCTL);
255 if (devctl & MUSB_DEVCTL_BDEVICE)
256 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
257 else
258 musb->xceiv->state = OTG_STATE_A_IDLE;
259 break;
260 default:
261 break;
262 }
263 spin_unlock_irqrestore(&musb->lock, flags);
264}
265
266static irqreturn_t davinci_musb_interrupt(int irq, void *__hci)
267{
268 unsigned long flags;
269 irqreturn_t retval = IRQ_NONE;
270 struct musb *musb = __hci;
271 void __iomem *tibase = musb->ctrl_base;
272 struct cppi *cppi;
273 u32 tmp;
274
275 spin_lock_irqsave(&musb->lock, flags);
276
277 /* NOTE: DaVinci shadows the Mentor IRQs. Don't manage them through
278 * the Mentor registers (except for setup), use the TI ones and EOI.
279 *
280 * Docs describe irq "vector" registers associated with the CPPI and
281 * USB EOI registers. These hold a bitmask corresponding to the
282 * current IRQ, not an irq handler address. Would using those bits
283 * resolve some of the races observed in this dispatch code??
284 */
285
286 /* CPPI interrupts share the same IRQ line, but have their own
287 * mask, state, "vector", and EOI registers.
288 */
289 cppi = container_of(musb->dma_controller, struct cppi, controller);
290 if (is_cppi_enabled() && musb->dma_controller && !cppi->irq)
291 retval = cppi_interrupt(irq, __hci);
292
293 /* ack and handle non-CPPI interrupts */
294 tmp = musb_readl(tibase, DAVINCI_USB_INT_SRC_MASKED_REG);
295 musb_writel(tibase, DAVINCI_USB_INT_SRC_CLR_REG, tmp);
296 dev_dbg(musb->controller, "IRQ %08x\n", tmp);
297
298 musb->int_rx = (tmp & DAVINCI_USB_RXINT_MASK)
299 >> DAVINCI_USB_RXINT_SHIFT;
300 musb->int_tx = (tmp & DAVINCI_USB_TXINT_MASK)
301 >> DAVINCI_USB_TXINT_SHIFT;
302 musb->int_usb = (tmp & DAVINCI_USB_USBINT_MASK)
303 >> DAVINCI_USB_USBINT_SHIFT;
304
305 /* DRVVBUS irqs are the only proxy we have (a very poor one!) for
306 * DaVinci's missing ID change IRQ. We need an ID change IRQ to
307 * switch appropriately between halves of the OTG state machine.
308 * Managing DEVCTL.SESSION per Mentor docs requires we know its
309 * value, but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
310 * Also, DRVVBUS pulses for SRP (but not at 5V) ...
311 */
312 if (tmp & (DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT)) {
313 int drvvbus = musb_readl(tibase, DAVINCI_USB_STAT_REG);
314 void __iomem *mregs = musb->mregs;
315 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
316 int err = musb->int_usb & MUSB_INTR_VBUSERROR;
317
318 err = is_host_enabled(musb)
319 && (musb->int_usb & MUSB_INTR_VBUSERROR);
320 if (err) {
321 /* The Mentor core doesn't debounce VBUS as needed
322 * to cope with device connect current spikes. This
323 * means it's not uncommon for bus-powered devices
324 * to get VBUS errors during enumeration.
325 *
326 * This is a workaround, but newer RTL from Mentor
327 * seems to allow a better one: "re"starting sessions
328 * without waiting (on EVM, a **long** time) for VBUS
329 * to stop registering in devctl.
330 */
331 musb->int_usb &= ~MUSB_INTR_VBUSERROR;
332 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
333 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
334 WARNING("VBUS error workaround (delay coming)\n");
335 } else if (is_host_enabled(musb) && drvvbus) {
336 MUSB_HST_MODE(musb);
337 musb->xceiv->default_a = 1;
338 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
339 portstate(musb->port1_status |= USB_PORT_STAT_POWER);
340 del_timer(&otg_workaround);
341 } else {
342 musb->is_active = 0;
343 MUSB_DEV_MODE(musb);
344 musb->xceiv->default_a = 0;
345 musb->xceiv->state = OTG_STATE_B_IDLE;
346 portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
347 }
348
349 /* NOTE: this must complete poweron within 100 msec
350 * (OTG_TIME_A_WAIT_VRISE) but we don't check for that.
351 */
352 davinci_musb_source_power(musb, drvvbus, 0);
353 dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
354 drvvbus ? "on" : "off",
355 otg_state_string(musb->xceiv->state),
356 err ? " ERROR" : "",
357 devctl);
358 retval = IRQ_HANDLED;
359 }
360
361 if (musb->int_tx || musb->int_rx || musb->int_usb)
362 retval |= musb_interrupt(musb);
363
364 /* irq stays asserted until EOI is written */
365 musb_writel(tibase, DAVINCI_USB_EOI_REG, 0);
366
367 /* poll for ID change */
368 if (is_otg_enabled(musb)
369 && musb->xceiv->state == OTG_STATE_B_IDLE)
370 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
371
372 spin_unlock_irqrestore(&musb->lock, flags);
373
374 return retval;
375}
376
377static int davinci_musb_set_mode(struct musb *musb, u8 mode)
378{
379 /* EVM can't do this (right?) */
380 return -EIO;
381}
382
383static int davinci_musb_init(struct musb *musb)
384{
385 void __iomem *tibase = musb->ctrl_base;
386 u32 revision;
387
388 usb_nop_xceiv_register();
389 musb->xceiv = otg_get_transceiver();
390 if (!musb->xceiv)
391 return -ENODEV;
392
393 musb->mregs += DAVINCI_BASE_OFFSET;
394
395 /* returns zero if e.g. not clocked */
396 revision = musb_readl(tibase, DAVINCI_USB_VERSION_REG);
397 if (revision == 0)
398 goto fail;
399
400 if (is_host_enabled(musb))
401 setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
402
403 davinci_musb_source_power(musb, 0, 1);
404
405 /* dm355 EVM swaps D+/D- for signal integrity, and
406 * is clocked from the main 24 MHz crystal.
407 */
408 if (machine_is_davinci_dm355_evm()) {
409 u32 phy_ctrl = __raw_readl(USB_PHY_CTRL);
410
411 phy_ctrl &= ~(3 << 9);
412 phy_ctrl |= USBPHY_DATAPOL;
413 __raw_writel(phy_ctrl, USB_PHY_CTRL);
414 }
415
416 /* On dm355, the default-A state machine needs DRVVBUS control.
417 * If we won't be a host, there's no need to turn it on.
418 */
419 if (cpu_is_davinci_dm355()) {
420 u32 deepsleep = __raw_readl(DM355_DEEPSLEEP);
421
422 if (is_host_enabled(musb)) {
423 deepsleep &= ~DRVVBUS_OVERRIDE;
424 } else {
425 deepsleep &= ~DRVVBUS_FORCE;
426 deepsleep |= DRVVBUS_OVERRIDE;
427 }
428 __raw_writel(deepsleep, DM355_DEEPSLEEP);
429 }
430
431 /* reset the controller */
432 musb_writel(tibase, DAVINCI_USB_CTRL_REG, 0x1);
433
434 /* start the on-chip PHY and its PLL */
435 phy_on();
436
437 msleep(5);
438
439 /* NOTE: irqs are in mixed mode, not bypass to pure-musb */
440 pr_debug("DaVinci OTG revision %08x phy %03x control %02x\n",
441 revision, __raw_readl(USB_PHY_CTRL),
442 musb_readb(tibase, DAVINCI_USB_CTRL_REG));
443
444 musb->isr = davinci_musb_interrupt;
445 return 0;
446
447fail:
448 otg_put_transceiver(musb->xceiv);
449 usb_nop_xceiv_unregister();
450 return -ENODEV;
451}
452
453static int davinci_musb_exit(struct musb *musb)
454{
455 if (is_host_enabled(musb))
456 del_timer_sync(&otg_workaround);
457
458 /* force VBUS off */
459 if (cpu_is_davinci_dm355()) {
460 u32 deepsleep = __raw_readl(DM355_DEEPSLEEP);
461
462 deepsleep &= ~DRVVBUS_FORCE;
463 deepsleep |= DRVVBUS_OVERRIDE;
464 __raw_writel(deepsleep, DM355_DEEPSLEEP);
465 }
466
467 davinci_musb_source_power(musb, 0 /*off*/, 1);
468
469 /* delay, to avoid problems with module reload */
470 if (is_host_enabled(musb) && musb->xceiv->default_a) {
471 int maxdelay = 30;
472 u8 devctl, warn = 0;
473
474 /* if there's no peripheral connected, this can take a
475 * long time to fall, especially on EVM with huge C133.
476 */
477 do {
478 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
479 if (!(devctl & MUSB_DEVCTL_VBUS))
480 break;
481 if ((devctl & MUSB_DEVCTL_VBUS) != warn) {
482 warn = devctl & MUSB_DEVCTL_VBUS;
483 dev_dbg(musb->controller, "VBUS %d\n",
484 warn >> MUSB_DEVCTL_VBUS_SHIFT);
485 }
486 msleep(1000);
487 maxdelay--;
488 } while (maxdelay > 0);
489
490 /* in OTG mode, another host might be connected */
491 if (devctl & MUSB_DEVCTL_VBUS)
492 dev_dbg(musb->controller, "VBUS off timeout (devctl %02x)\n", devctl);
493 }
494
495 phy_off();
496
497 otg_put_transceiver(musb->xceiv);
498 usb_nop_xceiv_unregister();
499
500 return 0;
501}
502
503static const struct musb_platform_ops davinci_ops = {
504 .init = davinci_musb_init,
505 .exit = davinci_musb_exit,
506
507 .enable = davinci_musb_enable,
508 .disable = davinci_musb_disable,
509
510 .set_mode = davinci_musb_set_mode,
511
512 .set_vbus = davinci_musb_set_vbus,
513};
514
515static u64 davinci_dmamask = DMA_BIT_MASK(32);
516
517static int __init davinci_probe(struct platform_device *pdev)
518{
519 struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data;
520 struct platform_device *musb;
521 struct davinci_glue *glue;
522 struct clk *clk;
523
524 int ret = -ENOMEM;
525
526 glue = kzalloc(sizeof(*glue), GFP_KERNEL);
527 if (!glue) {
528 dev_err(&pdev->dev, "failed to allocate glue context\n");
529 goto err0;
530 }
531
532 musb = platform_device_alloc("musb-hdrc", -1);
533 if (!musb) {
534 dev_err(&pdev->dev, "failed to allocate musb device\n");
535 goto err1;
536 }
537
538 clk = clk_get(&pdev->dev, "usb");
539 if (IS_ERR(clk)) {
540 dev_err(&pdev->dev, "failed to get clock\n");
541 ret = PTR_ERR(clk);
542 goto err2;
543 }
544
545 ret = clk_enable(clk);
546 if (ret) {
547 dev_err(&pdev->dev, "failed to enable clock\n");
548 goto err3;
549 }
550
551 musb->dev.parent = &pdev->dev;
552 musb->dev.dma_mask = &davinci_dmamask;
553 musb->dev.coherent_dma_mask = davinci_dmamask;
554
555 glue->dev = &pdev->dev;
556 glue->musb = musb;
557 glue->clk = clk;
558
559 pdata->platform_ops = &davinci_ops;
560
561 platform_set_drvdata(pdev, glue);
562
563 ret = platform_device_add_resources(musb, pdev->resource,
564 pdev->num_resources);
565 if (ret) {
566 dev_err(&pdev->dev, "failed to add resources\n");
567 goto err4;
568 }
569
570 ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
571 if (ret) {
572 dev_err(&pdev->dev, "failed to add platform_data\n");
573 goto err4;
574 }
575
576 ret = platform_device_add(musb);
577 if (ret) {
578 dev_err(&pdev->dev, "failed to register musb device\n");
579 goto err4;
580 }
581
582 return 0;
583
584err4:
585 clk_disable(clk);
586
587err3:
588 clk_put(clk);
589
590err2:
591 platform_device_put(musb);
592
593err1:
594 kfree(glue);
595
596err0:
597 return ret;
598}
599
600static int __exit davinci_remove(struct platform_device *pdev)
601{
602 struct davinci_glue *glue = platform_get_drvdata(pdev);
603
604 platform_device_del(glue->musb);
605 platform_device_put(glue->musb);
606 clk_disable(glue->clk);
607 clk_put(glue->clk);
608 kfree(glue);
609
610 return 0;
611}
612
613static struct platform_driver davinci_driver = {
614 .remove = __exit_p(davinci_remove),
615 .driver = {
616 .name = "musb-davinci",
617 },
618};
619
620MODULE_DESCRIPTION("DaVinci MUSB Glue Layer");
621MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
622MODULE_LICENSE("GPL v2");
623
624static int __init davinci_init(void)
625{
626 return platform_driver_probe(&davinci_driver, davinci_probe);
627}
628subsys_initcall(davinci_init);
629
630static void __exit davinci_exit(void)
631{
632 platform_driver_unregister(&davinci_driver);
633}
634module_exit(davinci_exit);
1/*
2 * Copyright (C) 2005-2006 by Texas Instruments
3 *
4 * This file is part of the Inventra Controller Driver for Linux.
5 *
6 * The Inventra Controller Driver for Linux is free software; you
7 * can redistribute it and/or modify it under the terms of the GNU
8 * General Public License version 2 as published by the Free Software
9 * Foundation.
10 *
11 * The Inventra Controller Driver for Linux is distributed in
12 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
13 * without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 * License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with The Inventra Controller Driver for Linux ; if not,
19 * write to the Free Software Foundation, Inc., 59 Temple Place,
20 * Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24#include <linux/module.h>
25#include <linux/kernel.h>
26#include <linux/sched.h>
27#include <linux/init.h>
28#include <linux/list.h>
29#include <linux/delay.h>
30#include <linux/clk.h>
31#include <linux/io.h>
32#include <linux/gpio.h>
33#include <linux/platform_device.h>
34#include <linux/dma-mapping.h>
35
36#include <mach/cputype.h>
37#include <mach/hardware.h>
38
39#include <asm/mach-types.h>
40
41#include "musb_core.h"
42
43#ifdef CONFIG_MACH_DAVINCI_EVM
44#define GPIO_nVBUS_DRV 160
45#endif
46
47#include "davinci.h"
48#include "cppi_dma.h"
49
50
51#define USB_PHY_CTRL IO_ADDRESS(USBPHY_CTL_PADDR)
52#define DM355_DEEPSLEEP IO_ADDRESS(DM355_DEEPSLEEP_PADDR)
53
54struct davinci_glue {
55 struct device *dev;
56 struct platform_device *musb;
57 struct clk *clk;
58};
59
60/* REVISIT (PM) we should be able to keep the PHY in low power mode most
61 * of the time (24 MHZ oscillator and PLL off, etc) by setting POWER.D0
62 * and, when in host mode, autosuspending idle root ports... PHYPLLON
63 * (overriding SUSPENDM?) then likely needs to stay off.
64 */
65
66static inline void phy_on(void)
67{
68 u32 phy_ctrl = __raw_readl(USB_PHY_CTRL);
69
70 /* power everything up; start the on-chip PHY and its PLL */
71 phy_ctrl &= ~(USBPHY_OSCPDWN | USBPHY_OTGPDWN | USBPHY_PHYPDWN);
72 phy_ctrl |= USBPHY_SESNDEN | USBPHY_VBDTCTEN | USBPHY_PHYPLLON;
73 __raw_writel(phy_ctrl, USB_PHY_CTRL);
74
75 /* wait for PLL to lock before proceeding */
76 while ((__raw_readl(USB_PHY_CTRL) & USBPHY_PHYCLKGD) == 0)
77 cpu_relax();
78}
79
80static inline void phy_off(void)
81{
82 u32 phy_ctrl = __raw_readl(USB_PHY_CTRL);
83
84 /* powerdown the on-chip PHY, its PLL, and the OTG block */
85 phy_ctrl &= ~(USBPHY_SESNDEN | USBPHY_VBDTCTEN | USBPHY_PHYPLLON);
86 phy_ctrl |= USBPHY_OSCPDWN | USBPHY_OTGPDWN | USBPHY_PHYPDWN;
87 __raw_writel(phy_ctrl, USB_PHY_CTRL);
88}
89
90static int dma_off = 1;
91
92static void davinci_musb_enable(struct musb *musb)
93{
94 u32 tmp, old, val;
95
96 /* workaround: setup irqs through both register sets */
97 tmp = (musb->epmask & DAVINCI_USB_TX_ENDPTS_MASK)
98 << DAVINCI_USB_TXINT_SHIFT;
99 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
100 old = tmp;
101 tmp = (musb->epmask & (0xfffe & DAVINCI_USB_RX_ENDPTS_MASK))
102 << DAVINCI_USB_RXINT_SHIFT;
103 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
104 tmp |= old;
105
106 val = ~MUSB_INTR_SOF;
107 tmp |= ((val & 0x01ff) << DAVINCI_USB_USBINT_SHIFT);
108 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
109
110 if (is_dma_capable() && !dma_off)
111 printk(KERN_WARNING "%s %s: dma not reactivated\n",
112 __FILE__, __func__);
113 else
114 dma_off = 0;
115
116 /* force a DRVVBUS irq so we can start polling for ID change */
117 if (is_otg_enabled(musb))
118 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG,
119 DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT);
120}
121
122/*
123 * Disable the HDRC and flush interrupts
124 */
125static void davinci_musb_disable(struct musb *musb)
126{
127 /* because we don't set CTRLR.UINT, "important" to:
128 * - not read/write INTRUSB/INTRUSBE
129 * - (except during initial setup, as workaround)
130 * - use INTSETR/INTCLRR instead
131 */
132 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_CLR_REG,
133 DAVINCI_USB_USBINT_MASK
134 | DAVINCI_USB_TXINT_MASK
135 | DAVINCI_USB_RXINT_MASK);
136 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
137 musb_writel(musb->ctrl_base, DAVINCI_USB_EOI_REG, 0);
138
139 if (is_dma_capable() && !dma_off)
140 WARNING("dma still active\n");
141}
142
143
144#define portstate(stmt) stmt
145
146/*
147 * VBUS SWITCHING IS BOARD-SPECIFIC ... at least for the DM6446 EVM,
148 * which doesn't wire DRVVBUS to the FET that switches it. Unclear
149 * if that's a problem with the DM6446 chip or just with that board.
150 *
151 * In either case, the DM355 EVM automates DRVVBUS the normal way,
152 * when J10 is out, and TI documents it as handling OTG.
153 */
154
155#ifdef CONFIG_MACH_DAVINCI_EVM
156
157static int vbus_state = -1;
158
159/* I2C operations are always synchronous, and require a task context.
160 * With unloaded systems, using the shared workqueue seems to suffice
161 * to satisfy the 100msec A_WAIT_VRISE timeout...
162 */
163static void evm_deferred_drvvbus(struct work_struct *ignored)
164{
165 gpio_set_value_cansleep(GPIO_nVBUS_DRV, vbus_state);
166 vbus_state = !vbus_state;
167}
168
169#endif /* EVM */
170
171static void davinci_musb_source_power(struct musb *musb, int is_on, int immediate)
172{
173#ifdef CONFIG_MACH_DAVINCI_EVM
174 if (is_on)
175 is_on = 1;
176
177 if (vbus_state == is_on)
178 return;
179 vbus_state = !is_on; /* 0/1 vs "-1 == unknown/init" */
180
181 if (machine_is_davinci_evm()) {
182 static DECLARE_WORK(evm_vbus_work, evm_deferred_drvvbus);
183
184 if (immediate)
185 gpio_set_value_cansleep(GPIO_nVBUS_DRV, vbus_state);
186 else
187 schedule_work(&evm_vbus_work);
188 }
189 if (immediate)
190 vbus_state = is_on;
191#endif
192}
193
194static void davinci_musb_set_vbus(struct musb *musb, int is_on)
195{
196 WARN_ON(is_on && is_peripheral_active(musb));
197 davinci_musb_source_power(musb, is_on, 0);
198}
199
200
201#define POLL_SECONDS 2
202
203static struct timer_list otg_workaround;
204
205static void otg_timer(unsigned long _musb)
206{
207 struct musb *musb = (void *)_musb;
208 void __iomem *mregs = musb->mregs;
209 u8 devctl;
210 unsigned long flags;
211
212 /* We poll because DaVinci's won't expose several OTG-critical
213 * status change events (from the transceiver) otherwise.
214 */
215 devctl = musb_readb(mregs, MUSB_DEVCTL);
216 dev_dbg(musb->controller, "poll devctl %02x (%s)\n", devctl,
217 otg_state_string(musb->xceiv->state));
218
219 spin_lock_irqsave(&musb->lock, flags);
220 switch (musb->xceiv->state) {
221 case OTG_STATE_A_WAIT_VFALL:
222 /* Wait till VBUS falls below SessionEnd (~0.2V); the 1.3 RTL
223 * seems to mis-handle session "start" otherwise (or in our
224 * case "recover"), in routine "VBUS was valid by the time
225 * VBUSERR got reported during enumeration" cases.
226 */
227 if (devctl & MUSB_DEVCTL_VBUS) {
228 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
229 break;
230 }
231 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
232 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG,
233 MUSB_INTR_VBUSERROR << DAVINCI_USB_USBINT_SHIFT);
234 break;
235 case OTG_STATE_B_IDLE:
236 if (!is_peripheral_enabled(musb))
237 break;
238
239 /* There's no ID-changed IRQ, so we have no good way to tell
240 * when to switch to the A-Default state machine (by setting
241 * the DEVCTL.SESSION flag).
242 *
243 * Workaround: whenever we're in B_IDLE, try setting the
244 * session flag every few seconds. If it works, ID was
245 * grounded and we're now in the A-Default state machine.
246 *
247 * NOTE setting the session flag is _supposed_ to trigger
248 * SRP, but clearly it doesn't.
249 */
250 musb_writeb(mregs, MUSB_DEVCTL,
251 devctl | MUSB_DEVCTL_SESSION);
252 devctl = musb_readb(mregs, MUSB_DEVCTL);
253 if (devctl & MUSB_DEVCTL_BDEVICE)
254 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
255 else
256 musb->xceiv->state = OTG_STATE_A_IDLE;
257 break;
258 default:
259 break;
260 }
261 spin_unlock_irqrestore(&musb->lock, flags);
262}
263
264static irqreturn_t davinci_musb_interrupt(int irq, void *__hci)
265{
266 unsigned long flags;
267 irqreturn_t retval = IRQ_NONE;
268 struct musb *musb = __hci;
269 struct usb_otg *otg = musb->xceiv->otg;
270 void __iomem *tibase = musb->ctrl_base;
271 struct cppi *cppi;
272 u32 tmp;
273
274 spin_lock_irqsave(&musb->lock, flags);
275
276 /* NOTE: DaVinci shadows the Mentor IRQs. Don't manage them through
277 * the Mentor registers (except for setup), use the TI ones and EOI.
278 *
279 * Docs describe irq "vector" registers associated with the CPPI and
280 * USB EOI registers. These hold a bitmask corresponding to the
281 * current IRQ, not an irq handler address. Would using those bits
282 * resolve some of the races observed in this dispatch code??
283 */
284
285 /* CPPI interrupts share the same IRQ line, but have their own
286 * mask, state, "vector", and EOI registers.
287 */
288 cppi = container_of(musb->dma_controller, struct cppi, controller);
289 if (is_cppi_enabled() && musb->dma_controller && !cppi->irq)
290 retval = cppi_interrupt(irq, __hci);
291
292 /* ack and handle non-CPPI interrupts */
293 tmp = musb_readl(tibase, DAVINCI_USB_INT_SRC_MASKED_REG);
294 musb_writel(tibase, DAVINCI_USB_INT_SRC_CLR_REG, tmp);
295 dev_dbg(musb->controller, "IRQ %08x\n", tmp);
296
297 musb->int_rx = (tmp & DAVINCI_USB_RXINT_MASK)
298 >> DAVINCI_USB_RXINT_SHIFT;
299 musb->int_tx = (tmp & DAVINCI_USB_TXINT_MASK)
300 >> DAVINCI_USB_TXINT_SHIFT;
301 musb->int_usb = (tmp & DAVINCI_USB_USBINT_MASK)
302 >> DAVINCI_USB_USBINT_SHIFT;
303
304 /* DRVVBUS irqs are the only proxy we have (a very poor one!) for
305 * DaVinci's missing ID change IRQ. We need an ID change IRQ to
306 * switch appropriately between halves of the OTG state machine.
307 * Managing DEVCTL.SESSION per Mentor docs requires we know its
308 * value, but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
309 * Also, DRVVBUS pulses for SRP (but not at 5V) ...
310 */
311 if (tmp & (DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT)) {
312 int drvvbus = musb_readl(tibase, DAVINCI_USB_STAT_REG);
313 void __iomem *mregs = musb->mregs;
314 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
315 int err = musb->int_usb & MUSB_INTR_VBUSERROR;
316
317 err = is_host_enabled(musb)
318 && (musb->int_usb & MUSB_INTR_VBUSERROR);
319 if (err) {
320 /* The Mentor core doesn't debounce VBUS as needed
321 * to cope with device connect current spikes. This
322 * means it's not uncommon for bus-powered devices
323 * to get VBUS errors during enumeration.
324 *
325 * This is a workaround, but newer RTL from Mentor
326 * seems to allow a better one: "re"starting sessions
327 * without waiting (on EVM, a **long** time) for VBUS
328 * to stop registering in devctl.
329 */
330 musb->int_usb &= ~MUSB_INTR_VBUSERROR;
331 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
332 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
333 WARNING("VBUS error workaround (delay coming)\n");
334 } else if (is_host_enabled(musb) && drvvbus) {
335 MUSB_HST_MODE(musb);
336 otg->default_a = 1;
337 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
338 portstate(musb->port1_status |= USB_PORT_STAT_POWER);
339 del_timer(&otg_workaround);
340 } else {
341 musb->is_active = 0;
342 MUSB_DEV_MODE(musb);
343 otg->default_a = 0;
344 musb->xceiv->state = OTG_STATE_B_IDLE;
345 portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
346 }
347
348 /* NOTE: this must complete poweron within 100 msec
349 * (OTG_TIME_A_WAIT_VRISE) but we don't check for that.
350 */
351 davinci_musb_source_power(musb, drvvbus, 0);
352 dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
353 drvvbus ? "on" : "off",
354 otg_state_string(musb->xceiv->state),
355 err ? " ERROR" : "",
356 devctl);
357 retval = IRQ_HANDLED;
358 }
359
360 if (musb->int_tx || musb->int_rx || musb->int_usb)
361 retval |= musb_interrupt(musb);
362
363 /* irq stays asserted until EOI is written */
364 musb_writel(tibase, DAVINCI_USB_EOI_REG, 0);
365
366 /* poll for ID change */
367 if (is_otg_enabled(musb)
368 && musb->xceiv->state == OTG_STATE_B_IDLE)
369 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
370
371 spin_unlock_irqrestore(&musb->lock, flags);
372
373 return retval;
374}
375
376static int davinci_musb_set_mode(struct musb *musb, u8 mode)
377{
378 /* EVM can't do this (right?) */
379 return -EIO;
380}
381
382static int davinci_musb_init(struct musb *musb)
383{
384 void __iomem *tibase = musb->ctrl_base;
385 u32 revision;
386
387 usb_nop_xceiv_register();
388 musb->xceiv = usb_get_transceiver();
389 if (!musb->xceiv)
390 goto unregister;
391
392 musb->mregs += DAVINCI_BASE_OFFSET;
393
394 /* returns zero if e.g. not clocked */
395 revision = musb_readl(tibase, DAVINCI_USB_VERSION_REG);
396 if (revision == 0)
397 goto fail;
398
399 if (is_host_enabled(musb))
400 setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
401
402 davinci_musb_source_power(musb, 0, 1);
403
404 /* dm355 EVM swaps D+/D- for signal integrity, and
405 * is clocked from the main 24 MHz crystal.
406 */
407 if (machine_is_davinci_dm355_evm()) {
408 u32 phy_ctrl = __raw_readl(USB_PHY_CTRL);
409
410 phy_ctrl &= ~(3 << 9);
411 phy_ctrl |= USBPHY_DATAPOL;
412 __raw_writel(phy_ctrl, USB_PHY_CTRL);
413 }
414
415 /* On dm355, the default-A state machine needs DRVVBUS control.
416 * If we won't be a host, there's no need to turn it on.
417 */
418 if (cpu_is_davinci_dm355()) {
419 u32 deepsleep = __raw_readl(DM355_DEEPSLEEP);
420
421 if (is_host_enabled(musb)) {
422 deepsleep &= ~DRVVBUS_OVERRIDE;
423 } else {
424 deepsleep &= ~DRVVBUS_FORCE;
425 deepsleep |= DRVVBUS_OVERRIDE;
426 }
427 __raw_writel(deepsleep, DM355_DEEPSLEEP);
428 }
429
430 /* reset the controller */
431 musb_writel(tibase, DAVINCI_USB_CTRL_REG, 0x1);
432
433 /* start the on-chip PHY and its PLL */
434 phy_on();
435
436 msleep(5);
437
438 /* NOTE: irqs are in mixed mode, not bypass to pure-musb */
439 pr_debug("DaVinci OTG revision %08x phy %03x control %02x\n",
440 revision, __raw_readl(USB_PHY_CTRL),
441 musb_readb(tibase, DAVINCI_USB_CTRL_REG));
442
443 musb->isr = davinci_musb_interrupt;
444 return 0;
445
446fail:
447 usb_put_transceiver(musb->xceiv);
448unregister:
449 usb_nop_xceiv_unregister();
450 return -ENODEV;
451}
452
453static int davinci_musb_exit(struct musb *musb)
454{
455 if (is_host_enabled(musb))
456 del_timer_sync(&otg_workaround);
457
458 /* force VBUS off */
459 if (cpu_is_davinci_dm355()) {
460 u32 deepsleep = __raw_readl(DM355_DEEPSLEEP);
461
462 deepsleep &= ~DRVVBUS_FORCE;
463 deepsleep |= DRVVBUS_OVERRIDE;
464 __raw_writel(deepsleep, DM355_DEEPSLEEP);
465 }
466
467 davinci_musb_source_power(musb, 0 /*off*/, 1);
468
469 /* delay, to avoid problems with module reload */
470 if (is_host_enabled(musb) && musb->xceiv->otg->default_a) {
471 int maxdelay = 30;
472 u8 devctl, warn = 0;
473
474 /* if there's no peripheral connected, this can take a
475 * long time to fall, especially on EVM with huge C133.
476 */
477 do {
478 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
479 if (!(devctl & MUSB_DEVCTL_VBUS))
480 break;
481 if ((devctl & MUSB_DEVCTL_VBUS) != warn) {
482 warn = devctl & MUSB_DEVCTL_VBUS;
483 dev_dbg(musb->controller, "VBUS %d\n",
484 warn >> MUSB_DEVCTL_VBUS_SHIFT);
485 }
486 msleep(1000);
487 maxdelay--;
488 } while (maxdelay > 0);
489
490 /* in OTG mode, another host might be connected */
491 if (devctl & MUSB_DEVCTL_VBUS)
492 dev_dbg(musb->controller, "VBUS off timeout (devctl %02x)\n", devctl);
493 }
494
495 phy_off();
496
497 usb_put_transceiver(musb->xceiv);
498 usb_nop_xceiv_unregister();
499
500 return 0;
501}
502
503static const struct musb_platform_ops davinci_ops = {
504 .init = davinci_musb_init,
505 .exit = davinci_musb_exit,
506
507 .enable = davinci_musb_enable,
508 .disable = davinci_musb_disable,
509
510 .set_mode = davinci_musb_set_mode,
511
512 .set_vbus = davinci_musb_set_vbus,
513};
514
515static u64 davinci_dmamask = DMA_BIT_MASK(32);
516
517static int __devinit davinci_probe(struct platform_device *pdev)
518{
519 struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data;
520 struct platform_device *musb;
521 struct davinci_glue *glue;
522 struct clk *clk;
523
524 int ret = -ENOMEM;
525
526 glue = kzalloc(sizeof(*glue), GFP_KERNEL);
527 if (!glue) {
528 dev_err(&pdev->dev, "failed to allocate glue context\n");
529 goto err0;
530 }
531
532 musb = platform_device_alloc("musb-hdrc", -1);
533 if (!musb) {
534 dev_err(&pdev->dev, "failed to allocate musb device\n");
535 goto err1;
536 }
537
538 clk = clk_get(&pdev->dev, "usb");
539 if (IS_ERR(clk)) {
540 dev_err(&pdev->dev, "failed to get clock\n");
541 ret = PTR_ERR(clk);
542 goto err2;
543 }
544
545 ret = clk_enable(clk);
546 if (ret) {
547 dev_err(&pdev->dev, "failed to enable clock\n");
548 goto err3;
549 }
550
551 musb->dev.parent = &pdev->dev;
552 musb->dev.dma_mask = &davinci_dmamask;
553 musb->dev.coherent_dma_mask = davinci_dmamask;
554
555 glue->dev = &pdev->dev;
556 glue->musb = musb;
557 glue->clk = clk;
558
559 pdata->platform_ops = &davinci_ops;
560
561 platform_set_drvdata(pdev, glue);
562
563 ret = platform_device_add_resources(musb, pdev->resource,
564 pdev->num_resources);
565 if (ret) {
566 dev_err(&pdev->dev, "failed to add resources\n");
567 goto err4;
568 }
569
570 ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
571 if (ret) {
572 dev_err(&pdev->dev, "failed to add platform_data\n");
573 goto err4;
574 }
575
576 ret = platform_device_add(musb);
577 if (ret) {
578 dev_err(&pdev->dev, "failed to register musb device\n");
579 goto err4;
580 }
581
582 return 0;
583
584err4:
585 clk_disable(clk);
586
587err3:
588 clk_put(clk);
589
590err2:
591 platform_device_put(musb);
592
593err1:
594 kfree(glue);
595
596err0:
597 return ret;
598}
599
600static int __devexit davinci_remove(struct platform_device *pdev)
601{
602 struct davinci_glue *glue = platform_get_drvdata(pdev);
603
604 platform_device_del(glue->musb);
605 platform_device_put(glue->musb);
606 clk_disable(glue->clk);
607 clk_put(glue->clk);
608 kfree(glue);
609
610 return 0;
611}
612
613static struct platform_driver davinci_driver = {
614 .probe = davinci_probe,
615 .remove = __devexit_p(davinci_remove),
616 .driver = {
617 .name = "musb-davinci",
618 },
619};
620
621MODULE_DESCRIPTION("DaVinci MUSB Glue Layer");
622MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
623MODULE_LICENSE("GPL v2");
624
625static int __init davinci_init(void)
626{
627 return platform_driver_register(&davinci_driver);
628}
629module_init(davinci_init);
630
631static void __exit davinci_exit(void)
632{
633 platform_driver_unregister(&davinci_driver);
634}
635module_exit(davinci_exit);