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1/**
2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
21 *
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 */
38
39#include <linux/kernel.h>
40#include <linux/delay.h>
41#include <linux/slab.h>
42#include <linux/spinlock.h>
43#include <linux/platform_device.h>
44#include <linux/pm_runtime.h>
45#include <linux/interrupt.h>
46#include <linux/io.h>
47#include <linux/list.h>
48#include <linux/dma-mapping.h>
49
50#include <linux/usb/ch9.h>
51#include <linux/usb/gadget.h>
52
53#include "core.h"
54#include "gadget.h"
55#include "io.h"
56
57/**
58 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
59 * @dwc: pointer to our context structure
60 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
61 *
62 * Caller should take care of locking. This function will
63 * return 0 on success or -EINVAL if wrong Test Selector
64 * is passed
65 */
66int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
67{
68 u32 reg;
69
70 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
71 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
72
73 switch (mode) {
74 case TEST_J:
75 case TEST_K:
76 case TEST_SE0_NAK:
77 case TEST_PACKET:
78 case TEST_FORCE_EN:
79 reg |= mode << 1;
80 break;
81 default:
82 return -EINVAL;
83 }
84
85 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
86
87 return 0;
88}
89
90/**
91 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
92 * @dwc: pointer to our context structure
93 * @state: the state to put link into
94 *
95 * Caller should take care of locking. This function will
96 * return 0 on success or -ETIMEDOUT.
97 */
98int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
99{
100 int retries = 10000;
101 u32 reg;
102
103 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
104 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
105
106 /* set requested state */
107 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
108 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
109
110 /* wait for a change in DSTS */
111 while (--retries) {
112 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
113
114 if (DWC3_DSTS_USBLNKST(reg) == state)
115 return 0;
116
117 udelay(5);
118 }
119
120 dev_vdbg(dwc->dev, "link state change request timed out\n");
121
122 return -ETIMEDOUT;
123}
124
125/**
126 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
127 * @dwc: pointer to our context structure
128 *
129 * This function will a best effort FIFO allocation in order
130 * to improve FIFO usage and throughput, while still allowing
131 * us to enable as many endpoints as possible.
132 *
133 * Keep in mind that this operation will be highly dependent
134 * on the configured size for RAM1 - which contains TxFifo -,
135 * the amount of endpoints enabled on coreConsultant tool, and
136 * the width of the Master Bus.
137 *
138 * In the ideal world, we would always be able to satisfy the
139 * following equation:
140 *
141 * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
142 * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
143 *
144 * Unfortunately, due to many variables that's not always the case.
145 */
146int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
147{
148 int last_fifo_depth = 0;
149 int ram1_depth;
150 int fifo_size;
151 int mdwidth;
152 int num;
153
154 if (!dwc->needs_fifo_resize)
155 return 0;
156
157 ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
158 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
159
160 /* MDWIDTH is represented in bits, we need it in bytes */
161 mdwidth >>= 3;
162
163 /*
164 * FIXME For now we will only allocate 1 wMaxPacketSize space
165 * for each enabled endpoint, later patches will come to
166 * improve this algorithm so that we better use the internal
167 * FIFO space
168 */
169 for (num = 0; num < DWC3_ENDPOINTS_NUM; num++) {
170 struct dwc3_ep *dep = dwc->eps[num];
171 int fifo_number = dep->number >> 1;
172 int mult = 1;
173 int tmp;
174
175 if (!(dep->number & 1))
176 continue;
177
178 if (!(dep->flags & DWC3_EP_ENABLED))
179 continue;
180
181 if (usb_endpoint_xfer_bulk(dep->endpoint.desc)
182 || usb_endpoint_xfer_isoc(dep->endpoint.desc))
183 mult = 3;
184
185 /*
186 * REVISIT: the following assumes we will always have enough
187 * space available on the FIFO RAM for all possible use cases.
188 * Make sure that's true somehow and change FIFO allocation
189 * accordingly.
190 *
191 * If we have Bulk or Isochronous endpoints, we want
192 * them to be able to be very, very fast. So we're giving
193 * those endpoints a fifo_size which is enough for 3 full
194 * packets
195 */
196 tmp = mult * (dep->endpoint.maxpacket + mdwidth);
197 tmp += mdwidth;
198
199 fifo_size = DIV_ROUND_UP(tmp, mdwidth);
200
201 fifo_size |= (last_fifo_depth << 16);
202
203 dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n",
204 dep->name, last_fifo_depth, fifo_size & 0xffff);
205
206 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(fifo_number),
207 fifo_size);
208
209 last_fifo_depth += (fifo_size & 0xffff);
210 }
211
212 return 0;
213}
214
215void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
216 int status)
217{
218 struct dwc3 *dwc = dep->dwc;
219
220 if (req->queued) {
221 if (req->request.num_mapped_sgs)
222 dep->busy_slot += req->request.num_mapped_sgs;
223 else
224 dep->busy_slot++;
225
226 /*
227 * Skip LINK TRB. We can't use req->trb and check for
228 * DWC3_TRBCTL_LINK_TRB because it points the TRB we just
229 * completed (not the LINK TRB).
230 */
231 if (((dep->busy_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
232 usb_endpoint_xfer_isoc(dep->endpoint.desc))
233 dep->busy_slot++;
234 }
235 list_del(&req->list);
236 req->trb = NULL;
237
238 if (req->request.status == -EINPROGRESS)
239 req->request.status = status;
240
241 if (dwc->ep0_bounced && dep->number == 0)
242 dwc->ep0_bounced = false;
243 else
244 usb_gadget_unmap_request(&dwc->gadget, &req->request,
245 req->direction);
246
247 dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
248 req, dep->name, req->request.actual,
249 req->request.length, status);
250
251 spin_unlock(&dwc->lock);
252 req->request.complete(&dep->endpoint, &req->request);
253 spin_lock(&dwc->lock);
254}
255
256static const char *dwc3_gadget_ep_cmd_string(u8 cmd)
257{
258 switch (cmd) {
259 case DWC3_DEPCMD_DEPSTARTCFG:
260 return "Start New Configuration";
261 case DWC3_DEPCMD_ENDTRANSFER:
262 return "End Transfer";
263 case DWC3_DEPCMD_UPDATETRANSFER:
264 return "Update Transfer";
265 case DWC3_DEPCMD_STARTTRANSFER:
266 return "Start Transfer";
267 case DWC3_DEPCMD_CLEARSTALL:
268 return "Clear Stall";
269 case DWC3_DEPCMD_SETSTALL:
270 return "Set Stall";
271 case DWC3_DEPCMD_GETSEQNUMBER:
272 return "Get Data Sequence Number";
273 case DWC3_DEPCMD_SETTRANSFRESOURCE:
274 return "Set Endpoint Transfer Resource";
275 case DWC3_DEPCMD_SETEPCONFIG:
276 return "Set Endpoint Configuration";
277 default:
278 return "UNKNOWN command";
279 }
280}
281
282int dwc3_send_gadget_generic_command(struct dwc3 *dwc, int cmd, u32 param)
283{
284 u32 timeout = 500;
285 u32 reg;
286
287 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
288 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
289
290 do {
291 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
292 if (!(reg & DWC3_DGCMD_CMDACT)) {
293 dev_vdbg(dwc->dev, "Command Complete --> %d\n",
294 DWC3_DGCMD_STATUS(reg));
295 return 0;
296 }
297
298 /*
299 * We can't sleep here, because it's also called from
300 * interrupt context.
301 */
302 timeout--;
303 if (!timeout)
304 return -ETIMEDOUT;
305 udelay(1);
306 } while (1);
307}
308
309int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
310 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
311{
312 struct dwc3_ep *dep = dwc->eps[ep];
313 u32 timeout = 500;
314 u32 reg;
315
316 dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n",
317 dep->name,
318 dwc3_gadget_ep_cmd_string(cmd), params->param0,
319 params->param1, params->param2);
320
321 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
322 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
323 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
324
325 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
326 do {
327 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
328 if (!(reg & DWC3_DEPCMD_CMDACT)) {
329 dev_vdbg(dwc->dev, "Command Complete --> %d\n",
330 DWC3_DEPCMD_STATUS(reg));
331 return 0;
332 }
333
334 /*
335 * We can't sleep here, because it is also called from
336 * interrupt context.
337 */
338 timeout--;
339 if (!timeout)
340 return -ETIMEDOUT;
341
342 udelay(1);
343 } while (1);
344}
345
346static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
347 struct dwc3_trb *trb)
348{
349 u32 offset = (char *) trb - (char *) dep->trb_pool;
350
351 return dep->trb_pool_dma + offset;
352}
353
354static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
355{
356 struct dwc3 *dwc = dep->dwc;
357
358 if (dep->trb_pool)
359 return 0;
360
361 if (dep->number == 0 || dep->number == 1)
362 return 0;
363
364 dep->trb_pool = dma_alloc_coherent(dwc->dev,
365 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
366 &dep->trb_pool_dma, GFP_KERNEL);
367 if (!dep->trb_pool) {
368 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
369 dep->name);
370 return -ENOMEM;
371 }
372
373 return 0;
374}
375
376static void dwc3_free_trb_pool(struct dwc3_ep *dep)
377{
378 struct dwc3 *dwc = dep->dwc;
379
380 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
381 dep->trb_pool, dep->trb_pool_dma);
382
383 dep->trb_pool = NULL;
384 dep->trb_pool_dma = 0;
385}
386
387static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
388{
389 struct dwc3_gadget_ep_cmd_params params;
390 u32 cmd;
391
392 memset(¶ms, 0x00, sizeof(params));
393
394 if (dep->number != 1) {
395 cmd = DWC3_DEPCMD_DEPSTARTCFG;
396 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
397 if (dep->number > 1) {
398 if (dwc->start_config_issued)
399 return 0;
400 dwc->start_config_issued = true;
401 cmd |= DWC3_DEPCMD_PARAM(2);
402 }
403
404 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, ¶ms);
405 }
406
407 return 0;
408}
409
410static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
411 const struct usb_endpoint_descriptor *desc,
412 const struct usb_ss_ep_comp_descriptor *comp_desc)
413{
414 struct dwc3_gadget_ep_cmd_params params;
415
416 memset(¶ms, 0x00, sizeof(params));
417
418 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
419 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc))
420 | DWC3_DEPCFG_BURST_SIZE(dep->endpoint.maxburst);
421
422 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
423 | DWC3_DEPCFG_XFER_NOT_READY_EN;
424
425 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
426 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
427 | DWC3_DEPCFG_STREAM_EVENT_EN;
428 dep->stream_capable = true;
429 }
430
431 if (usb_endpoint_xfer_isoc(desc))
432 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
433
434 /*
435 * We are doing 1:1 mapping for endpoints, meaning
436 * Physical Endpoints 2 maps to Logical Endpoint 2 and
437 * so on. We consider the direction bit as part of the physical
438 * endpoint number. So USB endpoint 0x81 is 0x03.
439 */
440 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
441
442 /*
443 * We must use the lower 16 TX FIFOs even though
444 * HW might have more
445 */
446 if (dep->direction)
447 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
448
449 if (desc->bInterval) {
450 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
451 dep->interval = 1 << (desc->bInterval - 1);
452 }
453
454 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
455 DWC3_DEPCMD_SETEPCONFIG, ¶ms);
456}
457
458static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
459{
460 struct dwc3_gadget_ep_cmd_params params;
461
462 memset(¶ms, 0x00, sizeof(params));
463
464 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
465
466 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
467 DWC3_DEPCMD_SETTRANSFRESOURCE, ¶ms);
468}
469
470/**
471 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
472 * @dep: endpoint to be initialized
473 * @desc: USB Endpoint Descriptor
474 *
475 * Caller should take care of locking
476 */
477static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
478 const struct usb_endpoint_descriptor *desc,
479 const struct usb_ss_ep_comp_descriptor *comp_desc)
480{
481 struct dwc3 *dwc = dep->dwc;
482 u32 reg;
483 int ret = -ENOMEM;
484
485 if (!(dep->flags & DWC3_EP_ENABLED)) {
486 ret = dwc3_gadget_start_config(dwc, dep);
487 if (ret)
488 return ret;
489 }
490
491 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc);
492 if (ret)
493 return ret;
494
495 if (!(dep->flags & DWC3_EP_ENABLED)) {
496 struct dwc3_trb *trb_st_hw;
497 struct dwc3_trb *trb_link;
498
499 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
500 if (ret)
501 return ret;
502
503 dep->endpoint.desc = desc;
504 dep->comp_desc = comp_desc;
505 dep->type = usb_endpoint_type(desc);
506 dep->flags |= DWC3_EP_ENABLED;
507
508 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
509 reg |= DWC3_DALEPENA_EP(dep->number);
510 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
511
512 if (!usb_endpoint_xfer_isoc(desc))
513 return 0;
514
515 memset(&trb_link, 0, sizeof(trb_link));
516
517 /* Link TRB for ISOC. The HWO bit is never reset */
518 trb_st_hw = &dep->trb_pool[0];
519
520 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
521
522 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
523 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
524 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
525 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
526 }
527
528 return 0;
529}
530
531static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum);
532static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
533{
534 struct dwc3_request *req;
535
536 if (!list_empty(&dep->req_queued))
537 dwc3_stop_active_transfer(dwc, dep->number);
538
539 while (!list_empty(&dep->request_list)) {
540 req = next_request(&dep->request_list);
541
542 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
543 }
544}
545
546/**
547 * __dwc3_gadget_ep_disable - Disables a HW endpoint
548 * @dep: the endpoint to disable
549 *
550 * This function also removes requests which are currently processed ny the
551 * hardware and those which are not yet scheduled.
552 * Caller should take care of locking.
553 */
554static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
555{
556 struct dwc3 *dwc = dep->dwc;
557 u32 reg;
558
559 dwc3_remove_requests(dwc, dep);
560
561 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
562 reg &= ~DWC3_DALEPENA_EP(dep->number);
563 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
564
565 dep->stream_capable = false;
566 dep->endpoint.desc = NULL;
567 dep->comp_desc = NULL;
568 dep->type = 0;
569 dep->flags = 0;
570
571 return 0;
572}
573
574/* -------------------------------------------------------------------------- */
575
576static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
577 const struct usb_endpoint_descriptor *desc)
578{
579 return -EINVAL;
580}
581
582static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
583{
584 return -EINVAL;
585}
586
587/* -------------------------------------------------------------------------- */
588
589static int dwc3_gadget_ep_enable(struct usb_ep *ep,
590 const struct usb_endpoint_descriptor *desc)
591{
592 struct dwc3_ep *dep;
593 struct dwc3 *dwc;
594 unsigned long flags;
595 int ret;
596
597 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
598 pr_debug("dwc3: invalid parameters\n");
599 return -EINVAL;
600 }
601
602 if (!desc->wMaxPacketSize) {
603 pr_debug("dwc3: missing wMaxPacketSize\n");
604 return -EINVAL;
605 }
606
607 dep = to_dwc3_ep(ep);
608 dwc = dep->dwc;
609
610 switch (usb_endpoint_type(desc)) {
611 case USB_ENDPOINT_XFER_CONTROL:
612 strlcat(dep->name, "-control", sizeof(dep->name));
613 break;
614 case USB_ENDPOINT_XFER_ISOC:
615 strlcat(dep->name, "-isoc", sizeof(dep->name));
616 break;
617 case USB_ENDPOINT_XFER_BULK:
618 strlcat(dep->name, "-bulk", sizeof(dep->name));
619 break;
620 case USB_ENDPOINT_XFER_INT:
621 strlcat(dep->name, "-int", sizeof(dep->name));
622 break;
623 default:
624 dev_err(dwc->dev, "invalid endpoint transfer type\n");
625 }
626
627 if (dep->flags & DWC3_EP_ENABLED) {
628 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n",
629 dep->name);
630 return 0;
631 }
632
633 dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
634
635 spin_lock_irqsave(&dwc->lock, flags);
636 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc);
637 spin_unlock_irqrestore(&dwc->lock, flags);
638
639 return ret;
640}
641
642static int dwc3_gadget_ep_disable(struct usb_ep *ep)
643{
644 struct dwc3_ep *dep;
645 struct dwc3 *dwc;
646 unsigned long flags;
647 int ret;
648
649 if (!ep) {
650 pr_debug("dwc3: invalid parameters\n");
651 return -EINVAL;
652 }
653
654 dep = to_dwc3_ep(ep);
655 dwc = dep->dwc;
656
657 if (!(dep->flags & DWC3_EP_ENABLED)) {
658 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n",
659 dep->name);
660 return 0;
661 }
662
663 snprintf(dep->name, sizeof(dep->name), "ep%d%s",
664 dep->number >> 1,
665 (dep->number & 1) ? "in" : "out");
666
667 spin_lock_irqsave(&dwc->lock, flags);
668 ret = __dwc3_gadget_ep_disable(dep);
669 spin_unlock_irqrestore(&dwc->lock, flags);
670
671 return ret;
672}
673
674static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
675 gfp_t gfp_flags)
676{
677 struct dwc3_request *req;
678 struct dwc3_ep *dep = to_dwc3_ep(ep);
679 struct dwc3 *dwc = dep->dwc;
680
681 req = kzalloc(sizeof(*req), gfp_flags);
682 if (!req) {
683 dev_err(dwc->dev, "not enough memory\n");
684 return NULL;
685 }
686
687 req->epnum = dep->number;
688 req->dep = dep;
689
690 return &req->request;
691}
692
693static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
694 struct usb_request *request)
695{
696 struct dwc3_request *req = to_dwc3_request(request);
697
698 kfree(req);
699}
700
701/**
702 * dwc3_prepare_one_trb - setup one TRB from one request
703 * @dep: endpoint for which this request is prepared
704 * @req: dwc3_request pointer
705 */
706static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
707 struct dwc3_request *req, dma_addr_t dma,
708 unsigned length, unsigned last, unsigned chain)
709{
710 struct dwc3 *dwc = dep->dwc;
711 struct dwc3_trb *trb;
712
713 unsigned int cur_slot;
714
715 dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n",
716 dep->name, req, (unsigned long long) dma,
717 length, last ? " last" : "",
718 chain ? " chain" : "");
719
720 trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
721 cur_slot = dep->free_slot;
722 dep->free_slot++;
723
724 /* Skip the LINK-TRB on ISOC */
725 if (((cur_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
726 usb_endpoint_xfer_isoc(dep->endpoint.desc))
727 return;
728
729 if (!req->trb) {
730 dwc3_gadget_move_request_queued(req);
731 req->trb = trb;
732 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
733 }
734
735 trb->size = DWC3_TRB_SIZE_LENGTH(length);
736 trb->bpl = lower_32_bits(dma);
737 trb->bph = upper_32_bits(dma);
738
739 switch (usb_endpoint_type(dep->endpoint.desc)) {
740 case USB_ENDPOINT_XFER_CONTROL:
741 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
742 break;
743
744 case USB_ENDPOINT_XFER_ISOC:
745 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
746
747 /* IOC every DWC3_TRB_NUM / 4 so we can refill */
748 if (!(cur_slot % (DWC3_TRB_NUM / 4)))
749 trb->ctrl |= DWC3_TRB_CTRL_IOC;
750 break;
751
752 case USB_ENDPOINT_XFER_BULK:
753 case USB_ENDPOINT_XFER_INT:
754 trb->ctrl = DWC3_TRBCTL_NORMAL;
755 break;
756 default:
757 /*
758 * This is only possible with faulty memory because we
759 * checked it already :)
760 */
761 BUG();
762 }
763
764 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
765 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
766 trb->ctrl |= DWC3_TRB_CTRL_CSP;
767 } else {
768 if (chain)
769 trb->ctrl |= DWC3_TRB_CTRL_CHN;
770
771 if (last)
772 trb->ctrl |= DWC3_TRB_CTRL_LST;
773 }
774
775 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
776 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
777
778 trb->ctrl |= DWC3_TRB_CTRL_HWO;
779}
780
781/*
782 * dwc3_prepare_trbs - setup TRBs from requests
783 * @dep: endpoint for which requests are being prepared
784 * @starting: true if the endpoint is idle and no requests are queued.
785 *
786 * The function goes through the requests list and sets up TRBs for the
787 * transfers. The function returns once there are no more TRBs available or
788 * it runs out of requests.
789 */
790static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
791{
792 struct dwc3_request *req, *n;
793 u32 trbs_left;
794 u32 max;
795 unsigned int last_one = 0;
796
797 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
798
799 /* the first request must not be queued */
800 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
801
802 /* Can't wrap around on a non-isoc EP since there's no link TRB */
803 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
804 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
805 if (trbs_left > max)
806 trbs_left = max;
807 }
808
809 /*
810 * If busy & slot are equal than it is either full or empty. If we are
811 * starting to process requests then we are empty. Otherwise we are
812 * full and don't do anything
813 */
814 if (!trbs_left) {
815 if (!starting)
816 return;
817 trbs_left = DWC3_TRB_NUM;
818 /*
819 * In case we start from scratch, we queue the ISOC requests
820 * starting from slot 1. This is done because we use ring
821 * buffer and have no LST bit to stop us. Instead, we place
822 * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
823 * after the first request so we start at slot 1 and have
824 * 7 requests proceed before we hit the first IOC.
825 * Other transfer types don't use the ring buffer and are
826 * processed from the first TRB until the last one. Since we
827 * don't wrap around we have to start at the beginning.
828 */
829 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
830 dep->busy_slot = 1;
831 dep->free_slot = 1;
832 } else {
833 dep->busy_slot = 0;
834 dep->free_slot = 0;
835 }
836 }
837
838 /* The last TRB is a link TRB, not used for xfer */
839 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
840 return;
841
842 list_for_each_entry_safe(req, n, &dep->request_list, list) {
843 unsigned length;
844 dma_addr_t dma;
845
846 if (req->request.num_mapped_sgs > 0) {
847 struct usb_request *request = &req->request;
848 struct scatterlist *sg = request->sg;
849 struct scatterlist *s;
850 int i;
851
852 for_each_sg(sg, s, request->num_mapped_sgs, i) {
853 unsigned chain = true;
854
855 length = sg_dma_len(s);
856 dma = sg_dma_address(s);
857
858 if (i == (request->num_mapped_sgs - 1) ||
859 sg_is_last(s)) {
860 last_one = true;
861 chain = false;
862 }
863
864 trbs_left--;
865 if (!trbs_left)
866 last_one = true;
867
868 if (last_one)
869 chain = false;
870
871 dwc3_prepare_one_trb(dep, req, dma, length,
872 last_one, chain);
873
874 if (last_one)
875 break;
876 }
877 } else {
878 dma = req->request.dma;
879 length = req->request.length;
880 trbs_left--;
881
882 if (!trbs_left)
883 last_one = 1;
884
885 /* Is this the last request? */
886 if (list_is_last(&req->list, &dep->request_list))
887 last_one = 1;
888
889 dwc3_prepare_one_trb(dep, req, dma, length,
890 last_one, false);
891
892 if (last_one)
893 break;
894 }
895 }
896}
897
898static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
899 int start_new)
900{
901 struct dwc3_gadget_ep_cmd_params params;
902 struct dwc3_request *req;
903 struct dwc3 *dwc = dep->dwc;
904 int ret;
905 u32 cmd;
906
907 if (start_new && (dep->flags & DWC3_EP_BUSY)) {
908 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
909 return -EBUSY;
910 }
911 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
912
913 /*
914 * If we are getting here after a short-out-packet we don't enqueue any
915 * new requests as we try to set the IOC bit only on the last request.
916 */
917 if (start_new) {
918 if (list_empty(&dep->req_queued))
919 dwc3_prepare_trbs(dep, start_new);
920
921 /* req points to the first request which will be sent */
922 req = next_request(&dep->req_queued);
923 } else {
924 dwc3_prepare_trbs(dep, start_new);
925
926 /*
927 * req points to the first request where HWO changed from 0 to 1
928 */
929 req = next_request(&dep->req_queued);
930 }
931 if (!req) {
932 dep->flags |= DWC3_EP_PENDING_REQUEST;
933 return 0;
934 }
935
936 memset(¶ms, 0, sizeof(params));
937 params.param0 = upper_32_bits(req->trb_dma);
938 params.param1 = lower_32_bits(req->trb_dma);
939
940 if (start_new)
941 cmd = DWC3_DEPCMD_STARTTRANSFER;
942 else
943 cmd = DWC3_DEPCMD_UPDATETRANSFER;
944
945 cmd |= DWC3_DEPCMD_PARAM(cmd_param);
946 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
947 if (ret < 0) {
948 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
949
950 /*
951 * FIXME we need to iterate over the list of requests
952 * here and stop, unmap, free and del each of the linked
953 * requests instead of what we do now.
954 */
955 usb_gadget_unmap_request(&dwc->gadget, &req->request,
956 req->direction);
957 list_del(&req->list);
958 return ret;
959 }
960
961 dep->flags |= DWC3_EP_BUSY;
962
963 if (start_new) {
964 dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc,
965 dep->number);
966 WARN_ON_ONCE(!dep->res_trans_idx);
967 }
968
969 return 0;
970}
971
972static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
973{
974 struct dwc3 *dwc = dep->dwc;
975 int ret;
976
977 req->request.actual = 0;
978 req->request.status = -EINPROGRESS;
979 req->direction = dep->direction;
980 req->epnum = dep->number;
981
982 /*
983 * We only add to our list of requests now and
984 * start consuming the list once we get XferNotReady
985 * IRQ.
986 *
987 * That way, we avoid doing anything that we don't need
988 * to do now and defer it until the point we receive a
989 * particular token from the Host side.
990 *
991 * This will also avoid Host cancelling URBs due to too
992 * many NAKs.
993 */
994 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
995 dep->direction);
996 if (ret)
997 return ret;
998
999 list_add_tail(&req->list, &dep->request_list);
1000
1001 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && (dep->flags & DWC3_EP_BUSY))
1002 dep->flags |= DWC3_EP_PENDING_REQUEST;
1003
1004 /*
1005 * There are two special cases:
1006 *
1007 * 1. XferNotReady with empty list of requests. We need to kick the
1008 * transfer here in that situation, otherwise we will be NAKing
1009 * forever. If we get XferNotReady before gadget driver has a
1010 * chance to queue a request, we will ACK the IRQ but won't be
1011 * able to receive the data until the next request is queued.
1012 * The following code is handling exactly that.
1013 *
1014 * 2. XferInProgress on Isoc EP with an active transfer. We need to
1015 * kick the transfer here after queuing a request, otherwise the
1016 * core may not see the modified TRB(s).
1017 */
1018 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1019 int ret;
1020 int start_trans = 1;
1021 u8 trans_idx = dep->res_trans_idx;
1022
1023 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1024 (dep->flags & DWC3_EP_BUSY)) {
1025 start_trans = 0;
1026 WARN_ON_ONCE(!trans_idx);
1027 } else {
1028 trans_idx = 0;
1029 }
1030
1031 ret = __dwc3_gadget_kick_transfer(dep, trans_idx, start_trans);
1032 if (ret && ret != -EBUSY) {
1033 struct dwc3 *dwc = dep->dwc;
1034
1035 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1036 dep->name);
1037 }
1038 };
1039
1040 return 0;
1041}
1042
1043static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1044 gfp_t gfp_flags)
1045{
1046 struct dwc3_request *req = to_dwc3_request(request);
1047 struct dwc3_ep *dep = to_dwc3_ep(ep);
1048 struct dwc3 *dwc = dep->dwc;
1049
1050 unsigned long flags;
1051
1052 int ret;
1053
1054 if (!dep->endpoint.desc) {
1055 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
1056 request, ep->name);
1057 return -ESHUTDOWN;
1058 }
1059
1060 dev_vdbg(dwc->dev, "queing request %p to %s length %d\n",
1061 request, ep->name, request->length);
1062
1063 spin_lock_irqsave(&dwc->lock, flags);
1064 ret = __dwc3_gadget_ep_queue(dep, req);
1065 spin_unlock_irqrestore(&dwc->lock, flags);
1066
1067 return ret;
1068}
1069
1070static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1071 struct usb_request *request)
1072{
1073 struct dwc3_request *req = to_dwc3_request(request);
1074 struct dwc3_request *r = NULL;
1075
1076 struct dwc3_ep *dep = to_dwc3_ep(ep);
1077 struct dwc3 *dwc = dep->dwc;
1078
1079 unsigned long flags;
1080 int ret = 0;
1081
1082 spin_lock_irqsave(&dwc->lock, flags);
1083
1084 list_for_each_entry(r, &dep->request_list, list) {
1085 if (r == req)
1086 break;
1087 }
1088
1089 if (r != req) {
1090 list_for_each_entry(r, &dep->req_queued, list) {
1091 if (r == req)
1092 break;
1093 }
1094 if (r == req) {
1095 /* wait until it is processed */
1096 dwc3_stop_active_transfer(dwc, dep->number);
1097 goto out1;
1098 }
1099 dev_err(dwc->dev, "request %p was not queued to %s\n",
1100 request, ep->name);
1101 ret = -EINVAL;
1102 goto out0;
1103 }
1104
1105out1:
1106 /* giveback the request */
1107 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1108
1109out0:
1110 spin_unlock_irqrestore(&dwc->lock, flags);
1111
1112 return ret;
1113}
1114
1115int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value)
1116{
1117 struct dwc3_gadget_ep_cmd_params params;
1118 struct dwc3 *dwc = dep->dwc;
1119 int ret;
1120
1121 memset(¶ms, 0x00, sizeof(params));
1122
1123 if (value) {
1124 if (dep->number == 0 || dep->number == 1) {
1125 /*
1126 * Whenever EP0 is stalled, we will restart
1127 * the state machine, thus moving back to
1128 * Setup Phase
1129 */
1130 dwc->ep0state = EP0_SETUP_PHASE;
1131 }
1132
1133 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1134 DWC3_DEPCMD_SETSTALL, ¶ms);
1135 if (ret)
1136 dev_err(dwc->dev, "failed to %s STALL on %s\n",
1137 value ? "set" : "clear",
1138 dep->name);
1139 else
1140 dep->flags |= DWC3_EP_STALL;
1141 } else {
1142 if (dep->flags & DWC3_EP_WEDGE)
1143 return 0;
1144
1145 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1146 DWC3_DEPCMD_CLEARSTALL, ¶ms);
1147 if (ret)
1148 dev_err(dwc->dev, "failed to %s STALL on %s\n",
1149 value ? "set" : "clear",
1150 dep->name);
1151 else
1152 dep->flags &= ~DWC3_EP_STALL;
1153 }
1154
1155 return ret;
1156}
1157
1158static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1159{
1160 struct dwc3_ep *dep = to_dwc3_ep(ep);
1161 struct dwc3 *dwc = dep->dwc;
1162
1163 unsigned long flags;
1164
1165 int ret;
1166
1167 spin_lock_irqsave(&dwc->lock, flags);
1168
1169 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1170 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1171 ret = -EINVAL;
1172 goto out;
1173 }
1174
1175 ret = __dwc3_gadget_ep_set_halt(dep, value);
1176out:
1177 spin_unlock_irqrestore(&dwc->lock, flags);
1178
1179 return ret;
1180}
1181
1182static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1183{
1184 struct dwc3_ep *dep = to_dwc3_ep(ep);
1185 struct dwc3 *dwc = dep->dwc;
1186 unsigned long flags;
1187
1188 spin_lock_irqsave(&dwc->lock, flags);
1189 dep->flags |= DWC3_EP_WEDGE;
1190 spin_unlock_irqrestore(&dwc->lock, flags);
1191
1192 return dwc3_gadget_ep_set_halt(ep, 1);
1193}
1194
1195/* -------------------------------------------------------------------------- */
1196
1197static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1198 .bLength = USB_DT_ENDPOINT_SIZE,
1199 .bDescriptorType = USB_DT_ENDPOINT,
1200 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1201};
1202
1203static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1204 .enable = dwc3_gadget_ep0_enable,
1205 .disable = dwc3_gadget_ep0_disable,
1206 .alloc_request = dwc3_gadget_ep_alloc_request,
1207 .free_request = dwc3_gadget_ep_free_request,
1208 .queue = dwc3_gadget_ep0_queue,
1209 .dequeue = dwc3_gadget_ep_dequeue,
1210 .set_halt = dwc3_gadget_ep_set_halt,
1211 .set_wedge = dwc3_gadget_ep_set_wedge,
1212};
1213
1214static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1215 .enable = dwc3_gadget_ep_enable,
1216 .disable = dwc3_gadget_ep_disable,
1217 .alloc_request = dwc3_gadget_ep_alloc_request,
1218 .free_request = dwc3_gadget_ep_free_request,
1219 .queue = dwc3_gadget_ep_queue,
1220 .dequeue = dwc3_gadget_ep_dequeue,
1221 .set_halt = dwc3_gadget_ep_set_halt,
1222 .set_wedge = dwc3_gadget_ep_set_wedge,
1223};
1224
1225/* -------------------------------------------------------------------------- */
1226
1227static int dwc3_gadget_get_frame(struct usb_gadget *g)
1228{
1229 struct dwc3 *dwc = gadget_to_dwc(g);
1230 u32 reg;
1231
1232 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1233 return DWC3_DSTS_SOFFN(reg);
1234}
1235
1236static int dwc3_gadget_wakeup(struct usb_gadget *g)
1237{
1238 struct dwc3 *dwc = gadget_to_dwc(g);
1239
1240 unsigned long timeout;
1241 unsigned long flags;
1242
1243 u32 reg;
1244
1245 int ret = 0;
1246
1247 u8 link_state;
1248 u8 speed;
1249
1250 spin_lock_irqsave(&dwc->lock, flags);
1251
1252 /*
1253 * According to the Databook Remote wakeup request should
1254 * be issued only when the device is in early suspend state.
1255 *
1256 * We can check that via USB Link State bits in DSTS register.
1257 */
1258 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1259
1260 speed = reg & DWC3_DSTS_CONNECTSPD;
1261 if (speed == DWC3_DSTS_SUPERSPEED) {
1262 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
1263 ret = -EINVAL;
1264 goto out;
1265 }
1266
1267 link_state = DWC3_DSTS_USBLNKST(reg);
1268
1269 switch (link_state) {
1270 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1271 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1272 break;
1273 default:
1274 dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
1275 link_state);
1276 ret = -EINVAL;
1277 goto out;
1278 }
1279
1280 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1281 if (ret < 0) {
1282 dev_err(dwc->dev, "failed to put link in Recovery\n");
1283 goto out;
1284 }
1285
1286 /* write zeroes to Link Change Request */
1287 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1288 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1289
1290 /* poll until Link State changes to ON */
1291 timeout = jiffies + msecs_to_jiffies(100);
1292
1293 while (!time_after(jiffies, timeout)) {
1294 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1295
1296 /* in HS, means ON */
1297 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1298 break;
1299 }
1300
1301 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1302 dev_err(dwc->dev, "failed to send remote wakeup\n");
1303 ret = -EINVAL;
1304 }
1305
1306out:
1307 spin_unlock_irqrestore(&dwc->lock, flags);
1308
1309 return ret;
1310}
1311
1312static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1313 int is_selfpowered)
1314{
1315 struct dwc3 *dwc = gadget_to_dwc(g);
1316 unsigned long flags;
1317
1318 spin_lock_irqsave(&dwc->lock, flags);
1319 dwc->is_selfpowered = !!is_selfpowered;
1320 spin_unlock_irqrestore(&dwc->lock, flags);
1321
1322 return 0;
1323}
1324
1325static void dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on)
1326{
1327 u32 reg;
1328 u32 timeout = 500;
1329
1330 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1331 if (is_on) {
1332 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1333 reg |= (DWC3_DCTL_RUN_STOP
1334 | DWC3_DCTL_TRGTULST_RX_DET);
1335 } else {
1336 reg &= ~DWC3_DCTL_RUN_STOP;
1337 }
1338
1339 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1340
1341 do {
1342 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1343 if (is_on) {
1344 if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1345 break;
1346 } else {
1347 if (reg & DWC3_DSTS_DEVCTRLHLT)
1348 break;
1349 }
1350 timeout--;
1351 if (!timeout)
1352 break;
1353 udelay(1);
1354 } while (1);
1355
1356 dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
1357 dwc->gadget_driver
1358 ? dwc->gadget_driver->function : "no-function",
1359 is_on ? "connect" : "disconnect");
1360}
1361
1362static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1363{
1364 struct dwc3 *dwc = gadget_to_dwc(g);
1365 unsigned long flags;
1366
1367 is_on = !!is_on;
1368
1369 spin_lock_irqsave(&dwc->lock, flags);
1370 dwc3_gadget_run_stop(dwc, is_on);
1371 spin_unlock_irqrestore(&dwc->lock, flags);
1372
1373 return 0;
1374}
1375
1376static int dwc3_gadget_start(struct usb_gadget *g,
1377 struct usb_gadget_driver *driver)
1378{
1379 struct dwc3 *dwc = gadget_to_dwc(g);
1380 struct dwc3_ep *dep;
1381 unsigned long flags;
1382 int ret = 0;
1383 u32 reg;
1384
1385 spin_lock_irqsave(&dwc->lock, flags);
1386
1387 if (dwc->gadget_driver) {
1388 dev_err(dwc->dev, "%s is already bound to %s\n",
1389 dwc->gadget.name,
1390 dwc->gadget_driver->driver.name);
1391 ret = -EBUSY;
1392 goto err0;
1393 }
1394
1395 dwc->gadget_driver = driver;
1396 dwc->gadget.dev.driver = &driver->driver;
1397
1398 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1399 reg &= ~(DWC3_DCFG_SPEED_MASK);
1400
1401 /**
1402 * WORKAROUND: DWC3 revision < 2.20a have an issue
1403 * which would cause metastability state on Run/Stop
1404 * bit if we try to force the IP to USB2-only mode.
1405 *
1406 * Because of that, we cannot configure the IP to any
1407 * speed other than the SuperSpeed
1408 *
1409 * Refers to:
1410 *
1411 * STAR#9000525659: Clock Domain Crossing on DCTL in
1412 * USB 2.0 Mode
1413 */
1414 if (dwc->revision < DWC3_REVISION_220A)
1415 reg |= DWC3_DCFG_SUPERSPEED;
1416 else
1417 reg |= dwc->maximum_speed;
1418 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1419
1420 dwc->start_config_issued = false;
1421
1422 /* Start with SuperSpeed Default */
1423 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1424
1425 dep = dwc->eps[0];
1426 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
1427 if (ret) {
1428 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1429 goto err0;
1430 }
1431
1432 dep = dwc->eps[1];
1433 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
1434 if (ret) {
1435 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1436 goto err1;
1437 }
1438
1439 /* begin to receive SETUP packets */
1440 dwc->ep0state = EP0_SETUP_PHASE;
1441 dwc3_ep0_out_start(dwc);
1442
1443 spin_unlock_irqrestore(&dwc->lock, flags);
1444
1445 return 0;
1446
1447err1:
1448 __dwc3_gadget_ep_disable(dwc->eps[0]);
1449
1450err0:
1451 spin_unlock_irqrestore(&dwc->lock, flags);
1452
1453 return ret;
1454}
1455
1456static int dwc3_gadget_stop(struct usb_gadget *g,
1457 struct usb_gadget_driver *driver)
1458{
1459 struct dwc3 *dwc = gadget_to_dwc(g);
1460 unsigned long flags;
1461
1462 spin_lock_irqsave(&dwc->lock, flags);
1463
1464 __dwc3_gadget_ep_disable(dwc->eps[0]);
1465 __dwc3_gadget_ep_disable(dwc->eps[1]);
1466
1467 dwc->gadget_driver = NULL;
1468 dwc->gadget.dev.driver = NULL;
1469
1470 spin_unlock_irqrestore(&dwc->lock, flags);
1471
1472 return 0;
1473}
1474static const struct usb_gadget_ops dwc3_gadget_ops = {
1475 .get_frame = dwc3_gadget_get_frame,
1476 .wakeup = dwc3_gadget_wakeup,
1477 .set_selfpowered = dwc3_gadget_set_selfpowered,
1478 .pullup = dwc3_gadget_pullup,
1479 .udc_start = dwc3_gadget_start,
1480 .udc_stop = dwc3_gadget_stop,
1481};
1482
1483/* -------------------------------------------------------------------------- */
1484
1485static int __devinit dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1486{
1487 struct dwc3_ep *dep;
1488 u8 epnum;
1489
1490 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1491
1492 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1493 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1494 if (!dep) {
1495 dev_err(dwc->dev, "can't allocate endpoint %d\n",
1496 epnum);
1497 return -ENOMEM;
1498 }
1499
1500 dep->dwc = dwc;
1501 dep->number = epnum;
1502 dwc->eps[epnum] = dep;
1503
1504 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1505 (epnum & 1) ? "in" : "out");
1506 dep->endpoint.name = dep->name;
1507 dep->direction = (epnum & 1);
1508
1509 if (epnum == 0 || epnum == 1) {
1510 dep->endpoint.maxpacket = 512;
1511 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1512 if (!epnum)
1513 dwc->gadget.ep0 = &dep->endpoint;
1514 } else {
1515 int ret;
1516
1517 dep->endpoint.maxpacket = 1024;
1518 dep->endpoint.max_streams = 15;
1519 dep->endpoint.ops = &dwc3_gadget_ep_ops;
1520 list_add_tail(&dep->endpoint.ep_list,
1521 &dwc->gadget.ep_list);
1522
1523 ret = dwc3_alloc_trb_pool(dep);
1524 if (ret)
1525 return ret;
1526 }
1527
1528 INIT_LIST_HEAD(&dep->request_list);
1529 INIT_LIST_HEAD(&dep->req_queued);
1530 }
1531
1532 return 0;
1533}
1534
1535static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1536{
1537 struct dwc3_ep *dep;
1538 u8 epnum;
1539
1540 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1541 dep = dwc->eps[epnum];
1542 dwc3_free_trb_pool(dep);
1543
1544 if (epnum != 0 && epnum != 1)
1545 list_del(&dep->endpoint.ep_list);
1546
1547 kfree(dep);
1548 }
1549}
1550
1551static void dwc3_gadget_release(struct device *dev)
1552{
1553 dev_dbg(dev, "%s\n", __func__);
1554}
1555
1556/* -------------------------------------------------------------------------- */
1557static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1558 const struct dwc3_event_depevt *event, int status)
1559{
1560 struct dwc3_request *req;
1561 struct dwc3_trb *trb;
1562 unsigned int count;
1563 unsigned int s_pkt = 0;
1564
1565 do {
1566 req = next_request(&dep->req_queued);
1567 if (!req) {
1568 WARN_ON_ONCE(1);
1569 return 1;
1570 }
1571
1572 trb = req->trb;
1573
1574 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1575 /*
1576 * We continue despite the error. There is not much we
1577 * can do. If we don't clean it up we loop forever. If
1578 * we skip the TRB then it gets overwritten after a
1579 * while since we use them in a ring buffer. A BUG()
1580 * would help. Lets hope that if this occurs, someone
1581 * fixes the root cause instead of looking away :)
1582 */
1583 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1584 dep->name, req->trb);
1585 count = trb->size & DWC3_TRB_SIZE_MASK;
1586
1587 if (dep->direction) {
1588 if (count) {
1589 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1590 dep->name);
1591 status = -ECONNRESET;
1592 }
1593 } else {
1594 if (count && (event->status & DEPEVT_STATUS_SHORT))
1595 s_pkt = 1;
1596 }
1597
1598 /*
1599 * We assume here we will always receive the entire data block
1600 * which we should receive. Meaning, if we program RX to
1601 * receive 4K but we receive only 2K, we assume that's all we
1602 * should receive and we simply bounce the request back to the
1603 * gadget driver for further processing.
1604 */
1605 req->request.actual += req->request.length - count;
1606 dwc3_gadget_giveback(dep, req, status);
1607 if (s_pkt)
1608 break;
1609 if ((event->status & DEPEVT_STATUS_LST) &&
1610 (trb->ctrl & DWC3_TRB_CTRL_LST))
1611 break;
1612 if ((event->status & DEPEVT_STATUS_IOC) &&
1613 (trb->ctrl & DWC3_TRB_CTRL_IOC))
1614 break;
1615 } while (1);
1616
1617 if ((event->status & DEPEVT_STATUS_IOC) &&
1618 (trb->ctrl & DWC3_TRB_CTRL_IOC))
1619 return 0;
1620 return 1;
1621}
1622
1623static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1624 struct dwc3_ep *dep, const struct dwc3_event_depevt *event,
1625 int start_new)
1626{
1627 unsigned status = 0;
1628 int clean_busy;
1629
1630 if (event->status & DEPEVT_STATUS_BUSERR)
1631 status = -ECONNRESET;
1632
1633 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
1634 if (clean_busy)
1635 dep->flags &= ~DWC3_EP_BUSY;
1636
1637 /*
1638 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1639 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1640 */
1641 if (dwc->revision < DWC3_REVISION_183A) {
1642 u32 reg;
1643 int i;
1644
1645 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
1646 struct dwc3_ep *dep = dwc->eps[i];
1647
1648 if (!(dep->flags & DWC3_EP_ENABLED))
1649 continue;
1650
1651 if (!list_empty(&dep->req_queued))
1652 return;
1653 }
1654
1655 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1656 reg |= dwc->u1u2;
1657 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1658
1659 dwc->u1u2 = 0;
1660 }
1661}
1662
1663static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1664 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1665{
1666 u32 uf, mask;
1667
1668 if (list_empty(&dep->request_list)) {
1669 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
1670 dep->name);
1671 return;
1672 }
1673
1674 mask = ~(dep->interval - 1);
1675 uf = event->parameters & mask;
1676 /* 4 micro frames in the future */
1677 uf += dep->interval * 4;
1678
1679 __dwc3_gadget_kick_transfer(dep, uf, 1);
1680}
1681
1682static void dwc3_process_ep_cmd_complete(struct dwc3_ep *dep,
1683 const struct dwc3_event_depevt *event)
1684{
1685 struct dwc3 *dwc = dep->dwc;
1686 struct dwc3_event_depevt mod_ev = *event;
1687
1688 /*
1689 * We were asked to remove one request. It is possible that this
1690 * request and a few others were started together and have the same
1691 * transfer index. Since we stopped the complete endpoint we don't
1692 * know how many requests were already completed (and not yet)
1693 * reported and how could be done (later). We purge them all until
1694 * the end of the list.
1695 */
1696 mod_ev.status = DEPEVT_STATUS_LST;
1697 dwc3_cleanup_done_reqs(dwc, dep, &mod_ev, -ESHUTDOWN);
1698 dep->flags &= ~DWC3_EP_BUSY;
1699 /* pending requests are ignored and are queued on XferNotReady */
1700}
1701
1702static void dwc3_ep_cmd_compl(struct dwc3_ep *dep,
1703 const struct dwc3_event_depevt *event)
1704{
1705 u32 param = event->parameters;
1706 u32 cmd_type = (param >> 8) & ((1 << 5) - 1);
1707
1708 switch (cmd_type) {
1709 case DWC3_DEPCMD_ENDTRANSFER:
1710 dwc3_process_ep_cmd_complete(dep, event);
1711 break;
1712 case DWC3_DEPCMD_STARTTRANSFER:
1713 dep->res_trans_idx = param & 0x7f;
1714 break;
1715 default:
1716 printk(KERN_ERR "%s() unknown /unexpected type: %d\n",
1717 __func__, cmd_type);
1718 break;
1719 };
1720}
1721
1722static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
1723 const struct dwc3_event_depevt *event)
1724{
1725 struct dwc3_ep *dep;
1726 u8 epnum = event->endpoint_number;
1727
1728 dep = dwc->eps[epnum];
1729
1730 dev_vdbg(dwc->dev, "%s: %s\n", dep->name,
1731 dwc3_ep_event_string(event->endpoint_event));
1732
1733 if (epnum == 0 || epnum == 1) {
1734 dwc3_ep0_interrupt(dwc, event);
1735 return;
1736 }
1737
1738 switch (event->endpoint_event) {
1739 case DWC3_DEPEVT_XFERCOMPLETE:
1740 dep->res_trans_idx = 0;
1741
1742 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1743 dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
1744 dep->name);
1745 return;
1746 }
1747
1748 dwc3_endpoint_transfer_complete(dwc, dep, event, 1);
1749 break;
1750 case DWC3_DEPEVT_XFERINPROGRESS:
1751 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1752 dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n",
1753 dep->name);
1754 return;
1755 }
1756
1757 dwc3_endpoint_transfer_complete(dwc, dep, event, 0);
1758 break;
1759 case DWC3_DEPEVT_XFERNOTREADY:
1760 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1761 dwc3_gadget_start_isoc(dwc, dep, event);
1762 } else {
1763 int ret;
1764
1765 dev_vdbg(dwc->dev, "%s: reason %s\n",
1766 dep->name, event->status &
1767 DEPEVT_STATUS_TRANSFER_ACTIVE
1768 ? "Transfer Active"
1769 : "Transfer Not Active");
1770
1771 ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
1772 if (!ret || ret == -EBUSY)
1773 return;
1774
1775 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1776 dep->name);
1777 }
1778
1779 break;
1780 case DWC3_DEPEVT_STREAMEVT:
1781 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
1782 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
1783 dep->name);
1784 return;
1785 }
1786
1787 switch (event->status) {
1788 case DEPEVT_STREAMEVT_FOUND:
1789 dev_vdbg(dwc->dev, "Stream %d found and started\n",
1790 event->parameters);
1791
1792 break;
1793 case DEPEVT_STREAMEVT_NOTFOUND:
1794 /* FALLTHROUGH */
1795 default:
1796 dev_dbg(dwc->dev, "Couldn't find suitable stream\n");
1797 }
1798 break;
1799 case DWC3_DEPEVT_RXTXFIFOEVT:
1800 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
1801 break;
1802 case DWC3_DEPEVT_EPCMDCMPLT:
1803 dwc3_ep_cmd_compl(dep, event);
1804 break;
1805 }
1806}
1807
1808static void dwc3_disconnect_gadget(struct dwc3 *dwc)
1809{
1810 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
1811 spin_unlock(&dwc->lock);
1812 dwc->gadget_driver->disconnect(&dwc->gadget);
1813 spin_lock(&dwc->lock);
1814 }
1815}
1816
1817static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum)
1818{
1819 struct dwc3_ep *dep;
1820 struct dwc3_gadget_ep_cmd_params params;
1821 u32 cmd;
1822 int ret;
1823
1824 dep = dwc->eps[epnum];
1825
1826 WARN_ON(!dep->res_trans_idx);
1827 if (dep->res_trans_idx) {
1828 cmd = DWC3_DEPCMD_ENDTRANSFER;
1829 cmd |= DWC3_DEPCMD_HIPRI_FORCERM | DWC3_DEPCMD_CMDIOC;
1830 cmd |= DWC3_DEPCMD_PARAM(dep->res_trans_idx);
1831 memset(¶ms, 0, sizeof(params));
1832 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
1833 WARN_ON_ONCE(ret);
1834 dep->res_trans_idx = 0;
1835 }
1836}
1837
1838static void dwc3_stop_active_transfers(struct dwc3 *dwc)
1839{
1840 u32 epnum;
1841
1842 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1843 struct dwc3_ep *dep;
1844
1845 dep = dwc->eps[epnum];
1846 if (!(dep->flags & DWC3_EP_ENABLED))
1847 continue;
1848
1849 dwc3_remove_requests(dwc, dep);
1850 }
1851}
1852
1853static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
1854{
1855 u32 epnum;
1856
1857 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1858 struct dwc3_ep *dep;
1859 struct dwc3_gadget_ep_cmd_params params;
1860 int ret;
1861
1862 dep = dwc->eps[epnum];
1863
1864 if (!(dep->flags & DWC3_EP_STALL))
1865 continue;
1866
1867 dep->flags &= ~DWC3_EP_STALL;
1868
1869 memset(¶ms, 0, sizeof(params));
1870 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1871 DWC3_DEPCMD_CLEARSTALL, ¶ms);
1872 WARN_ON_ONCE(ret);
1873 }
1874}
1875
1876static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
1877{
1878 dev_vdbg(dwc->dev, "%s\n", __func__);
1879#if 0
1880 XXX
1881 U1/U2 is powersave optimization. Skip it for now. Anyway we need to
1882 enable it before we can disable it.
1883
1884 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1885 reg &= ~DWC3_DCTL_INITU1ENA;
1886 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1887
1888 reg &= ~DWC3_DCTL_INITU2ENA;
1889 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1890#endif
1891
1892 dwc3_stop_active_transfers(dwc);
1893 dwc3_disconnect_gadget(dwc);
1894 dwc->start_config_issued = false;
1895
1896 dwc->gadget.speed = USB_SPEED_UNKNOWN;
1897 dwc->setup_packet_pending = false;
1898}
1899
1900static void dwc3_gadget_usb3_phy_power(struct dwc3 *dwc, int on)
1901{
1902 u32 reg;
1903
1904 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
1905
1906 if (on)
1907 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
1908 else
1909 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
1910
1911 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
1912}
1913
1914static void dwc3_gadget_usb2_phy_power(struct dwc3 *dwc, int on)
1915{
1916 u32 reg;
1917
1918 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1919
1920 if (on)
1921 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
1922 else
1923 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
1924
1925 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1926}
1927
1928static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
1929{
1930 u32 reg;
1931
1932 dev_vdbg(dwc->dev, "%s\n", __func__);
1933
1934 /*
1935 * WORKAROUND: DWC3 revisions <1.88a have an issue which
1936 * would cause a missing Disconnect Event if there's a
1937 * pending Setup Packet in the FIFO.
1938 *
1939 * There's no suggested workaround on the official Bug
1940 * report, which states that "unless the driver/application
1941 * is doing any special handling of a disconnect event,
1942 * there is no functional issue".
1943 *
1944 * Unfortunately, it turns out that we _do_ some special
1945 * handling of a disconnect event, namely complete all
1946 * pending transfers, notify gadget driver of the
1947 * disconnection, and so on.
1948 *
1949 * Our suggested workaround is to follow the Disconnect
1950 * Event steps here, instead, based on a setup_packet_pending
1951 * flag. Such flag gets set whenever we have a XferNotReady
1952 * event on EP0 and gets cleared on XferComplete for the
1953 * same endpoint.
1954 *
1955 * Refers to:
1956 *
1957 * STAR#9000466709: RTL: Device : Disconnect event not
1958 * generated if setup packet pending in FIFO
1959 */
1960 if (dwc->revision < DWC3_REVISION_188A) {
1961 if (dwc->setup_packet_pending)
1962 dwc3_gadget_disconnect_interrupt(dwc);
1963 }
1964
1965 /* after reset -> Default State */
1966 dwc->dev_state = DWC3_DEFAULT_STATE;
1967
1968 /* Enable PHYs */
1969 dwc3_gadget_usb2_phy_power(dwc, true);
1970 dwc3_gadget_usb3_phy_power(dwc, true);
1971
1972 if (dwc->gadget.speed != USB_SPEED_UNKNOWN)
1973 dwc3_disconnect_gadget(dwc);
1974
1975 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1976 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
1977 reg &= ~(DWC3_DCTL_INITU1ENA | DWC3_DCTL_INITU2ENA);
1978 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1979 dwc->test_mode = false;
1980
1981 dwc3_stop_active_transfers(dwc);
1982 dwc3_clear_stall_all_ep(dwc);
1983 dwc->start_config_issued = false;
1984
1985 /* Reset device address to zero */
1986 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1987 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
1988 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1989}
1990
1991static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
1992{
1993 u32 reg;
1994 u32 usb30_clock = DWC3_GCTL_CLK_BUS;
1995
1996 /*
1997 * We change the clock only at SS but I dunno why I would want to do
1998 * this. Maybe it becomes part of the power saving plan.
1999 */
2000
2001 if (speed != DWC3_DSTS_SUPERSPEED)
2002 return;
2003
2004 /*
2005 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2006 * each time on Connect Done.
2007 */
2008 if (!usb30_clock)
2009 return;
2010
2011 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2012 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2013 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2014}
2015
2016static void dwc3_gadget_disable_phy(struct dwc3 *dwc, u8 speed)
2017{
2018 switch (speed) {
2019 case USB_SPEED_SUPER:
2020 dwc3_gadget_usb2_phy_power(dwc, false);
2021 break;
2022 case USB_SPEED_HIGH:
2023 case USB_SPEED_FULL:
2024 case USB_SPEED_LOW:
2025 dwc3_gadget_usb3_phy_power(dwc, false);
2026 break;
2027 }
2028}
2029
2030static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2031{
2032 struct dwc3_gadget_ep_cmd_params params;
2033 struct dwc3_ep *dep;
2034 int ret;
2035 u32 reg;
2036 u8 speed;
2037
2038 dev_vdbg(dwc->dev, "%s\n", __func__);
2039
2040 memset(¶ms, 0x00, sizeof(params));
2041
2042 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2043 speed = reg & DWC3_DSTS_CONNECTSPD;
2044 dwc->speed = speed;
2045
2046 dwc3_update_ram_clk_sel(dwc, speed);
2047
2048 switch (speed) {
2049 case DWC3_DCFG_SUPERSPEED:
2050 /*
2051 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2052 * would cause a missing USB3 Reset event.
2053 *
2054 * In such situations, we should force a USB3 Reset
2055 * event by calling our dwc3_gadget_reset_interrupt()
2056 * routine.
2057 *
2058 * Refers to:
2059 *
2060 * STAR#9000483510: RTL: SS : USB3 reset event may
2061 * not be generated always when the link enters poll
2062 */
2063 if (dwc->revision < DWC3_REVISION_190A)
2064 dwc3_gadget_reset_interrupt(dwc);
2065
2066 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2067 dwc->gadget.ep0->maxpacket = 512;
2068 dwc->gadget.speed = USB_SPEED_SUPER;
2069 break;
2070 case DWC3_DCFG_HIGHSPEED:
2071 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2072 dwc->gadget.ep0->maxpacket = 64;
2073 dwc->gadget.speed = USB_SPEED_HIGH;
2074 break;
2075 case DWC3_DCFG_FULLSPEED2:
2076 case DWC3_DCFG_FULLSPEED1:
2077 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2078 dwc->gadget.ep0->maxpacket = 64;
2079 dwc->gadget.speed = USB_SPEED_FULL;
2080 break;
2081 case DWC3_DCFG_LOWSPEED:
2082 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2083 dwc->gadget.ep0->maxpacket = 8;
2084 dwc->gadget.speed = USB_SPEED_LOW;
2085 break;
2086 }
2087
2088 /* Disable unneded PHY */
2089 dwc3_gadget_disable_phy(dwc, dwc->gadget.speed);
2090
2091 dep = dwc->eps[0];
2092 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
2093 if (ret) {
2094 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2095 return;
2096 }
2097
2098 dep = dwc->eps[1];
2099 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
2100 if (ret) {
2101 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2102 return;
2103 }
2104
2105 /*
2106 * Configure PHY via GUSB3PIPECTLn if required.
2107 *
2108 * Update GTXFIFOSIZn
2109 *
2110 * In both cases reset values should be sufficient.
2111 */
2112}
2113
2114static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2115{
2116 dev_vdbg(dwc->dev, "%s\n", __func__);
2117
2118 /*
2119 * TODO take core out of low power mode when that's
2120 * implemented.
2121 */
2122
2123 dwc->gadget_driver->resume(&dwc->gadget);
2124}
2125
2126static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2127 unsigned int evtinfo)
2128{
2129 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2130
2131 /*
2132 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2133 * on the link partner, the USB session might do multiple entry/exit
2134 * of low power states before a transfer takes place.
2135 *
2136 * Due to this problem, we might experience lower throughput. The
2137 * suggested workaround is to disable DCTL[12:9] bits if we're
2138 * transitioning from U1/U2 to U0 and enable those bits again
2139 * after a transfer completes and there are no pending transfers
2140 * on any of the enabled endpoints.
2141 *
2142 * This is the first half of that workaround.
2143 *
2144 * Refers to:
2145 *
2146 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2147 * core send LGO_Ux entering U0
2148 */
2149 if (dwc->revision < DWC3_REVISION_183A) {
2150 if (next == DWC3_LINK_STATE_U0) {
2151 u32 u1u2;
2152 u32 reg;
2153
2154 switch (dwc->link_state) {
2155 case DWC3_LINK_STATE_U1:
2156 case DWC3_LINK_STATE_U2:
2157 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2158 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2159 | DWC3_DCTL_ACCEPTU2ENA
2160 | DWC3_DCTL_INITU1ENA
2161 | DWC3_DCTL_ACCEPTU1ENA);
2162
2163 if (!dwc->u1u2)
2164 dwc->u1u2 = reg & u1u2;
2165
2166 reg &= ~u1u2;
2167
2168 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2169 break;
2170 default:
2171 /* do nothing */
2172 break;
2173 }
2174 }
2175 }
2176
2177 dwc->link_state = next;
2178
2179 dev_vdbg(dwc->dev, "%s link %d\n", __func__, dwc->link_state);
2180}
2181
2182static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2183 const struct dwc3_event_devt *event)
2184{
2185 switch (event->type) {
2186 case DWC3_DEVICE_EVENT_DISCONNECT:
2187 dwc3_gadget_disconnect_interrupt(dwc);
2188 break;
2189 case DWC3_DEVICE_EVENT_RESET:
2190 dwc3_gadget_reset_interrupt(dwc);
2191 break;
2192 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2193 dwc3_gadget_conndone_interrupt(dwc);
2194 break;
2195 case DWC3_DEVICE_EVENT_WAKEUP:
2196 dwc3_gadget_wakeup_interrupt(dwc);
2197 break;
2198 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2199 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2200 break;
2201 case DWC3_DEVICE_EVENT_EOPF:
2202 dev_vdbg(dwc->dev, "End of Periodic Frame\n");
2203 break;
2204 case DWC3_DEVICE_EVENT_SOF:
2205 dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
2206 break;
2207 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2208 dev_vdbg(dwc->dev, "Erratic Error\n");
2209 break;
2210 case DWC3_DEVICE_EVENT_CMD_CMPL:
2211 dev_vdbg(dwc->dev, "Command Complete\n");
2212 break;
2213 case DWC3_DEVICE_EVENT_OVERFLOW:
2214 dev_vdbg(dwc->dev, "Overflow\n");
2215 break;
2216 default:
2217 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2218 }
2219}
2220
2221static void dwc3_process_event_entry(struct dwc3 *dwc,
2222 const union dwc3_event *event)
2223{
2224 /* Endpoint IRQ, handle it and return early */
2225 if (event->type.is_devspec == 0) {
2226 /* depevt */
2227 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2228 }
2229
2230 switch (event->type.type) {
2231 case DWC3_EVENT_TYPE_DEV:
2232 dwc3_gadget_interrupt(dwc, &event->devt);
2233 break;
2234 /* REVISIT what to do with Carkit and I2C events ? */
2235 default:
2236 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2237 }
2238}
2239
2240static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
2241{
2242 struct dwc3_event_buffer *evt;
2243 int left;
2244 u32 count;
2245
2246 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2247 count &= DWC3_GEVNTCOUNT_MASK;
2248 if (!count)
2249 return IRQ_NONE;
2250
2251 evt = dwc->ev_buffs[buf];
2252 left = count;
2253
2254 while (left > 0) {
2255 union dwc3_event event;
2256
2257 event.raw = *(u32 *) (evt->buf + evt->lpos);
2258
2259 dwc3_process_event_entry(dwc, &event);
2260 /*
2261 * XXX we wrap around correctly to the next entry as almost all
2262 * entries are 4 bytes in size. There is one entry which has 12
2263 * bytes which is a regular entry followed by 8 bytes data. ATM
2264 * I don't know how things are organized if were get next to the
2265 * a boundary so I worry about that once we try to handle that.
2266 */
2267 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2268 left -= 4;
2269
2270 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
2271 }
2272
2273 return IRQ_HANDLED;
2274}
2275
2276static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2277{
2278 struct dwc3 *dwc = _dwc;
2279 int i;
2280 irqreturn_t ret = IRQ_NONE;
2281
2282 spin_lock(&dwc->lock);
2283
2284 for (i = 0; i < dwc->num_event_buffers; i++) {
2285 irqreturn_t status;
2286
2287 status = dwc3_process_event_buf(dwc, i);
2288 if (status == IRQ_HANDLED)
2289 ret = status;
2290 }
2291
2292 spin_unlock(&dwc->lock);
2293
2294 return ret;
2295}
2296
2297/**
2298 * dwc3_gadget_init - Initializes gadget related registers
2299 * @dwc: pointer to our controller context structure
2300 *
2301 * Returns 0 on success otherwise negative errno.
2302 */
2303int __devinit dwc3_gadget_init(struct dwc3 *dwc)
2304{
2305 u32 reg;
2306 int ret;
2307 int irq;
2308
2309 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2310 &dwc->ctrl_req_addr, GFP_KERNEL);
2311 if (!dwc->ctrl_req) {
2312 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2313 ret = -ENOMEM;
2314 goto err0;
2315 }
2316
2317 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2318 &dwc->ep0_trb_addr, GFP_KERNEL);
2319 if (!dwc->ep0_trb) {
2320 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2321 ret = -ENOMEM;
2322 goto err1;
2323 }
2324
2325 dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
2326 if (!dwc->setup_buf) {
2327 dev_err(dwc->dev, "failed to allocate setup buffer\n");
2328 ret = -ENOMEM;
2329 goto err2;
2330 }
2331
2332 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
2333 DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2334 GFP_KERNEL);
2335 if (!dwc->ep0_bounce) {
2336 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2337 ret = -ENOMEM;
2338 goto err3;
2339 }
2340
2341 dev_set_name(&dwc->gadget.dev, "gadget");
2342
2343 dwc->gadget.ops = &dwc3_gadget_ops;
2344 dwc->gadget.max_speed = USB_SPEED_SUPER;
2345 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2346 dwc->gadget.dev.parent = dwc->dev;
2347 dwc->gadget.sg_supported = true;
2348
2349 dma_set_coherent_mask(&dwc->gadget.dev, dwc->dev->coherent_dma_mask);
2350
2351 dwc->gadget.dev.dma_parms = dwc->dev->dma_parms;
2352 dwc->gadget.dev.dma_mask = dwc->dev->dma_mask;
2353 dwc->gadget.dev.release = dwc3_gadget_release;
2354 dwc->gadget.name = "dwc3-gadget";
2355
2356 /*
2357 * REVISIT: Here we should clear all pending IRQs to be
2358 * sure we're starting from a well known location.
2359 */
2360
2361 ret = dwc3_gadget_init_endpoints(dwc);
2362 if (ret)
2363 goto err4;
2364
2365 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
2366
2367 ret = request_irq(irq, dwc3_interrupt, IRQF_SHARED,
2368 "dwc3", dwc);
2369 if (ret) {
2370 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
2371 irq, ret);
2372 goto err5;
2373 }
2374
2375 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2376 reg |= DWC3_DCFG_LPM_CAP;
2377 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2378
2379 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2380 reg |= DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA;
2381 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2382
2383 /* Enable all but Start and End of Frame IRQs */
2384 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
2385 DWC3_DEVTEN_EVNTOVERFLOWEN |
2386 DWC3_DEVTEN_CMDCMPLTEN |
2387 DWC3_DEVTEN_ERRTICERREN |
2388 DWC3_DEVTEN_WKUPEVTEN |
2389 DWC3_DEVTEN_ULSTCNGEN |
2390 DWC3_DEVTEN_CONNECTDONEEN |
2391 DWC3_DEVTEN_USBRSTEN |
2392 DWC3_DEVTEN_DISCONNEVTEN);
2393 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
2394
2395 ret = device_register(&dwc->gadget.dev);
2396 if (ret) {
2397 dev_err(dwc->dev, "failed to register gadget device\n");
2398 put_device(&dwc->gadget.dev);
2399 goto err6;
2400 }
2401
2402 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2403 if (ret) {
2404 dev_err(dwc->dev, "failed to register udc\n");
2405 goto err7;
2406 }
2407
2408 return 0;
2409
2410err7:
2411 device_unregister(&dwc->gadget.dev);
2412
2413err6:
2414 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2415 free_irq(irq, dwc);
2416
2417err5:
2418 dwc3_gadget_free_endpoints(dwc);
2419
2420err4:
2421 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2422 dwc->ep0_bounce, dwc->ep0_bounce_addr);
2423
2424err3:
2425 kfree(dwc->setup_buf);
2426
2427err2:
2428 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2429 dwc->ep0_trb, dwc->ep0_trb_addr);
2430
2431err1:
2432 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2433 dwc->ctrl_req, dwc->ctrl_req_addr);
2434
2435err0:
2436 return ret;
2437}
2438
2439void dwc3_gadget_exit(struct dwc3 *dwc)
2440{
2441 int irq;
2442
2443 usb_del_gadget_udc(&dwc->gadget);
2444 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
2445
2446 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2447 free_irq(irq, dwc);
2448
2449 dwc3_gadget_free_endpoints(dwc);
2450
2451 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2452 dwc->ep0_bounce, dwc->ep0_bounce_addr);
2453
2454 kfree(dwc->setup_buf);
2455
2456 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2457 dwc->ep0_trb, dwc->ep0_trb_addr);
2458
2459 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2460 dwc->ctrl_req, dwc->ctrl_req_addr);
2461
2462 device_unregister(&dwc->gadget.dev);
2463}