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1/*
2 * mfd.c: driver for High Speed UART device of Intel Medfield platform
3 *
4 * Refer pxa.c, 8250.c and some other drivers in drivers/serial/
5 *
6 * (C) Copyright 2010 Intel Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; version 2
11 * of the License.
12 */
13
14/* Notes:
15 * 1. DMA channel allocation: 0/1 channel are assigned to port 0,
16 * 2/3 chan to port 1, 4/5 chan to port 3. Even number chans
17 * are used for RX, odd chans for TX
18 *
19 * 2. The RI/DSR/DCD/DTR are not pinned out, DCD & DSR are always
20 * asserted, only when the HW is reset the DDCD and DDSR will
21 * be triggered
22 */
23
24#include <linux/module.h>
25#include <linux/init.h>
26#include <linux/console.h>
27#include <linux/sysrq.h>
28#include <linux/slab.h>
29#include <linux/serial_reg.h>
30#include <linux/circ_buf.h>
31#include <linux/delay.h>
32#include <linux/interrupt.h>
33#include <linux/tty.h>
34#include <linux/tty_flip.h>
35#include <linux/serial_core.h>
36#include <linux/serial_mfd.h>
37#include <linux/dma-mapping.h>
38#include <linux/pci.h>
39#include <linux/io.h>
40#include <linux/debugfs.h>
41
42#define HSU_DMA_BUF_SIZE 2048
43
44#define chan_readl(chan, offset) readl(chan->reg + offset)
45#define chan_writel(chan, offset, val) writel(val, chan->reg + offset)
46
47#define mfd_readl(obj, offset) readl(obj->reg + offset)
48#define mfd_writel(obj, offset, val) writel(val, obj->reg + offset)
49
50static int hsu_dma_enable;
51module_param(hsu_dma_enable, int, 0);
52MODULE_PARM_DESC(hsu_dma_enable,
53 "It is a bitmap to set working mode, if bit[x] is 1, then port[x] will work in DMA mode, otherwise in PIO mode.");
54
55struct hsu_dma_buffer {
56 u8 *buf;
57 dma_addr_t dma_addr;
58 u32 dma_size;
59 u32 ofs;
60};
61
62struct hsu_dma_chan {
63 u32 id;
64 enum dma_data_direction dirt;
65 struct uart_hsu_port *uport;
66 void __iomem *reg;
67};
68
69struct uart_hsu_port {
70 struct uart_port port;
71 unsigned char ier;
72 unsigned char lcr;
73 unsigned char mcr;
74 unsigned int lsr_break_flag;
75 char name[12];
76 int index;
77 struct device *dev;
78
79 struct hsu_dma_chan *txc;
80 struct hsu_dma_chan *rxc;
81 struct hsu_dma_buffer txbuf;
82 struct hsu_dma_buffer rxbuf;
83 int use_dma; /* flag for DMA/PIO */
84 int running;
85 int dma_tx_on;
86};
87
88/* Top level data structure of HSU */
89struct hsu_port {
90 void __iomem *reg;
91 unsigned long paddr;
92 unsigned long iolen;
93 u32 irq;
94
95 struct uart_hsu_port port[3];
96 struct hsu_dma_chan chans[10];
97
98 struct dentry *debugfs;
99};
100
101static inline unsigned int serial_in(struct uart_hsu_port *up, int offset)
102{
103 unsigned int val;
104
105 if (offset > UART_MSR) {
106 offset <<= 2;
107 val = readl(up->port.membase + offset);
108 } else
109 val = (unsigned int)readb(up->port.membase + offset);
110
111 return val;
112}
113
114static inline void serial_out(struct uart_hsu_port *up, int offset, int value)
115{
116 if (offset > UART_MSR) {
117 offset <<= 2;
118 writel(value, up->port.membase + offset);
119 } else {
120 unsigned char val = value & 0xff;
121 writeb(val, up->port.membase + offset);
122 }
123}
124
125#ifdef CONFIG_DEBUG_FS
126
127#define HSU_REGS_BUFSIZE 1024
128
129static int hsu_show_regs_open(struct inode *inode, struct file *file)
130{
131 file->private_data = inode->i_private;
132 return 0;
133}
134
135static ssize_t port_show_regs(struct file *file, char __user *user_buf,
136 size_t count, loff_t *ppos)
137{
138 struct uart_hsu_port *up = file->private_data;
139 char *buf;
140 u32 len = 0;
141 ssize_t ret;
142
143 buf = kzalloc(HSU_REGS_BUFSIZE, GFP_KERNEL);
144 if (!buf)
145 return 0;
146
147 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
148 "MFD HSU port[%d] regs:\n", up->index);
149
150 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
151 "=================================\n");
152 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
153 "IER: \t\t0x%08x\n", serial_in(up, UART_IER));
154 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
155 "IIR: \t\t0x%08x\n", serial_in(up, UART_IIR));
156 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
157 "LCR: \t\t0x%08x\n", serial_in(up, UART_LCR));
158 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
159 "MCR: \t\t0x%08x\n", serial_in(up, UART_MCR));
160 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
161 "LSR: \t\t0x%08x\n", serial_in(up, UART_LSR));
162 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
163 "MSR: \t\t0x%08x\n", serial_in(up, UART_MSR));
164 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
165 "FOR: \t\t0x%08x\n", serial_in(up, UART_FOR));
166 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
167 "PS: \t\t0x%08x\n", serial_in(up, UART_PS));
168 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
169 "MUL: \t\t0x%08x\n", serial_in(up, UART_MUL));
170 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
171 "DIV: \t\t0x%08x\n", serial_in(up, UART_DIV));
172
173 if (len > HSU_REGS_BUFSIZE)
174 len = HSU_REGS_BUFSIZE;
175
176 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
177 kfree(buf);
178 return ret;
179}
180
181static ssize_t dma_show_regs(struct file *file, char __user *user_buf,
182 size_t count, loff_t *ppos)
183{
184 struct hsu_dma_chan *chan = file->private_data;
185 char *buf;
186 u32 len = 0;
187 ssize_t ret;
188
189 buf = kzalloc(HSU_REGS_BUFSIZE, GFP_KERNEL);
190 if (!buf)
191 return 0;
192
193 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
194 "MFD HSU DMA channel [%d] regs:\n", chan->id);
195
196 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
197 "=================================\n");
198 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
199 "CR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_CR));
200 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
201 "DCR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_DCR));
202 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
203 "BSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_BSR));
204 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
205 "MOTSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_MOTSR));
206 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
207 "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D0SAR));
208 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
209 "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D0TSR));
210 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
211 "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D1SAR));
212 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
213 "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D1TSR));
214 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
215 "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D2SAR));
216 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
217 "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D2TSR));
218 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
219 "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D3SAR));
220 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
221 "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D3TSR));
222
223 if (len > HSU_REGS_BUFSIZE)
224 len = HSU_REGS_BUFSIZE;
225
226 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
227 kfree(buf);
228 return ret;
229}
230
231static const struct file_operations port_regs_ops = {
232 .owner = THIS_MODULE,
233 .open = hsu_show_regs_open,
234 .read = port_show_regs,
235 .llseek = default_llseek,
236};
237
238static const struct file_operations dma_regs_ops = {
239 .owner = THIS_MODULE,
240 .open = hsu_show_regs_open,
241 .read = dma_show_regs,
242 .llseek = default_llseek,
243};
244
245static int hsu_debugfs_init(struct hsu_port *hsu)
246{
247 int i;
248 char name[32];
249
250 hsu->debugfs = debugfs_create_dir("hsu", NULL);
251 if (!hsu->debugfs)
252 return -ENOMEM;
253
254 for (i = 0; i < 3; i++) {
255 snprintf(name, sizeof(name), "port_%d_regs", i);
256 debugfs_create_file(name, S_IFREG | S_IRUGO,
257 hsu->debugfs, (void *)(&hsu->port[i]), &port_regs_ops);
258 }
259
260 for (i = 0; i < 6; i++) {
261 snprintf(name, sizeof(name), "dma_chan_%d_regs", i);
262 debugfs_create_file(name, S_IFREG | S_IRUGO,
263 hsu->debugfs, (void *)&hsu->chans[i], &dma_regs_ops);
264 }
265
266 return 0;
267}
268
269static void hsu_debugfs_remove(struct hsu_port *hsu)
270{
271 if (hsu->debugfs)
272 debugfs_remove_recursive(hsu->debugfs);
273}
274
275#else
276static inline int hsu_debugfs_init(struct hsu_port *hsu)
277{
278 return 0;
279}
280
281static inline void hsu_debugfs_remove(struct hsu_port *hsu)
282{
283}
284#endif /* CONFIG_DEBUG_FS */
285
286static void serial_hsu_enable_ms(struct uart_port *port)
287{
288 struct uart_hsu_port *up =
289 container_of(port, struct uart_hsu_port, port);
290
291 up->ier |= UART_IER_MSI;
292 serial_out(up, UART_IER, up->ier);
293}
294
295void hsu_dma_tx(struct uart_hsu_port *up)
296{
297 struct circ_buf *xmit = &up->port.state->xmit;
298 struct hsu_dma_buffer *dbuf = &up->txbuf;
299 int count;
300
301 /* test_and_set_bit may be better, but anyway it's in lock protected mode */
302 if (up->dma_tx_on)
303 return;
304
305 /* Update the circ buf info */
306 xmit->tail += dbuf->ofs;
307 xmit->tail &= UART_XMIT_SIZE - 1;
308
309 up->port.icount.tx += dbuf->ofs;
310 dbuf->ofs = 0;
311
312 /* Disable the channel */
313 chan_writel(up->txc, HSU_CH_CR, 0x0);
314
315 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&up->port)) {
316 dma_sync_single_for_device(up->port.dev,
317 dbuf->dma_addr,
318 dbuf->dma_size,
319 DMA_TO_DEVICE);
320
321 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
322 dbuf->ofs = count;
323
324 /* Reprogram the channel */
325 chan_writel(up->txc, HSU_CH_D0SAR, dbuf->dma_addr + xmit->tail);
326 chan_writel(up->txc, HSU_CH_D0TSR, count);
327
328 /* Reenable the channel */
329 chan_writel(up->txc, HSU_CH_DCR, 0x1
330 | (0x1 << 8)
331 | (0x1 << 16)
332 | (0x1 << 24));
333 up->dma_tx_on = 1;
334 chan_writel(up->txc, HSU_CH_CR, 0x1);
335 }
336
337 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
338 uart_write_wakeup(&up->port);
339}
340
341/* The buffer is already cache coherent */
342void hsu_dma_start_rx_chan(struct hsu_dma_chan *rxc, struct hsu_dma_buffer *dbuf)
343{
344 dbuf->ofs = 0;
345
346 chan_writel(rxc, HSU_CH_BSR, 32);
347 chan_writel(rxc, HSU_CH_MOTSR, 4);
348
349 chan_writel(rxc, HSU_CH_D0SAR, dbuf->dma_addr);
350 chan_writel(rxc, HSU_CH_D0TSR, dbuf->dma_size);
351 chan_writel(rxc, HSU_CH_DCR, 0x1 | (0x1 << 8)
352 | (0x1 << 16)
353 | (0x1 << 24) /* timeout bit, see HSU Errata 1 */
354 );
355 chan_writel(rxc, HSU_CH_CR, 0x3);
356}
357
358/* Protected by spin_lock_irqsave(port->lock) */
359static void serial_hsu_start_tx(struct uart_port *port)
360{
361 struct uart_hsu_port *up =
362 container_of(port, struct uart_hsu_port, port);
363
364 if (up->use_dma) {
365 hsu_dma_tx(up);
366 } else if (!(up->ier & UART_IER_THRI)) {
367 up->ier |= UART_IER_THRI;
368 serial_out(up, UART_IER, up->ier);
369 }
370}
371
372static void serial_hsu_stop_tx(struct uart_port *port)
373{
374 struct uart_hsu_port *up =
375 container_of(port, struct uart_hsu_port, port);
376 struct hsu_dma_chan *txc = up->txc;
377
378 if (up->use_dma)
379 chan_writel(txc, HSU_CH_CR, 0x0);
380 else if (up->ier & UART_IER_THRI) {
381 up->ier &= ~UART_IER_THRI;
382 serial_out(up, UART_IER, up->ier);
383 }
384}
385
386/* This is always called in spinlock protected mode, so
387 * modify timeout timer is safe here */
388void hsu_dma_rx(struct uart_hsu_port *up, u32 int_sts)
389{
390 struct hsu_dma_buffer *dbuf = &up->rxbuf;
391 struct hsu_dma_chan *chan = up->rxc;
392 struct uart_port *port = &up->port;
393 struct tty_struct *tty = port->state->port.tty;
394 int count;
395
396 if (!tty)
397 return;
398
399 /*
400 * First need to know how many is already transferred,
401 * then check if its a timeout DMA irq, and return
402 * the trail bytes out, push them up and reenable the
403 * channel
404 */
405
406 /* Timeout IRQ, need wait some time, see Errata 2 */
407 if (int_sts & 0xf00)
408 udelay(2);
409
410 /* Stop the channel */
411 chan_writel(chan, HSU_CH_CR, 0x0);
412
413 count = chan_readl(chan, HSU_CH_D0SAR) - dbuf->dma_addr;
414 if (!count) {
415 /* Restart the channel before we leave */
416 chan_writel(chan, HSU_CH_CR, 0x3);
417 return;
418 }
419
420 dma_sync_single_for_cpu(port->dev, dbuf->dma_addr,
421 dbuf->dma_size, DMA_FROM_DEVICE);
422
423 /*
424 * Head will only wrap around when we recycle
425 * the DMA buffer, and when that happens, we
426 * explicitly set tail to 0. So head will
427 * always be greater than tail.
428 */
429 tty_insert_flip_string(tty, dbuf->buf, count);
430 port->icount.rx += count;
431
432 dma_sync_single_for_device(up->port.dev, dbuf->dma_addr,
433 dbuf->dma_size, DMA_FROM_DEVICE);
434
435 /* Reprogram the channel */
436 chan_writel(chan, HSU_CH_D0SAR, dbuf->dma_addr);
437 chan_writel(chan, HSU_CH_D0TSR, dbuf->dma_size);
438 chan_writel(chan, HSU_CH_DCR, 0x1
439 | (0x1 << 8)
440 | (0x1 << 16)
441 | (0x1 << 24) /* timeout bit, see HSU Errata 1 */
442 );
443 tty_flip_buffer_push(tty);
444
445 chan_writel(chan, HSU_CH_CR, 0x3);
446
447}
448
449static void serial_hsu_stop_rx(struct uart_port *port)
450{
451 struct uart_hsu_port *up =
452 container_of(port, struct uart_hsu_port, port);
453 struct hsu_dma_chan *chan = up->rxc;
454
455 if (up->use_dma)
456 chan_writel(chan, HSU_CH_CR, 0x2);
457 else {
458 up->ier &= ~UART_IER_RLSI;
459 up->port.read_status_mask &= ~UART_LSR_DR;
460 serial_out(up, UART_IER, up->ier);
461 }
462}
463
464static inline void receive_chars(struct uart_hsu_port *up, int *status)
465{
466 struct tty_struct *tty = up->port.state->port.tty;
467 unsigned int ch, flag;
468 unsigned int max_count = 256;
469
470 if (!tty)
471 return;
472
473 do {
474 ch = serial_in(up, UART_RX);
475 flag = TTY_NORMAL;
476 up->port.icount.rx++;
477
478 if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE |
479 UART_LSR_FE | UART_LSR_OE))) {
480
481 dev_warn(up->dev, "We really rush into ERR/BI case"
482 "status = 0x%02x", *status);
483 /* For statistics only */
484 if (*status & UART_LSR_BI) {
485 *status &= ~(UART_LSR_FE | UART_LSR_PE);
486 up->port.icount.brk++;
487 /*
488 * We do the SysRQ and SAK checking
489 * here because otherwise the break
490 * may get masked by ignore_status_mask
491 * or read_status_mask.
492 */
493 if (uart_handle_break(&up->port))
494 goto ignore_char;
495 } else if (*status & UART_LSR_PE)
496 up->port.icount.parity++;
497 else if (*status & UART_LSR_FE)
498 up->port.icount.frame++;
499 if (*status & UART_LSR_OE)
500 up->port.icount.overrun++;
501
502 /* Mask off conditions which should be ignored. */
503 *status &= up->port.read_status_mask;
504
505#ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE
506 if (up->port.cons &&
507 up->port.cons->index == up->port.line) {
508 /* Recover the break flag from console xmit */
509 *status |= up->lsr_break_flag;
510 up->lsr_break_flag = 0;
511 }
512#endif
513 if (*status & UART_LSR_BI) {
514 flag = TTY_BREAK;
515 } else if (*status & UART_LSR_PE)
516 flag = TTY_PARITY;
517 else if (*status & UART_LSR_FE)
518 flag = TTY_FRAME;
519 }
520
521 if (uart_handle_sysrq_char(&up->port, ch))
522 goto ignore_char;
523
524 uart_insert_char(&up->port, *status, UART_LSR_OE, ch, flag);
525 ignore_char:
526 *status = serial_in(up, UART_LSR);
527 } while ((*status & UART_LSR_DR) && max_count--);
528 tty_flip_buffer_push(tty);
529}
530
531static void transmit_chars(struct uart_hsu_port *up)
532{
533 struct circ_buf *xmit = &up->port.state->xmit;
534 int count;
535
536 if (up->port.x_char) {
537 serial_out(up, UART_TX, up->port.x_char);
538 up->port.icount.tx++;
539 up->port.x_char = 0;
540 return;
541 }
542 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
543 serial_hsu_stop_tx(&up->port);
544 return;
545 }
546
547 /* The IRQ is for TX FIFO half-empty */
548 count = up->port.fifosize / 2;
549
550 do {
551 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
552 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
553
554 up->port.icount.tx++;
555 if (uart_circ_empty(xmit))
556 break;
557 } while (--count > 0);
558
559 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
560 uart_write_wakeup(&up->port);
561
562 if (uart_circ_empty(xmit))
563 serial_hsu_stop_tx(&up->port);
564}
565
566static inline void check_modem_status(struct uart_hsu_port *up)
567{
568 int status;
569
570 status = serial_in(up, UART_MSR);
571
572 if ((status & UART_MSR_ANY_DELTA) == 0)
573 return;
574
575 if (status & UART_MSR_TERI)
576 up->port.icount.rng++;
577 if (status & UART_MSR_DDSR)
578 up->port.icount.dsr++;
579 /* We may only get DDCD when HW init and reset */
580 if (status & UART_MSR_DDCD)
581 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
582 /* Will start/stop_tx accordingly */
583 if (status & UART_MSR_DCTS)
584 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
585
586 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
587}
588
589/*
590 * This handles the interrupt from one port.
591 */
592static irqreturn_t port_irq(int irq, void *dev_id)
593{
594 struct uart_hsu_port *up = dev_id;
595 unsigned int iir, lsr;
596 unsigned long flags;
597
598 if (unlikely(!up->running))
599 return IRQ_NONE;
600
601 spin_lock_irqsave(&up->port.lock, flags);
602 if (up->use_dma) {
603 lsr = serial_in(up, UART_LSR);
604 if (unlikely(lsr & (UART_LSR_BI | UART_LSR_PE |
605 UART_LSR_FE | UART_LSR_OE)))
606 dev_warn(up->dev,
607 "Got lsr irq while using DMA, lsr = 0x%2x\n",
608 lsr);
609 check_modem_status(up);
610 spin_unlock_irqrestore(&up->port.lock, flags);
611 return IRQ_HANDLED;
612 }
613
614 iir = serial_in(up, UART_IIR);
615 if (iir & UART_IIR_NO_INT) {
616 spin_unlock_irqrestore(&up->port.lock, flags);
617 return IRQ_NONE;
618 }
619
620 lsr = serial_in(up, UART_LSR);
621 if (lsr & UART_LSR_DR)
622 receive_chars(up, &lsr);
623 check_modem_status(up);
624
625 /* lsr will be renewed during the receive_chars */
626 if (lsr & UART_LSR_THRE)
627 transmit_chars(up);
628
629 spin_unlock_irqrestore(&up->port.lock, flags);
630 return IRQ_HANDLED;
631}
632
633static inline void dma_chan_irq(struct hsu_dma_chan *chan)
634{
635 struct uart_hsu_port *up = chan->uport;
636 unsigned long flags;
637 u32 int_sts;
638
639 spin_lock_irqsave(&up->port.lock, flags);
640
641 if (!up->use_dma || !up->running)
642 goto exit;
643
644 /*
645 * No matter what situation, need read clear the IRQ status
646 * There is a bug, see Errata 5, HSD 2900918
647 */
648 int_sts = chan_readl(chan, HSU_CH_SR);
649
650 /* Rx channel */
651 if (chan->dirt == DMA_FROM_DEVICE)
652 hsu_dma_rx(up, int_sts);
653
654 /* Tx channel */
655 if (chan->dirt == DMA_TO_DEVICE) {
656 chan_writel(chan, HSU_CH_CR, 0x0);
657 up->dma_tx_on = 0;
658 hsu_dma_tx(up);
659 }
660
661exit:
662 spin_unlock_irqrestore(&up->port.lock, flags);
663 return;
664}
665
666static irqreturn_t dma_irq(int irq, void *dev_id)
667{
668 struct hsu_port *hsu = dev_id;
669 u32 int_sts, i;
670
671 int_sts = mfd_readl(hsu, HSU_GBL_DMAISR);
672
673 /* Currently we only have 6 channels may be used */
674 for (i = 0; i < 6; i++) {
675 if (int_sts & 0x1)
676 dma_chan_irq(&hsu->chans[i]);
677 int_sts >>= 1;
678 }
679
680 return IRQ_HANDLED;
681}
682
683static unsigned int serial_hsu_tx_empty(struct uart_port *port)
684{
685 struct uart_hsu_port *up =
686 container_of(port, struct uart_hsu_port, port);
687 unsigned long flags;
688 unsigned int ret;
689
690 spin_lock_irqsave(&up->port.lock, flags);
691 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
692 spin_unlock_irqrestore(&up->port.lock, flags);
693
694 return ret;
695}
696
697static unsigned int serial_hsu_get_mctrl(struct uart_port *port)
698{
699 struct uart_hsu_port *up =
700 container_of(port, struct uart_hsu_port, port);
701 unsigned char status;
702 unsigned int ret;
703
704 status = serial_in(up, UART_MSR);
705
706 ret = 0;
707 if (status & UART_MSR_DCD)
708 ret |= TIOCM_CAR;
709 if (status & UART_MSR_RI)
710 ret |= TIOCM_RNG;
711 if (status & UART_MSR_DSR)
712 ret |= TIOCM_DSR;
713 if (status & UART_MSR_CTS)
714 ret |= TIOCM_CTS;
715 return ret;
716}
717
718static void serial_hsu_set_mctrl(struct uart_port *port, unsigned int mctrl)
719{
720 struct uart_hsu_port *up =
721 container_of(port, struct uart_hsu_port, port);
722 unsigned char mcr = 0;
723
724 if (mctrl & TIOCM_RTS)
725 mcr |= UART_MCR_RTS;
726 if (mctrl & TIOCM_DTR)
727 mcr |= UART_MCR_DTR;
728 if (mctrl & TIOCM_OUT1)
729 mcr |= UART_MCR_OUT1;
730 if (mctrl & TIOCM_OUT2)
731 mcr |= UART_MCR_OUT2;
732 if (mctrl & TIOCM_LOOP)
733 mcr |= UART_MCR_LOOP;
734
735 mcr |= up->mcr;
736
737 serial_out(up, UART_MCR, mcr);
738}
739
740static void serial_hsu_break_ctl(struct uart_port *port, int break_state)
741{
742 struct uart_hsu_port *up =
743 container_of(port, struct uart_hsu_port, port);
744 unsigned long flags;
745
746 spin_lock_irqsave(&up->port.lock, flags);
747 if (break_state == -1)
748 up->lcr |= UART_LCR_SBC;
749 else
750 up->lcr &= ~UART_LCR_SBC;
751 serial_out(up, UART_LCR, up->lcr);
752 spin_unlock_irqrestore(&up->port.lock, flags);
753}
754
755/*
756 * What special to do:
757 * 1. chose the 64B fifo mode
758 * 2. start dma or pio depends on configuration
759 * 3. we only allocate dma memory when needed
760 */
761static int serial_hsu_startup(struct uart_port *port)
762{
763 struct uart_hsu_port *up =
764 container_of(port, struct uart_hsu_port, port);
765 unsigned long flags;
766
767 /*
768 * Clear the FIFO buffers and disable them.
769 * (they will be reenabled in set_termios())
770 */
771 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
772 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
773 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
774 serial_out(up, UART_FCR, 0);
775
776 /* Clear the interrupt registers. */
777 (void) serial_in(up, UART_LSR);
778 (void) serial_in(up, UART_RX);
779 (void) serial_in(up, UART_IIR);
780 (void) serial_in(up, UART_MSR);
781
782 /* Now, initialize the UART, default is 8n1 */
783 serial_out(up, UART_LCR, UART_LCR_WLEN8);
784
785 spin_lock_irqsave(&up->port.lock, flags);
786
787 up->port.mctrl |= TIOCM_OUT2;
788 serial_hsu_set_mctrl(&up->port, up->port.mctrl);
789
790 /*
791 * Finally, enable interrupts. Note: Modem status interrupts
792 * are set via set_termios(), which will be occurring imminently
793 * anyway, so we don't enable them here.
794 */
795 if (!up->use_dma)
796 up->ier = UART_IER_RLSI | UART_IER_RDI | UART_IER_RTOIE;
797 else
798 up->ier = 0;
799 serial_out(up, UART_IER, up->ier);
800
801 spin_unlock_irqrestore(&up->port.lock, flags);
802
803 /* DMA init */
804 if (up->use_dma) {
805 struct hsu_dma_buffer *dbuf;
806 struct circ_buf *xmit = &port->state->xmit;
807
808 up->dma_tx_on = 0;
809
810 /* First allocate the RX buffer */
811 dbuf = &up->rxbuf;
812 dbuf->buf = kzalloc(HSU_DMA_BUF_SIZE, GFP_KERNEL);
813 if (!dbuf->buf) {
814 up->use_dma = 0;
815 goto exit;
816 }
817 dbuf->dma_addr = dma_map_single(port->dev,
818 dbuf->buf,
819 HSU_DMA_BUF_SIZE,
820 DMA_FROM_DEVICE);
821 dbuf->dma_size = HSU_DMA_BUF_SIZE;
822
823 /* Start the RX channel right now */
824 hsu_dma_start_rx_chan(up->rxc, dbuf);
825
826 /* Next init the TX DMA */
827 dbuf = &up->txbuf;
828 dbuf->buf = xmit->buf;
829 dbuf->dma_addr = dma_map_single(port->dev,
830 dbuf->buf,
831 UART_XMIT_SIZE,
832 DMA_TO_DEVICE);
833 dbuf->dma_size = UART_XMIT_SIZE;
834
835 /* This should not be changed all around */
836 chan_writel(up->txc, HSU_CH_BSR, 32);
837 chan_writel(up->txc, HSU_CH_MOTSR, 4);
838 dbuf->ofs = 0;
839 }
840
841exit:
842 /* And clear the interrupt registers again for luck. */
843 (void) serial_in(up, UART_LSR);
844 (void) serial_in(up, UART_RX);
845 (void) serial_in(up, UART_IIR);
846 (void) serial_in(up, UART_MSR);
847
848 up->running = 1;
849 return 0;
850}
851
852static void serial_hsu_shutdown(struct uart_port *port)
853{
854 struct uart_hsu_port *up =
855 container_of(port, struct uart_hsu_port, port);
856 unsigned long flags;
857
858 /* Disable interrupts from this port */
859 up->ier = 0;
860 serial_out(up, UART_IER, 0);
861 up->running = 0;
862
863 spin_lock_irqsave(&up->port.lock, flags);
864 up->port.mctrl &= ~TIOCM_OUT2;
865 serial_hsu_set_mctrl(&up->port, up->port.mctrl);
866 spin_unlock_irqrestore(&up->port.lock, flags);
867
868 /* Disable break condition and FIFOs */
869 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
870 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
871 UART_FCR_CLEAR_RCVR |
872 UART_FCR_CLEAR_XMIT);
873 serial_out(up, UART_FCR, 0);
874}
875
876static void
877serial_hsu_set_termios(struct uart_port *port, struct ktermios *termios,
878 struct ktermios *old)
879{
880 struct uart_hsu_port *up =
881 container_of(port, struct uart_hsu_port, port);
882 struct tty_struct *tty = port->state->port.tty;
883 unsigned char cval, fcr = 0;
884 unsigned long flags;
885 unsigned int baud, quot;
886 u32 ps, mul;
887
888 switch (termios->c_cflag & CSIZE) {
889 case CS5:
890 cval = UART_LCR_WLEN5;
891 break;
892 case CS6:
893 cval = UART_LCR_WLEN6;
894 break;
895 case CS7:
896 cval = UART_LCR_WLEN7;
897 break;
898 default:
899 case CS8:
900 cval = UART_LCR_WLEN8;
901 break;
902 }
903
904 /* CMSPAR isn't supported by this driver */
905 if (tty)
906 tty->termios->c_cflag &= ~CMSPAR;
907
908 if (termios->c_cflag & CSTOPB)
909 cval |= UART_LCR_STOP;
910 if (termios->c_cflag & PARENB)
911 cval |= UART_LCR_PARITY;
912 if (!(termios->c_cflag & PARODD))
913 cval |= UART_LCR_EPAR;
914
915 /*
916 * The base clk is 50Mhz, and the baud rate come from:
917 * baud = 50M * MUL / (DIV * PS * DLAB)
918 *
919 * For those basic low baud rate we can get the direct
920 * scalar from 2746800, like 115200 = 2746800/24. For those
921 * higher baud rate, we handle them case by case, mainly by
922 * adjusting the MUL/PS registers, and DIV register is kept
923 * as default value 0x3d09 to make things simple
924 */
925 baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
926
927 quot = 1;
928 ps = 0x10;
929 mul = 0x3600;
930 switch (baud) {
931 case 3500000:
932 mul = 0x3345;
933 ps = 0xC;
934 break;
935 case 1843200:
936 mul = 0x2400;
937 break;
938 case 3000000:
939 case 2500000:
940 case 2000000:
941 case 1500000:
942 case 1000000:
943 case 500000:
944 /* mul/ps/quot = 0x9C4/0x10/0x1 will make a 500000 bps */
945 mul = baud / 500000 * 0x9C4;
946 break;
947 default:
948 /* Use uart_get_divisor to get quot for other baud rates */
949 quot = 0;
950 }
951
952 if (!quot)
953 quot = uart_get_divisor(port, baud);
954
955 if ((up->port.uartclk / quot) < (2400 * 16))
956 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_1B;
957 else if ((up->port.uartclk / quot) < (230400 * 16))
958 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_16B;
959 else
960 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_32B;
961
962 fcr |= UART_FCR_HSU_64B_FIFO;
963
964 /*
965 * Ok, we're now changing the port state. Do it with
966 * interrupts disabled.
967 */
968 spin_lock_irqsave(&up->port.lock, flags);
969
970 /* Update the per-port timeout */
971 uart_update_timeout(port, termios->c_cflag, baud);
972
973 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
974 if (termios->c_iflag & INPCK)
975 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
976 if (termios->c_iflag & (BRKINT | PARMRK))
977 up->port.read_status_mask |= UART_LSR_BI;
978
979 /* Characters to ignore */
980 up->port.ignore_status_mask = 0;
981 if (termios->c_iflag & IGNPAR)
982 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
983 if (termios->c_iflag & IGNBRK) {
984 up->port.ignore_status_mask |= UART_LSR_BI;
985 /*
986 * If we're ignoring parity and break indicators,
987 * ignore overruns too (for real raw support).
988 */
989 if (termios->c_iflag & IGNPAR)
990 up->port.ignore_status_mask |= UART_LSR_OE;
991 }
992
993 /* Ignore all characters if CREAD is not set */
994 if ((termios->c_cflag & CREAD) == 0)
995 up->port.ignore_status_mask |= UART_LSR_DR;
996
997 /*
998 * CTS flow control flag and modem status interrupts, disable
999 * MSI by default
1000 */
1001 up->ier &= ~UART_IER_MSI;
1002 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
1003 up->ier |= UART_IER_MSI;
1004
1005 serial_out(up, UART_IER, up->ier);
1006
1007 if (termios->c_cflag & CRTSCTS)
1008 up->mcr |= UART_MCR_AFE | UART_MCR_RTS;
1009 else
1010 up->mcr &= ~UART_MCR_AFE;
1011
1012 serial_out(up, UART_LCR, cval | UART_LCR_DLAB); /* set DLAB */
1013 serial_out(up, UART_DLL, quot & 0xff); /* LS of divisor */
1014 serial_out(up, UART_DLM, quot >> 8); /* MS of divisor */
1015 serial_out(up, UART_LCR, cval); /* reset DLAB */
1016 serial_out(up, UART_MUL, mul); /* set MUL */
1017 serial_out(up, UART_PS, ps); /* set PS */
1018 up->lcr = cval; /* Save LCR */
1019 serial_hsu_set_mctrl(&up->port, up->port.mctrl);
1020 serial_out(up, UART_FCR, fcr);
1021 spin_unlock_irqrestore(&up->port.lock, flags);
1022}
1023
1024static void
1025serial_hsu_pm(struct uart_port *port, unsigned int state,
1026 unsigned int oldstate)
1027{
1028}
1029
1030static void serial_hsu_release_port(struct uart_port *port)
1031{
1032}
1033
1034static int serial_hsu_request_port(struct uart_port *port)
1035{
1036 return 0;
1037}
1038
1039static void serial_hsu_config_port(struct uart_port *port, int flags)
1040{
1041 struct uart_hsu_port *up =
1042 container_of(port, struct uart_hsu_port, port);
1043 up->port.type = PORT_MFD;
1044}
1045
1046static int
1047serial_hsu_verify_port(struct uart_port *port, struct serial_struct *ser)
1048{
1049 /* We don't want the core code to modify any port params */
1050 return -EINVAL;
1051}
1052
1053static const char *
1054serial_hsu_type(struct uart_port *port)
1055{
1056 struct uart_hsu_port *up =
1057 container_of(port, struct uart_hsu_port, port);
1058 return up->name;
1059}
1060
1061/* Mainly for uart console use */
1062static struct uart_hsu_port *serial_hsu_ports[3];
1063static struct uart_driver serial_hsu_reg;
1064
1065#ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE
1066
1067#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1068
1069/* Wait for transmitter & holding register to empty */
1070static inline void wait_for_xmitr(struct uart_hsu_port *up)
1071{
1072 unsigned int status, tmout = 1000;
1073
1074 /* Wait up to 1ms for the character to be sent. */
1075 do {
1076 status = serial_in(up, UART_LSR);
1077
1078 if (status & UART_LSR_BI)
1079 up->lsr_break_flag = UART_LSR_BI;
1080
1081 if (--tmout == 0)
1082 break;
1083 udelay(1);
1084 } while (!(status & BOTH_EMPTY));
1085
1086 /* Wait up to 1s for flow control if necessary */
1087 if (up->port.flags & UPF_CONS_FLOW) {
1088 tmout = 1000000;
1089 while (--tmout &&
1090 ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
1091 udelay(1);
1092 }
1093}
1094
1095static void serial_hsu_console_putchar(struct uart_port *port, int ch)
1096{
1097 struct uart_hsu_port *up =
1098 container_of(port, struct uart_hsu_port, port);
1099
1100 wait_for_xmitr(up);
1101 serial_out(up, UART_TX, ch);
1102}
1103
1104/*
1105 * Print a string to the serial port trying not to disturb
1106 * any possible real use of the port...
1107 *
1108 * The console_lock must be held when we get here.
1109 */
1110static void
1111serial_hsu_console_write(struct console *co, const char *s, unsigned int count)
1112{
1113 struct uart_hsu_port *up = serial_hsu_ports[co->index];
1114 unsigned long flags;
1115 unsigned int ier;
1116 int locked = 1;
1117
1118 local_irq_save(flags);
1119 if (up->port.sysrq)
1120 locked = 0;
1121 else if (oops_in_progress) {
1122 locked = spin_trylock(&up->port.lock);
1123 } else
1124 spin_lock(&up->port.lock);
1125
1126 /* First save the IER then disable the interrupts */
1127 ier = serial_in(up, UART_IER);
1128 serial_out(up, UART_IER, 0);
1129
1130 uart_console_write(&up->port, s, count, serial_hsu_console_putchar);
1131
1132 /*
1133 * Finally, wait for transmitter to become empty
1134 * and restore the IER
1135 */
1136 wait_for_xmitr(up);
1137 serial_out(up, UART_IER, ier);
1138
1139 if (locked)
1140 spin_unlock(&up->port.lock);
1141 local_irq_restore(flags);
1142}
1143
1144static struct console serial_hsu_console;
1145
1146static int __init
1147serial_hsu_console_setup(struct console *co, char *options)
1148{
1149 struct uart_hsu_port *up;
1150 int baud = 115200;
1151 int bits = 8;
1152 int parity = 'n';
1153 int flow = 'n';
1154 int ret;
1155
1156 if (co->index == -1 || co->index >= serial_hsu_reg.nr)
1157 co->index = 0;
1158 up = serial_hsu_ports[co->index];
1159 if (!up)
1160 return -ENODEV;
1161
1162 if (options)
1163 uart_parse_options(options, &baud, &parity, &bits, &flow);
1164
1165 ret = uart_set_options(&up->port, co, baud, parity, bits, flow);
1166
1167 return ret;
1168}
1169
1170static struct console serial_hsu_console = {
1171 .name = "ttyMFD",
1172 .write = serial_hsu_console_write,
1173 .device = uart_console_device,
1174 .setup = serial_hsu_console_setup,
1175 .flags = CON_PRINTBUFFER,
1176 .index = 2,
1177 .data = &serial_hsu_reg,
1178};
1179#endif
1180
1181struct uart_ops serial_hsu_pops = {
1182 .tx_empty = serial_hsu_tx_empty,
1183 .set_mctrl = serial_hsu_set_mctrl,
1184 .get_mctrl = serial_hsu_get_mctrl,
1185 .stop_tx = serial_hsu_stop_tx,
1186 .start_tx = serial_hsu_start_tx,
1187 .stop_rx = serial_hsu_stop_rx,
1188 .enable_ms = serial_hsu_enable_ms,
1189 .break_ctl = serial_hsu_break_ctl,
1190 .startup = serial_hsu_startup,
1191 .shutdown = serial_hsu_shutdown,
1192 .set_termios = serial_hsu_set_termios,
1193 .pm = serial_hsu_pm,
1194 .type = serial_hsu_type,
1195 .release_port = serial_hsu_release_port,
1196 .request_port = serial_hsu_request_port,
1197 .config_port = serial_hsu_config_port,
1198 .verify_port = serial_hsu_verify_port,
1199};
1200
1201static struct uart_driver serial_hsu_reg = {
1202 .owner = THIS_MODULE,
1203 .driver_name = "MFD serial",
1204 .dev_name = "ttyMFD",
1205 .major = TTY_MAJOR,
1206 .minor = 128,
1207 .nr = 3,
1208};
1209
1210#ifdef CONFIG_PM
1211static int serial_hsu_suspend(struct pci_dev *pdev, pm_message_t state)
1212{
1213 void *priv = pci_get_drvdata(pdev);
1214 struct uart_hsu_port *up;
1215
1216 /* Make sure this is not the internal dma controller */
1217 if (priv && (pdev->device != 0x081E)) {
1218 up = priv;
1219 uart_suspend_port(&serial_hsu_reg, &up->port);
1220 }
1221
1222 pci_save_state(pdev);
1223 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1224 return 0;
1225}
1226
1227static int serial_hsu_resume(struct pci_dev *pdev)
1228{
1229 void *priv = pci_get_drvdata(pdev);
1230 struct uart_hsu_port *up;
1231 int ret;
1232
1233 pci_set_power_state(pdev, PCI_D0);
1234 pci_restore_state(pdev);
1235
1236 ret = pci_enable_device(pdev);
1237 if (ret)
1238 dev_warn(&pdev->dev,
1239 "HSU: can't re-enable device, try to continue\n");
1240
1241 if (priv && (pdev->device != 0x081E)) {
1242 up = priv;
1243 uart_resume_port(&serial_hsu_reg, &up->port);
1244 }
1245 return 0;
1246}
1247#else
1248#define serial_hsu_suspend NULL
1249#define serial_hsu_resume NULL
1250#endif
1251
1252/* temp global pointer before we settle down on using one or four PCI dev */
1253static struct hsu_port *phsu;
1254
1255static int serial_hsu_probe(struct pci_dev *pdev,
1256 const struct pci_device_id *ent)
1257{
1258 struct uart_hsu_port *uport;
1259 int index, ret;
1260
1261 printk(KERN_INFO "HSU: found PCI Serial controller(ID: %04x:%04x)\n",
1262 pdev->vendor, pdev->device);
1263
1264 switch (pdev->device) {
1265 case 0x081B:
1266 index = 0;
1267 break;
1268 case 0x081C:
1269 index = 1;
1270 break;
1271 case 0x081D:
1272 index = 2;
1273 break;
1274 case 0x081E:
1275 /* internal DMA controller */
1276 index = 3;
1277 break;
1278 default:
1279 dev_err(&pdev->dev, "HSU: out of index!");
1280 return -ENODEV;
1281 }
1282
1283 ret = pci_enable_device(pdev);
1284 if (ret)
1285 return ret;
1286
1287 if (index == 3) {
1288 /* DMA controller */
1289 ret = request_irq(pdev->irq, dma_irq, 0, "hsu_dma", phsu);
1290 if (ret) {
1291 dev_err(&pdev->dev, "can not get IRQ\n");
1292 goto err_disable;
1293 }
1294 pci_set_drvdata(pdev, phsu);
1295 } else {
1296 /* UART port 0~2 */
1297 uport = &phsu->port[index];
1298 uport->port.irq = pdev->irq;
1299 uport->port.dev = &pdev->dev;
1300 uport->dev = &pdev->dev;
1301
1302 ret = request_irq(pdev->irq, port_irq, 0, uport->name, uport);
1303 if (ret) {
1304 dev_err(&pdev->dev, "can not get IRQ\n");
1305 goto err_disable;
1306 }
1307 uart_add_one_port(&serial_hsu_reg, &uport->port);
1308
1309#ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE
1310 if (index == 2) {
1311 register_console(&serial_hsu_console);
1312 uport->port.cons = &serial_hsu_console;
1313 }
1314#endif
1315 pci_set_drvdata(pdev, uport);
1316 }
1317
1318 return 0;
1319
1320err_disable:
1321 pci_disable_device(pdev);
1322 return ret;
1323}
1324
1325static void hsu_global_init(void)
1326{
1327 struct hsu_port *hsu;
1328 struct uart_hsu_port *uport;
1329 struct hsu_dma_chan *dchan;
1330 int i, ret;
1331
1332 hsu = kzalloc(sizeof(struct hsu_port), GFP_KERNEL);
1333 if (!hsu)
1334 return;
1335
1336 /* Get basic io resource and map it */
1337 hsu->paddr = 0xffa28000;
1338 hsu->iolen = 0x1000;
1339
1340 if (!(request_mem_region(hsu->paddr, hsu->iolen, "HSU global")))
1341 pr_warning("HSU: error in request mem region\n");
1342
1343 hsu->reg = ioremap_nocache((unsigned long)hsu->paddr, hsu->iolen);
1344 if (!hsu->reg) {
1345 pr_err("HSU: error in ioremap\n");
1346 ret = -ENOMEM;
1347 goto err_free_region;
1348 }
1349
1350 /* Initialise the 3 UART ports */
1351 uport = hsu->port;
1352 for (i = 0; i < 3; i++) {
1353 uport->port.type = PORT_MFD;
1354 uport->port.iotype = UPIO_MEM;
1355 uport->port.mapbase = (resource_size_t)hsu->paddr
1356 + HSU_PORT_REG_OFFSET
1357 + i * HSU_PORT_REG_LENGTH;
1358 uport->port.membase = hsu->reg + HSU_PORT_REG_OFFSET
1359 + i * HSU_PORT_REG_LENGTH;
1360
1361 sprintf(uport->name, "hsu_port%d", i);
1362 uport->port.fifosize = 64;
1363 uport->port.ops = &serial_hsu_pops;
1364 uport->port.line = i;
1365 uport->port.flags = UPF_IOREMAP;
1366 /* set the scalable maxim support rate to 2746800 bps */
1367 uport->port.uartclk = 115200 * 24 * 16;
1368
1369 uport->running = 0;
1370 uport->txc = &hsu->chans[i * 2];
1371 uport->rxc = &hsu->chans[i * 2 + 1];
1372
1373 serial_hsu_ports[i] = uport;
1374 uport->index = i;
1375
1376 if (hsu_dma_enable & (1<<i))
1377 uport->use_dma = 1;
1378 else
1379 uport->use_dma = 0;
1380
1381 uport++;
1382 }
1383
1384 /* Initialise 6 dma channels */
1385 dchan = hsu->chans;
1386 for (i = 0; i < 6; i++) {
1387 dchan->id = i;
1388 dchan->dirt = (i & 0x1) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1389 dchan->uport = &hsu->port[i/2];
1390 dchan->reg = hsu->reg + HSU_DMA_CHANS_REG_OFFSET +
1391 i * HSU_DMA_CHANS_REG_LENGTH;
1392
1393 dchan++;
1394 }
1395
1396 phsu = hsu;
1397 hsu_debugfs_init(hsu);
1398 return;
1399
1400err_free_region:
1401 release_mem_region(hsu->paddr, hsu->iolen);
1402 kfree(hsu);
1403 return;
1404}
1405
1406static void serial_hsu_remove(struct pci_dev *pdev)
1407{
1408 void *priv = pci_get_drvdata(pdev);
1409 struct uart_hsu_port *up;
1410
1411 if (!priv)
1412 return;
1413
1414 /* For port 0/1/2, priv is the address of uart_hsu_port */
1415 if (pdev->device != 0x081E) {
1416 up = priv;
1417 uart_remove_one_port(&serial_hsu_reg, &up->port);
1418 }
1419
1420 pci_set_drvdata(pdev, NULL);
1421 free_irq(pdev->irq, priv);
1422 pci_disable_device(pdev);
1423}
1424
1425/* First 3 are UART ports, and the 4th is the DMA */
1426static const struct pci_device_id pci_ids[] __devinitdata = {
1427 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081B) },
1428 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081C) },
1429 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081D) },
1430 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081E) },
1431 {},
1432};
1433
1434static struct pci_driver hsu_pci_driver = {
1435 .name = "HSU serial",
1436 .id_table = pci_ids,
1437 .probe = serial_hsu_probe,
1438 .remove = __devexit_p(serial_hsu_remove),
1439 .suspend = serial_hsu_suspend,
1440 .resume = serial_hsu_resume,
1441};
1442
1443static int __init hsu_pci_init(void)
1444{
1445 int ret;
1446
1447 hsu_global_init();
1448
1449 ret = uart_register_driver(&serial_hsu_reg);
1450 if (ret)
1451 return ret;
1452
1453 return pci_register_driver(&hsu_pci_driver);
1454}
1455
1456static void __exit hsu_pci_exit(void)
1457{
1458 pci_unregister_driver(&hsu_pci_driver);
1459 uart_unregister_driver(&serial_hsu_reg);
1460
1461 hsu_debugfs_remove(phsu);
1462
1463 kfree(phsu);
1464}
1465
1466module_init(hsu_pci_init);
1467module_exit(hsu_pci_exit);
1468
1469MODULE_LICENSE("GPL v2");
1470MODULE_ALIAS("platform:medfield-hsu");
1/*
2 * mfd.c: driver for High Speed UART device of Intel Medfield platform
3 *
4 * Refer pxa.c, 8250.c and some other drivers in drivers/serial/
5 *
6 * (C) Copyright 2010 Intel Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; version 2
11 * of the License.
12 */
13
14/* Notes:
15 * 1. DMA channel allocation: 0/1 channel are assigned to port 0,
16 * 2/3 chan to port 1, 4/5 chan to port 3. Even number chans
17 * are used for RX, odd chans for TX
18 *
19 * 2. The RI/DSR/DCD/DTR are not pinned out, DCD & DSR are always
20 * asserted, only when the HW is reset the DDCD and DDSR will
21 * be triggered
22 */
23
24#include <linux/module.h>
25#include <linux/init.h>
26#include <linux/console.h>
27#include <linux/sysrq.h>
28#include <linux/slab.h>
29#include <linux/serial_reg.h>
30#include <linux/circ_buf.h>
31#include <linux/delay.h>
32#include <linux/interrupt.h>
33#include <linux/tty.h>
34#include <linux/tty_flip.h>
35#include <linux/serial_core.h>
36#include <linux/serial_mfd.h>
37#include <linux/dma-mapping.h>
38#include <linux/pci.h>
39#include <linux/io.h>
40#include <linux/debugfs.h>
41#include <linux/pm_runtime.h>
42
43#define HSU_DMA_BUF_SIZE 2048
44
45#define chan_readl(chan, offset) readl(chan->reg + offset)
46#define chan_writel(chan, offset, val) writel(val, chan->reg + offset)
47
48#define mfd_readl(obj, offset) readl(obj->reg + offset)
49#define mfd_writel(obj, offset, val) writel(val, obj->reg + offset)
50
51static int hsu_dma_enable;
52module_param(hsu_dma_enable, int, 0);
53MODULE_PARM_DESC(hsu_dma_enable,
54 "It is a bitmap to set working mode, if bit[x] is 1, then port[x] will work in DMA mode, otherwise in PIO mode.");
55
56struct hsu_dma_buffer {
57 u8 *buf;
58 dma_addr_t dma_addr;
59 u32 dma_size;
60 u32 ofs;
61};
62
63struct hsu_dma_chan {
64 u32 id;
65 enum dma_data_direction dirt;
66 struct uart_hsu_port *uport;
67 void __iomem *reg;
68};
69
70struct uart_hsu_port {
71 struct uart_port port;
72 unsigned char ier;
73 unsigned char lcr;
74 unsigned char mcr;
75 unsigned int lsr_break_flag;
76 char name[12];
77 int index;
78 struct device *dev;
79
80 struct hsu_dma_chan *txc;
81 struct hsu_dma_chan *rxc;
82 struct hsu_dma_buffer txbuf;
83 struct hsu_dma_buffer rxbuf;
84 int use_dma; /* flag for DMA/PIO */
85 int running;
86 int dma_tx_on;
87};
88
89/* Top level data structure of HSU */
90struct hsu_port {
91 void __iomem *reg;
92 unsigned long paddr;
93 unsigned long iolen;
94 u32 irq;
95
96 struct uart_hsu_port port[3];
97 struct hsu_dma_chan chans[10];
98
99 struct dentry *debugfs;
100};
101
102static inline unsigned int serial_in(struct uart_hsu_port *up, int offset)
103{
104 unsigned int val;
105
106 if (offset > UART_MSR) {
107 offset <<= 2;
108 val = readl(up->port.membase + offset);
109 } else
110 val = (unsigned int)readb(up->port.membase + offset);
111
112 return val;
113}
114
115static inline void serial_out(struct uart_hsu_port *up, int offset, int value)
116{
117 if (offset > UART_MSR) {
118 offset <<= 2;
119 writel(value, up->port.membase + offset);
120 } else {
121 unsigned char val = value & 0xff;
122 writeb(val, up->port.membase + offset);
123 }
124}
125
126#ifdef CONFIG_DEBUG_FS
127
128#define HSU_REGS_BUFSIZE 1024
129
130
131static ssize_t port_show_regs(struct file *file, char __user *user_buf,
132 size_t count, loff_t *ppos)
133{
134 struct uart_hsu_port *up = file->private_data;
135 char *buf;
136 u32 len = 0;
137 ssize_t ret;
138
139 buf = kzalloc(HSU_REGS_BUFSIZE, GFP_KERNEL);
140 if (!buf)
141 return 0;
142
143 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
144 "MFD HSU port[%d] regs:\n", up->index);
145
146 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
147 "=================================\n");
148 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
149 "IER: \t\t0x%08x\n", serial_in(up, UART_IER));
150 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
151 "IIR: \t\t0x%08x\n", serial_in(up, UART_IIR));
152 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
153 "LCR: \t\t0x%08x\n", serial_in(up, UART_LCR));
154 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
155 "MCR: \t\t0x%08x\n", serial_in(up, UART_MCR));
156 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
157 "LSR: \t\t0x%08x\n", serial_in(up, UART_LSR));
158 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
159 "MSR: \t\t0x%08x\n", serial_in(up, UART_MSR));
160 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
161 "FOR: \t\t0x%08x\n", serial_in(up, UART_FOR));
162 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
163 "PS: \t\t0x%08x\n", serial_in(up, UART_PS));
164 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
165 "MUL: \t\t0x%08x\n", serial_in(up, UART_MUL));
166 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
167 "DIV: \t\t0x%08x\n", serial_in(up, UART_DIV));
168
169 if (len > HSU_REGS_BUFSIZE)
170 len = HSU_REGS_BUFSIZE;
171
172 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
173 kfree(buf);
174 return ret;
175}
176
177static ssize_t dma_show_regs(struct file *file, char __user *user_buf,
178 size_t count, loff_t *ppos)
179{
180 struct hsu_dma_chan *chan = file->private_data;
181 char *buf;
182 u32 len = 0;
183 ssize_t ret;
184
185 buf = kzalloc(HSU_REGS_BUFSIZE, GFP_KERNEL);
186 if (!buf)
187 return 0;
188
189 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
190 "MFD HSU DMA channel [%d] regs:\n", chan->id);
191
192 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
193 "=================================\n");
194 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
195 "CR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_CR));
196 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
197 "DCR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_DCR));
198 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
199 "BSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_BSR));
200 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
201 "MOTSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_MOTSR));
202 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
203 "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D0SAR));
204 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
205 "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D0TSR));
206 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
207 "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D1SAR));
208 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
209 "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D1TSR));
210 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
211 "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D2SAR));
212 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
213 "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D2TSR));
214 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
215 "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D3SAR));
216 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
217 "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D3TSR));
218
219 if (len > HSU_REGS_BUFSIZE)
220 len = HSU_REGS_BUFSIZE;
221
222 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
223 kfree(buf);
224 return ret;
225}
226
227static const struct file_operations port_regs_ops = {
228 .owner = THIS_MODULE,
229 .open = simple_open,
230 .read = port_show_regs,
231 .llseek = default_llseek,
232};
233
234static const struct file_operations dma_regs_ops = {
235 .owner = THIS_MODULE,
236 .open = simple_open,
237 .read = dma_show_regs,
238 .llseek = default_llseek,
239};
240
241static int hsu_debugfs_init(struct hsu_port *hsu)
242{
243 int i;
244 char name[32];
245
246 hsu->debugfs = debugfs_create_dir("hsu", NULL);
247 if (!hsu->debugfs)
248 return -ENOMEM;
249
250 for (i = 0; i < 3; i++) {
251 snprintf(name, sizeof(name), "port_%d_regs", i);
252 debugfs_create_file(name, S_IFREG | S_IRUGO,
253 hsu->debugfs, (void *)(&hsu->port[i]), &port_regs_ops);
254 }
255
256 for (i = 0; i < 6; i++) {
257 snprintf(name, sizeof(name), "dma_chan_%d_regs", i);
258 debugfs_create_file(name, S_IFREG | S_IRUGO,
259 hsu->debugfs, (void *)&hsu->chans[i], &dma_regs_ops);
260 }
261
262 return 0;
263}
264
265static void hsu_debugfs_remove(struct hsu_port *hsu)
266{
267 if (hsu->debugfs)
268 debugfs_remove_recursive(hsu->debugfs);
269}
270
271#else
272static inline int hsu_debugfs_init(struct hsu_port *hsu)
273{
274 return 0;
275}
276
277static inline void hsu_debugfs_remove(struct hsu_port *hsu)
278{
279}
280#endif /* CONFIG_DEBUG_FS */
281
282static void serial_hsu_enable_ms(struct uart_port *port)
283{
284 struct uart_hsu_port *up =
285 container_of(port, struct uart_hsu_port, port);
286
287 up->ier |= UART_IER_MSI;
288 serial_out(up, UART_IER, up->ier);
289}
290
291void hsu_dma_tx(struct uart_hsu_port *up)
292{
293 struct circ_buf *xmit = &up->port.state->xmit;
294 struct hsu_dma_buffer *dbuf = &up->txbuf;
295 int count;
296
297 /* test_and_set_bit may be better, but anyway it's in lock protected mode */
298 if (up->dma_tx_on)
299 return;
300
301 /* Update the circ buf info */
302 xmit->tail += dbuf->ofs;
303 xmit->tail &= UART_XMIT_SIZE - 1;
304
305 up->port.icount.tx += dbuf->ofs;
306 dbuf->ofs = 0;
307
308 /* Disable the channel */
309 chan_writel(up->txc, HSU_CH_CR, 0x0);
310
311 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&up->port)) {
312 dma_sync_single_for_device(up->port.dev,
313 dbuf->dma_addr,
314 dbuf->dma_size,
315 DMA_TO_DEVICE);
316
317 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
318 dbuf->ofs = count;
319
320 /* Reprogram the channel */
321 chan_writel(up->txc, HSU_CH_D0SAR, dbuf->dma_addr + xmit->tail);
322 chan_writel(up->txc, HSU_CH_D0TSR, count);
323
324 /* Reenable the channel */
325 chan_writel(up->txc, HSU_CH_DCR, 0x1
326 | (0x1 << 8)
327 | (0x1 << 16)
328 | (0x1 << 24));
329 up->dma_tx_on = 1;
330 chan_writel(up->txc, HSU_CH_CR, 0x1);
331 }
332
333 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
334 uart_write_wakeup(&up->port);
335}
336
337/* The buffer is already cache coherent */
338void hsu_dma_start_rx_chan(struct hsu_dma_chan *rxc, struct hsu_dma_buffer *dbuf)
339{
340 dbuf->ofs = 0;
341
342 chan_writel(rxc, HSU_CH_BSR, 32);
343 chan_writel(rxc, HSU_CH_MOTSR, 4);
344
345 chan_writel(rxc, HSU_CH_D0SAR, dbuf->dma_addr);
346 chan_writel(rxc, HSU_CH_D0TSR, dbuf->dma_size);
347 chan_writel(rxc, HSU_CH_DCR, 0x1 | (0x1 << 8)
348 | (0x1 << 16)
349 | (0x1 << 24) /* timeout bit, see HSU Errata 1 */
350 );
351 chan_writel(rxc, HSU_CH_CR, 0x3);
352}
353
354/* Protected by spin_lock_irqsave(port->lock) */
355static void serial_hsu_start_tx(struct uart_port *port)
356{
357 struct uart_hsu_port *up =
358 container_of(port, struct uart_hsu_port, port);
359
360 if (up->use_dma) {
361 hsu_dma_tx(up);
362 } else if (!(up->ier & UART_IER_THRI)) {
363 up->ier |= UART_IER_THRI;
364 serial_out(up, UART_IER, up->ier);
365 }
366}
367
368static void serial_hsu_stop_tx(struct uart_port *port)
369{
370 struct uart_hsu_port *up =
371 container_of(port, struct uart_hsu_port, port);
372 struct hsu_dma_chan *txc = up->txc;
373
374 if (up->use_dma)
375 chan_writel(txc, HSU_CH_CR, 0x0);
376 else if (up->ier & UART_IER_THRI) {
377 up->ier &= ~UART_IER_THRI;
378 serial_out(up, UART_IER, up->ier);
379 }
380}
381
382/* This is always called in spinlock protected mode, so
383 * modify timeout timer is safe here */
384void hsu_dma_rx(struct uart_hsu_port *up, u32 int_sts)
385{
386 struct hsu_dma_buffer *dbuf = &up->rxbuf;
387 struct hsu_dma_chan *chan = up->rxc;
388 struct uart_port *port = &up->port;
389 struct tty_struct *tty = port->state->port.tty;
390 int count;
391
392 if (!tty)
393 return;
394
395 /*
396 * First need to know how many is already transferred,
397 * then check if its a timeout DMA irq, and return
398 * the trail bytes out, push them up and reenable the
399 * channel
400 */
401
402 /* Timeout IRQ, need wait some time, see Errata 2 */
403 if (int_sts & 0xf00)
404 udelay(2);
405
406 /* Stop the channel */
407 chan_writel(chan, HSU_CH_CR, 0x0);
408
409 count = chan_readl(chan, HSU_CH_D0SAR) - dbuf->dma_addr;
410 if (!count) {
411 /* Restart the channel before we leave */
412 chan_writel(chan, HSU_CH_CR, 0x3);
413 return;
414 }
415
416 dma_sync_single_for_cpu(port->dev, dbuf->dma_addr,
417 dbuf->dma_size, DMA_FROM_DEVICE);
418
419 /*
420 * Head will only wrap around when we recycle
421 * the DMA buffer, and when that happens, we
422 * explicitly set tail to 0. So head will
423 * always be greater than tail.
424 */
425 tty_insert_flip_string(tty, dbuf->buf, count);
426 port->icount.rx += count;
427
428 dma_sync_single_for_device(up->port.dev, dbuf->dma_addr,
429 dbuf->dma_size, DMA_FROM_DEVICE);
430
431 /* Reprogram the channel */
432 chan_writel(chan, HSU_CH_D0SAR, dbuf->dma_addr);
433 chan_writel(chan, HSU_CH_D0TSR, dbuf->dma_size);
434 chan_writel(chan, HSU_CH_DCR, 0x1
435 | (0x1 << 8)
436 | (0x1 << 16)
437 | (0x1 << 24) /* timeout bit, see HSU Errata 1 */
438 );
439 tty_flip_buffer_push(tty);
440
441 chan_writel(chan, HSU_CH_CR, 0x3);
442
443}
444
445static void serial_hsu_stop_rx(struct uart_port *port)
446{
447 struct uart_hsu_port *up =
448 container_of(port, struct uart_hsu_port, port);
449 struct hsu_dma_chan *chan = up->rxc;
450
451 if (up->use_dma)
452 chan_writel(chan, HSU_CH_CR, 0x2);
453 else {
454 up->ier &= ~UART_IER_RLSI;
455 up->port.read_status_mask &= ~UART_LSR_DR;
456 serial_out(up, UART_IER, up->ier);
457 }
458}
459
460static inline void receive_chars(struct uart_hsu_port *up, int *status)
461{
462 struct tty_struct *tty = up->port.state->port.tty;
463 unsigned int ch, flag;
464 unsigned int max_count = 256;
465
466 if (!tty)
467 return;
468
469 do {
470 ch = serial_in(up, UART_RX);
471 flag = TTY_NORMAL;
472 up->port.icount.rx++;
473
474 if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE |
475 UART_LSR_FE | UART_LSR_OE))) {
476
477 dev_warn(up->dev, "We really rush into ERR/BI case"
478 "status = 0x%02x", *status);
479 /* For statistics only */
480 if (*status & UART_LSR_BI) {
481 *status &= ~(UART_LSR_FE | UART_LSR_PE);
482 up->port.icount.brk++;
483 /*
484 * We do the SysRQ and SAK checking
485 * here because otherwise the break
486 * may get masked by ignore_status_mask
487 * or read_status_mask.
488 */
489 if (uart_handle_break(&up->port))
490 goto ignore_char;
491 } else if (*status & UART_LSR_PE)
492 up->port.icount.parity++;
493 else if (*status & UART_LSR_FE)
494 up->port.icount.frame++;
495 if (*status & UART_LSR_OE)
496 up->port.icount.overrun++;
497
498 /* Mask off conditions which should be ignored. */
499 *status &= up->port.read_status_mask;
500
501#ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE
502 if (up->port.cons &&
503 up->port.cons->index == up->port.line) {
504 /* Recover the break flag from console xmit */
505 *status |= up->lsr_break_flag;
506 up->lsr_break_flag = 0;
507 }
508#endif
509 if (*status & UART_LSR_BI) {
510 flag = TTY_BREAK;
511 } else if (*status & UART_LSR_PE)
512 flag = TTY_PARITY;
513 else if (*status & UART_LSR_FE)
514 flag = TTY_FRAME;
515 }
516
517 if (uart_handle_sysrq_char(&up->port, ch))
518 goto ignore_char;
519
520 uart_insert_char(&up->port, *status, UART_LSR_OE, ch, flag);
521 ignore_char:
522 *status = serial_in(up, UART_LSR);
523 } while ((*status & UART_LSR_DR) && max_count--);
524 tty_flip_buffer_push(tty);
525}
526
527static void transmit_chars(struct uart_hsu_port *up)
528{
529 struct circ_buf *xmit = &up->port.state->xmit;
530 int count;
531
532 if (up->port.x_char) {
533 serial_out(up, UART_TX, up->port.x_char);
534 up->port.icount.tx++;
535 up->port.x_char = 0;
536 return;
537 }
538 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
539 serial_hsu_stop_tx(&up->port);
540 return;
541 }
542
543 /* The IRQ is for TX FIFO half-empty */
544 count = up->port.fifosize / 2;
545
546 do {
547 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
548 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
549
550 up->port.icount.tx++;
551 if (uart_circ_empty(xmit))
552 break;
553 } while (--count > 0);
554
555 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
556 uart_write_wakeup(&up->port);
557
558 if (uart_circ_empty(xmit))
559 serial_hsu_stop_tx(&up->port);
560}
561
562static inline void check_modem_status(struct uart_hsu_port *up)
563{
564 int status;
565
566 status = serial_in(up, UART_MSR);
567
568 if ((status & UART_MSR_ANY_DELTA) == 0)
569 return;
570
571 if (status & UART_MSR_TERI)
572 up->port.icount.rng++;
573 if (status & UART_MSR_DDSR)
574 up->port.icount.dsr++;
575 /* We may only get DDCD when HW init and reset */
576 if (status & UART_MSR_DDCD)
577 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
578 /* Will start/stop_tx accordingly */
579 if (status & UART_MSR_DCTS)
580 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
581
582 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
583}
584
585/*
586 * This handles the interrupt from one port.
587 */
588static irqreturn_t port_irq(int irq, void *dev_id)
589{
590 struct uart_hsu_port *up = dev_id;
591 unsigned int iir, lsr;
592 unsigned long flags;
593
594 if (unlikely(!up->running))
595 return IRQ_NONE;
596
597 spin_lock_irqsave(&up->port.lock, flags);
598 if (up->use_dma) {
599 lsr = serial_in(up, UART_LSR);
600 if (unlikely(lsr & (UART_LSR_BI | UART_LSR_PE |
601 UART_LSR_FE | UART_LSR_OE)))
602 dev_warn(up->dev,
603 "Got lsr irq while using DMA, lsr = 0x%2x\n",
604 lsr);
605 check_modem_status(up);
606 spin_unlock_irqrestore(&up->port.lock, flags);
607 return IRQ_HANDLED;
608 }
609
610 iir = serial_in(up, UART_IIR);
611 if (iir & UART_IIR_NO_INT) {
612 spin_unlock_irqrestore(&up->port.lock, flags);
613 return IRQ_NONE;
614 }
615
616 lsr = serial_in(up, UART_LSR);
617 if (lsr & UART_LSR_DR)
618 receive_chars(up, &lsr);
619 check_modem_status(up);
620
621 /* lsr will be renewed during the receive_chars */
622 if (lsr & UART_LSR_THRE)
623 transmit_chars(up);
624
625 spin_unlock_irqrestore(&up->port.lock, flags);
626 return IRQ_HANDLED;
627}
628
629static inline void dma_chan_irq(struct hsu_dma_chan *chan)
630{
631 struct uart_hsu_port *up = chan->uport;
632 unsigned long flags;
633 u32 int_sts;
634
635 spin_lock_irqsave(&up->port.lock, flags);
636
637 if (!up->use_dma || !up->running)
638 goto exit;
639
640 /*
641 * No matter what situation, need read clear the IRQ status
642 * There is a bug, see Errata 5, HSD 2900918
643 */
644 int_sts = chan_readl(chan, HSU_CH_SR);
645
646 /* Rx channel */
647 if (chan->dirt == DMA_FROM_DEVICE)
648 hsu_dma_rx(up, int_sts);
649
650 /* Tx channel */
651 if (chan->dirt == DMA_TO_DEVICE) {
652 chan_writel(chan, HSU_CH_CR, 0x0);
653 up->dma_tx_on = 0;
654 hsu_dma_tx(up);
655 }
656
657exit:
658 spin_unlock_irqrestore(&up->port.lock, flags);
659 return;
660}
661
662static irqreturn_t dma_irq(int irq, void *dev_id)
663{
664 struct hsu_port *hsu = dev_id;
665 u32 int_sts, i;
666
667 int_sts = mfd_readl(hsu, HSU_GBL_DMAISR);
668
669 /* Currently we only have 6 channels may be used */
670 for (i = 0; i < 6; i++) {
671 if (int_sts & 0x1)
672 dma_chan_irq(&hsu->chans[i]);
673 int_sts >>= 1;
674 }
675
676 return IRQ_HANDLED;
677}
678
679static unsigned int serial_hsu_tx_empty(struct uart_port *port)
680{
681 struct uart_hsu_port *up =
682 container_of(port, struct uart_hsu_port, port);
683 unsigned long flags;
684 unsigned int ret;
685
686 spin_lock_irqsave(&up->port.lock, flags);
687 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
688 spin_unlock_irqrestore(&up->port.lock, flags);
689
690 return ret;
691}
692
693static unsigned int serial_hsu_get_mctrl(struct uart_port *port)
694{
695 struct uart_hsu_port *up =
696 container_of(port, struct uart_hsu_port, port);
697 unsigned char status;
698 unsigned int ret;
699
700 status = serial_in(up, UART_MSR);
701
702 ret = 0;
703 if (status & UART_MSR_DCD)
704 ret |= TIOCM_CAR;
705 if (status & UART_MSR_RI)
706 ret |= TIOCM_RNG;
707 if (status & UART_MSR_DSR)
708 ret |= TIOCM_DSR;
709 if (status & UART_MSR_CTS)
710 ret |= TIOCM_CTS;
711 return ret;
712}
713
714static void serial_hsu_set_mctrl(struct uart_port *port, unsigned int mctrl)
715{
716 struct uart_hsu_port *up =
717 container_of(port, struct uart_hsu_port, port);
718 unsigned char mcr = 0;
719
720 if (mctrl & TIOCM_RTS)
721 mcr |= UART_MCR_RTS;
722 if (mctrl & TIOCM_DTR)
723 mcr |= UART_MCR_DTR;
724 if (mctrl & TIOCM_OUT1)
725 mcr |= UART_MCR_OUT1;
726 if (mctrl & TIOCM_OUT2)
727 mcr |= UART_MCR_OUT2;
728 if (mctrl & TIOCM_LOOP)
729 mcr |= UART_MCR_LOOP;
730
731 mcr |= up->mcr;
732
733 serial_out(up, UART_MCR, mcr);
734}
735
736static void serial_hsu_break_ctl(struct uart_port *port, int break_state)
737{
738 struct uart_hsu_port *up =
739 container_of(port, struct uart_hsu_port, port);
740 unsigned long flags;
741
742 spin_lock_irqsave(&up->port.lock, flags);
743 if (break_state == -1)
744 up->lcr |= UART_LCR_SBC;
745 else
746 up->lcr &= ~UART_LCR_SBC;
747 serial_out(up, UART_LCR, up->lcr);
748 spin_unlock_irqrestore(&up->port.lock, flags);
749}
750
751/*
752 * What special to do:
753 * 1. chose the 64B fifo mode
754 * 2. start dma or pio depends on configuration
755 * 3. we only allocate dma memory when needed
756 */
757static int serial_hsu_startup(struct uart_port *port)
758{
759 struct uart_hsu_port *up =
760 container_of(port, struct uart_hsu_port, port);
761 unsigned long flags;
762
763 pm_runtime_get_sync(up->dev);
764
765 /*
766 * Clear the FIFO buffers and disable them.
767 * (they will be reenabled in set_termios())
768 */
769 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
770 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
771 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
772 serial_out(up, UART_FCR, 0);
773
774 /* Clear the interrupt registers. */
775 (void) serial_in(up, UART_LSR);
776 (void) serial_in(up, UART_RX);
777 (void) serial_in(up, UART_IIR);
778 (void) serial_in(up, UART_MSR);
779
780 /* Now, initialize the UART, default is 8n1 */
781 serial_out(up, UART_LCR, UART_LCR_WLEN8);
782
783 spin_lock_irqsave(&up->port.lock, flags);
784
785 up->port.mctrl |= TIOCM_OUT2;
786 serial_hsu_set_mctrl(&up->port, up->port.mctrl);
787
788 /*
789 * Finally, enable interrupts. Note: Modem status interrupts
790 * are set via set_termios(), which will be occurring imminently
791 * anyway, so we don't enable them here.
792 */
793 if (!up->use_dma)
794 up->ier = UART_IER_RLSI | UART_IER_RDI | UART_IER_RTOIE;
795 else
796 up->ier = 0;
797 serial_out(up, UART_IER, up->ier);
798
799 spin_unlock_irqrestore(&up->port.lock, flags);
800
801 /* DMA init */
802 if (up->use_dma) {
803 struct hsu_dma_buffer *dbuf;
804 struct circ_buf *xmit = &port->state->xmit;
805
806 up->dma_tx_on = 0;
807
808 /* First allocate the RX buffer */
809 dbuf = &up->rxbuf;
810 dbuf->buf = kzalloc(HSU_DMA_BUF_SIZE, GFP_KERNEL);
811 if (!dbuf->buf) {
812 up->use_dma = 0;
813 goto exit;
814 }
815 dbuf->dma_addr = dma_map_single(port->dev,
816 dbuf->buf,
817 HSU_DMA_BUF_SIZE,
818 DMA_FROM_DEVICE);
819 dbuf->dma_size = HSU_DMA_BUF_SIZE;
820
821 /* Start the RX channel right now */
822 hsu_dma_start_rx_chan(up->rxc, dbuf);
823
824 /* Next init the TX DMA */
825 dbuf = &up->txbuf;
826 dbuf->buf = xmit->buf;
827 dbuf->dma_addr = dma_map_single(port->dev,
828 dbuf->buf,
829 UART_XMIT_SIZE,
830 DMA_TO_DEVICE);
831 dbuf->dma_size = UART_XMIT_SIZE;
832
833 /* This should not be changed all around */
834 chan_writel(up->txc, HSU_CH_BSR, 32);
835 chan_writel(up->txc, HSU_CH_MOTSR, 4);
836 dbuf->ofs = 0;
837 }
838
839exit:
840 /* And clear the interrupt registers again for luck. */
841 (void) serial_in(up, UART_LSR);
842 (void) serial_in(up, UART_RX);
843 (void) serial_in(up, UART_IIR);
844 (void) serial_in(up, UART_MSR);
845
846 up->running = 1;
847 return 0;
848}
849
850static void serial_hsu_shutdown(struct uart_port *port)
851{
852 struct uart_hsu_port *up =
853 container_of(port, struct uart_hsu_port, port);
854 unsigned long flags;
855
856 /* Disable interrupts from this port */
857 up->ier = 0;
858 serial_out(up, UART_IER, 0);
859 up->running = 0;
860
861 spin_lock_irqsave(&up->port.lock, flags);
862 up->port.mctrl &= ~TIOCM_OUT2;
863 serial_hsu_set_mctrl(&up->port, up->port.mctrl);
864 spin_unlock_irqrestore(&up->port.lock, flags);
865
866 /* Disable break condition and FIFOs */
867 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
868 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
869 UART_FCR_CLEAR_RCVR |
870 UART_FCR_CLEAR_XMIT);
871 serial_out(up, UART_FCR, 0);
872
873 pm_runtime_put(up->dev);
874}
875
876static void
877serial_hsu_set_termios(struct uart_port *port, struct ktermios *termios,
878 struct ktermios *old)
879{
880 struct uart_hsu_port *up =
881 container_of(port, struct uart_hsu_port, port);
882 unsigned char cval, fcr = 0;
883 unsigned long flags;
884 unsigned int baud, quot;
885 u32 ps, mul;
886
887 switch (termios->c_cflag & CSIZE) {
888 case CS5:
889 cval = UART_LCR_WLEN5;
890 break;
891 case CS6:
892 cval = UART_LCR_WLEN6;
893 break;
894 case CS7:
895 cval = UART_LCR_WLEN7;
896 break;
897 default:
898 case CS8:
899 cval = UART_LCR_WLEN8;
900 break;
901 }
902
903 /* CMSPAR isn't supported by this driver */
904 termios->c_cflag &= ~CMSPAR;
905
906 if (termios->c_cflag & CSTOPB)
907 cval |= UART_LCR_STOP;
908 if (termios->c_cflag & PARENB)
909 cval |= UART_LCR_PARITY;
910 if (!(termios->c_cflag & PARODD))
911 cval |= UART_LCR_EPAR;
912
913 /*
914 * The base clk is 50Mhz, and the baud rate come from:
915 * baud = 50M * MUL / (DIV * PS * DLAB)
916 *
917 * For those basic low baud rate we can get the direct
918 * scalar from 2746800, like 115200 = 2746800/24. For those
919 * higher baud rate, we handle them case by case, mainly by
920 * adjusting the MUL/PS registers, and DIV register is kept
921 * as default value 0x3d09 to make things simple
922 */
923 baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
924
925 quot = 1;
926 ps = 0x10;
927 mul = 0x3600;
928 switch (baud) {
929 case 3500000:
930 mul = 0x3345;
931 ps = 0xC;
932 break;
933 case 1843200:
934 mul = 0x2400;
935 break;
936 case 3000000:
937 case 2500000:
938 case 2000000:
939 case 1500000:
940 case 1000000:
941 case 500000:
942 /* mul/ps/quot = 0x9C4/0x10/0x1 will make a 500000 bps */
943 mul = baud / 500000 * 0x9C4;
944 break;
945 default:
946 /* Use uart_get_divisor to get quot for other baud rates */
947 quot = 0;
948 }
949
950 if (!quot)
951 quot = uart_get_divisor(port, baud);
952
953 if ((up->port.uartclk / quot) < (2400 * 16))
954 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_1B;
955 else if ((up->port.uartclk / quot) < (230400 * 16))
956 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_16B;
957 else
958 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_32B;
959
960 fcr |= UART_FCR_HSU_64B_FIFO;
961
962 /*
963 * Ok, we're now changing the port state. Do it with
964 * interrupts disabled.
965 */
966 spin_lock_irqsave(&up->port.lock, flags);
967
968 /* Update the per-port timeout */
969 uart_update_timeout(port, termios->c_cflag, baud);
970
971 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
972 if (termios->c_iflag & INPCK)
973 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
974 if (termios->c_iflag & (BRKINT | PARMRK))
975 up->port.read_status_mask |= UART_LSR_BI;
976
977 /* Characters to ignore */
978 up->port.ignore_status_mask = 0;
979 if (termios->c_iflag & IGNPAR)
980 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
981 if (termios->c_iflag & IGNBRK) {
982 up->port.ignore_status_mask |= UART_LSR_BI;
983 /*
984 * If we're ignoring parity and break indicators,
985 * ignore overruns too (for real raw support).
986 */
987 if (termios->c_iflag & IGNPAR)
988 up->port.ignore_status_mask |= UART_LSR_OE;
989 }
990
991 /* Ignore all characters if CREAD is not set */
992 if ((termios->c_cflag & CREAD) == 0)
993 up->port.ignore_status_mask |= UART_LSR_DR;
994
995 /*
996 * CTS flow control flag and modem status interrupts, disable
997 * MSI by default
998 */
999 up->ier &= ~UART_IER_MSI;
1000 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
1001 up->ier |= UART_IER_MSI;
1002
1003 serial_out(up, UART_IER, up->ier);
1004
1005 if (termios->c_cflag & CRTSCTS)
1006 up->mcr |= UART_MCR_AFE | UART_MCR_RTS;
1007 else
1008 up->mcr &= ~UART_MCR_AFE;
1009
1010 serial_out(up, UART_LCR, cval | UART_LCR_DLAB); /* set DLAB */
1011 serial_out(up, UART_DLL, quot & 0xff); /* LS of divisor */
1012 serial_out(up, UART_DLM, quot >> 8); /* MS of divisor */
1013 serial_out(up, UART_LCR, cval); /* reset DLAB */
1014 serial_out(up, UART_MUL, mul); /* set MUL */
1015 serial_out(up, UART_PS, ps); /* set PS */
1016 up->lcr = cval; /* Save LCR */
1017 serial_hsu_set_mctrl(&up->port, up->port.mctrl);
1018 serial_out(up, UART_FCR, fcr);
1019 spin_unlock_irqrestore(&up->port.lock, flags);
1020}
1021
1022static void
1023serial_hsu_pm(struct uart_port *port, unsigned int state,
1024 unsigned int oldstate)
1025{
1026}
1027
1028static void serial_hsu_release_port(struct uart_port *port)
1029{
1030}
1031
1032static int serial_hsu_request_port(struct uart_port *port)
1033{
1034 return 0;
1035}
1036
1037static void serial_hsu_config_port(struct uart_port *port, int flags)
1038{
1039 struct uart_hsu_port *up =
1040 container_of(port, struct uart_hsu_port, port);
1041 up->port.type = PORT_MFD;
1042}
1043
1044static int
1045serial_hsu_verify_port(struct uart_port *port, struct serial_struct *ser)
1046{
1047 /* We don't want the core code to modify any port params */
1048 return -EINVAL;
1049}
1050
1051static const char *
1052serial_hsu_type(struct uart_port *port)
1053{
1054 struct uart_hsu_port *up =
1055 container_of(port, struct uart_hsu_port, port);
1056 return up->name;
1057}
1058
1059/* Mainly for uart console use */
1060static struct uart_hsu_port *serial_hsu_ports[3];
1061static struct uart_driver serial_hsu_reg;
1062
1063#ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE
1064
1065#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1066
1067/* Wait for transmitter & holding register to empty */
1068static inline void wait_for_xmitr(struct uart_hsu_port *up)
1069{
1070 unsigned int status, tmout = 1000;
1071
1072 /* Wait up to 1ms for the character to be sent. */
1073 do {
1074 status = serial_in(up, UART_LSR);
1075
1076 if (status & UART_LSR_BI)
1077 up->lsr_break_flag = UART_LSR_BI;
1078
1079 if (--tmout == 0)
1080 break;
1081 udelay(1);
1082 } while (!(status & BOTH_EMPTY));
1083
1084 /* Wait up to 1s for flow control if necessary */
1085 if (up->port.flags & UPF_CONS_FLOW) {
1086 tmout = 1000000;
1087 while (--tmout &&
1088 ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
1089 udelay(1);
1090 }
1091}
1092
1093static void serial_hsu_console_putchar(struct uart_port *port, int ch)
1094{
1095 struct uart_hsu_port *up =
1096 container_of(port, struct uart_hsu_port, port);
1097
1098 wait_for_xmitr(up);
1099 serial_out(up, UART_TX, ch);
1100}
1101
1102/*
1103 * Print a string to the serial port trying not to disturb
1104 * any possible real use of the port...
1105 *
1106 * The console_lock must be held when we get here.
1107 */
1108static void
1109serial_hsu_console_write(struct console *co, const char *s, unsigned int count)
1110{
1111 struct uart_hsu_port *up = serial_hsu_ports[co->index];
1112 unsigned long flags;
1113 unsigned int ier;
1114 int locked = 1;
1115
1116 local_irq_save(flags);
1117 if (up->port.sysrq)
1118 locked = 0;
1119 else if (oops_in_progress) {
1120 locked = spin_trylock(&up->port.lock);
1121 } else
1122 spin_lock(&up->port.lock);
1123
1124 /* First save the IER then disable the interrupts */
1125 ier = serial_in(up, UART_IER);
1126 serial_out(up, UART_IER, 0);
1127
1128 uart_console_write(&up->port, s, count, serial_hsu_console_putchar);
1129
1130 /*
1131 * Finally, wait for transmitter to become empty
1132 * and restore the IER
1133 */
1134 wait_for_xmitr(up);
1135 serial_out(up, UART_IER, ier);
1136
1137 if (locked)
1138 spin_unlock(&up->port.lock);
1139 local_irq_restore(flags);
1140}
1141
1142static struct console serial_hsu_console;
1143
1144static int __init
1145serial_hsu_console_setup(struct console *co, char *options)
1146{
1147 struct uart_hsu_port *up;
1148 int baud = 115200;
1149 int bits = 8;
1150 int parity = 'n';
1151 int flow = 'n';
1152
1153 if (co->index == -1 || co->index >= serial_hsu_reg.nr)
1154 co->index = 0;
1155 up = serial_hsu_ports[co->index];
1156 if (!up)
1157 return -ENODEV;
1158
1159 if (options)
1160 uart_parse_options(options, &baud, &parity, &bits, &flow);
1161
1162 return uart_set_options(&up->port, co, baud, parity, bits, flow);
1163}
1164
1165static struct console serial_hsu_console = {
1166 .name = "ttyMFD",
1167 .write = serial_hsu_console_write,
1168 .device = uart_console_device,
1169 .setup = serial_hsu_console_setup,
1170 .flags = CON_PRINTBUFFER,
1171 .index = -1,
1172 .data = &serial_hsu_reg,
1173};
1174
1175#define SERIAL_HSU_CONSOLE (&serial_hsu_console)
1176#else
1177#define SERIAL_HSU_CONSOLE NULL
1178#endif
1179
1180struct uart_ops serial_hsu_pops = {
1181 .tx_empty = serial_hsu_tx_empty,
1182 .set_mctrl = serial_hsu_set_mctrl,
1183 .get_mctrl = serial_hsu_get_mctrl,
1184 .stop_tx = serial_hsu_stop_tx,
1185 .start_tx = serial_hsu_start_tx,
1186 .stop_rx = serial_hsu_stop_rx,
1187 .enable_ms = serial_hsu_enable_ms,
1188 .break_ctl = serial_hsu_break_ctl,
1189 .startup = serial_hsu_startup,
1190 .shutdown = serial_hsu_shutdown,
1191 .set_termios = serial_hsu_set_termios,
1192 .pm = serial_hsu_pm,
1193 .type = serial_hsu_type,
1194 .release_port = serial_hsu_release_port,
1195 .request_port = serial_hsu_request_port,
1196 .config_port = serial_hsu_config_port,
1197 .verify_port = serial_hsu_verify_port,
1198};
1199
1200static struct uart_driver serial_hsu_reg = {
1201 .owner = THIS_MODULE,
1202 .driver_name = "MFD serial",
1203 .dev_name = "ttyMFD",
1204 .major = TTY_MAJOR,
1205 .minor = 128,
1206 .nr = 3,
1207 .cons = SERIAL_HSU_CONSOLE,
1208};
1209
1210#ifdef CONFIG_PM
1211static int serial_hsu_suspend(struct pci_dev *pdev, pm_message_t state)
1212{
1213 void *priv = pci_get_drvdata(pdev);
1214 struct uart_hsu_port *up;
1215
1216 /* Make sure this is not the internal dma controller */
1217 if (priv && (pdev->device != 0x081E)) {
1218 up = priv;
1219 uart_suspend_port(&serial_hsu_reg, &up->port);
1220 }
1221
1222 pci_save_state(pdev);
1223 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1224 return 0;
1225}
1226
1227static int serial_hsu_resume(struct pci_dev *pdev)
1228{
1229 void *priv = pci_get_drvdata(pdev);
1230 struct uart_hsu_port *up;
1231 int ret;
1232
1233 pci_set_power_state(pdev, PCI_D0);
1234 pci_restore_state(pdev);
1235
1236 ret = pci_enable_device(pdev);
1237 if (ret)
1238 dev_warn(&pdev->dev,
1239 "HSU: can't re-enable device, try to continue\n");
1240
1241 if (priv && (pdev->device != 0x081E)) {
1242 up = priv;
1243 uart_resume_port(&serial_hsu_reg, &up->port);
1244 }
1245 return 0;
1246}
1247#else
1248#define serial_hsu_suspend NULL
1249#define serial_hsu_resume NULL
1250#endif
1251
1252#ifdef CONFIG_PM_RUNTIME
1253static int serial_hsu_runtime_idle(struct device *dev)
1254{
1255 int err;
1256
1257 err = pm_schedule_suspend(dev, 500);
1258 if (err)
1259 return -EBUSY;
1260
1261 return 0;
1262}
1263
1264static int serial_hsu_runtime_suspend(struct device *dev)
1265{
1266 return 0;
1267}
1268
1269static int serial_hsu_runtime_resume(struct device *dev)
1270{
1271 return 0;
1272}
1273#else
1274#define serial_hsu_runtime_idle NULL
1275#define serial_hsu_runtime_suspend NULL
1276#define serial_hsu_runtime_resume NULL
1277#endif
1278
1279static const struct dev_pm_ops serial_hsu_pm_ops = {
1280 .runtime_suspend = serial_hsu_runtime_suspend,
1281 .runtime_resume = serial_hsu_runtime_resume,
1282 .runtime_idle = serial_hsu_runtime_idle,
1283};
1284
1285/* temp global pointer before we settle down on using one or four PCI dev */
1286static struct hsu_port *phsu;
1287
1288static int serial_hsu_probe(struct pci_dev *pdev,
1289 const struct pci_device_id *ent)
1290{
1291 struct uart_hsu_port *uport;
1292 int index, ret;
1293
1294 printk(KERN_INFO "HSU: found PCI Serial controller(ID: %04x:%04x)\n",
1295 pdev->vendor, pdev->device);
1296
1297 switch (pdev->device) {
1298 case 0x081B:
1299 index = 0;
1300 break;
1301 case 0x081C:
1302 index = 1;
1303 break;
1304 case 0x081D:
1305 index = 2;
1306 break;
1307 case 0x081E:
1308 /* internal DMA controller */
1309 index = 3;
1310 break;
1311 default:
1312 dev_err(&pdev->dev, "HSU: out of index!");
1313 return -ENODEV;
1314 }
1315
1316 ret = pci_enable_device(pdev);
1317 if (ret)
1318 return ret;
1319
1320 if (index == 3) {
1321 /* DMA controller */
1322 ret = request_irq(pdev->irq, dma_irq, 0, "hsu_dma", phsu);
1323 if (ret) {
1324 dev_err(&pdev->dev, "can not get IRQ\n");
1325 goto err_disable;
1326 }
1327 pci_set_drvdata(pdev, phsu);
1328 } else {
1329 /* UART port 0~2 */
1330 uport = &phsu->port[index];
1331 uport->port.irq = pdev->irq;
1332 uport->port.dev = &pdev->dev;
1333 uport->dev = &pdev->dev;
1334
1335 ret = request_irq(pdev->irq, port_irq, 0, uport->name, uport);
1336 if (ret) {
1337 dev_err(&pdev->dev, "can not get IRQ\n");
1338 goto err_disable;
1339 }
1340 uart_add_one_port(&serial_hsu_reg, &uport->port);
1341
1342 pci_set_drvdata(pdev, uport);
1343 }
1344
1345 pm_runtime_put_noidle(&pdev->dev);
1346 pm_runtime_allow(&pdev->dev);
1347
1348 return 0;
1349
1350err_disable:
1351 pci_disable_device(pdev);
1352 return ret;
1353}
1354
1355static void hsu_global_init(void)
1356{
1357 struct hsu_port *hsu;
1358 struct uart_hsu_port *uport;
1359 struct hsu_dma_chan *dchan;
1360 int i, ret;
1361
1362 hsu = kzalloc(sizeof(struct hsu_port), GFP_KERNEL);
1363 if (!hsu)
1364 return;
1365
1366 /* Get basic io resource and map it */
1367 hsu->paddr = 0xffa28000;
1368 hsu->iolen = 0x1000;
1369
1370 if (!(request_mem_region(hsu->paddr, hsu->iolen, "HSU global")))
1371 pr_warning("HSU: error in request mem region\n");
1372
1373 hsu->reg = ioremap_nocache((unsigned long)hsu->paddr, hsu->iolen);
1374 if (!hsu->reg) {
1375 pr_err("HSU: error in ioremap\n");
1376 ret = -ENOMEM;
1377 goto err_free_region;
1378 }
1379
1380 /* Initialise the 3 UART ports */
1381 uport = hsu->port;
1382 for (i = 0; i < 3; i++) {
1383 uport->port.type = PORT_MFD;
1384 uport->port.iotype = UPIO_MEM;
1385 uport->port.mapbase = (resource_size_t)hsu->paddr
1386 + HSU_PORT_REG_OFFSET
1387 + i * HSU_PORT_REG_LENGTH;
1388 uport->port.membase = hsu->reg + HSU_PORT_REG_OFFSET
1389 + i * HSU_PORT_REG_LENGTH;
1390
1391 sprintf(uport->name, "hsu_port%d", i);
1392 uport->port.fifosize = 64;
1393 uport->port.ops = &serial_hsu_pops;
1394 uport->port.line = i;
1395 uport->port.flags = UPF_IOREMAP;
1396 /* set the scalable maxim support rate to 2746800 bps */
1397 uport->port.uartclk = 115200 * 24 * 16;
1398
1399 uport->running = 0;
1400 uport->txc = &hsu->chans[i * 2];
1401 uport->rxc = &hsu->chans[i * 2 + 1];
1402
1403 serial_hsu_ports[i] = uport;
1404 uport->index = i;
1405
1406 if (hsu_dma_enable & (1<<i))
1407 uport->use_dma = 1;
1408 else
1409 uport->use_dma = 0;
1410
1411 uport++;
1412 }
1413
1414 /* Initialise 6 dma channels */
1415 dchan = hsu->chans;
1416 for (i = 0; i < 6; i++) {
1417 dchan->id = i;
1418 dchan->dirt = (i & 0x1) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1419 dchan->uport = &hsu->port[i/2];
1420 dchan->reg = hsu->reg + HSU_DMA_CHANS_REG_OFFSET +
1421 i * HSU_DMA_CHANS_REG_LENGTH;
1422
1423 dchan++;
1424 }
1425
1426 phsu = hsu;
1427 hsu_debugfs_init(hsu);
1428 return;
1429
1430err_free_region:
1431 release_mem_region(hsu->paddr, hsu->iolen);
1432 kfree(hsu);
1433 return;
1434}
1435
1436static void serial_hsu_remove(struct pci_dev *pdev)
1437{
1438 void *priv = pci_get_drvdata(pdev);
1439 struct uart_hsu_port *up;
1440
1441 if (!priv)
1442 return;
1443
1444 pm_runtime_forbid(&pdev->dev);
1445 pm_runtime_get_noresume(&pdev->dev);
1446
1447 /* For port 0/1/2, priv is the address of uart_hsu_port */
1448 if (pdev->device != 0x081E) {
1449 up = priv;
1450 uart_remove_one_port(&serial_hsu_reg, &up->port);
1451 }
1452
1453 pci_set_drvdata(pdev, NULL);
1454 free_irq(pdev->irq, priv);
1455 pci_disable_device(pdev);
1456}
1457
1458/* First 3 are UART ports, and the 4th is the DMA */
1459static const struct pci_device_id pci_ids[] __devinitconst = {
1460 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081B) },
1461 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081C) },
1462 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081D) },
1463 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081E) },
1464 {},
1465};
1466
1467static struct pci_driver hsu_pci_driver = {
1468 .name = "HSU serial",
1469 .id_table = pci_ids,
1470 .probe = serial_hsu_probe,
1471 .remove = __devexit_p(serial_hsu_remove),
1472 .suspend = serial_hsu_suspend,
1473 .resume = serial_hsu_resume,
1474 .driver = {
1475 .pm = &serial_hsu_pm_ops,
1476 },
1477};
1478
1479static int __init hsu_pci_init(void)
1480{
1481 int ret;
1482
1483 hsu_global_init();
1484
1485 ret = uart_register_driver(&serial_hsu_reg);
1486 if (ret)
1487 return ret;
1488
1489 return pci_register_driver(&hsu_pci_driver);
1490}
1491
1492static void __exit hsu_pci_exit(void)
1493{
1494 pci_unregister_driver(&hsu_pci_driver);
1495 uart_unregister_driver(&serial_hsu_reg);
1496
1497 hsu_debugfs_remove(phsu);
1498
1499 kfree(phsu);
1500}
1501
1502module_init(hsu_pci_init);
1503module_exit(hsu_pci_exit);
1504
1505MODULE_LICENSE("GPL v2");
1506MODULE_ALIAS("platform:medfield-hsu");