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1/*
2 * SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs
3 *
4 * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * This driver has been based on the spi-gpio.c:
7 * Copyright (C) 2006,2008 David Brownell
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 */
14
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/spinlock.h>
19#include <linux/workqueue.h>
20#include <linux/platform_device.h>
21#include <linux/io.h>
22#include <linux/spi/spi.h>
23#include <linux/spi/spi_bitbang.h>
24#include <linux/bitops.h>
25#include <linux/gpio.h>
26
27#include <asm/mach-ath79/ar71xx_regs.h>
28#include <asm/mach-ath79/ath79_spi_platform.h>
29
30#define DRV_NAME "ath79-spi"
31
32struct ath79_spi {
33 struct spi_bitbang bitbang;
34 u32 ioc_base;
35 u32 reg_ctrl;
36 void __iomem *base;
37};
38
39static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned reg)
40{
41 return ioread32(sp->base + reg);
42}
43
44static inline void ath79_spi_wr(struct ath79_spi *sp, unsigned reg, u32 val)
45{
46 iowrite32(val, sp->base + reg);
47}
48
49static inline struct ath79_spi *ath79_spidev_to_sp(struct spi_device *spi)
50{
51 return spi_master_get_devdata(spi->master);
52}
53
54static void ath79_spi_chipselect(struct spi_device *spi, int is_active)
55{
56 struct ath79_spi *sp = ath79_spidev_to_sp(spi);
57 int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active;
58
59 if (is_active) {
60 /* set initial clock polarity */
61 if (spi->mode & SPI_CPOL)
62 sp->ioc_base |= AR71XX_SPI_IOC_CLK;
63 else
64 sp->ioc_base &= ~AR71XX_SPI_IOC_CLK;
65
66 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
67 }
68
69 if (spi->chip_select) {
70 struct ath79_spi_controller_data *cdata = spi->controller_data;
71
72 /* SPI is normally active-low */
73 gpio_set_value(cdata->gpio, cs_high);
74 } else {
75 if (cs_high)
76 sp->ioc_base |= AR71XX_SPI_IOC_CS0;
77 else
78 sp->ioc_base &= ~AR71XX_SPI_IOC_CS0;
79
80 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
81 }
82
83}
84
85static int ath79_spi_setup_cs(struct spi_device *spi)
86{
87 struct ath79_spi *sp = ath79_spidev_to_sp(spi);
88 struct ath79_spi_controller_data *cdata;
89
90 cdata = spi->controller_data;
91 if (spi->chip_select && !cdata)
92 return -EINVAL;
93
94 /* enable GPIO mode */
95 ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
96
97 /* save CTRL register */
98 sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL);
99 sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC);
100
101 /* TODO: setup speed? */
102 ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
103
104 if (spi->chip_select) {
105 int status = 0;
106
107 status = gpio_request(cdata->gpio, dev_name(&spi->dev));
108 if (status)
109 return status;
110
111 status = gpio_direction_output(cdata->gpio,
112 spi->mode & SPI_CS_HIGH);
113 if (status) {
114 gpio_free(cdata->gpio);
115 return status;
116 }
117 } else {
118 if (spi->mode & SPI_CS_HIGH)
119 sp->ioc_base |= AR71XX_SPI_IOC_CS0;
120 else
121 sp->ioc_base &= ~AR71XX_SPI_IOC_CS0;
122 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
123 }
124
125 return 0;
126}
127
128static void ath79_spi_cleanup_cs(struct spi_device *spi)
129{
130 struct ath79_spi *sp = ath79_spidev_to_sp(spi);
131
132 if (spi->chip_select) {
133 struct ath79_spi_controller_data *cdata = spi->controller_data;
134 gpio_free(cdata->gpio);
135 }
136
137 /* restore CTRL register */
138 ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl);
139 /* disable GPIO mode */
140 ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
141}
142
143static int ath79_spi_setup(struct spi_device *spi)
144{
145 int status = 0;
146
147 if (spi->bits_per_word > 32)
148 return -EINVAL;
149
150 if (!spi->controller_state) {
151 status = ath79_spi_setup_cs(spi);
152 if (status)
153 return status;
154 }
155
156 status = spi_bitbang_setup(spi);
157 if (status && !spi->controller_state)
158 ath79_spi_cleanup_cs(spi);
159
160 return status;
161}
162
163static void ath79_spi_cleanup(struct spi_device *spi)
164{
165 ath79_spi_cleanup_cs(spi);
166 spi_bitbang_cleanup(spi);
167}
168
169static u32 ath79_spi_txrx_mode0(struct spi_device *spi, unsigned nsecs,
170 u32 word, u8 bits)
171{
172 struct ath79_spi *sp = ath79_spidev_to_sp(spi);
173 u32 ioc = sp->ioc_base;
174
175 /* clock starts at inactive polarity */
176 for (word <<= (32 - bits); likely(bits); bits--) {
177 u32 out;
178
179 if (word & (1 << 31))
180 out = ioc | AR71XX_SPI_IOC_DO;
181 else
182 out = ioc & ~AR71XX_SPI_IOC_DO;
183
184 /* setup MSB (to slave) on trailing edge */
185 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
186 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK);
187
188 word <<= 1;
189 }
190
191 return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS);
192}
193
194static __devinit int ath79_spi_probe(struct platform_device *pdev)
195{
196 struct spi_master *master;
197 struct ath79_spi *sp;
198 struct ath79_spi_platform_data *pdata;
199 struct resource *r;
200 int ret;
201
202 master = spi_alloc_master(&pdev->dev, sizeof(*sp));
203 if (master == NULL) {
204 dev_err(&pdev->dev, "failed to allocate spi master\n");
205 return -ENOMEM;
206 }
207
208 sp = spi_master_get_devdata(master);
209 platform_set_drvdata(pdev, sp);
210
211 pdata = pdev->dev.platform_data;
212
213 master->setup = ath79_spi_setup;
214 master->cleanup = ath79_spi_cleanup;
215 if (pdata) {
216 master->bus_num = pdata->bus_num;
217 master->num_chipselect = pdata->num_chipselect;
218 } else {
219 master->bus_num = -1;
220 master->num_chipselect = 1;
221 }
222
223 sp->bitbang.master = spi_master_get(master);
224 sp->bitbang.chipselect = ath79_spi_chipselect;
225 sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0;
226 sp->bitbang.setup_transfer = spi_bitbang_setup_transfer;
227 sp->bitbang.flags = SPI_CS_HIGH;
228
229 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
230 if (r == NULL) {
231 ret = -ENOENT;
232 goto err_put_master;
233 }
234
235 sp->base = ioremap(r->start, resource_size(r));
236 if (!sp->base) {
237 ret = -ENXIO;
238 goto err_put_master;
239 }
240
241 ret = spi_bitbang_start(&sp->bitbang);
242 if (ret)
243 goto err_unmap;
244
245 return 0;
246
247err_unmap:
248 iounmap(sp->base);
249err_put_master:
250 platform_set_drvdata(pdev, NULL);
251 spi_master_put(sp->bitbang.master);
252
253 return ret;
254}
255
256static __devexit int ath79_spi_remove(struct platform_device *pdev)
257{
258 struct ath79_spi *sp = platform_get_drvdata(pdev);
259
260 spi_bitbang_stop(&sp->bitbang);
261 iounmap(sp->base);
262 platform_set_drvdata(pdev, NULL);
263 spi_master_put(sp->bitbang.master);
264
265 return 0;
266}
267
268static struct platform_driver ath79_spi_driver = {
269 .probe = ath79_spi_probe,
270 .remove = __devexit_p(ath79_spi_remove),
271 .driver = {
272 .name = DRV_NAME,
273 .owner = THIS_MODULE,
274 },
275};
276
277static __init int ath79_spi_init(void)
278{
279 return platform_driver_register(&ath79_spi_driver);
280}
281module_init(ath79_spi_init);
282
283static __exit void ath79_spi_exit(void)
284{
285 platform_driver_unregister(&ath79_spi_driver);
286}
287module_exit(ath79_spi_exit);
288
289MODULE_DESCRIPTION("SPI controller driver for Atheros AR71XX/AR724X/AR913X");
290MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
291MODULE_LICENSE("GPL v2");
292MODULE_ALIAS("platform:" DRV_NAME);
1/*
2 * SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs
3 *
4 * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * This driver has been based on the spi-gpio.c:
7 * Copyright (C) 2006,2008 David Brownell
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 */
14
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/init.h>
18#include <linux/delay.h>
19#include <linux/spinlock.h>
20#include <linux/workqueue.h>
21#include <linux/platform_device.h>
22#include <linux/io.h>
23#include <linux/spi/spi.h>
24#include <linux/spi/spi_bitbang.h>
25#include <linux/bitops.h>
26#include <linux/gpio.h>
27
28#include <asm/mach-ath79/ar71xx_regs.h>
29#include <asm/mach-ath79/ath79_spi_platform.h>
30
31#define DRV_NAME "ath79-spi"
32
33struct ath79_spi {
34 struct spi_bitbang bitbang;
35 u32 ioc_base;
36 u32 reg_ctrl;
37 void __iomem *base;
38};
39
40static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned reg)
41{
42 return ioread32(sp->base + reg);
43}
44
45static inline void ath79_spi_wr(struct ath79_spi *sp, unsigned reg, u32 val)
46{
47 iowrite32(val, sp->base + reg);
48}
49
50static inline struct ath79_spi *ath79_spidev_to_sp(struct spi_device *spi)
51{
52 return spi_master_get_devdata(spi->master);
53}
54
55static void ath79_spi_chipselect(struct spi_device *spi, int is_active)
56{
57 struct ath79_spi *sp = ath79_spidev_to_sp(spi);
58 int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active;
59
60 if (is_active) {
61 /* set initial clock polarity */
62 if (spi->mode & SPI_CPOL)
63 sp->ioc_base |= AR71XX_SPI_IOC_CLK;
64 else
65 sp->ioc_base &= ~AR71XX_SPI_IOC_CLK;
66
67 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
68 }
69
70 if (spi->chip_select) {
71 struct ath79_spi_controller_data *cdata = spi->controller_data;
72
73 /* SPI is normally active-low */
74 gpio_set_value(cdata->gpio, cs_high);
75 } else {
76 if (cs_high)
77 sp->ioc_base |= AR71XX_SPI_IOC_CS0;
78 else
79 sp->ioc_base &= ~AR71XX_SPI_IOC_CS0;
80
81 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
82 }
83
84}
85
86static int ath79_spi_setup_cs(struct spi_device *spi)
87{
88 struct ath79_spi *sp = ath79_spidev_to_sp(spi);
89 struct ath79_spi_controller_data *cdata;
90
91 cdata = spi->controller_data;
92 if (spi->chip_select && !cdata)
93 return -EINVAL;
94
95 /* enable GPIO mode */
96 ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
97
98 /* save CTRL register */
99 sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL);
100 sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC);
101
102 /* TODO: setup speed? */
103 ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
104
105 if (spi->chip_select) {
106 int status = 0;
107
108 status = gpio_request(cdata->gpio, dev_name(&spi->dev));
109 if (status)
110 return status;
111
112 status = gpio_direction_output(cdata->gpio,
113 spi->mode & SPI_CS_HIGH);
114 if (status) {
115 gpio_free(cdata->gpio);
116 return status;
117 }
118 } else {
119 if (spi->mode & SPI_CS_HIGH)
120 sp->ioc_base |= AR71XX_SPI_IOC_CS0;
121 else
122 sp->ioc_base &= ~AR71XX_SPI_IOC_CS0;
123 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
124 }
125
126 return 0;
127}
128
129static void ath79_spi_cleanup_cs(struct spi_device *spi)
130{
131 struct ath79_spi *sp = ath79_spidev_to_sp(spi);
132
133 if (spi->chip_select) {
134 struct ath79_spi_controller_data *cdata = spi->controller_data;
135 gpio_free(cdata->gpio);
136 }
137
138 /* restore CTRL register */
139 ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl);
140 /* disable GPIO mode */
141 ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
142}
143
144static int ath79_spi_setup(struct spi_device *spi)
145{
146 int status = 0;
147
148 if (spi->bits_per_word > 32)
149 return -EINVAL;
150
151 if (!spi->controller_state) {
152 status = ath79_spi_setup_cs(spi);
153 if (status)
154 return status;
155 }
156
157 status = spi_bitbang_setup(spi);
158 if (status && !spi->controller_state)
159 ath79_spi_cleanup_cs(spi);
160
161 return status;
162}
163
164static void ath79_spi_cleanup(struct spi_device *spi)
165{
166 ath79_spi_cleanup_cs(spi);
167 spi_bitbang_cleanup(spi);
168}
169
170static u32 ath79_spi_txrx_mode0(struct spi_device *spi, unsigned nsecs,
171 u32 word, u8 bits)
172{
173 struct ath79_spi *sp = ath79_spidev_to_sp(spi);
174 u32 ioc = sp->ioc_base;
175
176 /* clock starts at inactive polarity */
177 for (word <<= (32 - bits); likely(bits); bits--) {
178 u32 out;
179
180 if (word & (1 << 31))
181 out = ioc | AR71XX_SPI_IOC_DO;
182 else
183 out = ioc & ~AR71XX_SPI_IOC_DO;
184
185 /* setup MSB (to slave) on trailing edge */
186 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
187 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK);
188
189 word <<= 1;
190 }
191
192 return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS);
193}
194
195static __devinit int ath79_spi_probe(struct platform_device *pdev)
196{
197 struct spi_master *master;
198 struct ath79_spi *sp;
199 struct ath79_spi_platform_data *pdata;
200 struct resource *r;
201 int ret;
202
203 master = spi_alloc_master(&pdev->dev, sizeof(*sp));
204 if (master == NULL) {
205 dev_err(&pdev->dev, "failed to allocate spi master\n");
206 return -ENOMEM;
207 }
208
209 sp = spi_master_get_devdata(master);
210 platform_set_drvdata(pdev, sp);
211
212 pdata = pdev->dev.platform_data;
213
214 master->setup = ath79_spi_setup;
215 master->cleanup = ath79_spi_cleanup;
216 if (pdata) {
217 master->bus_num = pdata->bus_num;
218 master->num_chipselect = pdata->num_chipselect;
219 }
220
221 sp->bitbang.master = spi_master_get(master);
222 sp->bitbang.chipselect = ath79_spi_chipselect;
223 sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0;
224 sp->bitbang.setup_transfer = spi_bitbang_setup_transfer;
225 sp->bitbang.flags = SPI_CS_HIGH;
226
227 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
228 if (r == NULL) {
229 ret = -ENOENT;
230 goto err_put_master;
231 }
232
233 sp->base = ioremap(r->start, resource_size(r));
234 if (!sp->base) {
235 ret = -ENXIO;
236 goto err_put_master;
237 }
238
239 ret = spi_bitbang_start(&sp->bitbang);
240 if (ret)
241 goto err_unmap;
242
243 return 0;
244
245err_unmap:
246 iounmap(sp->base);
247err_put_master:
248 platform_set_drvdata(pdev, NULL);
249 spi_master_put(sp->bitbang.master);
250
251 return ret;
252}
253
254static __devexit int ath79_spi_remove(struct platform_device *pdev)
255{
256 struct ath79_spi *sp = platform_get_drvdata(pdev);
257
258 spi_bitbang_stop(&sp->bitbang);
259 iounmap(sp->base);
260 platform_set_drvdata(pdev, NULL);
261 spi_master_put(sp->bitbang.master);
262
263 return 0;
264}
265
266static struct platform_driver ath79_spi_driver = {
267 .probe = ath79_spi_probe,
268 .remove = __devexit_p(ath79_spi_remove),
269 .driver = {
270 .name = DRV_NAME,
271 .owner = THIS_MODULE,
272 },
273};
274module_platform_driver(ath79_spi_driver);
275
276MODULE_DESCRIPTION("SPI controller driver for Atheros AR71XX/AR724X/AR913X");
277MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
278MODULE_LICENSE("GPL v2");
279MODULE_ALIAS("platform:" DRV_NAME);