1/******************************************************************************
   2 *
   3 * Copyright(c) 2009-2010  Realtek Corporation.
   4 *
   5 * This program is free software; you can redistribute it and/or modify it
   6 * under the terms of version 2 of the GNU General Public License as
   7 * published by the Free Software Foundation.
   8 *
   9 * This program is distributed in the hope that it will be useful, but WITHOUT
  10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12 * more details.
  13 *
  14 * You should have received a copy of the GNU General Public License along with
  15 * this program; if not, write to the Free Software Foundation, Inc.,
  16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17 *
  18 * The full GNU General Public License is included in this distribution in the
  19 * file called LICENSE.
  20 *
  21 * Contact Information:
  22 * wlanfae <wlanfae@realtek.com>
  23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24 * Hsinchu 300, Taiwan.
  25 *
  26 * Larry Finger <Larry.Finger@lwfinger.net>
  27 *
  28 *****************************************************************************/
  29
  30#ifndef __RTL_WIFI_H__
  31#define __RTL_WIFI_H__
  32
 
 
  33#include <linux/sched.h>
  34#include <linux/firmware.h>
  35#include <linux/etherdevice.h>
  36#include <linux/vmalloc.h>
  37#include <linux/usb.h>
  38#include <net/mac80211.h>
 
  39#include "debug.h"
  40
  41#define RF_CHANGE_BY_INIT			0
  42#define RF_CHANGE_BY_IPS			BIT(28)
  43#define RF_CHANGE_BY_PS				BIT(29)
  44#define RF_CHANGE_BY_HW				BIT(30)
  45#define RF_CHANGE_BY_SW				BIT(31)
  46
  47#define IQK_ADDA_REG_NUM			16
  48#define IQK_MAC_REG_NUM				4
  49
  50#define MAX_KEY_LEN				61
  51#define KEY_BUF_SIZE				5
  52
  53/* QoS related. */
  54/*aci: 0x00	Best Effort*/
  55/*aci: 0x01	Background*/
  56/*aci: 0x10	Video*/
  57/*aci: 0x11	Voice*/
  58/*Max: define total number.*/
  59#define AC0_BE					0
  60#define AC1_BK					1
  61#define AC2_VI					2
  62#define AC3_VO					3
  63#define AC_MAX					4
  64#define QOS_QUEUE_NUM				4
  65#define RTL_MAC80211_NUM_QUEUE			5
  66
 
  67#define QBSS_LOAD_SIZE				5
  68#define MAX_WMMELE_LENGTH			64
  69
  70#define TOTAL_CAM_ENTRY				32
  71
  72/*slot time for 11g. */
  73#define RTL_SLOT_TIME_9				9
  74#define RTL_SLOT_TIME_20			20
  75
  76/*related with tcp/ip. */
  77/*if_ehther.h*/
  78#define ETH_P_PAE		0x888E	/*Port Access Entity (IEEE 802.1X) */
  79#define ETH_P_IP		0x0800	/*Internet Protocol packet */
  80#define ETH_P_ARP		0x0806	/*Address Resolution packet */
  81#define SNAP_SIZE		6
  82#define PROTOC_TYPE_SIZE	2
  83
  84/*related with 802.11 frame*/
  85#define MAC80211_3ADDR_LEN			24
  86#define MAC80211_4ADDR_LEN			30
  87
  88#define CHANNEL_MAX_NUMBER	(14 + 24 + 21)	/* 14 is the max channel no */
  89#define CHANNEL_GROUP_MAX	(3 + 9)	/*  ch1~3, 4~9, 10~14 = three groups */
  90#define MAX_PG_GROUP			13
  91#define	CHANNEL_GROUP_MAX_2G		3
  92#define	CHANNEL_GROUP_IDX_5GL		3
  93#define	CHANNEL_GROUP_IDX_5GM		6
  94#define	CHANNEL_GROUP_IDX_5GH		9
  95#define	CHANNEL_GROUP_MAX_5G		9
  96#define CHANNEL_MAX_NUMBER_2G		14
  97#define AVG_THERMAL_NUM			8
  98#define MAX_TID_COUNT			9
  99
 100/* for early mode */
 101#define FCS_LEN				4
 102#define EM_HDR_LEN			8
 103enum intf_type {
 104	INTF_PCI = 0,
 105	INTF_USB = 1,
 106};
 107
 108enum radio_path {
 109	RF90_PATH_A = 0,
 110	RF90_PATH_B = 1,
 111	RF90_PATH_C = 2,
 112	RF90_PATH_D = 3,
 113};
 114
 115enum rt_eeprom_type {
 116	EEPROM_93C46,
 117	EEPROM_93C56,
 118	EEPROM_BOOT_EFUSE,
 119};
 120
 121enum rtl_status {
 122	RTL_STATUS_INTERFACE_START = 0,
 123};
 124
 125enum hardware_type {
 126	HARDWARE_TYPE_RTL8192E,
 127	HARDWARE_TYPE_RTL8192U,
 128	HARDWARE_TYPE_RTL8192SE,
 129	HARDWARE_TYPE_RTL8192SU,
 130	HARDWARE_TYPE_RTL8192CE,
 131	HARDWARE_TYPE_RTL8192CU,
 132	HARDWARE_TYPE_RTL8192DE,
 133	HARDWARE_TYPE_RTL8192DU,
 134	HARDWARE_TYPE_RTL8723E,
 135	HARDWARE_TYPE_RTL8723U,
 136
 137	/* keep it last */
 138	HARDWARE_TYPE_NUM
 139};
 140
 141#define IS_HARDWARE_TYPE_8192SU(rtlhal)			\
 142	(rtlhal->hw_type == HARDWARE_TYPE_RTL8192SU)
 143#define IS_HARDWARE_TYPE_8192SE(rtlhal)			\
 144	(rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
 145#define IS_HARDWARE_TYPE_8192CE(rtlhal)			\
 146	(rtlhal->hw_type == HARDWARE_TYPE_RTL8192CE)
 147#define IS_HARDWARE_TYPE_8192CU(rtlhal)			\
 148	(rtlhal->hw_type == HARDWARE_TYPE_RTL8192CU)
 149#define IS_HARDWARE_TYPE_8192DE(rtlhal)			\
 150	(rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE)
 151#define IS_HARDWARE_TYPE_8192DU(rtlhal)			\
 152	(rtlhal->hw_type == HARDWARE_TYPE_RTL8192DU)
 153#define IS_HARDWARE_TYPE_8723E(rtlhal)			\
 154	(rtlhal->hw_type == HARDWARE_TYPE_RTL8723E)
 155#define IS_HARDWARE_TYPE_8723U(rtlhal)			\
 156	(rtlhal->hw_type == HARDWARE_TYPE_RTL8723U)
 157#define	IS_HARDWARE_TYPE_8192S(rtlhal)			\
 158(IS_HARDWARE_TYPE_8192SE(rtlhal) || IS_HARDWARE_TYPE_8192SU(rtlhal))
 159#define	IS_HARDWARE_TYPE_8192C(rtlhal)			\
 160(IS_HARDWARE_TYPE_8192CE(rtlhal) || IS_HARDWARE_TYPE_8192CU(rtlhal))
 161#define	IS_HARDWARE_TYPE_8192D(rtlhal)			\
 162(IS_HARDWARE_TYPE_8192DE(rtlhal) || IS_HARDWARE_TYPE_8192DU(rtlhal))
 163#define	IS_HARDWARE_TYPE_8723(rtlhal)			\
 164(IS_HARDWARE_TYPE_8723E(rtlhal) || IS_HARDWARE_TYPE_8723U(rtlhal))
 165#define IS_HARDWARE_TYPE_8723U(rtlhal)			\
 166	(rtlhal->hw_type == HARDWARE_TYPE_RTL8723U)
 167
 
 
 
 
 
 
 168enum scan_operation_backup_opt {
 169	SCAN_OPT_BACKUP = 0,
 170	SCAN_OPT_RESTORE,
 171	SCAN_OPT_MAX
 172};
 173
 174/*RF state.*/
 175enum rf_pwrstate {
 176	ERFON,
 177	ERFSLEEP,
 178	ERFOFF
 179};
 180
 181struct bb_reg_def {
 182	u32 rfintfs;
 183	u32 rfintfi;
 184	u32 rfintfo;
 185	u32 rfintfe;
 186	u32 rf3wire_offset;
 187	u32 rflssi_select;
 188	u32 rftxgain_stage;
 189	u32 rfhssi_para1;
 190	u32 rfhssi_para2;
 191	u32 rfswitch_control;
 192	u32 rfagc_control1;
 193	u32 rfagc_control2;
 194	u32 rfrxiq_imbalance;
 195	u32 rfrx_afe;
 196	u32 rftxiq_imbalance;
 197	u32 rftx_afe;
 198	u32 rflssi_readback;
 199	u32 rflssi_readbackpi;
 200};
 201
 202enum io_type {
 203	IO_CMD_PAUSE_DM_BY_SCAN = 0,
 204	IO_CMD_RESUME_DM_BY_SCAN = 1,
 205};
 206
 207enum hw_variables {
 208	HW_VAR_ETHER_ADDR,
 209	HW_VAR_MULTICAST_REG,
 210	HW_VAR_BASIC_RATE,
 211	HW_VAR_BSSID,
 212	HW_VAR_MEDIA_STATUS,
 213	HW_VAR_SECURITY_CONF,
 214	HW_VAR_BEACON_INTERVAL,
 215	HW_VAR_ATIM_WINDOW,
 216	HW_VAR_LISTEN_INTERVAL,
 217	HW_VAR_CS_COUNTER,
 218	HW_VAR_DEFAULTKEY0,
 219	HW_VAR_DEFAULTKEY1,
 220	HW_VAR_DEFAULTKEY2,
 221	HW_VAR_DEFAULTKEY3,
 222	HW_VAR_SIFS,
 223	HW_VAR_DIFS,
 224	HW_VAR_EIFS,
 225	HW_VAR_SLOT_TIME,
 226	HW_VAR_ACK_PREAMBLE,
 227	HW_VAR_CW_CONFIG,
 228	HW_VAR_CW_VALUES,
 229	HW_VAR_RATE_FALLBACK_CONTROL,
 230	HW_VAR_CONTENTION_WINDOW,
 231	HW_VAR_RETRY_COUNT,
 232	HW_VAR_TR_SWITCH,
 233	HW_VAR_COMMAND,
 234	HW_VAR_WPA_CONFIG,
 235	HW_VAR_AMPDU_MIN_SPACE,
 236	HW_VAR_SHORTGI_DENSITY,
 237	HW_VAR_AMPDU_FACTOR,
 238	HW_VAR_MCS_RATE_AVAILABLE,
 239	HW_VAR_AC_PARAM,
 240	HW_VAR_ACM_CTRL,
 241	HW_VAR_DIS_Req_Qsize,
 242	HW_VAR_CCX_CHNL_LOAD,
 243	HW_VAR_CCX_NOISE_HISTOGRAM,
 244	HW_VAR_CCX_CLM_NHM,
 245	HW_VAR_TxOPLimit,
 246	HW_VAR_TURBO_MODE,
 247	HW_VAR_RF_STATE,
 248	HW_VAR_RF_OFF_BY_HW,
 249	HW_VAR_BUS_SPEED,
 250	HW_VAR_SET_DEV_POWER,
 251
 252	HW_VAR_RCR,
 253	HW_VAR_RATR_0,
 254	HW_VAR_RRSR,
 255	HW_VAR_CPU_RST,
 256	HW_VAR_CECHK_BSSID,
 257	HW_VAR_LBK_MODE,
 258	HW_VAR_AES_11N_FIX,
 259	HW_VAR_USB_RX_AGGR,
 260	HW_VAR_USER_CONTROL_TURBO_MODE,
 261	HW_VAR_RETRY_LIMIT,
 262	HW_VAR_INIT_TX_RATE,
 263	HW_VAR_TX_RATE_REG,
 264	HW_VAR_EFUSE_USAGE,
 265	HW_VAR_EFUSE_BYTES,
 266	HW_VAR_AUTOLOAD_STATUS,
 267	HW_VAR_RF_2R_DISABLE,
 268	HW_VAR_SET_RPWM,
 269	HW_VAR_H2C_FW_PWRMODE,
 270	HW_VAR_H2C_FW_JOINBSSRPT,
 271	HW_VAR_FW_PSMODE_STATUS,
 272	HW_VAR_1X1_RECV_COMBINE,
 273	HW_VAR_STOP_SEND_BEACON,
 274	HW_VAR_TSF_TIMER,
 275	HW_VAR_IO_CMD,
 276
 277	HW_VAR_RF_RECOVERY,
 278	HW_VAR_H2C_FW_UPDATE_GTK,
 279	HW_VAR_WF_MASK,
 280	HW_VAR_WF_CRC,
 281	HW_VAR_WF_IS_MAC_ADDR,
 282	HW_VAR_H2C_FW_OFFLOAD,
 283	HW_VAR_RESET_WFCRC,
 284
 285	HW_VAR_HANDLE_FW_C2H,
 286	HW_VAR_DL_FW_RSVD_PAGE,
 287	HW_VAR_AID,
 288	HW_VAR_HW_SEQ_ENABLE,
 289	HW_VAR_CORRECT_TSF,
 290	HW_VAR_BCN_VALID,
 291	HW_VAR_FWLPS_RF_ON,
 292	HW_VAR_DUAL_TSF_RST,
 293	HW_VAR_SWITCH_EPHY_WoWLAN,
 294	HW_VAR_INT_MIGRATION,
 295	HW_VAR_INT_AC,
 296	HW_VAR_RF_TIMING,
 297
 298	HW_VAR_MRC,
 299
 300	HW_VAR_MGT_FILTER,
 301	HW_VAR_CTRL_FILTER,
 302	HW_VAR_DATA_FILTER,
 303};
 304
 305enum _RT_MEDIA_STATUS {
 306	RT_MEDIA_DISCONNECT = 0,
 307	RT_MEDIA_CONNECT = 1
 308};
 309
 310enum rt_oem_id {
 311	RT_CID_DEFAULT = 0,
 312	RT_CID_8187_ALPHA0 = 1,
 313	RT_CID_8187_SERCOMM_PS = 2,
 314	RT_CID_8187_HW_LED = 3,
 315	RT_CID_8187_NETGEAR = 4,
 316	RT_CID_WHQL = 5,
 317	RT_CID_819x_CAMEO = 6,
 318	RT_CID_819x_RUNTOP = 7,
 319	RT_CID_819x_Senao = 8,
 320	RT_CID_TOSHIBA = 9,
 321	RT_CID_819x_Netcore = 10,
 322	RT_CID_Nettronix = 11,
 323	RT_CID_DLINK = 12,
 324	RT_CID_PRONET = 13,
 325	RT_CID_COREGA = 14,
 326	RT_CID_819x_ALPHA = 15,
 327	RT_CID_819x_Sitecom = 16,
 328	RT_CID_CCX = 17,
 329	RT_CID_819x_Lenovo = 18,
 330	RT_CID_819x_QMI = 19,
 331	RT_CID_819x_Edimax_Belkin = 20,
 332	RT_CID_819x_Sercomm_Belkin = 21,
 333	RT_CID_819x_CAMEO1 = 22,
 334	RT_CID_819x_MSI = 23,
 335	RT_CID_819x_Acer = 24,
 336	RT_CID_819x_HP = 27,
 337	RT_CID_819x_CLEVO = 28,
 338	RT_CID_819x_Arcadyan_Belkin = 29,
 339	RT_CID_819x_SAMSUNG = 30,
 340	RT_CID_819x_WNC_COREGA = 31,
 341	RT_CID_819x_Foxcoon = 32,
 342	RT_CID_819x_DELL = 33,
 343};
 344
 345enum hw_descs {
 346	HW_DESC_OWN,
 347	HW_DESC_RXOWN,
 348	HW_DESC_TX_NEXTDESC_ADDR,
 349	HW_DESC_TXBUFF_ADDR,
 350	HW_DESC_RXBUFF_ADDR,
 351	HW_DESC_RXPKT_LEN,
 352	HW_DESC_RXERO,
 353};
 354
 355enum prime_sc {
 356	PRIME_CHNL_OFFSET_DONT_CARE = 0,
 357	PRIME_CHNL_OFFSET_LOWER = 1,
 358	PRIME_CHNL_OFFSET_UPPER = 2,
 359};
 360
 361enum rf_type {
 362	RF_1T1R = 0,
 363	RF_1T2R = 1,
 364	RF_2T2R = 2,
 365	RF_2T2R_GREEN = 3,
 366};
 367
 368enum ht_channel_width {
 369	HT_CHANNEL_WIDTH_20 = 0,
 370	HT_CHANNEL_WIDTH_20_40 = 1,
 371};
 372
 373/* Ref: 802.11i sepc D10.0 7.3.2.25.1
 374Cipher Suites Encryption Algorithms */
 375enum rt_enc_alg {
 376	NO_ENCRYPTION = 0,
 377	WEP40_ENCRYPTION = 1,
 378	TKIP_ENCRYPTION = 2,
 379	RSERVED_ENCRYPTION = 3,
 380	AESCCMP_ENCRYPTION = 4,
 381	WEP104_ENCRYPTION = 5,
 382};
 383
 384enum rtl_hal_state {
 385	_HAL_STATE_STOP = 0,
 386	_HAL_STATE_START = 1,
 387};
 388
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 389enum rtl_var_map {
 390	/*reg map */
 391	SYS_ISO_CTRL = 0,
 392	SYS_FUNC_EN,
 393	SYS_CLK,
 394	MAC_RCR_AM,
 395	MAC_RCR_AB,
 396	MAC_RCR_ACRC32,
 397	MAC_RCR_ACF,
 398	MAC_RCR_AAP,
 399
 400	/*efuse map */
 401	EFUSE_TEST,
 402	EFUSE_CTRL,
 403	EFUSE_CLK,
 404	EFUSE_CLK_CTRL,
 405	EFUSE_PWC_EV12V,
 406	EFUSE_FEN_ELDR,
 407	EFUSE_LOADER_CLK_EN,
 408	EFUSE_ANA8M,
 409	EFUSE_HWSET_MAX_SIZE,
 410	EFUSE_MAX_SECTION_MAP,
 411	EFUSE_REAL_CONTENT_SIZE,
 
 412
 413	/*CAM map */
 414	RWCAM,
 415	WCAMI,
 416	RCAMO,
 417	CAMDBG,
 418	SECR,
 419	SEC_CAM_NONE,
 420	SEC_CAM_WEP40,
 421	SEC_CAM_TKIP,
 422	SEC_CAM_AES,
 423	SEC_CAM_WEP104,
 424
 425	/*IMR map */
 426	RTL_IMR_BCNDMAINT6,	/*Beacon DMA Interrupt 6 */
 427	RTL_IMR_BCNDMAINT5,	/*Beacon DMA Interrupt 5 */
 428	RTL_IMR_BCNDMAINT4,	/*Beacon DMA Interrupt 4 */
 429	RTL_IMR_BCNDMAINT3,	/*Beacon DMA Interrupt 3 */
 430	RTL_IMR_BCNDMAINT2,	/*Beacon DMA Interrupt 2 */
 431	RTL_IMR_BCNDMAINT1,	/*Beacon DMA Interrupt 1 */
 432	RTL_IMR_BCNDOK8,	/*Beacon Queue DMA OK Interrup 8 */
 433	RTL_IMR_BCNDOK7,	/*Beacon Queue DMA OK Interrup 7 */
 434	RTL_IMR_BCNDOK6,	/*Beacon Queue DMA OK Interrup 6 */
 435	RTL_IMR_BCNDOK5,	/*Beacon Queue DMA OK Interrup 5 */
 436	RTL_IMR_BCNDOK4,	/*Beacon Queue DMA OK Interrup 4 */
 437	RTL_IMR_BCNDOK3,	/*Beacon Queue DMA OK Interrup 3 */
 438	RTL_IMR_BCNDOK2,	/*Beacon Queue DMA OK Interrup 2 */
 439	RTL_IMR_BCNDOK1,	/*Beacon Queue DMA OK Interrup 1 */
 440	RTL_IMR_TIMEOUT2,	/*Timeout interrupt 2 */
 441	RTL_IMR_TIMEOUT1,	/*Timeout interrupt 1 */
 442	RTL_IMR_TXFOVW,		/*Transmit FIFO Overflow */
 443	RTL_IMR_PSTIMEOUT,	/*Power save time out interrupt */
 444	RTL_IMR_BcnInt,		/*Beacon DMA Interrupt 0 */
 445	RTL_IMR_RXFOVW,		/*Receive FIFO Overflow */
 446	RTL_IMR_RDU,		/*Receive Descriptor Unavailable */
 447	RTL_IMR_ATIMEND,	/*For 92C,ATIM Window End Interrupt */
 448	RTL_IMR_BDOK,		/*Beacon Queue DMA OK Interrup */
 449	RTL_IMR_HIGHDOK,	/*High Queue DMA OK Interrupt */
 450	RTL_IMR_COMDOK,		/*Command Queue DMA OK Interrupt*/
 451	RTL_IMR_TBDOK,		/*Transmit Beacon OK interrup */
 452	RTL_IMR_MGNTDOK,	/*Management Queue DMA OK Interrupt */
 453	RTL_IMR_TBDER,		/*For 92C,Transmit Beacon Error Interrupt */
 454	RTL_IMR_BKDOK,		/*AC_BK DMA OK Interrupt */
 455	RTL_IMR_BEDOK,		/*AC_BE DMA OK Interrupt */
 456	RTL_IMR_VIDOK,		/*AC_VI DMA OK Interrupt */
 457	RTL_IMR_VODOK,		/*AC_VO DMA Interrupt */
 458	RTL_IMR_ROK,		/*Receive DMA OK Interrupt */
 459	RTL_IBSS_INT_MASKS,	/*(RTL_IMR_BcnInt | RTL_IMR_TBDOK |
 460				 * RTL_IMR_TBDER) */
 461
 462	/*CCK Rates, TxHT = 0 */
 463	RTL_RC_CCK_RATE1M,
 464	RTL_RC_CCK_RATE2M,
 465	RTL_RC_CCK_RATE5_5M,
 466	RTL_RC_CCK_RATE11M,
 467
 468	/*OFDM Rates, TxHT = 0 */
 469	RTL_RC_OFDM_RATE6M,
 470	RTL_RC_OFDM_RATE9M,
 471	RTL_RC_OFDM_RATE12M,
 472	RTL_RC_OFDM_RATE18M,
 473	RTL_RC_OFDM_RATE24M,
 474	RTL_RC_OFDM_RATE36M,
 475	RTL_RC_OFDM_RATE48M,
 476	RTL_RC_OFDM_RATE54M,
 477
 478	RTL_RC_HT_RATEMCS7,
 479	RTL_RC_HT_RATEMCS15,
 480
 481	/*keep it last */
 482	RTL_VAR_MAP_MAX,
 483};
 484
 485/*Firmware PS mode for control LPS.*/
 486enum _fw_ps_mode {
 487	FW_PS_ACTIVE_MODE = 0,
 488	FW_PS_MIN_MODE = 1,
 489	FW_PS_MAX_MODE = 2,
 490	FW_PS_DTIM_MODE = 3,
 491	FW_PS_VOIP_MODE = 4,
 492	FW_PS_UAPSD_WMM_MODE = 5,
 493	FW_PS_UAPSD_MODE = 6,
 494	FW_PS_IBSS_MODE = 7,
 495	FW_PS_WWLAN_MODE = 8,
 496	FW_PS_PM_Radio_Off = 9,
 497	FW_PS_PM_Card_Disable = 10,
 498};
 499
 500enum rt_psmode {
 501	EACTIVE,		/*Active/Continuous access. */
 502	EMAXPS,			/*Max power save mode. */
 503	EFASTPS,		/*Fast power save mode. */
 504	EAUTOPS,		/*Auto power save mode. */
 505};
 506
 507/*LED related.*/
 508enum led_ctl_mode {
 509	LED_CTL_POWER_ON = 1,
 510	LED_CTL_LINK = 2,
 511	LED_CTL_NO_LINK = 3,
 512	LED_CTL_TX = 4,
 513	LED_CTL_RX = 5,
 514	LED_CTL_SITE_SURVEY = 6,
 515	LED_CTL_POWER_OFF = 7,
 516	LED_CTL_START_TO_LINK = 8,
 517	LED_CTL_START_WPS = 9,
 518	LED_CTL_STOP_WPS = 10,
 519};
 520
 521enum rtl_led_pin {
 522	LED_PIN_GPIO0,
 523	LED_PIN_LED0,
 524	LED_PIN_LED1,
 525	LED_PIN_LED2
 526};
 527
 528/*QoS related.*/
 529/*acm implementation method.*/
 530enum acm_method {
 531	eAcmWay0_SwAndHw = 0,
 532	eAcmWay1_HW = 1,
 533	eAcmWay2_SW = 2,
 534};
 535
 536enum macphy_mode {
 537	SINGLEMAC_SINGLEPHY = 0,
 538	DUALMAC_DUALPHY,
 539	DUALMAC_SINGLEPHY,
 540};
 541
 542enum band_type {
 543	BAND_ON_2_4G = 0,
 544	BAND_ON_5G,
 545	BAND_ON_BOTH,
 546	BANDMAX
 547};
 548
 549/*aci/aifsn Field.
 550Ref: WMM spec 2.2.2: WME Parameter Element, p.12.*/
 551union aci_aifsn {
 552	u8 char_data;
 553
 554	struct {
 555		u8 aifsn:4;
 556		u8 acm:1;
 557		u8 aci:2;
 558		u8 reserved:1;
 559	} f;			/* Field */
 560};
 561
 562/*mlme related.*/
 563enum wireless_mode {
 564	WIRELESS_MODE_UNKNOWN = 0x00,
 565	WIRELESS_MODE_A = 0x01,
 566	WIRELESS_MODE_B = 0x02,
 567	WIRELESS_MODE_G = 0x04,
 568	WIRELESS_MODE_AUTO = 0x08,
 569	WIRELESS_MODE_N_24G = 0x10,
 570	WIRELESS_MODE_N_5G = 0x20
 571};
 572
 573#define IS_WIRELESS_MODE_A(wirelessmode)	\
 574	(wirelessmode == WIRELESS_MODE_A)
 575#define IS_WIRELESS_MODE_B(wirelessmode)	\
 576	(wirelessmode == WIRELESS_MODE_B)
 577#define IS_WIRELESS_MODE_G(wirelessmode)	\
 578	(wirelessmode == WIRELESS_MODE_G)
 579#define IS_WIRELESS_MODE_N_24G(wirelessmode)	\
 580	(wirelessmode == WIRELESS_MODE_N_24G)
 581#define IS_WIRELESS_MODE_N_5G(wirelessmode)	\
 582	(wirelessmode == WIRELESS_MODE_N_5G)
 583
 584enum ratr_table_mode {
 585	RATR_INX_WIRELESS_NGB = 0,
 586	RATR_INX_WIRELESS_NG = 1,
 587	RATR_INX_WIRELESS_NB = 2,
 588	RATR_INX_WIRELESS_N = 3,
 589	RATR_INX_WIRELESS_GB = 4,
 590	RATR_INX_WIRELESS_G = 5,
 591	RATR_INX_WIRELESS_B = 6,
 592	RATR_INX_WIRELESS_MC = 7,
 593	RATR_INX_WIRELESS_A = 8,
 594};
 595
 596enum rtl_link_state {
 597	MAC80211_NOLINK = 0,
 598	MAC80211_LINKING = 1,
 599	MAC80211_LINKED = 2,
 600	MAC80211_LINKED_SCANNING = 3,
 601};
 602
 603enum act_category {
 604	ACT_CAT_QOS = 1,
 605	ACT_CAT_DLS = 2,
 606	ACT_CAT_BA = 3,
 607	ACT_CAT_HT = 7,
 608	ACT_CAT_WMM = 17,
 609};
 610
 611enum ba_action {
 612	ACT_ADDBAREQ = 0,
 613	ACT_ADDBARSP = 1,
 614	ACT_DELBA = 2,
 615};
 616
 617struct octet_string {
 618	u8 *octet;
 619	u16 length;
 620};
 621
 622struct rtl_hdr_3addr {
 623	__le16 frame_ctl;
 624	__le16 duration_id;
 625	u8 addr1[ETH_ALEN];
 626	u8 addr2[ETH_ALEN];
 627	u8 addr3[ETH_ALEN];
 628	__le16 seq_ctl;
 629	u8 payload[0];
 630} __packed;
 631
 632struct rtl_info_element {
 633	u8 id;
 634	u8 len;
 635	u8 data[0];
 636} __packed;
 637
 638struct rtl_probe_rsp {
 639	struct rtl_hdr_3addr header;
 640	u32 time_stamp[2];
 641	__le16 beacon_interval;
 642	__le16 capability;
 643	/*SSID, supported rates, FH params, DS params,
 644	   CF params, IBSS params, TIM (if beacon), RSN */
 645	struct rtl_info_element info_element[0];
 646} __packed;
 647
 648/*LED related.*/
 649/*ledpin Identify how to implement this SW led.*/
 650struct rtl_led {
 651	void *hw;
 652	enum rtl_led_pin ledpin;
 653	bool ledon;
 654};
 655
 656struct rtl_led_ctl {
 657	bool led_opendrain;
 658	struct rtl_led sw_led0;
 659	struct rtl_led sw_led1;
 660};
 661
 662struct rtl_qos_parameters {
 663	__le16 cw_min;
 664	__le16 cw_max;
 665	u8 aifs;
 666	u8 flag;
 667	__le16 tx_op;
 668} __packed;
 669
 670struct rt_smooth_data {
 671	u32 elements[100];	/*array to store values */
 672	u32 index;		/*index to current array to store */
 673	u32 total_num;		/*num of valid elements */
 674	u32 total_val;		/*sum of valid elements */
 675};
 676
 677struct false_alarm_statistics {
 678	u32 cnt_parity_fail;
 679	u32 cnt_rate_illegal;
 680	u32 cnt_crc8_fail;
 681	u32 cnt_mcs_fail;
 682	u32 cnt_fast_fsync_fail;
 683	u32 cnt_sb_search_fail;
 684	u32 cnt_ofdm_fail;
 685	u32 cnt_cck_fail;
 686	u32 cnt_all;
 687};
 688
 689struct init_gain {
 690	u8 xaagccore1;
 691	u8 xbagccore1;
 692	u8 xcagccore1;
 693	u8 xdagccore1;
 694	u8 cca;
 695
 696};
 697
 698struct wireless_stats {
 699	unsigned long txbytesunicast;
 700	unsigned long txbytesmulticast;
 701	unsigned long txbytesbroadcast;
 702	unsigned long rxbytesunicast;
 703
 704	long rx_snr_db[4];
 705	/*Correct smoothed ss in Dbm, only used
 706	   in driver to report real power now. */
 707	long recv_signal_power;
 708	long signal_quality;
 709	long last_sigstrength_inpercent;
 710
 711	u32 rssi_calculate_cnt;
 712
 713	/*Transformed, in dbm. Beautified signal
 714	   strength for UI, not correct. */
 715	long signal_strength;
 716
 717	u8 rx_rssi_percentage[4];
 718	u8 rx_evm_percentage[2];
 719
 720	struct rt_smooth_data ui_rssi;
 721	struct rt_smooth_data ui_link_quality;
 722};
 723
 724struct rate_adaptive {
 725	u8 rate_adaptive_disabled;
 726	u8 ratr_state;
 727	u16 reserve;
 728
 729	u32 high_rssi_thresh_for_ra;
 730	u32 high2low_rssi_thresh_for_ra;
 731	u8 low2high_rssi_thresh_for_ra40m;
 732	u32 low_rssi_thresh_for_ra40M;
 733	u8 low2high_rssi_thresh_for_ra20m;
 734	u32 low_rssi_thresh_for_ra20M;
 735	u32 upper_rssi_threshold_ratr;
 736	u32 middleupper_rssi_threshold_ratr;
 737	u32 middle_rssi_threshold_ratr;
 738	u32 middlelow_rssi_threshold_ratr;
 739	u32 low_rssi_threshold_ratr;
 740	u32 ultralow_rssi_threshold_ratr;
 741	u32 low_rssi_threshold_ratr_40m;
 742	u32 low_rssi_threshold_ratr_20m;
 743	u8 ping_rssi_enable;
 744	u32 ping_rssi_ratr;
 745	u32 ping_rssi_thresh_for_ra;
 746	u32 last_ratr;
 747	u8 pre_ratr_state;
 748};
 749
 750struct regd_pair_mapping {
 751	u16 reg_dmnenum;
 752	u16 reg_5ghz_ctl;
 753	u16 reg_2ghz_ctl;
 754};
 755
 756struct rtl_regulatory {
 757	char alpha2[2];
 758	u16 country_code;
 759	u16 max_power_level;
 760	u32 tp_scale;
 761	u16 current_rd;
 762	u16 current_rd_ext;
 763	int16_t power_limit;
 764	struct regd_pair_mapping *regpair;
 765};
 766
 767struct rtl_rfkill {
 768	bool rfkill_state;	/*0 is off, 1 is on */
 769};
 770
 771#define IQK_MATRIX_REG_NUM	8
 772#define IQK_MATRIX_SETTINGS_NUM	(1 + 24 + 21)
 773struct iqk_matrix_regs {
 774	bool iqk_done;
 775	long value[1][IQK_MATRIX_REG_NUM];
 776};
 777
 778struct phy_parameters {
 779	u16 length;
 780	u32 *pdata;
 781};
 782
 783enum hw_param_tab_index {
 784	PHY_REG_2T,
 785	PHY_REG_1T,
 786	PHY_REG_PG,
 787	RADIOA_2T,
 788	RADIOB_2T,
 789	RADIOA_1T,
 790	RADIOB_1T,
 791	MAC_REG,
 792	AGCTAB_2T,
 793	AGCTAB_1T,
 794	MAX_TAB
 795};
 796
 797struct rtl_phy {
 798	struct bb_reg_def phyreg_def[4];	/*Radio A/B/C/D */
 799	struct init_gain initgain_backup;
 800	enum io_type current_io_type;
 801
 802	u8 rf_mode;
 803	u8 rf_type;
 804	u8 current_chan_bw;
 805	u8 set_bwmode_inprogress;
 806	u8 sw_chnl_inprogress;
 807	u8 sw_chnl_stage;
 808	u8 sw_chnl_step;
 809	u8 current_channel;
 810	u8 h2c_box_num;
 811	u8 set_io_inprogress;
 812	u8 lck_inprogress;
 813
 814	/* record for power tracking */
 815	s32 reg_e94;
 816	s32 reg_e9c;
 817	s32 reg_ea4;
 818	s32 reg_eac;
 819	s32 reg_eb4;
 820	s32 reg_ebc;
 821	s32 reg_ec4;
 822	s32 reg_ecc;
 823	u8 rfpienable;
 824	u8 reserve_0;
 825	u16 reserve_1;
 826	u32 reg_c04, reg_c08, reg_874;
 827	u32 adda_backup[16];
 828	u32 iqk_mac_backup[IQK_MAC_REG_NUM];
 829	u32 iqk_bb_backup[10];
 830
 831	/* Dual mac */
 832	bool need_iqk;
 833	struct iqk_matrix_regs iqk_matrix_regsetting[IQK_MATRIX_SETTINGS_NUM];
 834
 835	bool rfpi_enable;
 836
 837	u8 pwrgroup_cnt;
 838	u8 cck_high_power;
 839	/* MAX_PG_GROUP groups of pwr diff by rates */
 840	u32 mcs_txpwrlevel_origoffset[MAX_PG_GROUP][16];
 841	u8 default_initialgain[4];
 842
 843	/* the current Tx power level */
 844	u8 cur_cck_txpwridx;
 845	u8 cur_ofdm24g_txpwridx;
 846
 847	u32 rfreg_chnlval[2];
 848	bool apk_done;
 849	u32 reg_rf3c[2];	/* pathA / pathB  */
 850
 851	/* bfsync */
 852	u8 framesync;
 853	u32 framesync_c34;
 854
 855	u8 num_total_rfpath;
 856	struct phy_parameters hwparam_tables[MAX_TAB];
 857	u16 rf_pathmap;
 858};
 859
 860#define MAX_TID_COUNT				9
 861#define RTL_AGG_STOP				0
 862#define RTL_AGG_PROGRESS			1
 863#define RTL_AGG_START				2
 864#define RTL_AGG_OPERATIONAL			3
 865#define RTL_AGG_OFF				0
 866#define RTL_AGG_ON				1
 867#define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA		2
 868#define RTL_AGG_EMPTYING_HW_QUEUE_DELBA		3
 869
 870struct rtl_ht_agg {
 871	u16 txq_id;
 872	u16 wait_for_ba;
 873	u16 start_idx;
 874	u64 bitmap;
 875	u32 rate_n_flags;
 876	u8 agg_state;
 877};
 878
 879struct rtl_tid_data {
 880	u16 seq_number;
 881	struct rtl_ht_agg agg;
 882};
 883
 884struct rtl_sta_info {
 885	u8 ratr_index;
 886	u8 wireless_mode;
 887	u8 mimo_ps;
 888	struct rtl_tid_data tids[MAX_TID_COUNT];
 889} __packed;
 890
 891struct rtl_priv;
 892struct rtl_io {
 893	struct device *dev;
 894	struct mutex bb_mutex;
 895
 896	/*PCI MEM map */
 897	unsigned long pci_mem_end;	/*shared mem end        */
 898	unsigned long pci_mem_start;	/*shared mem start */
 899
 900	/*PCI IO map */
 901	unsigned long pci_base_addr;	/*device I/O address */
 902
 903	void (*write8_async) (struct rtl_priv *rtlpriv, u32 addr, u8 val);
 904	void (*write16_async) (struct rtl_priv *rtlpriv, u32 addr, u16 val);
 905	void (*write32_async) (struct rtl_priv *rtlpriv, u32 addr, u32 val);
 906	int (*writeN_async) (struct rtl_priv *rtlpriv, u32 addr, u16 len,
 907			     u8 *pdata);
 908
 909	u8(*read8_sync) (struct rtl_priv *rtlpriv, u32 addr);
 910	u16(*read16_sync) (struct rtl_priv *rtlpriv, u32 addr);
 911	u32(*read32_sync) (struct rtl_priv *rtlpriv, u32 addr);
 912	int (*readN_sync) (struct rtl_priv *rtlpriv, u32 addr, u16 len,
 913			    u8 *pdata);
 914
 915};
 916
 917struct rtl_mac {
 918	u8 mac_addr[ETH_ALEN];
 919	u8 mac80211_registered;
 920	u8 beacon_enabled;
 921
 922	u32 tx_ss_num;
 923	u32 rx_ss_num;
 924
 925	struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
 926	struct ieee80211_hw *hw;
 927	struct ieee80211_vif *vif;
 928	enum nl80211_iftype opmode;
 929
 930	/*Probe Beacon management */
 931	struct rtl_tid_data tids[MAX_TID_COUNT];
 932	enum rtl_link_state link_state;
 933
 934	int n_channels;
 935	int n_bitrates;
 936
 937	bool offchan_delay;
 938
 939	/*filters */
 940	u32 rx_conf;
 941	u16 rx_mgt_filter;
 942	u16 rx_ctrl_filter;
 943	u16 rx_data_filter;
 944
 945	bool act_scanning;
 946	u8 cnt_after_linked;
 947
 948	/* early mode */
 949	/* skb wait queue */
 950	struct sk_buff_head skb_waitq[MAX_TID_COUNT];
 951	u8 earlymode_threshold;
 952
 953	/*RDG*/
 954	bool rdg_en;
 955
 956	/*AP*/
 957	u8 bssid[6];
 958	u32 vendor;
 959	u8 mcs[16];	/* 16 bytes mcs for HT rates. */
 960	u32 basic_rates; /* b/g rates */
 961	u8 ht_enable;
 962	u8 sgi_40;
 963	u8 sgi_20;
 964	u8 bw_40;
 965	u8 mode;		/* wireless mode */
 966	u8 slot_time;
 967	u8 short_preamble;
 968	u8 use_cts_protect;
 969	u8 cur_40_prime_sc;
 970	u8 cur_40_prime_sc_bk;
 971	u64 tsf;
 972	u8 retry_short;
 973	u8 retry_long;
 974	u16 assoc_id;
 975
 976	/*IBSS*/
 977	int beacon_interval;
 978
 979	/*AMPDU*/
 980	u8 min_space_cfg;	/*For Min spacing configurations */
 981	u8 max_mss_density;
 982	u8 current_ampdu_factor;
 983	u8 current_ampdu_density;
 984
 985	/*QOS & EDCA */
 986	struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE];
 987	struct rtl_qos_parameters ac[AC_MAX];
 988};
 989
 990struct rtl_hal {
 991	struct ieee80211_hw *hw;
 992
 993	enum intf_type interface;
 994	u16 hw_type;		/*92c or 92d or 92s and so on */
 995	u8 ic_class;
 996	u8 oem_id;
 997	u32 version;		/*version of chip */
 998	u8 state;		/*stop 0, start 1 */
 999
1000	/*firmware */
1001	u32 fwsize;
1002	u8 *pfirmware;
1003	u16 fw_version;
1004	u16 fw_subversion;
1005	bool h2c_setinprogress;
1006	u8 last_hmeboxnum;
1007	bool fw_ready;
1008	/*Reserve page start offset except beacon in TxQ. */
1009	u8 fw_rsvdpage_startoffset;
1010	u8 h2c_txcmd_seq;
1011
1012	/* FW Cmd IO related */
1013	u16 fwcmd_iomap;
1014	u32 fwcmd_ioparam;
1015	bool set_fwcmd_inprogress;
1016	u8 current_fwcmd_io;
1017
1018	/**/
1019	bool driver_going2unload;
1020
1021	/*AMPDU init min space*/
1022	u8 minspace_cfg;	/*For Min spacing configurations */
1023
1024	/* Dual mac */
1025	enum macphy_mode macphymode;
1026	enum band_type current_bandtype;	/* 0:2.4G, 1:5G */
1027	enum band_type current_bandtypebackup;
1028	enum band_type bandset;
1029	/* dual MAC 0--Mac0 1--Mac1 */
1030	u32 interfaceindex;
1031	/* just for DualMac S3S4 */
1032	u8 macphyctl_reg;
1033	bool earlymode_enable;
1034	/* Dual mac*/
1035	bool during_mac0init_radiob;
1036	bool during_mac1init_radioa;
1037	bool reloadtxpowerindex;
1038	/* True if IMR or IQK  have done
1039	for 2.4G in scan progress */
1040	bool load_imrandiqk_setting_for2g;
1041
1042	bool disable_amsdu_8k;
1043};
1044
1045struct rtl_security {
1046	/*default 0 */
1047	bool use_sw_sec;
1048
1049	bool being_setkey;
1050	bool use_defaultkey;
1051	/*Encryption Algorithm for Unicast Packet */
1052	enum rt_enc_alg pairwise_enc_algorithm;
1053	/*Encryption Algorithm for Brocast/Multicast */
1054	enum rt_enc_alg group_enc_algorithm;
1055	/*Cam Entry Bitmap */
1056	u32 hwsec_cam_bitmap;
1057	u8 hwsec_cam_sta_addr[TOTAL_CAM_ENTRY][ETH_ALEN];
1058	/*local Key buffer, indx 0 is for
1059	   pairwise key 1-4 is for agoup key. */
1060	u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN];
1061	u8 key_len[KEY_BUF_SIZE];
1062
1063	/*The pointer of Pairwise Key,
1064	   it always points to KeyBuf[4] */
1065	u8 *pairwise_key;
1066};
1067
1068struct rtl_dm {
1069	/*PHY status for Dynamic Management */
1070	long entry_min_undecoratedsmoothed_pwdb;
1071	long undecorated_smoothed_pwdb;	/*out dm */
1072	long entry_max_undecoratedsmoothed_pwdb;
1073	bool dm_initialgain_enable;
1074	bool dynamic_txpower_enable;
1075	bool current_turbo_edca;
1076	bool is_any_nonbepkts;	/*out dm */
1077	bool is_cur_rdlstate;
1078	bool txpower_trackinginit;
1079	bool disable_framebursting;
1080	bool cck_inch14;
1081	bool txpower_tracking;
1082	bool useramask;
1083	bool rfpath_rxenable[4];
1084	bool inform_fw_driverctrldm;
1085	bool current_mrc_switch;
1086	u8 txpowercount;
1087
1088	u8 thermalvalue_rxgain;
1089	u8 thermalvalue_iqk;
1090	u8 thermalvalue_lck;
1091	u8 thermalvalue;
1092	u8 last_dtp_lvl;
1093	u8 thermalvalue_avg[AVG_THERMAL_NUM];
1094	u8 thermalvalue_avg_index;
1095	bool done_txpower;
1096	u8 dynamic_txhighpower_lvl;	/*Tx high power level */
1097	u8 dm_flag;		/*Indicate each dynamic mechanism's status. */
1098	u8 dm_type;
1099	u8 txpower_track_control;
1100	bool interrupt_migration;
1101	bool disable_tx_int;
1102	char ofdm_index[2];
1103	char cck_index;
1104};
1105
1106#define	EFUSE_MAX_LOGICAL_SIZE			256
1107
1108struct rtl_efuse {
1109	bool autoLoad_ok;
1110	bool bootfromefuse;
1111	u16 max_physical_size;
1112
1113	u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE];
1114	u16 efuse_usedbytes;
1115	u8 efuse_usedpercentage;
1116#ifdef EFUSE_REPG_WORKAROUND
1117	bool efuse_re_pg_sec1flag;
1118	u8 efuse_re_pg_data[8];
1119#endif
1120
1121	u8 autoload_failflag;
1122	u8 autoload_status;
1123
1124	short epromtype;
1125	u16 eeprom_vid;
1126	u16 eeprom_did;
1127	u16 eeprom_svid;
1128	u16 eeprom_smid;
1129	u8 eeprom_oemid;
1130	u16 eeprom_channelplan;
1131	u8 eeprom_version;
1132	u8 board_type;
1133	u8 external_pa;
1134
1135	u8 dev_addr[6];
1136
1137	bool txpwr_fromeprom;
1138	u8 eeprom_crystalcap;
1139	u8 eeprom_tssi[2];
1140	u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */
1141	u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX];
1142	u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX];
1143	u8 eeprom_chnlarea_txpwr_cck[2][CHANNEL_GROUP_MAX_2G];
1144	u8 eeprom_chnlarea_txpwr_ht40_1s[2][CHANNEL_GROUP_MAX];
1145	u8 eeprom_chnlarea_txpwr_ht40_2sdiif[2][CHANNEL_GROUP_MAX];
1146	u8 txpwrlevel_cck[2][CHANNEL_MAX_NUMBER_2G];
1147	u8 txpwrlevel_ht40_1s[2][CHANNEL_MAX_NUMBER];	/*For HT 40MHZ pwr */
1148	u8 txpwrlevel_ht40_2s[2][CHANNEL_MAX_NUMBER];	/*For HT 40MHZ pwr */
1149
1150	u8 internal_pa_5g[2];	/* pathA / pathB */
1151	u8 eeprom_c9;
1152	u8 eeprom_cc;
1153
1154	/*For power group */
1155	u8 eeprom_pwrgroup[2][3];
1156	u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER];
1157	u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER];
1158
1159	char txpwr_ht20diff[2][CHANNEL_MAX_NUMBER]; /*HT 20<->40 Pwr diff */
1160	/*For HT<->legacy pwr diff*/
1161	u8 txpwr_legacyhtdiff[2][CHANNEL_MAX_NUMBER];
1162	u8 txpwr_safetyflag;			/* Band edge enable flag */
1163	u16 eeprom_txpowerdiff;
1164	u8 legacy_httxpowerdiff;	/* Legacy to HT rate power diff */
1165	u8 antenna_txpwdiff[3];
1166
1167	u8 eeprom_regulatory;
1168	u8 eeprom_thermalmeter;
1169	u8 thermalmeter[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */
1170	u16 tssi_13dbm;
1171	u8 crystalcap;		/* CrystalCap. */
1172	u8 delta_iqk;
1173	u8 delta_lck;
1174
1175	u8 legacy_ht_txpowerdiff;	/*Legacy to HT rate power diff */
1176	bool apk_thermalmeterignore;
1177
1178	bool b1x1_recvcombine;
1179	bool b1ss_support;
1180
1181	/*channel plan */
1182	u8 channel_plan;
1183};
1184
1185struct rtl_ps_ctl {
1186	bool pwrdomain_protect;
1187	bool in_powersavemode;
1188	bool rfchange_inprogress;
1189	bool swrf_processing;
1190	bool hwradiooff;
1191
1192	/*
1193	 * just for PCIE ASPM
1194	 * If it supports ASPM, Offset[560h] = 0x40,
1195	 * otherwise Offset[560h] = 0x00.
1196	 * */
1197	bool support_aspm;
1198
1199	bool support_backdoor;
1200
1201	/*for LPS */
1202	enum rt_psmode dot11_psmode;	/*Power save mode configured. */
1203	bool swctrl_lps;
1204	bool leisure_ps;
1205	bool fwctrl_lps;
1206	u8 fwctrl_psmode;
1207	/*For Fw control LPS mode */
1208	u8 reg_fwctrl_lps;
1209	/*Record Fw PS mode status. */
1210	bool fw_current_inpsmode;
1211	u8 reg_max_lps_awakeintvl;
1212	bool report_linked;
1213
1214	/*for IPS */
1215	bool inactiveps;
1216
1217	u32 rfoff_reason;
1218
1219	/*RF OFF Level */
1220	u32 cur_ps_level;
1221	u32 reg_rfps_level;
1222
1223	/*just for PCIE ASPM */
1224	u8 const_amdpci_aspm;
1225	bool pwrdown_mode;
1226
1227	enum rf_pwrstate inactive_pwrstate;
1228	enum rf_pwrstate rfpwr_state;	/*cur power state */
1229
1230	/* for SW LPS*/
1231	bool sw_ps_enabled;
1232	bool state;
1233	bool state_inap;
1234	bool multi_buffered;
1235	u16 nullfunc_seq;
1236	unsigned int dtim_counter;
1237	unsigned int sleep_ms;
1238	unsigned long last_sleep_jiffies;
1239	unsigned long last_awake_jiffies;
1240	unsigned long last_delaylps_stamp_jiffies;
1241	unsigned long last_dtim;
1242	unsigned long last_beacon;
1243	unsigned long last_action;
1244	unsigned long last_slept;
1245};
1246
1247struct rtl_stats {
1248	u32 mac_time[2];
1249	s8 rssi;
1250	u8 signal;
1251	u8 noise;
1252	u16 rate;		/*in 100 kbps */
1253	u8 received_channel;
1254	u8 control;
1255	u8 mask;
1256	u8 freq;
1257	u16 len;
1258	u64 tsf;
1259	u32 beacon_time;
1260	u8 nic_type;
1261	u16 length;
1262	u8 signalquality;	/*in 0-100 index. */
1263	/*
1264	 * Real power in dBm for this packet,
1265	 * no beautification and aggregation.
1266	 * */
1267	s32 recvsignalpower;
1268	s8 rxpower;		/*in dBm Translate from PWdB */
1269	u8 signalstrength;	/*in 0-100 index. */
1270	u16 hwerror:1;
1271	u16 crc:1;
1272	u16 icv:1;
1273	u16 shortpreamble:1;
1274	u16 antenna:1;
1275	u16 decrypted:1;
1276	u16 wakeup:1;
1277	u32 timestamp_low;
1278	u32 timestamp_high;
1279
1280	u8 rx_drvinfo_size;
1281	u8 rx_bufshift;
1282	bool isampdu;
1283	bool isfirst_ampdu;
1284	bool rx_is40Mhzpacket;
1285	u32 rx_pwdb_all;
1286	u8 rx_mimo_signalstrength[4];	/*in 0~100 index */
1287	s8 rx_mimo_signalquality[2];
1288	bool packet_matchbssid;
1289	bool is_cck;
 
1290	bool packet_toself;
1291	bool packet_beacon;	/*for rssi */
1292	char cck_adc_pwdb[4];	/*for rx path selection */
1293};
1294
1295struct rt_link_detect {
1296	u32 num_tx_in4period[4];
1297	u32 num_rx_in4period[4];
1298
1299	u32 num_tx_inperiod;
1300	u32 num_rx_inperiod;
1301
1302	bool busytraffic;
1303	bool higher_busytraffic;
1304	bool higher_busyrxtraffic;
1305
1306	u32 tidtx_in4period[MAX_TID_COUNT][4];
1307	u32 tidtx_inperiod[MAX_TID_COUNT];
1308	bool higher_busytxtraffic[MAX_TID_COUNT];
1309};
1310
1311struct rtl_tcb_desc {
1312	u8 packet_bw:1;
1313	u8 multicast:1;
1314	u8 broadcast:1;
1315
1316	u8 rts_stbc:1;
1317	u8 rts_enable:1;
1318	u8 cts_enable:1;
1319	u8 rts_use_shortpreamble:1;
1320	u8 rts_use_shortgi:1;
1321	u8 rts_sc:1;
1322	u8 rts_bw:1;
1323	u8 rts_rate;
1324
1325	u8 use_shortgi:1;
1326	u8 use_shortpreamble:1;
1327	u8 use_driver_rate:1;
1328	u8 disable_ratefallback:1;
1329
1330	u8 ratr_index;
1331	u8 mac_id;
1332	u8 hw_rate;
1333
1334	u8 last_inipkt:1;
1335	u8 cmd_or_init:1;
1336	u8 queue_index;
1337
1338	/* early mode */
1339	u8 empkt_num;
1340	/* The max value by HW */
1341	u32 empkt_len[5];
1342};
1343
1344struct rtl_hal_ops {
1345	int (*init_sw_vars) (struct ieee80211_hw *hw);
1346	void (*deinit_sw_vars) (struct ieee80211_hw *hw);
1347	void (*read_chip_version)(struct ieee80211_hw *hw);
1348	void (*read_eeprom_info) (struct ieee80211_hw *hw);
1349	void (*interrupt_recognized) (struct ieee80211_hw *hw,
1350				      u32 *p_inta, u32 *p_intb);
1351	int (*hw_init) (struct ieee80211_hw *hw);
1352	void (*hw_disable) (struct ieee80211_hw *hw);
1353	void (*hw_suspend) (struct ieee80211_hw *hw);
1354	void (*hw_resume) (struct ieee80211_hw *hw);
1355	void (*enable_interrupt) (struct ieee80211_hw *hw);
1356	void (*disable_interrupt) (struct ieee80211_hw *hw);
1357	int (*set_network_type) (struct ieee80211_hw *hw,
1358				 enum nl80211_iftype type);
1359	void (*set_chk_bssid)(struct ieee80211_hw *hw,
1360				bool check_bssid);
1361	void (*set_bw_mode) (struct ieee80211_hw *hw,
1362			     enum nl80211_channel_type ch_type);
1363	 u8(*switch_channel) (struct ieee80211_hw *hw);
1364	void (*set_qos) (struct ieee80211_hw *hw, int aci);
1365	void (*set_bcn_reg) (struct ieee80211_hw *hw);
1366	void (*set_bcn_intv) (struct ieee80211_hw *hw);
1367	void (*update_interrupt_mask) (struct ieee80211_hw *hw,
1368				       u32 add_msr, u32 rm_msr);
1369	void (*get_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
1370	void (*set_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
1371	void (*update_rate_tbl) (struct ieee80211_hw *hw,
1372			      struct ieee80211_sta *sta, u8 rssi_level);
1373	void (*update_rate_mask) (struct ieee80211_hw *hw, u8 rssi_level);
1374	void (*fill_tx_desc) (struct ieee80211_hw *hw,
1375			      struct ieee80211_hdr *hdr, u8 *pdesc_tx,
1376			      struct ieee80211_tx_info *info,
1377			      struct sk_buff *skb, u8 hw_queue,
1378			      struct rtl_tcb_desc *ptcb_desc);
1379	void (*fill_fake_txdesc) (struct ieee80211_hw *hw, u8 *pDesc,
1380				  u32 buffer_len, bool bIsPsPoll);
1381	void (*fill_tx_cmddesc) (struct ieee80211_hw *hw, u8 *pdesc,
1382				 bool firstseg, bool lastseg,
1383				 struct sk_buff *skb);
1384	bool (*cmd_send_packet)(struct ieee80211_hw *hw, struct sk_buff *skb);
1385	bool (*query_rx_desc) (struct ieee80211_hw *hw,
1386			       struct rtl_stats *stats,
1387			       struct ieee80211_rx_status *rx_status,
1388			       u8 *pdesc, struct sk_buff *skb);
1389	void (*set_channel_access) (struct ieee80211_hw *hw);
1390	bool (*radio_onoff_checking) (struct ieee80211_hw *hw, u8 *valid);
1391	void (*dm_watchdog) (struct ieee80211_hw *hw);
1392	void (*scan_operation_backup) (struct ieee80211_hw *hw, u8 operation);
1393	bool (*set_rf_power_state) (struct ieee80211_hw *hw,
1394				    enum rf_pwrstate rfpwr_state);
1395	void (*led_control) (struct ieee80211_hw *hw,
1396			     enum led_ctl_mode ledaction);
1397	void (*set_desc) (u8 *pdesc, bool istx, u8 desc_name, u8 *val);
1398	u32 (*get_desc) (u8 *pdesc, bool istx, u8 desc_name);
1399	void (*tx_polling) (struct ieee80211_hw *hw, u8 hw_queue);
1400	void (*enable_hw_sec) (struct ieee80211_hw *hw);
1401	void (*set_key) (struct ieee80211_hw *hw, u32 key_index,
1402			 u8 *macaddr, bool is_group, u8 enc_algo,
1403			 bool is_wepkey, bool clear_all);
1404	void (*init_sw_leds) (struct ieee80211_hw *hw);
1405	void (*deinit_sw_leds) (struct ieee80211_hw *hw);
1406	u32 (*get_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask);
1407	void (*set_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
1408			   u32 data);
1409	u32 (*get_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
1410			  u32 regaddr, u32 bitmask);
1411	void (*set_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
1412			   u32 regaddr, u32 bitmask, u32 data);
1413	void (*linked_set_reg) (struct ieee80211_hw *hw);
1414	bool (*phy_rf6052_config) (struct ieee80211_hw *hw);
1415	void (*phy_rf6052_set_cck_txpower) (struct ieee80211_hw *hw,
1416					    u8 *powerlevel);
1417	void (*phy_rf6052_set_ofdm_txpower) (struct ieee80211_hw *hw,
1418					     u8 *ppowerlevel, u8 channel);
1419	bool (*config_bb_with_headerfile) (struct ieee80211_hw *hw,
1420					   u8 configtype);
1421	bool (*config_bb_with_pgheaderfile) (struct ieee80211_hw *hw,
1422					     u8 configtype);
1423	void (*phy_lc_calibrate) (struct ieee80211_hw *hw, bool is2t);
1424	void (*phy_set_bw_mode_callback) (struct ieee80211_hw *hw);
1425	void (*dm_dynamic_txpower) (struct ieee80211_hw *hw);
1426};
1427
1428struct rtl_intf_ops {
1429	/*com */
1430	void (*read_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf);
1431	int (*adapter_start) (struct ieee80211_hw *hw);
1432	void (*adapter_stop) (struct ieee80211_hw *hw);
1433
1434	int (*adapter_tx) (struct ieee80211_hw *hw, struct sk_buff *skb,
1435			struct rtl_tcb_desc *ptcb_desc);
1436	void (*flush)(struct ieee80211_hw *hw, bool drop);
1437	int (*reset_trx_ring) (struct ieee80211_hw *hw);
1438	bool (*waitq_insert) (struct ieee80211_hw *hw, struct sk_buff *skb);
1439
1440	/*pci */
1441	void (*disable_aspm) (struct ieee80211_hw *hw);
1442	void (*enable_aspm) (struct ieee80211_hw *hw);
1443
1444	/*usb */
1445};
1446
1447struct rtl_mod_params {
1448	/* default: 0 = using hardware encryption */
1449	int sw_crypto;
 
 
 
1450
1451	/* default: 1 = using no linked power save */
1452	bool inactiveps;
1453
1454	/* default: 1 = using linked sw power save */
1455	bool swctrl_lps;
1456
1457	/* default: 1 = using linked fw power save */
1458	bool fwctrl_lps;
1459};
1460
1461struct rtl_hal_usbint_cfg {
1462	/* data - rx */
1463	u32 in_ep_num;
1464	u32 rx_urb_num;
1465	u32 rx_max_size;
1466
1467	/* op - rx */
1468	void (*usb_rx_hdl)(struct ieee80211_hw *, struct sk_buff *);
1469	void (*usb_rx_segregate_hdl)(struct ieee80211_hw *, struct sk_buff *,
1470				     struct sk_buff_head *);
1471
1472	/* tx */
1473	void (*usb_tx_cleanup)(struct ieee80211_hw *, struct sk_buff *);
1474	int (*usb_tx_post_hdl)(struct ieee80211_hw *, struct urb *,
1475			       struct sk_buff *);
1476	struct sk_buff *(*usb_tx_aggregate_hdl)(struct ieee80211_hw *,
1477						struct sk_buff_head *);
1478
1479	/* endpoint mapping */
1480	int (*usb_endpoint_mapping)(struct ieee80211_hw *hw);
1481	u16 (*usb_mq_to_hwq)(__le16 fc, u16 mac80211_queue_index);
1482};
1483
1484struct rtl_hal_cfg {
1485	u8 bar_id;
1486	bool write_readback;
1487	char *name;
1488	char *fw_name;
1489	struct rtl_hal_ops *ops;
1490	struct rtl_mod_params *mod_params;
1491	struct rtl_hal_usbint_cfg *usb_interface_cfg;
1492
1493	/*this map used for some registers or vars
1494	   defined int HAL but used in MAIN */
1495	u32 maps[RTL_VAR_MAP_MAX];
1496
1497};
1498
1499struct rtl_locks {
1500	/* mutex */
1501	struct mutex conf_mutex;
 
1502
1503	/*spin lock */
1504	spinlock_t ips_lock;
1505	spinlock_t irq_th_lock;
1506	spinlock_t h2c_lock;
1507	spinlock_t rf_ps_lock;
1508	spinlock_t rf_lock;
1509	spinlock_t lps_lock;
1510	spinlock_t waitq_lock;
 
1511
1512	/*Dual mac*/
1513	spinlock_t cck_and_rw_pagea_lock;
1514};
1515
1516struct rtl_works {
1517	struct ieee80211_hw *hw;
1518
1519	/*timer */
1520	struct timer_list watchdog_timer;
1521
1522	/*task */
1523	struct tasklet_struct irq_tasklet;
1524	struct tasklet_struct irq_prepare_bcn_tasklet;
1525
1526	/*work queue */
1527	struct workqueue_struct *rtl_wq;
1528	struct delayed_work watchdog_wq;
1529	struct delayed_work ips_nic_off_wq;
1530
1531	/* For SW LPS */
1532	struct delayed_work ps_work;
1533	struct delayed_work ps_rfon_wq;
1534	struct tasklet_struct ips_leave_tasklet;
 
1535};
1536
1537struct rtl_debug {
1538	u32 dbgp_type[DBGP_TYPE_MAX];
1539	u32 global_debuglevel;
1540	u64 global_debugcomponents;
1541
1542	/* add for proc debug */
1543	struct proc_dir_entry *proc_dir;
1544	char proc_name[20];
1545};
1546
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1547struct rtl_priv {
 
1548	struct rtl_locks locks;
1549	struct rtl_works works;
1550	struct rtl_mac mac80211;
1551	struct rtl_hal rtlhal;
1552	struct rtl_regulatory regd;
1553	struct rtl_rfkill rfkill;
1554	struct rtl_io io;
1555	struct rtl_phy phy;
1556	struct rtl_dm dm;
1557	struct rtl_security sec;
1558	struct rtl_efuse efuse;
1559
1560	struct rtl_ps_ctl psc;
1561	struct rate_adaptive ra;
1562	struct wireless_stats stats;
1563	struct rt_link_detect link_info;
1564	struct false_alarm_statistics falsealm_cnt;
1565
1566	struct rtl_rate_priv *rate_priv;
1567
1568	struct rtl_debug dbg;
 
1569
1570	/*
1571	 *hal_cfg : for diff cards
1572	 *intf_ops : for diff interrface usb/pcie
1573	 */
1574	struct rtl_hal_cfg *cfg;
1575	struct rtl_intf_ops *intf_ops;
1576
1577	/*this var will be set by set_bit,
1578	   and was used to indicate status of
1579	   interface or hardware */
1580	unsigned long status;
1581
 
 
 
 
 
 
 
 
1582	/*This must be the last item so
1583	   that it points to the data allocated
1584	   beyond  this structure like:
1585	   rtl_pci_priv or rtl_usb_priv */
1586	u8 priv[0];
1587};
1588
1589#define rtl_priv(hw)		(((struct rtl_priv *)(hw)->priv))
1590#define rtl_mac(rtlpriv)	(&((rtlpriv)->mac80211))
1591#define rtl_hal(rtlpriv)	(&((rtlpriv)->rtlhal))
1592#define rtl_efuse(rtlpriv)	(&((rtlpriv)->efuse))
1593#define rtl_psc(rtlpriv)	(&((rtlpriv)->psc))
1594
1595
1596/***************************************
1597    Bluetooth Co-existence Related
1598****************************************/
1599
1600enum bt_ant_num {
1601	ANT_X2 = 0,
1602	ANT_X1 = 1,
1603};
1604
1605enum bt_co_type {
1606	BT_2WIRE = 0,
1607	BT_ISSC_3WIRE = 1,
1608	BT_ACCEL = 2,
1609	BT_CSR_BC4 = 3,
1610	BT_CSR_BC8 = 4,
1611	BT_RTL8756 = 5,
1612};
1613
1614enum bt_cur_state {
1615	BT_OFF = 0,
1616	BT_ON = 1,
1617};
1618
1619enum bt_service_type {
1620	BT_SCO = 0,
1621	BT_A2DP = 1,
1622	BT_HID = 2,
1623	BT_HID_IDLE = 3,
1624	BT_SCAN = 4,
1625	BT_IDLE = 5,
1626	BT_OTHER_ACTION = 6,
1627	BT_BUSY = 7,
1628	BT_OTHERBUSY = 8,
1629	BT_PAN = 9,
1630};
1631
1632enum bt_radio_shared {
1633	BT_RADIO_SHARED = 0,
1634	BT_RADIO_INDIVIDUAL = 1,
1635};
1636
1637struct bt_coexist_info {
1638
1639	/* EEPROM BT info. */
1640	u8 eeprom_bt_coexist;
1641	u8 eeprom_bt_type;
1642	u8 eeprom_bt_ant_num;
1643	u8 eeprom_bt_ant_isolation;
1644	u8 eeprom_bt_radio_shared;
1645
1646	u8 bt_coexistence;
1647	u8 bt_ant_num;
1648	u8 bt_coexist_type;
1649	u8 bt_state;
1650	u8 bt_cur_state;	/* 0:on, 1:off */
1651	u8 bt_ant_isolation;	/* 0:good, 1:bad */
1652	u8 bt_pape_ctrl;	/* 0:SW, 1:SW/HW dynamic */
1653	u8 bt_service;
1654	u8 bt_radio_shared_type;
1655	u8 bt_rfreg_origin_1e;
1656	u8 bt_rfreg_origin_1f;
1657	u8 bt_rssi_state;
1658	u32 ratio_tx;
1659	u32 ratio_pri;
1660	u32 bt_edca_ul;
1661	u32 bt_edca_dl;
1662
1663	bool init_set;
1664	bool bt_busy_traffic;
1665	bool bt_traffic_mode_set;
1666	bool bt_non_traffic_mode_set;
1667
1668	bool fw_coexist_all_off;
1669	bool sw_coexist_all_off;
1670	u32 current_state;
1671	u32 previous_state;
1672	u8 bt_pre_rssi_state;
1673
1674	u8 reg_bt_iso;
1675	u8 reg_bt_sco;
1676
1677};
1678
1679
1680/****************************************
1681	mem access macro define start
1682	Call endian free function when
1683	1. Read/write packet content.
1684	2. Before write integer to IO.
1685	3. After read integer from IO.
1686****************************************/
1687/* Convert little data endian to host ordering */
1688#define EF1BYTE(_val)		\
1689	((u8)(_val))
1690#define EF2BYTE(_val)		\
1691	(le16_to_cpu(_val))
1692#define EF4BYTE(_val)		\
1693	(le32_to_cpu(_val))
1694
1695/* Read data from memory */
1696#define READEF1BYTE(_ptr)	\
1697	EF1BYTE(*((u8 *)(_ptr)))
1698/* Read le16 data from memory and convert to host ordering */
1699#define READEF2BYTE(_ptr)	\
1700	EF2BYTE(*((u16 *)(_ptr)))
1701#define READEF4BYTE(_ptr)	\
1702	EF4BYTE(*((u32 *)(_ptr)))
1703
1704/* Write data to memory */
1705#define WRITEEF1BYTE(_ptr, _val)	\
1706	(*((u8 *)(_ptr))) = EF1BYTE(_val)
1707/* Write le16 data to memory in host ordering */
1708#define WRITEEF2BYTE(_ptr, _val)	\
1709	(*((u16 *)(_ptr))) = EF2BYTE(_val)
1710#define WRITEEF4BYTE(_ptr, _val)	\
1711	(*((u16 *)(_ptr))) = EF2BYTE(_val)
1712
1713/* Create a bit mask
1714 * Examples:
1715 * BIT_LEN_MASK_32(0) => 0x00000000
1716 * BIT_LEN_MASK_32(1) => 0x00000001
1717 * BIT_LEN_MASK_32(2) => 0x00000003
1718 * BIT_LEN_MASK_32(32) => 0xFFFFFFFF
1719 */
1720#define BIT_LEN_MASK_32(__bitlen)	 \
1721	(0xFFFFFFFF >> (32 - (__bitlen)))
1722#define BIT_LEN_MASK_16(__bitlen)	 \
1723	(0xFFFF >> (16 - (__bitlen)))
1724#define BIT_LEN_MASK_8(__bitlen) \
1725	(0xFF >> (8 - (__bitlen)))
1726
1727/* Create an offset bit mask
1728 * Examples:
1729 * BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
1730 * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
1731 */
1732#define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \
1733	(BIT_LEN_MASK_32(__bitlen) << (__bitoffset))
1734#define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \
1735	(BIT_LEN_MASK_16(__bitlen) << (__bitoffset))
1736#define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \
1737	(BIT_LEN_MASK_8(__bitlen) << (__bitoffset))
1738
1739/*Description:
1740 * Return 4-byte value in host byte ordering from
1741 * 4-byte pointer in little-endian system.
1742 */
1743#define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \
1744	(EF4BYTE(*((u32 *)(__pstart))))
1745#define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \
1746	(EF2BYTE(*((u16 *)(__pstart))))
1747#define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \
1748	(EF1BYTE(*((u8 *)(__pstart))))
1749
1750/*Description:
1751Translate subfield (continuous bits in little-endian) of 4-byte
1752value to host byte ordering.*/
1753#define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
1754	( \
1755		(LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset))  & \
1756		BIT_LEN_MASK_32(__bitlen) \
1757	)
1758#define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
1759	( \
1760		(LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset)) & \
1761		BIT_LEN_MASK_16(__bitlen) \
1762	)
1763#define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
1764	( \
1765		(LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset)) & \
1766		BIT_LEN_MASK_8(__bitlen) \
1767	)
1768
1769/* Description:
1770 * Mask subfield (continuous bits in little-endian) of 4-byte value
1771 * and return the result in 4-byte value in host byte ordering.
1772 */
1773#define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
1774	( \
1775		LE_P4BYTE_TO_HOST_4BYTE(__pstart)  & \
1776		(~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \
1777	)
1778#define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
1779	( \
1780		LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \
1781		(~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \
1782	)
1783#define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
1784	( \
1785		LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \
1786		(~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \
1787	)
1788
1789/* Description:
1790 * Set subfield of little-endian 4-byte value to specified value.
1791 */
1792#define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \
1793	*((u32 *)(__pstart)) = EF4BYTE \
1794	( \
1795		LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \
1796		((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \
1797	);
1798#define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \
1799	*((u16 *)(__pstart)) = EF2BYTE \
1800	( \
1801		LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \
1802		((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \
1803	);
1804#define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \
1805	*((u8 *)(__pstart)) = EF1BYTE \
1806	( \
1807		LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \
1808		((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \
1809	);
1810
1811#define	N_BYTE_ALIGMENT(__value, __aligment) ((__aligment == 1) ? \
1812	(__value) : (((__value + __aligment - 1) / __aligment) * __aligment))
1813
1814/****************************************
1815	mem access macro define end
1816****************************************/
1817
1818#define byte(x, n) ((x >> (8 * n)) & 0xff)
1819
1820#define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC)
1821#define RTL_WATCH_DOG_TIME	2000
1822#define MSECS(t)		msecs_to_jiffies(t)
1823#define WLAN_FC_GET_VERS(fc)	(le16_to_cpu(fc) & IEEE80211_FCTL_VERS)
1824#define WLAN_FC_GET_TYPE(fc)	(le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE)
1825#define WLAN_FC_GET_STYPE(fc)	(le16_to_cpu(fc) & IEEE80211_FCTL_STYPE)
1826#define WLAN_FC_MORE_DATA(fc)	(le16_to_cpu(fc) & IEEE80211_FCTL_MOREDATA)
1827#define SEQ_TO_SN(seq)		(((seq) & IEEE80211_SCTL_SEQ) >> 4)
1828#define SN_TO_SEQ(ssn)		(((ssn) << 4) & IEEE80211_SCTL_SEQ)
1829#define MAX_SN			((IEEE80211_SCTL_SEQ) >> 4)
1830
1831#define	RT_RF_OFF_LEVL_ASPM		BIT(0)	/*PCI ASPM */
1832#define	RT_RF_OFF_LEVL_CLK_REQ		BIT(1)	/*PCI clock request */
1833#define	RT_RF_OFF_LEVL_PCI_D3		BIT(2)	/*PCI D3 mode */
1834/*NIC halt, re-initialize hw parameters*/
1835#define	RT_RF_OFF_LEVL_HALT_NIC		BIT(3)
1836#define	RT_RF_OFF_LEVL_FREE_FW		BIT(4)	/*FW free, re-download the FW */
1837#define	RT_RF_OFF_LEVL_FW_32K		BIT(5)	/*FW in 32k */
1838/*Always enable ASPM and Clock Req in initialization.*/
1839#define	RT_RF_PS_LEVEL_ALWAYS_ASPM	BIT(6)
1840/* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/
1841#define	RT_PS_LEVEL_ASPM		BIT(7)
1842/*When LPS is on, disable 2R if no packet is received or transmittd.*/
1843#define	RT_RF_LPS_DISALBE_2R		BIT(30)
1844#define	RT_RF_LPS_LEVEL_ASPM		BIT(31)	/*LPS with ASPM */
1845#define	RT_IN_PS_LEVEL(ppsc, _ps_flg)		\
1846	((ppsc->cur_ps_level & _ps_flg) ? true : false)
1847#define	RT_CLEAR_PS_LEVEL(ppsc, _ps_flg)	\
1848	(ppsc->cur_ps_level &= (~(_ps_flg)))
1849#define	RT_SET_PS_LEVEL(ppsc, _ps_flg)		\
1850	(ppsc->cur_ps_level |= _ps_flg)
1851
1852#define container_of_dwork_rtl(x, y, z) \
1853	container_of(container_of(x, struct delayed_work, work), y, z)
1854
1855#define FILL_OCTET_STRING(_os, _octet, _len)	\
1856		(_os).octet = (u8 *)(_octet);		\
1857		(_os).length = (_len);
1858
1859#define CP_MACADDR(des, src)	\
1860	((des)[0] = (src)[0], (des)[1] = (src)[1],\
1861	(des)[2] = (src)[2], (des)[3] = (src)[3],\
1862	(des)[4] = (src)[4], (des)[5] = (src)[5])
1863
1864static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr)
1865{
1866	return rtlpriv->io.read8_sync(rtlpriv, addr);
1867}
1868
1869static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr)
1870{
1871	return rtlpriv->io.read16_sync(rtlpriv, addr);
1872}
1873
1874static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr)
1875{
1876	return rtlpriv->io.read32_sync(rtlpriv, addr);
1877}
1878
1879static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8)
1880{
1881	rtlpriv->io.write8_async(rtlpriv, addr, val8);
1882
1883	if (rtlpriv->cfg->write_readback)
1884		rtlpriv->io.read8_sync(rtlpriv, addr);
1885}
1886
1887static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16)
1888{
1889	rtlpriv->io.write16_async(rtlpriv, addr, val16);
1890
1891	if (rtlpriv->cfg->write_readback)
1892		rtlpriv->io.read16_sync(rtlpriv, addr);
1893}
1894
1895static inline void rtl_write_dword(struct rtl_priv *rtlpriv,
1896				   u32 addr, u32 val32)
1897{
1898	rtlpriv->io.write32_async(rtlpriv, addr, val32);
1899
1900	if (rtlpriv->cfg->write_readback)
1901		rtlpriv->io.read32_sync(rtlpriv, addr);
1902}
1903
1904static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw,
1905				u32 regaddr, u32 bitmask)
1906{
1907	return ((struct rtl_priv *)(hw)->priv)->cfg->ops->get_bbreg(hw,
1908								    regaddr,
1909								    bitmask);
1910}
1911
1912static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr,
1913				 u32 bitmask, u32 data)
1914{
1915	((struct rtl_priv *)(hw)->priv)->cfg->ops->set_bbreg(hw,
1916							     regaddr, bitmask,
1917							     data);
1918
 
1919}
1920
1921static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw,
1922				enum radio_path rfpath, u32 regaddr,
1923				u32 bitmask)
1924{
1925	return ((struct rtl_priv *)(hw)->priv)->cfg->ops->get_rfreg(hw,
1926								    rfpath,
1927								    regaddr,
1928								    bitmask);
1929}
1930
1931static inline void rtl_set_rfreg(struct ieee80211_hw *hw,
1932				 enum radio_path rfpath, u32 regaddr,
1933				 u32 bitmask, u32 data)
1934{
1935	((struct rtl_priv *)(hw)->priv)->cfg->ops->set_rfreg(hw,
1936							     rfpath, regaddr,
1937							     bitmask, data);
1938}
1939
1940static inline bool is_hal_stop(struct rtl_hal *rtlhal)
1941{
1942	return (_HAL_STATE_STOP == rtlhal->state);
1943}
1944
1945static inline void set_hal_start(struct rtl_hal *rtlhal)
1946{
1947	rtlhal->state = _HAL_STATE_START;
1948}
1949
1950static inline void set_hal_stop(struct rtl_hal *rtlhal)
1951{
1952	rtlhal->state = _HAL_STATE_STOP;
1953}
1954
1955static inline u8 get_rf_type(struct rtl_phy *rtlphy)
1956{
1957	return rtlphy->rf_type;
1958}
1959
1960static inline struct ieee80211_hdr *rtl_get_hdr(struct sk_buff *skb)
1961{
1962	return (struct ieee80211_hdr *)(skb->data);
1963}
1964
1965static inline __le16 rtl_get_fc(struct sk_buff *skb)
1966{
1967	return rtl_get_hdr(skb)->frame_control;
1968}
1969
1970static inline u16 rtl_get_tid_h(struct ieee80211_hdr *hdr)
1971{
1972	return (ieee80211_get_qos_ctl(hdr))[0] & IEEE80211_QOS_CTL_TID_MASK;
1973}
1974
1975static inline u16 rtl_get_tid(struct sk_buff *skb)
1976{
1977	return rtl_get_tid_h(rtl_get_hdr(skb));
1978}
1979
1980static inline struct ieee80211_sta *get_sta(struct ieee80211_hw *hw,
1981					    struct ieee80211_vif *vif,
1982					    const u8 *bssid)
1983{
1984	return ieee80211_find_sta(vif, bssid);
1985}
1986
1987#endif