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1/*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/nl80211.h>
18#include <linux/pci.h>
19#include <linux/pci-aspm.h>
20#include <linux/ath9k_platform.h>
21#include "ath9k.h"
22
23static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
24 { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */
25 { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
26 { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */
27 { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */
28 { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
29 { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
30 { PCI_VDEVICE(ATHEROS, 0x002C) }, /* PCI-E 802.11n bonded out */
31 { PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI */
32 { PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */
33 { PCI_VDEVICE(ATHEROS, 0x0030) }, /* PCI-E AR9300 */
34 { PCI_VDEVICE(ATHEROS, 0x0032) }, /* PCI-E AR9485 */
35 { 0 }
36};
37
38/* return bus cachesize in 4B word units */
39static void ath_pci_read_cachesize(struct ath_common *common, int *csz)
40{
41 struct ath_softc *sc = (struct ath_softc *) common->priv;
42 u8 u8tmp;
43
44 pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE, &u8tmp);
45 *csz = (int)u8tmp;
46
47 /*
48 * This check was put in to avoid "unpleasant" consequences if
49 * the bootrom has not fully initialized all PCI devices.
50 * Sometimes the cache line size register is not set
51 */
52
53 if (*csz == 0)
54 *csz = DEFAULT_CACHELINE >> 2; /* Use the default size */
55}
56
57static bool ath_pci_eeprom_read(struct ath_common *common, u32 off, u16 *data)
58{
59 struct ath_softc *sc = (struct ath_softc *) common->priv;
60 struct ath9k_platform_data *pdata = sc->dev->platform_data;
61
62 if (pdata) {
63 if (off >= (ARRAY_SIZE(pdata->eeprom_data))) {
64 ath_err(common,
65 "%s: eeprom read failed, offset %08x is out of range\n",
66 __func__, off);
67 }
68
69 *data = pdata->eeprom_data[off];
70 } else {
71 struct ath_hw *ah = (struct ath_hw *) common->ah;
72
73 common->ops->read(ah, AR5416_EEPROM_OFFSET +
74 (off << AR5416_EEPROM_S));
75
76 if (!ath9k_hw_wait(ah,
77 AR_EEPROM_STATUS_DATA,
78 AR_EEPROM_STATUS_DATA_BUSY |
79 AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
80 AH_WAIT_TIMEOUT)) {
81 return false;
82 }
83
84 *data = MS(common->ops->read(ah, AR_EEPROM_STATUS_DATA),
85 AR_EEPROM_STATUS_DATA_VAL);
86 }
87
88 return true;
89}
90
91/*
92 * Bluetooth coexistance requires disabling ASPM.
93 */
94static void ath_pci_bt_coex_prep(struct ath_common *common)
95{
96 struct ath_softc *sc = (struct ath_softc *) common->priv;
97 struct pci_dev *pdev = to_pci_dev(sc->dev);
98 u8 aspm;
99
100 if (!pci_is_pcie(pdev))
101 return;
102
103 pci_read_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, &aspm);
104 aspm &= ~(ATH_PCIE_CAP_LINK_L0S | ATH_PCIE_CAP_LINK_L1);
105 pci_write_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, aspm);
106}
107
108static void ath_pci_extn_synch_enable(struct ath_common *common)
109{
110 struct ath_softc *sc = (struct ath_softc *) common->priv;
111 struct pci_dev *pdev = to_pci_dev(sc->dev);
112 u8 lnkctl;
113
114 pci_read_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, &lnkctl);
115 lnkctl |= PCI_EXP_LNKCTL_ES;
116 pci_write_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, lnkctl);
117}
118
119static void ath_pci_aspm_init(struct ath_common *common)
120{
121 struct ath_softc *sc = (struct ath_softc *) common->priv;
122 struct ath_hw *ah = sc->sc_ah;
123 struct pci_dev *pdev = to_pci_dev(sc->dev);
124 struct pci_dev *parent;
125 int pos;
126 u8 aspm;
127
128 if (!pci_is_pcie(pdev))
129 return;
130
131 parent = pdev->bus->self;
132 if (WARN_ON(!parent))
133 return;
134
135 pos = pci_pcie_cap(parent);
136 pci_read_config_byte(parent, pos + PCI_EXP_LNKCTL, &aspm);
137 if (aspm & (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1)) {
138 ah->aspm_enabled = true;
139 /* Initialize PCIe PM and SERDES registers. */
140 ath9k_hw_configpcipowersave(ah, 0, 0);
141 }
142}
143
144static const struct ath_bus_ops ath_pci_bus_ops = {
145 .ath_bus_type = ATH_PCI,
146 .read_cachesize = ath_pci_read_cachesize,
147 .eeprom_read = ath_pci_eeprom_read,
148 .bt_coex_prep = ath_pci_bt_coex_prep,
149 .extn_synch_en = ath_pci_extn_synch_enable,
150 .aspm_init = ath_pci_aspm_init,
151};
152
153static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
154{
155 void __iomem *mem;
156 struct ath_softc *sc;
157 struct ieee80211_hw *hw;
158 u8 csz;
159 u16 subsysid;
160 u32 val;
161 int ret = 0;
162 char hw_name[64];
163
164 if (pci_enable_device(pdev))
165 return -EIO;
166
167 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
168 if (ret) {
169 printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
170 goto err_dma;
171 }
172
173 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
174 if (ret) {
175 printk(KERN_ERR "ath9k: 32-bit DMA consistent "
176 "DMA enable failed\n");
177 goto err_dma;
178 }
179
180 /*
181 * Cache line size is used to size and align various
182 * structures used to communicate with the hardware.
183 */
184 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
185 if (csz == 0) {
186 /*
187 * Linux 2.4.18 (at least) writes the cache line size
188 * register as a 16-bit wide register which is wrong.
189 * We must have this setup properly for rx buffer
190 * DMA to work so force a reasonable value here if it
191 * comes up zero.
192 */
193 csz = L1_CACHE_BYTES / sizeof(u32);
194 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
195 }
196 /*
197 * The default setting of latency timer yields poor results,
198 * set it to the value used by other systems. It may be worth
199 * tweaking this setting more.
200 */
201 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
202
203 pci_set_master(pdev);
204
205 /*
206 * Disable the RETRY_TIMEOUT register (0x41) to keep
207 * PCI Tx retries from interfering with C3 CPU state.
208 */
209 pci_read_config_dword(pdev, 0x40, &val);
210 if ((val & 0x0000ff00) != 0)
211 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
212
213 ret = pci_request_region(pdev, 0, "ath9k");
214 if (ret) {
215 dev_err(&pdev->dev, "PCI memory region reserve error\n");
216 ret = -ENODEV;
217 goto err_region;
218 }
219
220 mem = pci_iomap(pdev, 0, 0);
221 if (!mem) {
222 printk(KERN_ERR "PCI memory map error\n") ;
223 ret = -EIO;
224 goto err_iomap;
225 }
226
227 hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
228 if (!hw) {
229 dev_err(&pdev->dev, "No memory for ieee80211_hw\n");
230 ret = -ENOMEM;
231 goto err_alloc_hw;
232 }
233
234 SET_IEEE80211_DEV(hw, &pdev->dev);
235 pci_set_drvdata(pdev, hw);
236
237 sc = hw->priv;
238 sc->hw = hw;
239 sc->dev = &pdev->dev;
240 sc->mem = mem;
241
242 /* Will be cleared in ath9k_start() */
243 sc->sc_flags |= SC_OP_INVALID;
244
245 ret = request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath9k", sc);
246 if (ret) {
247 dev_err(&pdev->dev, "request_irq failed\n");
248 goto err_irq;
249 }
250
251 sc->irq = pdev->irq;
252
253 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &subsysid);
254 ret = ath9k_init_device(id->device, sc, subsysid, &ath_pci_bus_ops);
255 if (ret) {
256 dev_err(&pdev->dev, "Failed to initialize device\n");
257 goto err_init;
258 }
259
260 ath9k_hw_name(sc->sc_ah, hw_name, sizeof(hw_name));
261 wiphy_info(hw->wiphy, "%s mem=0x%lx, irq=%d\n",
262 hw_name, (unsigned long)mem, pdev->irq);
263
264 return 0;
265
266err_init:
267 free_irq(sc->irq, sc);
268err_irq:
269 ieee80211_free_hw(hw);
270err_alloc_hw:
271 pci_iounmap(pdev, mem);
272err_iomap:
273 pci_release_region(pdev, 0);
274err_region:
275 /* Nothing */
276err_dma:
277 pci_disable_device(pdev);
278 return ret;
279}
280
281static void ath_pci_remove(struct pci_dev *pdev)
282{
283 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
284 struct ath_softc *sc = hw->priv;
285 void __iomem *mem = sc->mem;
286
287 if (!is_ath9k_unloaded)
288 sc->sc_ah->ah_flags |= AH_UNPLUGGED;
289 ath9k_deinit_device(sc);
290 free_irq(sc->irq, sc);
291 ieee80211_free_hw(sc->hw);
292
293 pci_iounmap(pdev, mem);
294 pci_disable_device(pdev);
295 pci_release_region(pdev, 0);
296}
297
298#ifdef CONFIG_PM
299
300static int ath_pci_suspend(struct device *device)
301{
302 struct pci_dev *pdev = to_pci_dev(device);
303 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
304 struct ath_softc *sc = hw->priv;
305
306 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
307
308 /* The device has to be moved to FULLSLEEP forcibly.
309 * Otherwise the chip never moved to full sleep,
310 * when no interface is up.
311 */
312 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
313
314 return 0;
315}
316
317static int ath_pci_resume(struct device *device)
318{
319 struct pci_dev *pdev = to_pci_dev(device);
320 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
321 struct ath_softc *sc = hw->priv;
322 u32 val;
323
324 /*
325 * Suspend/Resume resets the PCI configuration space, so we have to
326 * re-disable the RETRY_TIMEOUT register (0x41) to keep
327 * PCI Tx retries from interfering with C3 CPU state
328 */
329 pci_read_config_dword(pdev, 0x40, &val);
330 if ((val & 0x0000ff00) != 0)
331 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
332
333 /* Enable LED */
334 ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
335 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
336 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
337
338 /*
339 * Reset key cache to sane defaults (all entries cleared) instead of
340 * semi-random values after suspend/resume.
341 */
342 ath9k_ps_wakeup(sc);
343 ath9k_init_crypto(sc);
344 ath9k_ps_restore(sc);
345
346 sc->ps_idle = true;
347 ath_radio_disable(sc, hw);
348
349 return 0;
350}
351
352static const struct dev_pm_ops ath9k_pm_ops = {
353 .suspend = ath_pci_suspend,
354 .resume = ath_pci_resume,
355 .freeze = ath_pci_suspend,
356 .thaw = ath_pci_resume,
357 .poweroff = ath_pci_suspend,
358 .restore = ath_pci_resume,
359};
360
361#define ATH9K_PM_OPS (&ath9k_pm_ops)
362
363#else /* !CONFIG_PM */
364
365#define ATH9K_PM_OPS NULL
366
367#endif /* !CONFIG_PM */
368
369
370MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
371
372static struct pci_driver ath_pci_driver = {
373 .name = "ath9k",
374 .id_table = ath_pci_id_table,
375 .probe = ath_pci_probe,
376 .remove = ath_pci_remove,
377 .driver.pm = ATH9K_PM_OPS,
378};
379
380int ath_pci_init(void)
381{
382 return pci_register_driver(&ath_pci_driver);
383}
384
385void ath_pci_exit(void)
386{
387 pci_unregister_driver(&ath_pci_driver);
388}
1/*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18
19#include <linux/nl80211.h>
20#include <linux/pci.h>
21#include <linux/pci-aspm.h>
22#include <linux/ath9k_platform.h>
23#include <linux/module.h>
24#include "ath9k.h"
25
26static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
27 { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */
28 { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
29 { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */
30 { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */
31 { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
32 { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
33 { PCI_VDEVICE(ATHEROS, 0x002C) }, /* PCI-E 802.11n bonded out */
34 { PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI */
35 { PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */
36 { PCI_VDEVICE(ATHEROS, 0x0030) }, /* PCI-E AR9300 */
37 { PCI_VDEVICE(ATHEROS, 0x0032) }, /* PCI-E AR9485 */
38 { PCI_VDEVICE(ATHEROS, 0x0033) }, /* PCI-E AR9580 */
39 { PCI_VDEVICE(ATHEROS, 0x0034) }, /* PCI-E AR9462 */
40 { PCI_VDEVICE(ATHEROS, 0x0037) }, /* PCI-E AR1111/AR9485 */
41 { 0 }
42};
43
44
45/* return bus cachesize in 4B word units */
46static void ath_pci_read_cachesize(struct ath_common *common, int *csz)
47{
48 struct ath_softc *sc = (struct ath_softc *) common->priv;
49 u8 u8tmp;
50
51 pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE, &u8tmp);
52 *csz = (int)u8tmp;
53
54 /*
55 * This check was put in to avoid "unpleasant" consequences if
56 * the bootrom has not fully initialized all PCI devices.
57 * Sometimes the cache line size register is not set
58 */
59
60 if (*csz == 0)
61 *csz = DEFAULT_CACHELINE >> 2; /* Use the default size */
62}
63
64static bool ath_pci_eeprom_read(struct ath_common *common, u32 off, u16 *data)
65{
66 struct ath_softc *sc = (struct ath_softc *) common->priv;
67 struct ath9k_platform_data *pdata = sc->dev->platform_data;
68
69 if (pdata) {
70 if (off >= (ARRAY_SIZE(pdata->eeprom_data))) {
71 ath_err(common,
72 "%s: eeprom read failed, offset %08x is out of range\n",
73 __func__, off);
74 }
75
76 *data = pdata->eeprom_data[off];
77 } else {
78 struct ath_hw *ah = (struct ath_hw *) common->ah;
79
80 common->ops->read(ah, AR5416_EEPROM_OFFSET +
81 (off << AR5416_EEPROM_S));
82
83 if (!ath9k_hw_wait(ah,
84 AR_EEPROM_STATUS_DATA,
85 AR_EEPROM_STATUS_DATA_BUSY |
86 AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
87 AH_WAIT_TIMEOUT)) {
88 return false;
89 }
90
91 *data = MS(common->ops->read(ah, AR_EEPROM_STATUS_DATA),
92 AR_EEPROM_STATUS_DATA_VAL);
93 }
94
95 return true;
96}
97
98static void ath_pci_extn_synch_enable(struct ath_common *common)
99{
100 struct ath_softc *sc = (struct ath_softc *) common->priv;
101 struct pci_dev *pdev = to_pci_dev(sc->dev);
102 u8 lnkctl;
103
104 pci_read_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, &lnkctl);
105 lnkctl |= PCI_EXP_LNKCTL_ES;
106 pci_write_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, lnkctl);
107}
108
109/* Need to be called after we discover btcoex capabilities */
110static void ath_pci_aspm_init(struct ath_common *common)
111{
112 struct ath_softc *sc = (struct ath_softc *) common->priv;
113 struct ath_hw *ah = sc->sc_ah;
114 struct pci_dev *pdev = to_pci_dev(sc->dev);
115 struct pci_dev *parent;
116 int pos;
117 u8 aspm;
118
119 pos = pci_pcie_cap(pdev);
120 if (!pos)
121 return;
122
123 parent = pdev->bus->self;
124 if (!parent)
125 return;
126
127 if ((ath9k_hw_get_btcoex_scheme(ah) != ATH_BTCOEX_CFG_NONE) &&
128 (AR_SREV_9285(ah))) {
129 /* Bluetooth coexistance requires disabling ASPM for AR9285. */
130 pci_read_config_byte(pdev, pos + PCI_EXP_LNKCTL, &aspm);
131 aspm &= ~(PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
132 pci_write_config_byte(pdev, pos + PCI_EXP_LNKCTL, aspm);
133
134 /*
135 * Both upstream and downstream PCIe components should
136 * have the same ASPM settings.
137 */
138 pos = pci_pcie_cap(parent);
139 pci_read_config_byte(parent, pos + PCI_EXP_LNKCTL, &aspm);
140 aspm &= ~(PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
141 pci_write_config_byte(parent, pos + PCI_EXP_LNKCTL, aspm);
142
143 return;
144 }
145
146 pos = pci_pcie_cap(parent);
147 pci_read_config_byte(parent, pos + PCI_EXP_LNKCTL, &aspm);
148 if (aspm & (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1)) {
149 ah->aspm_enabled = true;
150 /* Initialize PCIe PM and SERDES registers. */
151 ath9k_hw_configpcipowersave(ah, false);
152 }
153}
154
155static const struct ath_bus_ops ath_pci_bus_ops = {
156 .ath_bus_type = ATH_PCI,
157 .read_cachesize = ath_pci_read_cachesize,
158 .eeprom_read = ath_pci_eeprom_read,
159 .extn_synch_en = ath_pci_extn_synch_enable,
160 .aspm_init = ath_pci_aspm_init,
161};
162
163static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
164{
165 void __iomem *mem;
166 struct ath_softc *sc;
167 struct ieee80211_hw *hw;
168 u8 csz;
169 u32 val;
170 int ret = 0;
171 char hw_name[64];
172
173 if (pci_enable_device(pdev))
174 return -EIO;
175
176 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
177 if (ret) {
178 pr_err("32-bit DMA not available\n");
179 goto err_dma;
180 }
181
182 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
183 if (ret) {
184 pr_err("32-bit DMA consistent DMA enable failed\n");
185 goto err_dma;
186 }
187
188 /*
189 * Cache line size is used to size and align various
190 * structures used to communicate with the hardware.
191 */
192 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
193 if (csz == 0) {
194 /*
195 * Linux 2.4.18 (at least) writes the cache line size
196 * register as a 16-bit wide register which is wrong.
197 * We must have this setup properly for rx buffer
198 * DMA to work so force a reasonable value here if it
199 * comes up zero.
200 */
201 csz = L1_CACHE_BYTES / sizeof(u32);
202 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
203 }
204 /*
205 * The default setting of latency timer yields poor results,
206 * set it to the value used by other systems. It may be worth
207 * tweaking this setting more.
208 */
209 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
210
211 pci_set_master(pdev);
212
213 /*
214 * Disable the RETRY_TIMEOUT register (0x41) to keep
215 * PCI Tx retries from interfering with C3 CPU state.
216 */
217 pci_read_config_dword(pdev, 0x40, &val);
218 if ((val & 0x0000ff00) != 0)
219 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
220
221 ret = pci_request_region(pdev, 0, "ath9k");
222 if (ret) {
223 dev_err(&pdev->dev, "PCI memory region reserve error\n");
224 ret = -ENODEV;
225 goto err_region;
226 }
227
228 mem = pci_iomap(pdev, 0, 0);
229 if (!mem) {
230 pr_err("PCI memory map error\n") ;
231 ret = -EIO;
232 goto err_iomap;
233 }
234
235 hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
236 if (!hw) {
237 dev_err(&pdev->dev, "No memory for ieee80211_hw\n");
238 ret = -ENOMEM;
239 goto err_alloc_hw;
240 }
241
242 SET_IEEE80211_DEV(hw, &pdev->dev);
243 pci_set_drvdata(pdev, hw);
244
245 sc = hw->priv;
246 sc->hw = hw;
247 sc->dev = &pdev->dev;
248 sc->mem = mem;
249
250 /* Will be cleared in ath9k_start() */
251 sc->sc_flags |= SC_OP_INVALID;
252
253 ret = request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath9k", sc);
254 if (ret) {
255 dev_err(&pdev->dev, "request_irq failed\n");
256 goto err_irq;
257 }
258
259 sc->irq = pdev->irq;
260
261 ret = ath9k_init_device(id->device, sc, &ath_pci_bus_ops);
262 if (ret) {
263 dev_err(&pdev->dev, "Failed to initialize device\n");
264 goto err_init;
265 }
266
267 ath9k_hw_name(sc->sc_ah, hw_name, sizeof(hw_name));
268 wiphy_info(hw->wiphy, "%s mem=0x%lx, irq=%d\n",
269 hw_name, (unsigned long)mem, pdev->irq);
270
271 return 0;
272
273err_init:
274 free_irq(sc->irq, sc);
275err_irq:
276 ieee80211_free_hw(hw);
277err_alloc_hw:
278 pci_iounmap(pdev, mem);
279err_iomap:
280 pci_release_region(pdev, 0);
281err_region:
282 /* Nothing */
283err_dma:
284 pci_disable_device(pdev);
285 return ret;
286}
287
288static void ath_pci_remove(struct pci_dev *pdev)
289{
290 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
291 struct ath_softc *sc = hw->priv;
292 void __iomem *mem = sc->mem;
293
294 if (!is_ath9k_unloaded)
295 sc->sc_ah->ah_flags |= AH_UNPLUGGED;
296 ath9k_deinit_device(sc);
297 free_irq(sc->irq, sc);
298 ieee80211_free_hw(sc->hw);
299
300 pci_iounmap(pdev, mem);
301 pci_disable_device(pdev);
302 pci_release_region(pdev, 0);
303}
304
305#ifdef CONFIG_PM
306
307static int ath_pci_suspend(struct device *device)
308{
309 struct pci_dev *pdev = to_pci_dev(device);
310 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
311 struct ath_softc *sc = hw->priv;
312
313 /* The device has to be moved to FULLSLEEP forcibly.
314 * Otherwise the chip never moved to full sleep,
315 * when no interface is up.
316 */
317 ath9k_stop_btcoex(sc);
318 ath9k_hw_disable(sc->sc_ah);
319 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
320
321 return 0;
322}
323
324static int ath_pci_resume(struct device *device)
325{
326 struct pci_dev *pdev = to_pci_dev(device);
327 u32 val;
328
329 /*
330 * Suspend/Resume resets the PCI configuration space, so we have to
331 * re-disable the RETRY_TIMEOUT register (0x41) to keep
332 * PCI Tx retries from interfering with C3 CPU state
333 */
334 pci_read_config_dword(pdev, 0x40, &val);
335 if ((val & 0x0000ff00) != 0)
336 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
337
338 return 0;
339}
340
341static const struct dev_pm_ops ath9k_pm_ops = {
342 .suspend = ath_pci_suspend,
343 .resume = ath_pci_resume,
344 .freeze = ath_pci_suspend,
345 .thaw = ath_pci_resume,
346 .poweroff = ath_pci_suspend,
347 .restore = ath_pci_resume,
348};
349
350#define ATH9K_PM_OPS (&ath9k_pm_ops)
351
352#else /* !CONFIG_PM */
353
354#define ATH9K_PM_OPS NULL
355
356#endif /* !CONFIG_PM */
357
358
359MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
360
361static struct pci_driver ath_pci_driver = {
362 .name = "ath9k",
363 .id_table = ath_pci_id_table,
364 .probe = ath_pci_probe,
365 .remove = ath_pci_remove,
366 .driver.pm = ATH9K_PM_OPS,
367};
368
369int ath_pci_init(void)
370{
371 return pci_register_driver(&ath_pci_driver);
372}
373
374void ath_pci_exit(void)
375{
376 pci_unregister_driver(&ath_pci_driver);
377}