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1/****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2005-2011 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11#include <linux/module.h>
12#include <linux/pci.h>
13#include <linux/netdevice.h>
14#include <linux/etherdevice.h>
15#include <linux/delay.h>
16#include <linux/notifier.h>
17#include <linux/ip.h>
18#include <linux/tcp.h>
19#include <linux/in.h>
20#include <linux/crc32.h>
21#include <linux/ethtool.h>
22#include <linux/topology.h>
23#include <linux/gfp.h>
24#include <linux/cpu_rmap.h>
25#include "net_driver.h"
26#include "efx.h"
27#include "nic.h"
28
29#include "mcdi.h"
30#include "workarounds.h"
31
32/**************************************************************************
33 *
34 * Type name strings
35 *
36 **************************************************************************
37 */
38
39/* Loopback mode names (see LOOPBACK_MODE()) */
40const unsigned int efx_loopback_mode_max = LOOPBACK_MAX;
41const char *efx_loopback_mode_names[] = {
42 [LOOPBACK_NONE] = "NONE",
43 [LOOPBACK_DATA] = "DATAPATH",
44 [LOOPBACK_GMAC] = "GMAC",
45 [LOOPBACK_XGMII] = "XGMII",
46 [LOOPBACK_XGXS] = "XGXS",
47 [LOOPBACK_XAUI] = "XAUI",
48 [LOOPBACK_GMII] = "GMII",
49 [LOOPBACK_SGMII] = "SGMII",
50 [LOOPBACK_XGBR] = "XGBR",
51 [LOOPBACK_XFI] = "XFI",
52 [LOOPBACK_XAUI_FAR] = "XAUI_FAR",
53 [LOOPBACK_GMII_FAR] = "GMII_FAR",
54 [LOOPBACK_SGMII_FAR] = "SGMII_FAR",
55 [LOOPBACK_XFI_FAR] = "XFI_FAR",
56 [LOOPBACK_GPHY] = "GPHY",
57 [LOOPBACK_PHYXS] = "PHYXS",
58 [LOOPBACK_PCS] = "PCS",
59 [LOOPBACK_PMAPMD] = "PMA/PMD",
60 [LOOPBACK_XPORT] = "XPORT",
61 [LOOPBACK_XGMII_WS] = "XGMII_WS",
62 [LOOPBACK_XAUI_WS] = "XAUI_WS",
63 [LOOPBACK_XAUI_WS_FAR] = "XAUI_WS_FAR",
64 [LOOPBACK_XAUI_WS_NEAR] = "XAUI_WS_NEAR",
65 [LOOPBACK_GMII_WS] = "GMII_WS",
66 [LOOPBACK_XFI_WS] = "XFI_WS",
67 [LOOPBACK_XFI_WS_FAR] = "XFI_WS_FAR",
68 [LOOPBACK_PHYXS_WS] = "PHYXS_WS",
69};
70
71const unsigned int efx_reset_type_max = RESET_TYPE_MAX;
72const char *efx_reset_type_names[] = {
73 [RESET_TYPE_INVISIBLE] = "INVISIBLE",
74 [RESET_TYPE_ALL] = "ALL",
75 [RESET_TYPE_WORLD] = "WORLD",
76 [RESET_TYPE_DISABLE] = "DISABLE",
77 [RESET_TYPE_TX_WATCHDOG] = "TX_WATCHDOG",
78 [RESET_TYPE_INT_ERROR] = "INT_ERROR",
79 [RESET_TYPE_RX_RECOVERY] = "RX_RECOVERY",
80 [RESET_TYPE_RX_DESC_FETCH] = "RX_DESC_FETCH",
81 [RESET_TYPE_TX_DESC_FETCH] = "TX_DESC_FETCH",
82 [RESET_TYPE_TX_SKIP] = "TX_SKIP",
83 [RESET_TYPE_MC_FAILURE] = "MC_FAILURE",
84};
85
86#define EFX_MAX_MTU (9 * 1024)
87
88/* Reset workqueue. If any NIC has a hardware failure then a reset will be
89 * queued onto this work queue. This is not a per-nic work queue, because
90 * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised.
91 */
92static struct workqueue_struct *reset_workqueue;
93
94/**************************************************************************
95 *
96 * Configurable values
97 *
98 *************************************************************************/
99
100/*
101 * Use separate channels for TX and RX events
102 *
103 * Set this to 1 to use separate channels for TX and RX. It allows us
104 * to control interrupt affinity separately for TX and RX.
105 *
106 * This is only used in MSI-X interrupt mode
107 */
108static unsigned int separate_tx_channels;
109module_param(separate_tx_channels, uint, 0444);
110MODULE_PARM_DESC(separate_tx_channels,
111 "Use separate channels for TX and RX");
112
113/* This is the weight assigned to each of the (per-channel) virtual
114 * NAPI devices.
115 */
116static int napi_weight = 64;
117
118/* This is the time (in jiffies) between invocations of the hardware
119 * monitor. On Falcon-based NICs, this will:
120 * - Check the on-board hardware monitor;
121 * - Poll the link state and reconfigure the hardware as necessary.
122 */
123static unsigned int efx_monitor_interval = 1 * HZ;
124
125/* This controls whether or not the driver will initialise devices
126 * with invalid MAC addresses stored in the EEPROM or flash. If true,
127 * such devices will be initialised with a random locally-generated
128 * MAC address. This allows for loading the sfc_mtd driver to
129 * reprogram the flash, even if the flash contents (including the MAC
130 * address) have previously been erased.
131 */
132static unsigned int allow_bad_hwaddr;
133
134/* Initial interrupt moderation settings. They can be modified after
135 * module load with ethtool.
136 *
137 * The default for RX should strike a balance between increasing the
138 * round-trip latency and reducing overhead.
139 */
140static unsigned int rx_irq_mod_usec = 60;
141
142/* Initial interrupt moderation settings. They can be modified after
143 * module load with ethtool.
144 *
145 * This default is chosen to ensure that a 10G link does not go idle
146 * while a TX queue is stopped after it has become full. A queue is
147 * restarted when it drops below half full. The time this takes (assuming
148 * worst case 3 descriptors per packet and 1024 descriptors) is
149 * 512 / 3 * 1.2 = 205 usec.
150 */
151static unsigned int tx_irq_mod_usec = 150;
152
153/* This is the first interrupt mode to try out of:
154 * 0 => MSI-X
155 * 1 => MSI
156 * 2 => legacy
157 */
158static unsigned int interrupt_mode;
159
160/* This is the requested number of CPUs to use for Receive-Side Scaling (RSS),
161 * i.e. the number of CPUs among which we may distribute simultaneous
162 * interrupt handling.
163 *
164 * Cards without MSI-X will only target one CPU via legacy or MSI interrupt.
165 * The default (0) means to assign an interrupt to each package (level II cache)
166 */
167static unsigned int rss_cpus;
168module_param(rss_cpus, uint, 0444);
169MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling");
170
171static int phy_flash_cfg;
172module_param(phy_flash_cfg, int, 0644);
173MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially");
174
175static unsigned irq_adapt_low_thresh = 10000;
176module_param(irq_adapt_low_thresh, uint, 0644);
177MODULE_PARM_DESC(irq_adapt_low_thresh,
178 "Threshold score for reducing IRQ moderation");
179
180static unsigned irq_adapt_high_thresh = 20000;
181module_param(irq_adapt_high_thresh, uint, 0644);
182MODULE_PARM_DESC(irq_adapt_high_thresh,
183 "Threshold score for increasing IRQ moderation");
184
185static unsigned debug = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
186 NETIF_MSG_LINK | NETIF_MSG_IFDOWN |
187 NETIF_MSG_IFUP | NETIF_MSG_RX_ERR |
188 NETIF_MSG_TX_ERR | NETIF_MSG_HW);
189module_param(debug, uint, 0);
190MODULE_PARM_DESC(debug, "Bitmapped debugging message enable value");
191
192/**************************************************************************
193 *
194 * Utility functions and prototypes
195 *
196 *************************************************************************/
197
198static void efx_remove_channels(struct efx_nic *efx);
199static void efx_remove_port(struct efx_nic *efx);
200static void efx_init_napi(struct efx_nic *efx);
201static void efx_fini_napi(struct efx_nic *efx);
202static void efx_fini_napi_channel(struct efx_channel *channel);
203static void efx_fini_struct(struct efx_nic *efx);
204static void efx_start_all(struct efx_nic *efx);
205static void efx_stop_all(struct efx_nic *efx);
206
207#define EFX_ASSERT_RESET_SERIALISED(efx) \
208 do { \
209 if ((efx->state == STATE_RUNNING) || \
210 (efx->state == STATE_DISABLED)) \
211 ASSERT_RTNL(); \
212 } while (0)
213
214/**************************************************************************
215 *
216 * Event queue processing
217 *
218 *************************************************************************/
219
220/* Process channel's event queue
221 *
222 * This function is responsible for processing the event queue of a
223 * single channel. The caller must guarantee that this function will
224 * never be concurrently called more than once on the same channel,
225 * though different channels may be being processed concurrently.
226 */
227static int efx_process_channel(struct efx_channel *channel, int budget)
228{
229 struct efx_nic *efx = channel->efx;
230 int spent;
231
232 if (unlikely(efx->reset_pending || !channel->enabled))
233 return 0;
234
235 spent = efx_nic_process_eventq(channel, budget);
236 if (spent == 0)
237 return 0;
238
239 /* Deliver last RX packet. */
240 if (channel->rx_pkt) {
241 __efx_rx_packet(channel, channel->rx_pkt,
242 channel->rx_pkt_csummed);
243 channel->rx_pkt = NULL;
244 }
245
246 efx_rx_strategy(channel);
247
248 efx_fast_push_rx_descriptors(efx_channel_get_rx_queue(channel));
249
250 return spent;
251}
252
253/* Mark channel as finished processing
254 *
255 * Note that since we will not receive further interrupts for this
256 * channel before we finish processing and call the eventq_read_ack()
257 * method, there is no need to use the interrupt hold-off timers.
258 */
259static inline void efx_channel_processed(struct efx_channel *channel)
260{
261 /* The interrupt handler for this channel may set work_pending
262 * as soon as we acknowledge the events we've seen. Make sure
263 * it's cleared before then. */
264 channel->work_pending = false;
265 smp_wmb();
266
267 efx_nic_eventq_read_ack(channel);
268}
269
270/* NAPI poll handler
271 *
272 * NAPI guarantees serialisation of polls of the same device, which
273 * provides the guarantee required by efx_process_channel().
274 */
275static int efx_poll(struct napi_struct *napi, int budget)
276{
277 struct efx_channel *channel =
278 container_of(napi, struct efx_channel, napi_str);
279 struct efx_nic *efx = channel->efx;
280 int spent;
281
282 netif_vdbg(efx, intr, efx->net_dev,
283 "channel %d NAPI poll executing on CPU %d\n",
284 channel->channel, raw_smp_processor_id());
285
286 spent = efx_process_channel(channel, budget);
287
288 if (spent < budget) {
289 if (channel->channel < efx->n_rx_channels &&
290 efx->irq_rx_adaptive &&
291 unlikely(++channel->irq_count == 1000)) {
292 if (unlikely(channel->irq_mod_score <
293 irq_adapt_low_thresh)) {
294 if (channel->irq_moderation > 1) {
295 channel->irq_moderation -= 1;
296 efx->type->push_irq_moderation(channel);
297 }
298 } else if (unlikely(channel->irq_mod_score >
299 irq_adapt_high_thresh)) {
300 if (channel->irq_moderation <
301 efx->irq_rx_moderation) {
302 channel->irq_moderation += 1;
303 efx->type->push_irq_moderation(channel);
304 }
305 }
306 channel->irq_count = 0;
307 channel->irq_mod_score = 0;
308 }
309
310 efx_filter_rfs_expire(channel);
311
312 /* There is no race here; although napi_disable() will
313 * only wait for napi_complete(), this isn't a problem
314 * since efx_channel_processed() will have no effect if
315 * interrupts have already been disabled.
316 */
317 napi_complete(napi);
318 efx_channel_processed(channel);
319 }
320
321 return spent;
322}
323
324/* Process the eventq of the specified channel immediately on this CPU
325 *
326 * Disable hardware generated interrupts, wait for any existing
327 * processing to finish, then directly poll (and ack ) the eventq.
328 * Finally reenable NAPI and interrupts.
329 *
330 * This is for use only during a loopback self-test. It must not
331 * deliver any packets up the stack as this can result in deadlock.
332 */
333void efx_process_channel_now(struct efx_channel *channel)
334{
335 struct efx_nic *efx = channel->efx;
336
337 BUG_ON(channel->channel >= efx->n_channels);
338 BUG_ON(!channel->enabled);
339 BUG_ON(!efx->loopback_selftest);
340
341 /* Disable interrupts and wait for ISRs to complete */
342 efx_nic_disable_interrupts(efx);
343 if (efx->legacy_irq) {
344 synchronize_irq(efx->legacy_irq);
345 efx->legacy_irq_enabled = false;
346 }
347 if (channel->irq)
348 synchronize_irq(channel->irq);
349
350 /* Wait for any NAPI processing to complete */
351 napi_disable(&channel->napi_str);
352
353 /* Poll the channel */
354 efx_process_channel(channel, channel->eventq_mask + 1);
355
356 /* Ack the eventq. This may cause an interrupt to be generated
357 * when they are reenabled */
358 efx_channel_processed(channel);
359
360 napi_enable(&channel->napi_str);
361 if (efx->legacy_irq)
362 efx->legacy_irq_enabled = true;
363 efx_nic_enable_interrupts(efx);
364}
365
366/* Create event queue
367 * Event queue memory allocations are done only once. If the channel
368 * is reset, the memory buffer will be reused; this guards against
369 * errors during channel reset and also simplifies interrupt handling.
370 */
371static int efx_probe_eventq(struct efx_channel *channel)
372{
373 struct efx_nic *efx = channel->efx;
374 unsigned long entries;
375
376 netif_dbg(channel->efx, probe, channel->efx->net_dev,
377 "chan %d create event queue\n", channel->channel);
378
379 /* Build an event queue with room for one event per tx and rx buffer,
380 * plus some extra for link state events and MCDI completions. */
381 entries = roundup_pow_of_two(efx->rxq_entries + efx->txq_entries + 128);
382 EFX_BUG_ON_PARANOID(entries > EFX_MAX_EVQ_SIZE);
383 channel->eventq_mask = max(entries, EFX_MIN_EVQ_SIZE) - 1;
384
385 return efx_nic_probe_eventq(channel);
386}
387
388/* Prepare channel's event queue */
389static void efx_init_eventq(struct efx_channel *channel)
390{
391 netif_dbg(channel->efx, drv, channel->efx->net_dev,
392 "chan %d init event queue\n", channel->channel);
393
394 channel->eventq_read_ptr = 0;
395
396 efx_nic_init_eventq(channel);
397}
398
399static void efx_fini_eventq(struct efx_channel *channel)
400{
401 netif_dbg(channel->efx, drv, channel->efx->net_dev,
402 "chan %d fini event queue\n", channel->channel);
403
404 efx_nic_fini_eventq(channel);
405}
406
407static void efx_remove_eventq(struct efx_channel *channel)
408{
409 netif_dbg(channel->efx, drv, channel->efx->net_dev,
410 "chan %d remove event queue\n", channel->channel);
411
412 efx_nic_remove_eventq(channel);
413}
414
415/**************************************************************************
416 *
417 * Channel handling
418 *
419 *************************************************************************/
420
421/* Allocate and initialise a channel structure, optionally copying
422 * parameters (but not resources) from an old channel structure. */
423static struct efx_channel *
424efx_alloc_channel(struct efx_nic *efx, int i, struct efx_channel *old_channel)
425{
426 struct efx_channel *channel;
427 struct efx_rx_queue *rx_queue;
428 struct efx_tx_queue *tx_queue;
429 int j;
430
431 if (old_channel) {
432 channel = kmalloc(sizeof(*channel), GFP_KERNEL);
433 if (!channel)
434 return NULL;
435
436 *channel = *old_channel;
437
438 channel->napi_dev = NULL;
439 memset(&channel->eventq, 0, sizeof(channel->eventq));
440
441 rx_queue = &channel->rx_queue;
442 rx_queue->buffer = NULL;
443 memset(&rx_queue->rxd, 0, sizeof(rx_queue->rxd));
444
445 for (j = 0; j < EFX_TXQ_TYPES; j++) {
446 tx_queue = &channel->tx_queue[j];
447 if (tx_queue->channel)
448 tx_queue->channel = channel;
449 tx_queue->buffer = NULL;
450 memset(&tx_queue->txd, 0, sizeof(tx_queue->txd));
451 }
452 } else {
453 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
454 if (!channel)
455 return NULL;
456
457 channel->efx = efx;
458 channel->channel = i;
459
460 for (j = 0; j < EFX_TXQ_TYPES; j++) {
461 tx_queue = &channel->tx_queue[j];
462 tx_queue->efx = efx;
463 tx_queue->queue = i * EFX_TXQ_TYPES + j;
464 tx_queue->channel = channel;
465 }
466 }
467
468 rx_queue = &channel->rx_queue;
469 rx_queue->efx = efx;
470 setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill,
471 (unsigned long)rx_queue);
472
473 return channel;
474}
475
476static int efx_probe_channel(struct efx_channel *channel)
477{
478 struct efx_tx_queue *tx_queue;
479 struct efx_rx_queue *rx_queue;
480 int rc;
481
482 netif_dbg(channel->efx, probe, channel->efx->net_dev,
483 "creating channel %d\n", channel->channel);
484
485 rc = efx_probe_eventq(channel);
486 if (rc)
487 goto fail1;
488
489 efx_for_each_channel_tx_queue(tx_queue, channel) {
490 rc = efx_probe_tx_queue(tx_queue);
491 if (rc)
492 goto fail2;
493 }
494
495 efx_for_each_channel_rx_queue(rx_queue, channel) {
496 rc = efx_probe_rx_queue(rx_queue);
497 if (rc)
498 goto fail3;
499 }
500
501 channel->n_rx_frm_trunc = 0;
502
503 return 0;
504
505 fail3:
506 efx_for_each_channel_rx_queue(rx_queue, channel)
507 efx_remove_rx_queue(rx_queue);
508 fail2:
509 efx_for_each_channel_tx_queue(tx_queue, channel)
510 efx_remove_tx_queue(tx_queue);
511 fail1:
512 return rc;
513}
514
515
516static void efx_set_channel_names(struct efx_nic *efx)
517{
518 struct efx_channel *channel;
519 const char *type = "";
520 int number;
521
522 efx_for_each_channel(channel, efx) {
523 number = channel->channel;
524 if (efx->n_channels > efx->n_rx_channels) {
525 if (channel->channel < efx->n_rx_channels) {
526 type = "-rx";
527 } else {
528 type = "-tx";
529 number -= efx->n_rx_channels;
530 }
531 }
532 snprintf(efx->channel_name[channel->channel],
533 sizeof(efx->channel_name[0]),
534 "%s%s-%d", efx->name, type, number);
535 }
536}
537
538static int efx_probe_channels(struct efx_nic *efx)
539{
540 struct efx_channel *channel;
541 int rc;
542
543 /* Restart special buffer allocation */
544 efx->next_buffer_table = 0;
545
546 efx_for_each_channel(channel, efx) {
547 rc = efx_probe_channel(channel);
548 if (rc) {
549 netif_err(efx, probe, efx->net_dev,
550 "failed to create channel %d\n",
551 channel->channel);
552 goto fail;
553 }
554 }
555 efx_set_channel_names(efx);
556
557 return 0;
558
559fail:
560 efx_remove_channels(efx);
561 return rc;
562}
563
564/* Channels are shutdown and reinitialised whilst the NIC is running
565 * to propagate configuration changes (mtu, checksum offload), or
566 * to clear hardware error conditions
567 */
568static void efx_init_channels(struct efx_nic *efx)
569{
570 struct efx_tx_queue *tx_queue;
571 struct efx_rx_queue *rx_queue;
572 struct efx_channel *channel;
573
574 /* Calculate the rx buffer allocation parameters required to
575 * support the current MTU, including padding for header
576 * alignment and overruns.
577 */
578 efx->rx_buffer_len = (max(EFX_PAGE_IP_ALIGN, NET_IP_ALIGN) +
579 EFX_MAX_FRAME_LEN(efx->net_dev->mtu) +
580 efx->type->rx_buffer_hash_size +
581 efx->type->rx_buffer_padding);
582 efx->rx_buffer_order = get_order(efx->rx_buffer_len +
583 sizeof(struct efx_rx_page_state));
584
585 /* Initialise the channels */
586 efx_for_each_channel(channel, efx) {
587 netif_dbg(channel->efx, drv, channel->efx->net_dev,
588 "init chan %d\n", channel->channel);
589
590 efx_init_eventq(channel);
591
592 efx_for_each_channel_tx_queue(tx_queue, channel)
593 efx_init_tx_queue(tx_queue);
594
595 /* The rx buffer allocation strategy is MTU dependent */
596 efx_rx_strategy(channel);
597
598 efx_for_each_channel_rx_queue(rx_queue, channel)
599 efx_init_rx_queue(rx_queue);
600
601 WARN_ON(channel->rx_pkt != NULL);
602 efx_rx_strategy(channel);
603 }
604}
605
606/* This enables event queue processing and packet transmission.
607 *
608 * Note that this function is not allowed to fail, since that would
609 * introduce too much complexity into the suspend/resume path.
610 */
611static void efx_start_channel(struct efx_channel *channel)
612{
613 struct efx_rx_queue *rx_queue;
614
615 netif_dbg(channel->efx, ifup, channel->efx->net_dev,
616 "starting chan %d\n", channel->channel);
617
618 /* The interrupt handler for this channel may set work_pending
619 * as soon as we enable it. Make sure it's cleared before
620 * then. Similarly, make sure it sees the enabled flag set. */
621 channel->work_pending = false;
622 channel->enabled = true;
623 smp_wmb();
624
625 /* Fill the queues before enabling NAPI */
626 efx_for_each_channel_rx_queue(rx_queue, channel)
627 efx_fast_push_rx_descriptors(rx_queue);
628
629 napi_enable(&channel->napi_str);
630}
631
632/* This disables event queue processing and packet transmission.
633 * This function does not guarantee that all queue processing
634 * (e.g. RX refill) is complete.
635 */
636static void efx_stop_channel(struct efx_channel *channel)
637{
638 if (!channel->enabled)
639 return;
640
641 netif_dbg(channel->efx, ifdown, channel->efx->net_dev,
642 "stop chan %d\n", channel->channel);
643
644 channel->enabled = false;
645 napi_disable(&channel->napi_str);
646}
647
648static void efx_fini_channels(struct efx_nic *efx)
649{
650 struct efx_channel *channel;
651 struct efx_tx_queue *tx_queue;
652 struct efx_rx_queue *rx_queue;
653 int rc;
654
655 EFX_ASSERT_RESET_SERIALISED(efx);
656 BUG_ON(efx->port_enabled);
657
658 rc = efx_nic_flush_queues(efx);
659 if (rc && EFX_WORKAROUND_7803(efx)) {
660 /* Schedule a reset to recover from the flush failure. The
661 * descriptor caches reference memory we're about to free,
662 * but falcon_reconfigure_mac_wrapper() won't reconnect
663 * the MACs because of the pending reset. */
664 netif_err(efx, drv, efx->net_dev,
665 "Resetting to recover from flush failure\n");
666 efx_schedule_reset(efx, RESET_TYPE_ALL);
667 } else if (rc) {
668 netif_err(efx, drv, efx->net_dev, "failed to flush queues\n");
669 } else {
670 netif_dbg(efx, drv, efx->net_dev,
671 "successfully flushed all queues\n");
672 }
673
674 efx_for_each_channel(channel, efx) {
675 netif_dbg(channel->efx, drv, channel->efx->net_dev,
676 "shut down chan %d\n", channel->channel);
677
678 efx_for_each_channel_rx_queue(rx_queue, channel)
679 efx_fini_rx_queue(rx_queue);
680 efx_for_each_possible_channel_tx_queue(tx_queue, channel)
681 efx_fini_tx_queue(tx_queue);
682 efx_fini_eventq(channel);
683 }
684}
685
686static void efx_remove_channel(struct efx_channel *channel)
687{
688 struct efx_tx_queue *tx_queue;
689 struct efx_rx_queue *rx_queue;
690
691 netif_dbg(channel->efx, drv, channel->efx->net_dev,
692 "destroy chan %d\n", channel->channel);
693
694 efx_for_each_channel_rx_queue(rx_queue, channel)
695 efx_remove_rx_queue(rx_queue);
696 efx_for_each_possible_channel_tx_queue(tx_queue, channel)
697 efx_remove_tx_queue(tx_queue);
698 efx_remove_eventq(channel);
699}
700
701static void efx_remove_channels(struct efx_nic *efx)
702{
703 struct efx_channel *channel;
704
705 efx_for_each_channel(channel, efx)
706 efx_remove_channel(channel);
707}
708
709int
710efx_realloc_channels(struct efx_nic *efx, u32 rxq_entries, u32 txq_entries)
711{
712 struct efx_channel *other_channel[EFX_MAX_CHANNELS], *channel;
713 u32 old_rxq_entries, old_txq_entries;
714 unsigned i;
715 int rc;
716
717 efx_stop_all(efx);
718 efx_fini_channels(efx);
719
720 /* Clone channels */
721 memset(other_channel, 0, sizeof(other_channel));
722 for (i = 0; i < efx->n_channels; i++) {
723 channel = efx_alloc_channel(efx, i, efx->channel[i]);
724 if (!channel) {
725 rc = -ENOMEM;
726 goto out;
727 }
728 other_channel[i] = channel;
729 }
730
731 /* Swap entry counts and channel pointers */
732 old_rxq_entries = efx->rxq_entries;
733 old_txq_entries = efx->txq_entries;
734 efx->rxq_entries = rxq_entries;
735 efx->txq_entries = txq_entries;
736 for (i = 0; i < efx->n_channels; i++) {
737 channel = efx->channel[i];
738 efx->channel[i] = other_channel[i];
739 other_channel[i] = channel;
740 }
741
742 rc = efx_probe_channels(efx);
743 if (rc)
744 goto rollback;
745
746 efx_init_napi(efx);
747
748 /* Destroy old channels */
749 for (i = 0; i < efx->n_channels; i++) {
750 efx_fini_napi_channel(other_channel[i]);
751 efx_remove_channel(other_channel[i]);
752 }
753out:
754 /* Free unused channel structures */
755 for (i = 0; i < efx->n_channels; i++)
756 kfree(other_channel[i]);
757
758 efx_init_channels(efx);
759 efx_start_all(efx);
760 return rc;
761
762rollback:
763 /* Swap back */
764 efx->rxq_entries = old_rxq_entries;
765 efx->txq_entries = old_txq_entries;
766 for (i = 0; i < efx->n_channels; i++) {
767 channel = efx->channel[i];
768 efx->channel[i] = other_channel[i];
769 other_channel[i] = channel;
770 }
771 goto out;
772}
773
774void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue)
775{
776 mod_timer(&rx_queue->slow_fill, jiffies + msecs_to_jiffies(100));
777}
778
779/**************************************************************************
780 *
781 * Port handling
782 *
783 **************************************************************************/
784
785/* This ensures that the kernel is kept informed (via
786 * netif_carrier_on/off) of the link status, and also maintains the
787 * link status's stop on the port's TX queue.
788 */
789void efx_link_status_changed(struct efx_nic *efx)
790{
791 struct efx_link_state *link_state = &efx->link_state;
792
793 /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure
794 * that no events are triggered between unregister_netdev() and the
795 * driver unloading. A more general condition is that NETDEV_CHANGE
796 * can only be generated between NETDEV_UP and NETDEV_DOWN */
797 if (!netif_running(efx->net_dev))
798 return;
799
800 if (link_state->up != netif_carrier_ok(efx->net_dev)) {
801 efx->n_link_state_changes++;
802
803 if (link_state->up)
804 netif_carrier_on(efx->net_dev);
805 else
806 netif_carrier_off(efx->net_dev);
807 }
808
809 /* Status message for kernel log */
810 if (link_state->up) {
811 netif_info(efx, link, efx->net_dev,
812 "link up at %uMbps %s-duplex (MTU %d)%s\n",
813 link_state->speed, link_state->fd ? "full" : "half",
814 efx->net_dev->mtu,
815 (efx->promiscuous ? " [PROMISC]" : ""));
816 } else {
817 netif_info(efx, link, efx->net_dev, "link down\n");
818 }
819
820}
821
822void efx_link_set_advertising(struct efx_nic *efx, u32 advertising)
823{
824 efx->link_advertising = advertising;
825 if (advertising) {
826 if (advertising & ADVERTISED_Pause)
827 efx->wanted_fc |= (EFX_FC_TX | EFX_FC_RX);
828 else
829 efx->wanted_fc &= ~(EFX_FC_TX | EFX_FC_RX);
830 if (advertising & ADVERTISED_Asym_Pause)
831 efx->wanted_fc ^= EFX_FC_TX;
832 }
833}
834
835void efx_link_set_wanted_fc(struct efx_nic *efx, u8 wanted_fc)
836{
837 efx->wanted_fc = wanted_fc;
838 if (efx->link_advertising) {
839 if (wanted_fc & EFX_FC_RX)
840 efx->link_advertising |= (ADVERTISED_Pause |
841 ADVERTISED_Asym_Pause);
842 else
843 efx->link_advertising &= ~(ADVERTISED_Pause |
844 ADVERTISED_Asym_Pause);
845 if (wanted_fc & EFX_FC_TX)
846 efx->link_advertising ^= ADVERTISED_Asym_Pause;
847 }
848}
849
850static void efx_fini_port(struct efx_nic *efx);
851
852/* Push loopback/power/transmit disable settings to the PHY, and reconfigure
853 * the MAC appropriately. All other PHY configuration changes are pushed
854 * through phy_op->set_settings(), and pushed asynchronously to the MAC
855 * through efx_monitor().
856 *
857 * Callers must hold the mac_lock
858 */
859int __efx_reconfigure_port(struct efx_nic *efx)
860{
861 enum efx_phy_mode phy_mode;
862 int rc;
863
864 WARN_ON(!mutex_is_locked(&efx->mac_lock));
865
866 /* Serialise the promiscuous flag with efx_set_multicast_list. */
867 if (efx_dev_registered(efx)) {
868 netif_addr_lock_bh(efx->net_dev);
869 netif_addr_unlock_bh(efx->net_dev);
870 }
871
872 /* Disable PHY transmit in mac level loopbacks */
873 phy_mode = efx->phy_mode;
874 if (LOOPBACK_INTERNAL(efx))
875 efx->phy_mode |= PHY_MODE_TX_DISABLED;
876 else
877 efx->phy_mode &= ~PHY_MODE_TX_DISABLED;
878
879 rc = efx->type->reconfigure_port(efx);
880
881 if (rc)
882 efx->phy_mode = phy_mode;
883
884 return rc;
885}
886
887/* Reinitialise the MAC to pick up new PHY settings, even if the port is
888 * disabled. */
889int efx_reconfigure_port(struct efx_nic *efx)
890{
891 int rc;
892
893 EFX_ASSERT_RESET_SERIALISED(efx);
894
895 mutex_lock(&efx->mac_lock);
896 rc = __efx_reconfigure_port(efx);
897 mutex_unlock(&efx->mac_lock);
898
899 return rc;
900}
901
902/* Asynchronous work item for changing MAC promiscuity and multicast
903 * hash. Avoid a drain/rx_ingress enable by reconfiguring the current
904 * MAC directly. */
905static void efx_mac_work(struct work_struct *data)
906{
907 struct efx_nic *efx = container_of(data, struct efx_nic, mac_work);
908
909 mutex_lock(&efx->mac_lock);
910 if (efx->port_enabled) {
911 efx->type->push_multicast_hash(efx);
912 efx->mac_op->reconfigure(efx);
913 }
914 mutex_unlock(&efx->mac_lock);
915}
916
917static int efx_probe_port(struct efx_nic *efx)
918{
919 unsigned char *perm_addr;
920 int rc;
921
922 netif_dbg(efx, probe, efx->net_dev, "create port\n");
923
924 if (phy_flash_cfg)
925 efx->phy_mode = PHY_MODE_SPECIAL;
926
927 /* Connect up MAC/PHY operations table */
928 rc = efx->type->probe_port(efx);
929 if (rc)
930 return rc;
931
932 /* Sanity check MAC address */
933 perm_addr = efx->net_dev->perm_addr;
934 if (is_valid_ether_addr(perm_addr)) {
935 memcpy(efx->net_dev->dev_addr, perm_addr, ETH_ALEN);
936 } else {
937 netif_err(efx, probe, efx->net_dev, "invalid MAC address %pM\n",
938 perm_addr);
939 if (!allow_bad_hwaddr) {
940 rc = -EINVAL;
941 goto err;
942 }
943 random_ether_addr(efx->net_dev->dev_addr);
944 netif_info(efx, probe, efx->net_dev,
945 "using locally-generated MAC %pM\n",
946 efx->net_dev->dev_addr);
947 }
948
949 return 0;
950
951 err:
952 efx->type->remove_port(efx);
953 return rc;
954}
955
956static int efx_init_port(struct efx_nic *efx)
957{
958 int rc;
959
960 netif_dbg(efx, drv, efx->net_dev, "init port\n");
961
962 mutex_lock(&efx->mac_lock);
963
964 rc = efx->phy_op->init(efx);
965 if (rc)
966 goto fail1;
967
968 efx->port_initialized = true;
969
970 /* Reconfigure the MAC before creating dma queues (required for
971 * Falcon/A1 where RX_INGR_EN/TX_DRAIN_EN isn't supported) */
972 efx->mac_op->reconfigure(efx);
973
974 /* Ensure the PHY advertises the correct flow control settings */
975 rc = efx->phy_op->reconfigure(efx);
976 if (rc)
977 goto fail2;
978
979 mutex_unlock(&efx->mac_lock);
980 return 0;
981
982fail2:
983 efx->phy_op->fini(efx);
984fail1:
985 mutex_unlock(&efx->mac_lock);
986 return rc;
987}
988
989static void efx_start_port(struct efx_nic *efx)
990{
991 netif_dbg(efx, ifup, efx->net_dev, "start port\n");
992 BUG_ON(efx->port_enabled);
993
994 mutex_lock(&efx->mac_lock);
995 efx->port_enabled = true;
996
997 /* efx_mac_work() might have been scheduled after efx_stop_port(),
998 * and then cancelled by efx_flush_all() */
999 efx->type->push_multicast_hash(efx);
1000 efx->mac_op->reconfigure(efx);
1001
1002 mutex_unlock(&efx->mac_lock);
1003}
1004
1005/* Prevent efx_mac_work() and efx_monitor() from working */
1006static void efx_stop_port(struct efx_nic *efx)
1007{
1008 netif_dbg(efx, ifdown, efx->net_dev, "stop port\n");
1009
1010 mutex_lock(&efx->mac_lock);
1011 efx->port_enabled = false;
1012 mutex_unlock(&efx->mac_lock);
1013
1014 /* Serialise against efx_set_multicast_list() */
1015 if (efx_dev_registered(efx)) {
1016 netif_addr_lock_bh(efx->net_dev);
1017 netif_addr_unlock_bh(efx->net_dev);
1018 }
1019}
1020
1021static void efx_fini_port(struct efx_nic *efx)
1022{
1023 netif_dbg(efx, drv, efx->net_dev, "shut down port\n");
1024
1025 if (!efx->port_initialized)
1026 return;
1027
1028 efx->phy_op->fini(efx);
1029 efx->port_initialized = false;
1030
1031 efx->link_state.up = false;
1032 efx_link_status_changed(efx);
1033}
1034
1035static void efx_remove_port(struct efx_nic *efx)
1036{
1037 netif_dbg(efx, drv, efx->net_dev, "destroying port\n");
1038
1039 efx->type->remove_port(efx);
1040}
1041
1042/**************************************************************************
1043 *
1044 * NIC handling
1045 *
1046 **************************************************************************/
1047
1048/* This configures the PCI device to enable I/O and DMA. */
1049static int efx_init_io(struct efx_nic *efx)
1050{
1051 struct pci_dev *pci_dev = efx->pci_dev;
1052 dma_addr_t dma_mask = efx->type->max_dma_mask;
1053 int rc;
1054
1055 netif_dbg(efx, probe, efx->net_dev, "initialising I/O\n");
1056
1057 rc = pci_enable_device(pci_dev);
1058 if (rc) {
1059 netif_err(efx, probe, efx->net_dev,
1060 "failed to enable PCI device\n");
1061 goto fail1;
1062 }
1063
1064 pci_set_master(pci_dev);
1065
1066 /* Set the PCI DMA mask. Try all possibilities from our
1067 * genuine mask down to 32 bits, because some architectures
1068 * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit
1069 * masks event though they reject 46 bit masks.
1070 */
1071 while (dma_mask > 0x7fffffffUL) {
1072 if (pci_dma_supported(pci_dev, dma_mask) &&
1073 ((rc = pci_set_dma_mask(pci_dev, dma_mask)) == 0))
1074 break;
1075 dma_mask >>= 1;
1076 }
1077 if (rc) {
1078 netif_err(efx, probe, efx->net_dev,
1079 "could not find a suitable DMA mask\n");
1080 goto fail2;
1081 }
1082 netif_dbg(efx, probe, efx->net_dev,
1083 "using DMA mask %llx\n", (unsigned long long) dma_mask);
1084 rc = pci_set_consistent_dma_mask(pci_dev, dma_mask);
1085 if (rc) {
1086 /* pci_set_consistent_dma_mask() is not *allowed* to
1087 * fail with a mask that pci_set_dma_mask() accepted,
1088 * but just in case...
1089 */
1090 netif_err(efx, probe, efx->net_dev,
1091 "failed to set consistent DMA mask\n");
1092 goto fail2;
1093 }
1094
1095 efx->membase_phys = pci_resource_start(efx->pci_dev, EFX_MEM_BAR);
1096 rc = pci_request_region(pci_dev, EFX_MEM_BAR, "sfc");
1097 if (rc) {
1098 netif_err(efx, probe, efx->net_dev,
1099 "request for memory BAR failed\n");
1100 rc = -EIO;
1101 goto fail3;
1102 }
1103 efx->membase = ioremap_nocache(efx->membase_phys,
1104 efx->type->mem_map_size);
1105 if (!efx->membase) {
1106 netif_err(efx, probe, efx->net_dev,
1107 "could not map memory BAR at %llx+%x\n",
1108 (unsigned long long)efx->membase_phys,
1109 efx->type->mem_map_size);
1110 rc = -ENOMEM;
1111 goto fail4;
1112 }
1113 netif_dbg(efx, probe, efx->net_dev,
1114 "memory BAR at %llx+%x (virtual %p)\n",
1115 (unsigned long long)efx->membase_phys,
1116 efx->type->mem_map_size, efx->membase);
1117
1118 return 0;
1119
1120 fail4:
1121 pci_release_region(efx->pci_dev, EFX_MEM_BAR);
1122 fail3:
1123 efx->membase_phys = 0;
1124 fail2:
1125 pci_disable_device(efx->pci_dev);
1126 fail1:
1127 return rc;
1128}
1129
1130static void efx_fini_io(struct efx_nic *efx)
1131{
1132 netif_dbg(efx, drv, efx->net_dev, "shutting down I/O\n");
1133
1134 if (efx->membase) {
1135 iounmap(efx->membase);
1136 efx->membase = NULL;
1137 }
1138
1139 if (efx->membase_phys) {
1140 pci_release_region(efx->pci_dev, EFX_MEM_BAR);
1141 efx->membase_phys = 0;
1142 }
1143
1144 pci_disable_device(efx->pci_dev);
1145}
1146
1147/* Get number of channels wanted. Each channel will have its own IRQ,
1148 * 1 RX queue and/or 2 TX queues. */
1149static int efx_wanted_channels(void)
1150{
1151 cpumask_var_t core_mask;
1152 int count;
1153 int cpu;
1154
1155 if (rss_cpus)
1156 return rss_cpus;
1157
1158 if (unlikely(!zalloc_cpumask_var(&core_mask, GFP_KERNEL))) {
1159 printk(KERN_WARNING
1160 "sfc: RSS disabled due to allocation failure\n");
1161 return 1;
1162 }
1163
1164 count = 0;
1165 for_each_online_cpu(cpu) {
1166 if (!cpumask_test_cpu(cpu, core_mask)) {
1167 ++count;
1168 cpumask_or(core_mask, core_mask,
1169 topology_core_cpumask(cpu));
1170 }
1171 }
1172
1173 free_cpumask_var(core_mask);
1174 return count;
1175}
1176
1177static int
1178efx_init_rx_cpu_rmap(struct efx_nic *efx, struct msix_entry *xentries)
1179{
1180#ifdef CONFIG_RFS_ACCEL
1181 int i, rc;
1182
1183 efx->net_dev->rx_cpu_rmap = alloc_irq_cpu_rmap(efx->n_rx_channels);
1184 if (!efx->net_dev->rx_cpu_rmap)
1185 return -ENOMEM;
1186 for (i = 0; i < efx->n_rx_channels; i++) {
1187 rc = irq_cpu_rmap_add(efx->net_dev->rx_cpu_rmap,
1188 xentries[i].vector);
1189 if (rc) {
1190 free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap);
1191 efx->net_dev->rx_cpu_rmap = NULL;
1192 return rc;
1193 }
1194 }
1195#endif
1196 return 0;
1197}
1198
1199/* Probe the number and type of interrupts we are able to obtain, and
1200 * the resulting numbers of channels and RX queues.
1201 */
1202static int efx_probe_interrupts(struct efx_nic *efx)
1203{
1204 int max_channels =
1205 min_t(int, efx->type->phys_addr_channels, EFX_MAX_CHANNELS);
1206 int rc, i;
1207
1208 if (efx->interrupt_mode == EFX_INT_MODE_MSIX) {
1209 struct msix_entry xentries[EFX_MAX_CHANNELS];
1210 int n_channels;
1211
1212 n_channels = efx_wanted_channels();
1213 if (separate_tx_channels)
1214 n_channels *= 2;
1215 n_channels = min(n_channels, max_channels);
1216
1217 for (i = 0; i < n_channels; i++)
1218 xentries[i].entry = i;
1219 rc = pci_enable_msix(efx->pci_dev, xentries, n_channels);
1220 if (rc > 0) {
1221 netif_err(efx, drv, efx->net_dev,
1222 "WARNING: Insufficient MSI-X vectors"
1223 " available (%d < %d).\n", rc, n_channels);
1224 netif_err(efx, drv, efx->net_dev,
1225 "WARNING: Performance may be reduced.\n");
1226 EFX_BUG_ON_PARANOID(rc >= n_channels);
1227 n_channels = rc;
1228 rc = pci_enable_msix(efx->pci_dev, xentries,
1229 n_channels);
1230 }
1231
1232 if (rc == 0) {
1233 efx->n_channels = n_channels;
1234 if (separate_tx_channels) {
1235 efx->n_tx_channels =
1236 max(efx->n_channels / 2, 1U);
1237 efx->n_rx_channels =
1238 max(efx->n_channels -
1239 efx->n_tx_channels, 1U);
1240 } else {
1241 efx->n_tx_channels = efx->n_channels;
1242 efx->n_rx_channels = efx->n_channels;
1243 }
1244 rc = efx_init_rx_cpu_rmap(efx, xentries);
1245 if (rc) {
1246 pci_disable_msix(efx->pci_dev);
1247 return rc;
1248 }
1249 for (i = 0; i < n_channels; i++)
1250 efx_get_channel(efx, i)->irq =
1251 xentries[i].vector;
1252 } else {
1253 /* Fall back to single channel MSI */
1254 efx->interrupt_mode = EFX_INT_MODE_MSI;
1255 netif_err(efx, drv, efx->net_dev,
1256 "could not enable MSI-X\n");
1257 }
1258 }
1259
1260 /* Try single interrupt MSI */
1261 if (efx->interrupt_mode == EFX_INT_MODE_MSI) {
1262 efx->n_channels = 1;
1263 efx->n_rx_channels = 1;
1264 efx->n_tx_channels = 1;
1265 rc = pci_enable_msi(efx->pci_dev);
1266 if (rc == 0) {
1267 efx_get_channel(efx, 0)->irq = efx->pci_dev->irq;
1268 } else {
1269 netif_err(efx, drv, efx->net_dev,
1270 "could not enable MSI\n");
1271 efx->interrupt_mode = EFX_INT_MODE_LEGACY;
1272 }
1273 }
1274
1275 /* Assume legacy interrupts */
1276 if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) {
1277 efx->n_channels = 1 + (separate_tx_channels ? 1 : 0);
1278 efx->n_rx_channels = 1;
1279 efx->n_tx_channels = 1;
1280 efx->legacy_irq = efx->pci_dev->irq;
1281 }
1282
1283 return 0;
1284}
1285
1286static void efx_remove_interrupts(struct efx_nic *efx)
1287{
1288 struct efx_channel *channel;
1289
1290 /* Remove MSI/MSI-X interrupts */
1291 efx_for_each_channel(channel, efx)
1292 channel->irq = 0;
1293 pci_disable_msi(efx->pci_dev);
1294 pci_disable_msix(efx->pci_dev);
1295
1296 /* Remove legacy interrupt */
1297 efx->legacy_irq = 0;
1298}
1299
1300static void efx_set_channels(struct efx_nic *efx)
1301{
1302 struct efx_channel *channel;
1303 struct efx_tx_queue *tx_queue;
1304
1305 efx->tx_channel_offset =
1306 separate_tx_channels ? efx->n_channels - efx->n_tx_channels : 0;
1307
1308 /* We need to adjust the TX queue numbers if we have separate
1309 * RX-only and TX-only channels.
1310 */
1311 efx_for_each_channel(channel, efx) {
1312 efx_for_each_channel_tx_queue(tx_queue, channel)
1313 tx_queue->queue -= (efx->tx_channel_offset *
1314 EFX_TXQ_TYPES);
1315 }
1316}
1317
1318static int efx_probe_nic(struct efx_nic *efx)
1319{
1320 size_t i;
1321 int rc;
1322
1323 netif_dbg(efx, probe, efx->net_dev, "creating NIC\n");
1324
1325 /* Carry out hardware-type specific initialisation */
1326 rc = efx->type->probe(efx);
1327 if (rc)
1328 return rc;
1329
1330 /* Determine the number of channels and queues by trying to hook
1331 * in MSI-X interrupts. */
1332 rc = efx_probe_interrupts(efx);
1333 if (rc)
1334 goto fail;
1335
1336 if (efx->n_channels > 1)
1337 get_random_bytes(&efx->rx_hash_key, sizeof(efx->rx_hash_key));
1338 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); i++)
1339 efx->rx_indir_table[i] = i % efx->n_rx_channels;
1340
1341 efx_set_channels(efx);
1342 netif_set_real_num_tx_queues(efx->net_dev, efx->n_tx_channels);
1343 netif_set_real_num_rx_queues(efx->net_dev, efx->n_rx_channels);
1344
1345 /* Initialise the interrupt moderation settings */
1346 efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec, true);
1347
1348 return 0;
1349
1350fail:
1351 efx->type->remove(efx);
1352 return rc;
1353}
1354
1355static void efx_remove_nic(struct efx_nic *efx)
1356{
1357 netif_dbg(efx, drv, efx->net_dev, "destroying NIC\n");
1358
1359 efx_remove_interrupts(efx);
1360 efx->type->remove(efx);
1361}
1362
1363/**************************************************************************
1364 *
1365 * NIC startup/shutdown
1366 *
1367 *************************************************************************/
1368
1369static int efx_probe_all(struct efx_nic *efx)
1370{
1371 int rc;
1372
1373 rc = efx_probe_nic(efx);
1374 if (rc) {
1375 netif_err(efx, probe, efx->net_dev, "failed to create NIC\n");
1376 goto fail1;
1377 }
1378
1379 rc = efx_probe_port(efx);
1380 if (rc) {
1381 netif_err(efx, probe, efx->net_dev, "failed to create port\n");
1382 goto fail2;
1383 }
1384
1385 efx->rxq_entries = efx->txq_entries = EFX_DEFAULT_DMAQ_SIZE;
1386 rc = efx_probe_channels(efx);
1387 if (rc)
1388 goto fail3;
1389
1390 rc = efx_probe_filters(efx);
1391 if (rc) {
1392 netif_err(efx, probe, efx->net_dev,
1393 "failed to create filter tables\n");
1394 goto fail4;
1395 }
1396
1397 return 0;
1398
1399 fail4:
1400 efx_remove_channels(efx);
1401 fail3:
1402 efx_remove_port(efx);
1403 fail2:
1404 efx_remove_nic(efx);
1405 fail1:
1406 return rc;
1407}
1408
1409/* Called after previous invocation(s) of efx_stop_all, restarts the
1410 * port, kernel transmit queue, NAPI processing and hardware interrupts,
1411 * and ensures that the port is scheduled to be reconfigured.
1412 * This function is safe to call multiple times when the NIC is in any
1413 * state. */
1414static void efx_start_all(struct efx_nic *efx)
1415{
1416 struct efx_channel *channel;
1417
1418 EFX_ASSERT_RESET_SERIALISED(efx);
1419
1420 /* Check that it is appropriate to restart the interface. All
1421 * of these flags are safe to read under just the rtnl lock */
1422 if (efx->port_enabled)
1423 return;
1424 if ((efx->state != STATE_RUNNING) && (efx->state != STATE_INIT))
1425 return;
1426 if (efx_dev_registered(efx) && !netif_running(efx->net_dev))
1427 return;
1428
1429 /* Mark the port as enabled so port reconfigurations can start, then
1430 * restart the transmit interface early so the watchdog timer stops */
1431 efx_start_port(efx);
1432
1433 if (efx_dev_registered(efx) && netif_device_present(efx->net_dev))
1434 netif_tx_wake_all_queues(efx->net_dev);
1435
1436 efx_for_each_channel(channel, efx)
1437 efx_start_channel(channel);
1438
1439 if (efx->legacy_irq)
1440 efx->legacy_irq_enabled = true;
1441 efx_nic_enable_interrupts(efx);
1442
1443 /* Switch to event based MCDI completions after enabling interrupts.
1444 * If a reset has been scheduled, then we need to stay in polled mode.
1445 * Rather than serialising efx_mcdi_mode_event() [which sleeps] and
1446 * reset_pending [modified from an atomic context], we instead guarantee
1447 * that efx_mcdi_mode_poll() isn't reverted erroneously */
1448 efx_mcdi_mode_event(efx);
1449 if (efx->reset_pending)
1450 efx_mcdi_mode_poll(efx);
1451
1452 /* Start the hardware monitor if there is one. Otherwise (we're link
1453 * event driven), we have to poll the PHY because after an event queue
1454 * flush, we could have a missed a link state change */
1455 if (efx->type->monitor != NULL) {
1456 queue_delayed_work(efx->workqueue, &efx->monitor_work,
1457 efx_monitor_interval);
1458 } else {
1459 mutex_lock(&efx->mac_lock);
1460 if (efx->phy_op->poll(efx))
1461 efx_link_status_changed(efx);
1462 mutex_unlock(&efx->mac_lock);
1463 }
1464
1465 efx->type->start_stats(efx);
1466}
1467
1468/* Flush all delayed work. Should only be called when no more delayed work
1469 * will be scheduled. This doesn't flush pending online resets (efx_reset),
1470 * since we're holding the rtnl_lock at this point. */
1471static void efx_flush_all(struct efx_nic *efx)
1472{
1473 /* Make sure the hardware monitor is stopped */
1474 cancel_delayed_work_sync(&efx->monitor_work);
1475 /* Stop scheduled port reconfigurations */
1476 cancel_work_sync(&efx->mac_work);
1477}
1478
1479/* Quiesce hardware and software without bringing the link down.
1480 * Safe to call multiple times, when the nic and interface is in any
1481 * state. The caller is guaranteed to subsequently be in a position
1482 * to modify any hardware and software state they see fit without
1483 * taking locks. */
1484static void efx_stop_all(struct efx_nic *efx)
1485{
1486 struct efx_channel *channel;
1487
1488 EFX_ASSERT_RESET_SERIALISED(efx);
1489
1490 /* port_enabled can be read safely under the rtnl lock */
1491 if (!efx->port_enabled)
1492 return;
1493
1494 efx->type->stop_stats(efx);
1495
1496 /* Switch to MCDI polling on Siena before disabling interrupts */
1497 efx_mcdi_mode_poll(efx);
1498
1499 /* Disable interrupts and wait for ISR to complete */
1500 efx_nic_disable_interrupts(efx);
1501 if (efx->legacy_irq) {
1502 synchronize_irq(efx->legacy_irq);
1503 efx->legacy_irq_enabled = false;
1504 }
1505 efx_for_each_channel(channel, efx) {
1506 if (channel->irq)
1507 synchronize_irq(channel->irq);
1508 }
1509
1510 /* Stop all NAPI processing and synchronous rx refills */
1511 efx_for_each_channel(channel, efx)
1512 efx_stop_channel(channel);
1513
1514 /* Stop all asynchronous port reconfigurations. Since all
1515 * event processing has already been stopped, there is no
1516 * window to loose phy events */
1517 efx_stop_port(efx);
1518
1519 /* Flush efx_mac_work(), refill_workqueue, monitor_work */
1520 efx_flush_all(efx);
1521
1522 /* Stop the kernel transmit interface late, so the watchdog
1523 * timer isn't ticking over the flush */
1524 if (efx_dev_registered(efx)) {
1525 netif_tx_stop_all_queues(efx->net_dev);
1526 netif_tx_lock_bh(efx->net_dev);
1527 netif_tx_unlock_bh(efx->net_dev);
1528 }
1529}
1530
1531static void efx_remove_all(struct efx_nic *efx)
1532{
1533 efx_remove_filters(efx);
1534 efx_remove_channels(efx);
1535 efx_remove_port(efx);
1536 efx_remove_nic(efx);
1537}
1538
1539/**************************************************************************
1540 *
1541 * Interrupt moderation
1542 *
1543 **************************************************************************/
1544
1545static unsigned irq_mod_ticks(int usecs, int resolution)
1546{
1547 if (usecs <= 0)
1548 return 0; /* cannot receive interrupts ahead of time :-) */
1549 if (usecs < resolution)
1550 return 1; /* never round down to 0 */
1551 return usecs / resolution;
1552}
1553
1554/* Set interrupt moderation parameters */
1555void efx_init_irq_moderation(struct efx_nic *efx, int tx_usecs, int rx_usecs,
1556 bool rx_adaptive)
1557{
1558 struct efx_channel *channel;
1559 unsigned tx_ticks = irq_mod_ticks(tx_usecs, EFX_IRQ_MOD_RESOLUTION);
1560 unsigned rx_ticks = irq_mod_ticks(rx_usecs, EFX_IRQ_MOD_RESOLUTION);
1561
1562 EFX_ASSERT_RESET_SERIALISED(efx);
1563
1564 efx->irq_rx_adaptive = rx_adaptive;
1565 efx->irq_rx_moderation = rx_ticks;
1566 efx_for_each_channel(channel, efx) {
1567 if (efx_channel_has_rx_queue(channel))
1568 channel->irq_moderation = rx_ticks;
1569 else if (efx_channel_has_tx_queues(channel))
1570 channel->irq_moderation = tx_ticks;
1571 }
1572}
1573
1574/**************************************************************************
1575 *
1576 * Hardware monitor
1577 *
1578 **************************************************************************/
1579
1580/* Run periodically off the general workqueue */
1581static void efx_monitor(struct work_struct *data)
1582{
1583 struct efx_nic *efx = container_of(data, struct efx_nic,
1584 monitor_work.work);
1585
1586 netif_vdbg(efx, timer, efx->net_dev,
1587 "hardware monitor executing on CPU %d\n",
1588 raw_smp_processor_id());
1589 BUG_ON(efx->type->monitor == NULL);
1590
1591 /* If the mac_lock is already held then it is likely a port
1592 * reconfiguration is already in place, which will likely do
1593 * most of the work of monitor() anyway. */
1594 if (mutex_trylock(&efx->mac_lock)) {
1595 if (efx->port_enabled)
1596 efx->type->monitor(efx);
1597 mutex_unlock(&efx->mac_lock);
1598 }
1599
1600 queue_delayed_work(efx->workqueue, &efx->monitor_work,
1601 efx_monitor_interval);
1602}
1603
1604/**************************************************************************
1605 *
1606 * ioctls
1607 *
1608 *************************************************************************/
1609
1610/* Net device ioctl
1611 * Context: process, rtnl_lock() held.
1612 */
1613static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd)
1614{
1615 struct efx_nic *efx = netdev_priv(net_dev);
1616 struct mii_ioctl_data *data = if_mii(ifr);
1617
1618 EFX_ASSERT_RESET_SERIALISED(efx);
1619
1620 /* Convert phy_id from older PRTAD/DEVAD format */
1621 if ((cmd == SIOCGMIIREG || cmd == SIOCSMIIREG) &&
1622 (data->phy_id & 0xfc00) == 0x0400)
1623 data->phy_id ^= MDIO_PHY_ID_C45 | 0x0400;
1624
1625 return mdio_mii_ioctl(&efx->mdio, data, cmd);
1626}
1627
1628/**************************************************************************
1629 *
1630 * NAPI interface
1631 *
1632 **************************************************************************/
1633
1634static void efx_init_napi(struct efx_nic *efx)
1635{
1636 struct efx_channel *channel;
1637
1638 efx_for_each_channel(channel, efx) {
1639 channel->napi_dev = efx->net_dev;
1640 netif_napi_add(channel->napi_dev, &channel->napi_str,
1641 efx_poll, napi_weight);
1642 }
1643}
1644
1645static void efx_fini_napi_channel(struct efx_channel *channel)
1646{
1647 if (channel->napi_dev)
1648 netif_napi_del(&channel->napi_str);
1649 channel->napi_dev = NULL;
1650}
1651
1652static void efx_fini_napi(struct efx_nic *efx)
1653{
1654 struct efx_channel *channel;
1655
1656 efx_for_each_channel(channel, efx)
1657 efx_fini_napi_channel(channel);
1658}
1659
1660/**************************************************************************
1661 *
1662 * Kernel netpoll interface
1663 *
1664 *************************************************************************/
1665
1666#ifdef CONFIG_NET_POLL_CONTROLLER
1667
1668/* Although in the common case interrupts will be disabled, this is not
1669 * guaranteed. However, all our work happens inside the NAPI callback,
1670 * so no locking is required.
1671 */
1672static void efx_netpoll(struct net_device *net_dev)
1673{
1674 struct efx_nic *efx = netdev_priv(net_dev);
1675 struct efx_channel *channel;
1676
1677 efx_for_each_channel(channel, efx)
1678 efx_schedule_channel(channel);
1679}
1680
1681#endif
1682
1683/**************************************************************************
1684 *
1685 * Kernel net device interface
1686 *
1687 *************************************************************************/
1688
1689/* Context: process, rtnl_lock() held. */
1690static int efx_net_open(struct net_device *net_dev)
1691{
1692 struct efx_nic *efx = netdev_priv(net_dev);
1693 EFX_ASSERT_RESET_SERIALISED(efx);
1694
1695 netif_dbg(efx, ifup, efx->net_dev, "opening device on CPU %d\n",
1696 raw_smp_processor_id());
1697
1698 if (efx->state == STATE_DISABLED)
1699 return -EIO;
1700 if (efx->phy_mode & PHY_MODE_SPECIAL)
1701 return -EBUSY;
1702 if (efx_mcdi_poll_reboot(efx) && efx_reset(efx, RESET_TYPE_ALL))
1703 return -EIO;
1704
1705 /* Notify the kernel of the link state polled during driver load,
1706 * before the monitor starts running */
1707 efx_link_status_changed(efx);
1708
1709 efx_start_all(efx);
1710 return 0;
1711}
1712
1713/* Context: process, rtnl_lock() held.
1714 * Note that the kernel will ignore our return code; this method
1715 * should really be a void.
1716 */
1717static int efx_net_stop(struct net_device *net_dev)
1718{
1719 struct efx_nic *efx = netdev_priv(net_dev);
1720
1721 netif_dbg(efx, ifdown, efx->net_dev, "closing on CPU %d\n",
1722 raw_smp_processor_id());
1723
1724 if (efx->state != STATE_DISABLED) {
1725 /* Stop the device and flush all the channels */
1726 efx_stop_all(efx);
1727 efx_fini_channels(efx);
1728 efx_init_channels(efx);
1729 }
1730
1731 return 0;
1732}
1733
1734/* Context: process, dev_base_lock or RTNL held, non-blocking. */
1735static struct rtnl_link_stats64 *efx_net_stats(struct net_device *net_dev, struct rtnl_link_stats64 *stats)
1736{
1737 struct efx_nic *efx = netdev_priv(net_dev);
1738 struct efx_mac_stats *mac_stats = &efx->mac_stats;
1739
1740 spin_lock_bh(&efx->stats_lock);
1741 efx->type->update_stats(efx);
1742 spin_unlock_bh(&efx->stats_lock);
1743
1744 stats->rx_packets = mac_stats->rx_packets;
1745 stats->tx_packets = mac_stats->tx_packets;
1746 stats->rx_bytes = mac_stats->rx_bytes;
1747 stats->tx_bytes = mac_stats->tx_bytes;
1748 stats->rx_dropped = efx->n_rx_nodesc_drop_cnt;
1749 stats->multicast = mac_stats->rx_multicast;
1750 stats->collisions = mac_stats->tx_collision;
1751 stats->rx_length_errors = (mac_stats->rx_gtjumbo +
1752 mac_stats->rx_length_error);
1753 stats->rx_crc_errors = mac_stats->rx_bad;
1754 stats->rx_frame_errors = mac_stats->rx_align_error;
1755 stats->rx_fifo_errors = mac_stats->rx_overflow;
1756 stats->rx_missed_errors = mac_stats->rx_missed;
1757 stats->tx_window_errors = mac_stats->tx_late_collision;
1758
1759 stats->rx_errors = (stats->rx_length_errors +
1760 stats->rx_crc_errors +
1761 stats->rx_frame_errors +
1762 mac_stats->rx_symbol_error);
1763 stats->tx_errors = (stats->tx_window_errors +
1764 mac_stats->tx_bad);
1765
1766 return stats;
1767}
1768
1769/* Context: netif_tx_lock held, BHs disabled. */
1770static void efx_watchdog(struct net_device *net_dev)
1771{
1772 struct efx_nic *efx = netdev_priv(net_dev);
1773
1774 netif_err(efx, tx_err, efx->net_dev,
1775 "TX stuck with port_enabled=%d: resetting channels\n",
1776 efx->port_enabled);
1777
1778 efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG);
1779}
1780
1781
1782/* Context: process, rtnl_lock() held. */
1783static int efx_change_mtu(struct net_device *net_dev, int new_mtu)
1784{
1785 struct efx_nic *efx = netdev_priv(net_dev);
1786 int rc = 0;
1787
1788 EFX_ASSERT_RESET_SERIALISED(efx);
1789
1790 if (new_mtu > EFX_MAX_MTU)
1791 return -EINVAL;
1792
1793 efx_stop_all(efx);
1794
1795 netif_dbg(efx, drv, efx->net_dev, "changing MTU to %d\n", new_mtu);
1796
1797 efx_fini_channels(efx);
1798
1799 mutex_lock(&efx->mac_lock);
1800 /* Reconfigure the MAC before enabling the dma queues so that
1801 * the RX buffers don't overflow */
1802 net_dev->mtu = new_mtu;
1803 efx->mac_op->reconfigure(efx);
1804 mutex_unlock(&efx->mac_lock);
1805
1806 efx_init_channels(efx);
1807
1808 efx_start_all(efx);
1809 return rc;
1810}
1811
1812static int efx_set_mac_address(struct net_device *net_dev, void *data)
1813{
1814 struct efx_nic *efx = netdev_priv(net_dev);
1815 struct sockaddr *addr = data;
1816 char *new_addr = addr->sa_data;
1817
1818 EFX_ASSERT_RESET_SERIALISED(efx);
1819
1820 if (!is_valid_ether_addr(new_addr)) {
1821 netif_err(efx, drv, efx->net_dev,
1822 "invalid ethernet MAC address requested: %pM\n",
1823 new_addr);
1824 return -EINVAL;
1825 }
1826
1827 memcpy(net_dev->dev_addr, new_addr, net_dev->addr_len);
1828
1829 /* Reconfigure the MAC */
1830 mutex_lock(&efx->mac_lock);
1831 efx->mac_op->reconfigure(efx);
1832 mutex_unlock(&efx->mac_lock);
1833
1834 return 0;
1835}
1836
1837/* Context: netif_addr_lock held, BHs disabled. */
1838static void efx_set_multicast_list(struct net_device *net_dev)
1839{
1840 struct efx_nic *efx = netdev_priv(net_dev);
1841 struct netdev_hw_addr *ha;
1842 union efx_multicast_hash *mc_hash = &efx->multicast_hash;
1843 u32 crc;
1844 int bit;
1845
1846 efx->promiscuous = !!(net_dev->flags & IFF_PROMISC);
1847
1848 /* Build multicast hash table */
1849 if (efx->promiscuous || (net_dev->flags & IFF_ALLMULTI)) {
1850 memset(mc_hash, 0xff, sizeof(*mc_hash));
1851 } else {
1852 memset(mc_hash, 0x00, sizeof(*mc_hash));
1853 netdev_for_each_mc_addr(ha, net_dev) {
1854 crc = ether_crc_le(ETH_ALEN, ha->addr);
1855 bit = crc & (EFX_MCAST_HASH_ENTRIES - 1);
1856 set_bit_le(bit, mc_hash->byte);
1857 }
1858
1859 /* Broadcast packets go through the multicast hash filter.
1860 * ether_crc_le() of the broadcast address is 0xbe2612ff
1861 * so we always add bit 0xff to the mask.
1862 */
1863 set_bit_le(0xff, mc_hash->byte);
1864 }
1865
1866 if (efx->port_enabled)
1867 queue_work(efx->workqueue, &efx->mac_work);
1868 /* Otherwise efx_start_port() will do this */
1869}
1870
1871static int efx_set_features(struct net_device *net_dev, u32 data)
1872{
1873 struct efx_nic *efx = netdev_priv(net_dev);
1874
1875 /* If disabling RX n-tuple filtering, clear existing filters */
1876 if (net_dev->features & ~data & NETIF_F_NTUPLE)
1877 efx_filter_clear_rx(efx, EFX_FILTER_PRI_MANUAL);
1878
1879 return 0;
1880}
1881
1882static const struct net_device_ops efx_netdev_ops = {
1883 .ndo_open = efx_net_open,
1884 .ndo_stop = efx_net_stop,
1885 .ndo_get_stats64 = efx_net_stats,
1886 .ndo_tx_timeout = efx_watchdog,
1887 .ndo_start_xmit = efx_hard_start_xmit,
1888 .ndo_validate_addr = eth_validate_addr,
1889 .ndo_do_ioctl = efx_ioctl,
1890 .ndo_change_mtu = efx_change_mtu,
1891 .ndo_set_mac_address = efx_set_mac_address,
1892 .ndo_set_multicast_list = efx_set_multicast_list,
1893 .ndo_set_features = efx_set_features,
1894#ifdef CONFIG_NET_POLL_CONTROLLER
1895 .ndo_poll_controller = efx_netpoll,
1896#endif
1897 .ndo_setup_tc = efx_setup_tc,
1898#ifdef CONFIG_RFS_ACCEL
1899 .ndo_rx_flow_steer = efx_filter_rfs,
1900#endif
1901};
1902
1903static void efx_update_name(struct efx_nic *efx)
1904{
1905 strcpy(efx->name, efx->net_dev->name);
1906 efx_mtd_rename(efx);
1907 efx_set_channel_names(efx);
1908}
1909
1910static int efx_netdev_event(struct notifier_block *this,
1911 unsigned long event, void *ptr)
1912{
1913 struct net_device *net_dev = ptr;
1914
1915 if (net_dev->netdev_ops == &efx_netdev_ops &&
1916 event == NETDEV_CHANGENAME)
1917 efx_update_name(netdev_priv(net_dev));
1918
1919 return NOTIFY_DONE;
1920}
1921
1922static struct notifier_block efx_netdev_notifier = {
1923 .notifier_call = efx_netdev_event,
1924};
1925
1926static ssize_t
1927show_phy_type(struct device *dev, struct device_attribute *attr, char *buf)
1928{
1929 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
1930 return sprintf(buf, "%d\n", efx->phy_type);
1931}
1932static DEVICE_ATTR(phy_type, 0644, show_phy_type, NULL);
1933
1934static int efx_register_netdev(struct efx_nic *efx)
1935{
1936 struct net_device *net_dev = efx->net_dev;
1937 struct efx_channel *channel;
1938 int rc;
1939
1940 net_dev->watchdog_timeo = 5 * HZ;
1941 net_dev->irq = efx->pci_dev->irq;
1942 net_dev->netdev_ops = &efx_netdev_ops;
1943 SET_ETHTOOL_OPS(net_dev, &efx_ethtool_ops);
1944
1945 /* Clear MAC statistics */
1946 efx->mac_op->update_stats(efx);
1947 memset(&efx->mac_stats, 0, sizeof(efx->mac_stats));
1948
1949 rtnl_lock();
1950
1951 rc = dev_alloc_name(net_dev, net_dev->name);
1952 if (rc < 0)
1953 goto fail_locked;
1954 efx_update_name(efx);
1955
1956 rc = register_netdevice(net_dev);
1957 if (rc)
1958 goto fail_locked;
1959
1960 efx_for_each_channel(channel, efx) {
1961 struct efx_tx_queue *tx_queue;
1962 efx_for_each_channel_tx_queue(tx_queue, channel)
1963 efx_init_tx_queue_core_txq(tx_queue);
1964 }
1965
1966 /* Always start with carrier off; PHY events will detect the link */
1967 netif_carrier_off(efx->net_dev);
1968
1969 rtnl_unlock();
1970
1971 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_type);
1972 if (rc) {
1973 netif_err(efx, drv, efx->net_dev,
1974 "failed to init net dev attributes\n");
1975 goto fail_registered;
1976 }
1977
1978 return 0;
1979
1980fail_locked:
1981 rtnl_unlock();
1982 netif_err(efx, drv, efx->net_dev, "could not register net dev\n");
1983 return rc;
1984
1985fail_registered:
1986 unregister_netdev(net_dev);
1987 return rc;
1988}
1989
1990static void efx_unregister_netdev(struct efx_nic *efx)
1991{
1992 struct efx_channel *channel;
1993 struct efx_tx_queue *tx_queue;
1994
1995 if (!efx->net_dev)
1996 return;
1997
1998 BUG_ON(netdev_priv(efx->net_dev) != efx);
1999
2000 /* Free up any skbs still remaining. This has to happen before
2001 * we try to unregister the netdev as running their destructors
2002 * may be needed to get the device ref. count to 0. */
2003 efx_for_each_channel(channel, efx) {
2004 efx_for_each_channel_tx_queue(tx_queue, channel)
2005 efx_release_tx_buffers(tx_queue);
2006 }
2007
2008 if (efx_dev_registered(efx)) {
2009 strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name));
2010 device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type);
2011 unregister_netdev(efx->net_dev);
2012 }
2013}
2014
2015/**************************************************************************
2016 *
2017 * Device reset and suspend
2018 *
2019 **************************************************************************/
2020
2021/* Tears down the entire software state and most of the hardware state
2022 * before reset. */
2023void efx_reset_down(struct efx_nic *efx, enum reset_type method)
2024{
2025 EFX_ASSERT_RESET_SERIALISED(efx);
2026
2027 efx_stop_all(efx);
2028 mutex_lock(&efx->mac_lock);
2029
2030 efx_fini_channels(efx);
2031 if (efx->port_initialized && method != RESET_TYPE_INVISIBLE)
2032 efx->phy_op->fini(efx);
2033 efx->type->fini(efx);
2034}
2035
2036/* This function will always ensure that the locks acquired in
2037 * efx_reset_down() are released. A failure return code indicates
2038 * that we were unable to reinitialise the hardware, and the
2039 * driver should be disabled. If ok is false, then the rx and tx
2040 * engines are not restarted, pending a RESET_DISABLE. */
2041int efx_reset_up(struct efx_nic *efx, enum reset_type method, bool ok)
2042{
2043 int rc;
2044
2045 EFX_ASSERT_RESET_SERIALISED(efx);
2046
2047 rc = efx->type->init(efx);
2048 if (rc) {
2049 netif_err(efx, drv, efx->net_dev, "failed to initialise NIC\n");
2050 goto fail;
2051 }
2052
2053 if (!ok)
2054 goto fail;
2055
2056 if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) {
2057 rc = efx->phy_op->init(efx);
2058 if (rc)
2059 goto fail;
2060 if (efx->phy_op->reconfigure(efx))
2061 netif_err(efx, drv, efx->net_dev,
2062 "could not restore PHY settings\n");
2063 }
2064
2065 efx->mac_op->reconfigure(efx);
2066
2067 efx_init_channels(efx);
2068 efx_restore_filters(efx);
2069
2070 mutex_unlock(&efx->mac_lock);
2071
2072 efx_start_all(efx);
2073
2074 return 0;
2075
2076fail:
2077 efx->port_initialized = false;
2078
2079 mutex_unlock(&efx->mac_lock);
2080
2081 return rc;
2082}
2083
2084/* Reset the NIC using the specified method. Note that the reset may
2085 * fail, in which case the card will be left in an unusable state.
2086 *
2087 * Caller must hold the rtnl_lock.
2088 */
2089int efx_reset(struct efx_nic *efx, enum reset_type method)
2090{
2091 int rc, rc2;
2092 bool disabled;
2093
2094 netif_info(efx, drv, efx->net_dev, "resetting (%s)\n",
2095 RESET_TYPE(method));
2096
2097 netif_device_detach(efx->net_dev);
2098 efx_reset_down(efx, method);
2099
2100 rc = efx->type->reset(efx, method);
2101 if (rc) {
2102 netif_err(efx, drv, efx->net_dev, "failed to reset hardware\n");
2103 goto out;
2104 }
2105
2106 /* Clear flags for the scopes we covered. We assume the NIC and
2107 * driver are now quiescent so that there is no race here.
2108 */
2109 efx->reset_pending &= -(1 << (method + 1));
2110
2111 /* Reinitialise bus-mastering, which may have been turned off before
2112 * the reset was scheduled. This is still appropriate, even in the
2113 * RESET_TYPE_DISABLE since this driver generally assumes the hardware
2114 * can respond to requests. */
2115 pci_set_master(efx->pci_dev);
2116
2117out:
2118 /* Leave device stopped if necessary */
2119 disabled = rc || method == RESET_TYPE_DISABLE;
2120 rc2 = efx_reset_up(efx, method, !disabled);
2121 if (rc2) {
2122 disabled = true;
2123 if (!rc)
2124 rc = rc2;
2125 }
2126
2127 if (disabled) {
2128 dev_close(efx->net_dev);
2129 netif_err(efx, drv, efx->net_dev, "has been disabled\n");
2130 efx->state = STATE_DISABLED;
2131 } else {
2132 netif_dbg(efx, drv, efx->net_dev, "reset complete\n");
2133 netif_device_attach(efx->net_dev);
2134 }
2135 return rc;
2136}
2137
2138/* The worker thread exists so that code that cannot sleep can
2139 * schedule a reset for later.
2140 */
2141static void efx_reset_work(struct work_struct *data)
2142{
2143 struct efx_nic *efx = container_of(data, struct efx_nic, reset_work);
2144 unsigned long pending = ACCESS_ONCE(efx->reset_pending);
2145
2146 if (!pending)
2147 return;
2148
2149 /* If we're not RUNNING then don't reset. Leave the reset_pending
2150 * flags set so that efx_pci_probe_main will be retried */
2151 if (efx->state != STATE_RUNNING) {
2152 netif_info(efx, drv, efx->net_dev,
2153 "scheduled reset quenched. NIC not RUNNING\n");
2154 return;
2155 }
2156
2157 rtnl_lock();
2158 (void)efx_reset(efx, fls(pending) - 1);
2159 rtnl_unlock();
2160}
2161
2162void efx_schedule_reset(struct efx_nic *efx, enum reset_type type)
2163{
2164 enum reset_type method;
2165
2166 switch (type) {
2167 case RESET_TYPE_INVISIBLE:
2168 case RESET_TYPE_ALL:
2169 case RESET_TYPE_WORLD:
2170 case RESET_TYPE_DISABLE:
2171 method = type;
2172 netif_dbg(efx, drv, efx->net_dev, "scheduling %s reset\n",
2173 RESET_TYPE(method));
2174 break;
2175 default:
2176 method = efx->type->map_reset_reason(type);
2177 netif_dbg(efx, drv, efx->net_dev,
2178 "scheduling %s reset for %s\n",
2179 RESET_TYPE(method), RESET_TYPE(type));
2180 break;
2181 }
2182
2183 set_bit(method, &efx->reset_pending);
2184
2185 /* efx_process_channel() will no longer read events once a
2186 * reset is scheduled. So switch back to poll'd MCDI completions. */
2187 efx_mcdi_mode_poll(efx);
2188
2189 queue_work(reset_workqueue, &efx->reset_work);
2190}
2191
2192/**************************************************************************
2193 *
2194 * List of NICs we support
2195 *
2196 **************************************************************************/
2197
2198/* PCI device ID table */
2199static DEFINE_PCI_DEVICE_TABLE(efx_pci_table) = {
2200 {PCI_DEVICE(EFX_VENDID_SFC, FALCON_A_P_DEVID),
2201 .driver_data = (unsigned long) &falcon_a1_nic_type},
2202 {PCI_DEVICE(EFX_VENDID_SFC, FALCON_B_P_DEVID),
2203 .driver_data = (unsigned long) &falcon_b0_nic_type},
2204 {PCI_DEVICE(EFX_VENDID_SFC, BETHPAGE_A_P_DEVID),
2205 .driver_data = (unsigned long) &siena_a0_nic_type},
2206 {PCI_DEVICE(EFX_VENDID_SFC, SIENA_A_P_DEVID),
2207 .driver_data = (unsigned long) &siena_a0_nic_type},
2208 {0} /* end of list */
2209};
2210
2211/**************************************************************************
2212 *
2213 * Dummy PHY/MAC operations
2214 *
2215 * Can be used for some unimplemented operations
2216 * Needed so all function pointers are valid and do not have to be tested
2217 * before use
2218 *
2219 **************************************************************************/
2220int efx_port_dummy_op_int(struct efx_nic *efx)
2221{
2222 return 0;
2223}
2224void efx_port_dummy_op_void(struct efx_nic *efx) {}
2225
2226static bool efx_port_dummy_op_poll(struct efx_nic *efx)
2227{
2228 return false;
2229}
2230
2231static const struct efx_phy_operations efx_dummy_phy_operations = {
2232 .init = efx_port_dummy_op_int,
2233 .reconfigure = efx_port_dummy_op_int,
2234 .poll = efx_port_dummy_op_poll,
2235 .fini = efx_port_dummy_op_void,
2236};
2237
2238/**************************************************************************
2239 *
2240 * Data housekeeping
2241 *
2242 **************************************************************************/
2243
2244/* This zeroes out and then fills in the invariants in a struct
2245 * efx_nic (including all sub-structures).
2246 */
2247static int efx_init_struct(struct efx_nic *efx, const struct efx_nic_type *type,
2248 struct pci_dev *pci_dev, struct net_device *net_dev)
2249{
2250 int i;
2251
2252 /* Initialise common structures */
2253 memset(efx, 0, sizeof(*efx));
2254 spin_lock_init(&efx->biu_lock);
2255#ifdef CONFIG_SFC_MTD
2256 INIT_LIST_HEAD(&efx->mtd_list);
2257#endif
2258 INIT_WORK(&efx->reset_work, efx_reset_work);
2259 INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor);
2260 efx->pci_dev = pci_dev;
2261 efx->msg_enable = debug;
2262 efx->state = STATE_INIT;
2263 strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name));
2264
2265 efx->net_dev = net_dev;
2266 spin_lock_init(&efx->stats_lock);
2267 mutex_init(&efx->mac_lock);
2268 efx->mac_op = type->default_mac_ops;
2269 efx->phy_op = &efx_dummy_phy_operations;
2270 efx->mdio.dev = net_dev;
2271 INIT_WORK(&efx->mac_work, efx_mac_work);
2272
2273 for (i = 0; i < EFX_MAX_CHANNELS; i++) {
2274 efx->channel[i] = efx_alloc_channel(efx, i, NULL);
2275 if (!efx->channel[i])
2276 goto fail;
2277 }
2278
2279 efx->type = type;
2280
2281 EFX_BUG_ON_PARANOID(efx->type->phys_addr_channels > EFX_MAX_CHANNELS);
2282
2283 /* Higher numbered interrupt modes are less capable! */
2284 efx->interrupt_mode = max(efx->type->max_interrupt_mode,
2285 interrupt_mode);
2286
2287 /* Would be good to use the net_dev name, but we're too early */
2288 snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s",
2289 pci_name(pci_dev));
2290 efx->workqueue = create_singlethread_workqueue(efx->workqueue_name);
2291 if (!efx->workqueue)
2292 goto fail;
2293
2294 return 0;
2295
2296fail:
2297 efx_fini_struct(efx);
2298 return -ENOMEM;
2299}
2300
2301static void efx_fini_struct(struct efx_nic *efx)
2302{
2303 int i;
2304
2305 for (i = 0; i < EFX_MAX_CHANNELS; i++)
2306 kfree(efx->channel[i]);
2307
2308 if (efx->workqueue) {
2309 destroy_workqueue(efx->workqueue);
2310 efx->workqueue = NULL;
2311 }
2312}
2313
2314/**************************************************************************
2315 *
2316 * PCI interface
2317 *
2318 **************************************************************************/
2319
2320/* Main body of final NIC shutdown code
2321 * This is called only at module unload (or hotplug removal).
2322 */
2323static void efx_pci_remove_main(struct efx_nic *efx)
2324{
2325#ifdef CONFIG_RFS_ACCEL
2326 free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap);
2327 efx->net_dev->rx_cpu_rmap = NULL;
2328#endif
2329 efx_nic_fini_interrupt(efx);
2330 efx_fini_channels(efx);
2331 efx_fini_port(efx);
2332 efx->type->fini(efx);
2333 efx_fini_napi(efx);
2334 efx_remove_all(efx);
2335}
2336
2337/* Final NIC shutdown
2338 * This is called only at module unload (or hotplug removal).
2339 */
2340static void efx_pci_remove(struct pci_dev *pci_dev)
2341{
2342 struct efx_nic *efx;
2343
2344 efx = pci_get_drvdata(pci_dev);
2345 if (!efx)
2346 return;
2347
2348 /* Mark the NIC as fini, then stop the interface */
2349 rtnl_lock();
2350 efx->state = STATE_FINI;
2351 dev_close(efx->net_dev);
2352
2353 /* Allow any queued efx_resets() to complete */
2354 rtnl_unlock();
2355
2356 efx_unregister_netdev(efx);
2357
2358 efx_mtd_remove(efx);
2359
2360 /* Wait for any scheduled resets to complete. No more will be
2361 * scheduled from this point because efx_stop_all() has been
2362 * called, we are no longer registered with driverlink, and
2363 * the net_device's have been removed. */
2364 cancel_work_sync(&efx->reset_work);
2365
2366 efx_pci_remove_main(efx);
2367
2368 efx_fini_io(efx);
2369 netif_dbg(efx, drv, efx->net_dev, "shutdown successful\n");
2370
2371 pci_set_drvdata(pci_dev, NULL);
2372 efx_fini_struct(efx);
2373 free_netdev(efx->net_dev);
2374};
2375
2376/* Main body of NIC initialisation
2377 * This is called at module load (or hotplug insertion, theoretically).
2378 */
2379static int efx_pci_probe_main(struct efx_nic *efx)
2380{
2381 int rc;
2382
2383 /* Do start-of-day initialisation */
2384 rc = efx_probe_all(efx);
2385 if (rc)
2386 goto fail1;
2387
2388 efx_init_napi(efx);
2389
2390 rc = efx->type->init(efx);
2391 if (rc) {
2392 netif_err(efx, probe, efx->net_dev,
2393 "failed to initialise NIC\n");
2394 goto fail3;
2395 }
2396
2397 rc = efx_init_port(efx);
2398 if (rc) {
2399 netif_err(efx, probe, efx->net_dev,
2400 "failed to initialise port\n");
2401 goto fail4;
2402 }
2403
2404 efx_init_channels(efx);
2405
2406 rc = efx_nic_init_interrupt(efx);
2407 if (rc)
2408 goto fail5;
2409
2410 return 0;
2411
2412 fail5:
2413 efx_fini_channels(efx);
2414 efx_fini_port(efx);
2415 fail4:
2416 efx->type->fini(efx);
2417 fail3:
2418 efx_fini_napi(efx);
2419 efx_remove_all(efx);
2420 fail1:
2421 return rc;
2422}
2423
2424/* NIC initialisation
2425 *
2426 * This is called at module load (or hotplug insertion,
2427 * theoretically). It sets up PCI mappings, tests and resets the NIC,
2428 * sets up and registers the network devices with the kernel and hooks
2429 * the interrupt service routine. It does not prepare the device for
2430 * transmission; this is left to the first time one of the network
2431 * interfaces is brought up (i.e. efx_net_open).
2432 */
2433static int __devinit efx_pci_probe(struct pci_dev *pci_dev,
2434 const struct pci_device_id *entry)
2435{
2436 const struct efx_nic_type *type = (const struct efx_nic_type *) entry->driver_data;
2437 struct net_device *net_dev;
2438 struct efx_nic *efx;
2439 int i, rc;
2440
2441 /* Allocate and initialise a struct net_device and struct efx_nic */
2442 net_dev = alloc_etherdev_mqs(sizeof(*efx), EFX_MAX_CORE_TX_QUEUES,
2443 EFX_MAX_RX_QUEUES);
2444 if (!net_dev)
2445 return -ENOMEM;
2446 net_dev->features |= (type->offload_features | NETIF_F_SG |
2447 NETIF_F_HIGHDMA | NETIF_F_TSO |
2448 NETIF_F_RXCSUM);
2449 if (type->offload_features & NETIF_F_V6_CSUM)
2450 net_dev->features |= NETIF_F_TSO6;
2451 /* Mask for features that also apply to VLAN devices */
2452 net_dev->vlan_features |= (NETIF_F_ALL_CSUM | NETIF_F_SG |
2453 NETIF_F_HIGHDMA | NETIF_F_ALL_TSO |
2454 NETIF_F_RXCSUM);
2455 /* All offloads can be toggled */
2456 net_dev->hw_features = net_dev->features & ~NETIF_F_HIGHDMA;
2457 efx = netdev_priv(net_dev);
2458 pci_set_drvdata(pci_dev, efx);
2459 SET_NETDEV_DEV(net_dev, &pci_dev->dev);
2460 rc = efx_init_struct(efx, type, pci_dev, net_dev);
2461 if (rc)
2462 goto fail1;
2463
2464 netif_info(efx, probe, efx->net_dev,
2465 "Solarflare NIC detected\n");
2466
2467 /* Set up basic I/O (BAR mappings etc) */
2468 rc = efx_init_io(efx);
2469 if (rc)
2470 goto fail2;
2471
2472 /* No serialisation is required with the reset path because
2473 * we're in STATE_INIT. */
2474 for (i = 0; i < 5; i++) {
2475 rc = efx_pci_probe_main(efx);
2476
2477 /* Serialise against efx_reset(). No more resets will be
2478 * scheduled since efx_stop_all() has been called, and we
2479 * have not and never have been registered with either
2480 * the rtnetlink or driverlink layers. */
2481 cancel_work_sync(&efx->reset_work);
2482
2483 if (rc == 0) {
2484 if (efx->reset_pending) {
2485 /* If there was a scheduled reset during
2486 * probe, the NIC is probably hosed anyway */
2487 efx_pci_remove_main(efx);
2488 rc = -EIO;
2489 } else {
2490 break;
2491 }
2492 }
2493
2494 /* Retry if a recoverably reset event has been scheduled */
2495 if (efx->reset_pending &
2496 ~(1 << RESET_TYPE_INVISIBLE | 1 << RESET_TYPE_ALL) ||
2497 !efx->reset_pending)
2498 goto fail3;
2499
2500 efx->reset_pending = 0;
2501 }
2502
2503 if (rc) {
2504 netif_err(efx, probe, efx->net_dev, "Could not reset NIC\n");
2505 goto fail4;
2506 }
2507
2508 /* Switch to the running state before we expose the device to the OS,
2509 * so that dev_open()|efx_start_all() will actually start the device */
2510 efx->state = STATE_RUNNING;
2511
2512 rc = efx_register_netdev(efx);
2513 if (rc)
2514 goto fail5;
2515
2516 netif_dbg(efx, probe, efx->net_dev, "initialisation successful\n");
2517
2518 rtnl_lock();
2519 efx_mtd_probe(efx); /* allowed to fail */
2520 rtnl_unlock();
2521 return 0;
2522
2523 fail5:
2524 efx_pci_remove_main(efx);
2525 fail4:
2526 fail3:
2527 efx_fini_io(efx);
2528 fail2:
2529 efx_fini_struct(efx);
2530 fail1:
2531 WARN_ON(rc > 0);
2532 netif_dbg(efx, drv, efx->net_dev, "initialisation failed. rc=%d\n", rc);
2533 free_netdev(net_dev);
2534 return rc;
2535}
2536
2537static int efx_pm_freeze(struct device *dev)
2538{
2539 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
2540
2541 efx->state = STATE_FINI;
2542
2543 netif_device_detach(efx->net_dev);
2544
2545 efx_stop_all(efx);
2546 efx_fini_channels(efx);
2547
2548 return 0;
2549}
2550
2551static int efx_pm_thaw(struct device *dev)
2552{
2553 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
2554
2555 efx->state = STATE_INIT;
2556
2557 efx_init_channels(efx);
2558
2559 mutex_lock(&efx->mac_lock);
2560 efx->phy_op->reconfigure(efx);
2561 mutex_unlock(&efx->mac_lock);
2562
2563 efx_start_all(efx);
2564
2565 netif_device_attach(efx->net_dev);
2566
2567 efx->state = STATE_RUNNING;
2568
2569 efx->type->resume_wol(efx);
2570
2571 /* Reschedule any quenched resets scheduled during efx_pm_freeze() */
2572 queue_work(reset_workqueue, &efx->reset_work);
2573
2574 return 0;
2575}
2576
2577static int efx_pm_poweroff(struct device *dev)
2578{
2579 struct pci_dev *pci_dev = to_pci_dev(dev);
2580 struct efx_nic *efx = pci_get_drvdata(pci_dev);
2581
2582 efx->type->fini(efx);
2583
2584 efx->reset_pending = 0;
2585
2586 pci_save_state(pci_dev);
2587 return pci_set_power_state(pci_dev, PCI_D3hot);
2588}
2589
2590/* Used for both resume and restore */
2591static int efx_pm_resume(struct device *dev)
2592{
2593 struct pci_dev *pci_dev = to_pci_dev(dev);
2594 struct efx_nic *efx = pci_get_drvdata(pci_dev);
2595 int rc;
2596
2597 rc = pci_set_power_state(pci_dev, PCI_D0);
2598 if (rc)
2599 return rc;
2600 pci_restore_state(pci_dev);
2601 rc = pci_enable_device(pci_dev);
2602 if (rc)
2603 return rc;
2604 pci_set_master(efx->pci_dev);
2605 rc = efx->type->reset(efx, RESET_TYPE_ALL);
2606 if (rc)
2607 return rc;
2608 rc = efx->type->init(efx);
2609 if (rc)
2610 return rc;
2611 efx_pm_thaw(dev);
2612 return 0;
2613}
2614
2615static int efx_pm_suspend(struct device *dev)
2616{
2617 int rc;
2618
2619 efx_pm_freeze(dev);
2620 rc = efx_pm_poweroff(dev);
2621 if (rc)
2622 efx_pm_resume(dev);
2623 return rc;
2624}
2625
2626static struct dev_pm_ops efx_pm_ops = {
2627 .suspend = efx_pm_suspend,
2628 .resume = efx_pm_resume,
2629 .freeze = efx_pm_freeze,
2630 .thaw = efx_pm_thaw,
2631 .poweroff = efx_pm_poweroff,
2632 .restore = efx_pm_resume,
2633};
2634
2635static struct pci_driver efx_pci_driver = {
2636 .name = KBUILD_MODNAME,
2637 .id_table = efx_pci_table,
2638 .probe = efx_pci_probe,
2639 .remove = efx_pci_remove,
2640 .driver.pm = &efx_pm_ops,
2641};
2642
2643/**************************************************************************
2644 *
2645 * Kernel module interface
2646 *
2647 *************************************************************************/
2648
2649module_param(interrupt_mode, uint, 0444);
2650MODULE_PARM_DESC(interrupt_mode,
2651 "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)");
2652
2653static int __init efx_init_module(void)
2654{
2655 int rc;
2656
2657 printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n");
2658
2659 rc = register_netdevice_notifier(&efx_netdev_notifier);
2660 if (rc)
2661 goto err_notifier;
2662
2663 reset_workqueue = create_singlethread_workqueue("sfc_reset");
2664 if (!reset_workqueue) {
2665 rc = -ENOMEM;
2666 goto err_reset;
2667 }
2668
2669 rc = pci_register_driver(&efx_pci_driver);
2670 if (rc < 0)
2671 goto err_pci;
2672
2673 return 0;
2674
2675 err_pci:
2676 destroy_workqueue(reset_workqueue);
2677 err_reset:
2678 unregister_netdevice_notifier(&efx_netdev_notifier);
2679 err_notifier:
2680 return rc;
2681}
2682
2683static void __exit efx_exit_module(void)
2684{
2685 printk(KERN_INFO "Solarflare NET driver unloading\n");
2686
2687 pci_unregister_driver(&efx_pci_driver);
2688 destroy_workqueue(reset_workqueue);
2689 unregister_netdevice_notifier(&efx_netdev_notifier);
2690
2691}
2692
2693module_init(efx_init_module);
2694module_exit(efx_exit_module);
2695
2696MODULE_AUTHOR("Solarflare Communications and "
2697 "Michael Brown <mbrown@fensystems.co.uk>");
2698MODULE_DESCRIPTION("Solarflare Communications network driver");
2699MODULE_LICENSE("GPL");
2700MODULE_DEVICE_TABLE(pci, efx_pci_table);