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1/*
2 * Network device driver for the MACE ethernet controller on
3 * Apple Powermacs. Assumes it's under a DBDMA controller.
4 *
5 * Copyright (C) 1996 Paul Mackerras.
6 */
7
8#include <linux/module.h>
9#include <linux/kernel.h>
10#include <linux/netdevice.h>
11#include <linux/etherdevice.h>
12#include <linux/delay.h>
13#include <linux/string.h>
14#include <linux/timer.h>
15#include <linux/init.h>
16#include <linux/interrupt.h>
17#include <linux/crc32.h>
18#include <linux/spinlock.h>
19#include <linux/bitrev.h>
20#include <linux/slab.h>
21#include <asm/prom.h>
22#include <asm/dbdma.h>
23#include <asm/io.h>
24#include <asm/pgtable.h>
25#include <asm/macio.h>
26
27#include "mace.h"
28
29static int port_aaui = -1;
30
31#define N_RX_RING 8
32#define N_TX_RING 6
33#define MAX_TX_ACTIVE 1
34#define NCMDS_TX 1 /* dma commands per element in tx ring */
35#define RX_BUFLEN (ETH_FRAME_LEN + 8)
36#define TX_TIMEOUT HZ /* 1 second */
37
38/* Chip rev needs workaround on HW & multicast addr change */
39#define BROKEN_ADDRCHG_REV 0x0941
40
41/* Bits in transmit DMA status */
42#define TX_DMA_ERR 0x80
43
44struct mace_data {
45 volatile struct mace __iomem *mace;
46 volatile struct dbdma_regs __iomem *tx_dma;
47 int tx_dma_intr;
48 volatile struct dbdma_regs __iomem *rx_dma;
49 int rx_dma_intr;
50 volatile struct dbdma_cmd *tx_cmds; /* xmit dma command list */
51 volatile struct dbdma_cmd *rx_cmds; /* recv dma command list */
52 struct sk_buff *rx_bufs[N_RX_RING];
53 int rx_fill;
54 int rx_empty;
55 struct sk_buff *tx_bufs[N_TX_RING];
56 int tx_fill;
57 int tx_empty;
58 unsigned char maccc;
59 unsigned char tx_fullup;
60 unsigned char tx_active;
61 unsigned char tx_bad_runt;
62 struct timer_list tx_timeout;
63 int timeout_active;
64 int port_aaui;
65 int chipid;
66 struct macio_dev *mdev;
67 spinlock_t lock;
68};
69
70/*
71 * Number of bytes of private data per MACE: allow enough for
72 * the rx and tx dma commands plus a branch dma command each,
73 * and another 16 bytes to allow us to align the dma command
74 * buffers on a 16 byte boundary.
75 */
76#define PRIV_BYTES (sizeof(struct mace_data) \
77 + (N_RX_RING + NCMDS_TX * N_TX_RING + 3) * sizeof(struct dbdma_cmd))
78
79static int mace_open(struct net_device *dev);
80static int mace_close(struct net_device *dev);
81static int mace_xmit_start(struct sk_buff *skb, struct net_device *dev);
82static void mace_set_multicast(struct net_device *dev);
83static void mace_reset(struct net_device *dev);
84static int mace_set_address(struct net_device *dev, void *addr);
85static irqreturn_t mace_interrupt(int irq, void *dev_id);
86static irqreturn_t mace_txdma_intr(int irq, void *dev_id);
87static irqreturn_t mace_rxdma_intr(int irq, void *dev_id);
88static void mace_set_timeout(struct net_device *dev);
89static void mace_tx_timeout(unsigned long data);
90static inline void dbdma_reset(volatile struct dbdma_regs __iomem *dma);
91static inline void mace_clean_rings(struct mace_data *mp);
92static void __mace_set_address(struct net_device *dev, void *addr);
93
94/*
95 * If we can't get a skbuff when we need it, we use this area for DMA.
96 */
97static unsigned char *dummy_buf;
98
99static const struct net_device_ops mace_netdev_ops = {
100 .ndo_open = mace_open,
101 .ndo_stop = mace_close,
102 .ndo_start_xmit = mace_xmit_start,
103 .ndo_set_multicast_list = mace_set_multicast,
104 .ndo_set_mac_address = mace_set_address,
105 .ndo_change_mtu = eth_change_mtu,
106 .ndo_validate_addr = eth_validate_addr,
107};
108
109static int __devinit mace_probe(struct macio_dev *mdev, const struct of_device_id *match)
110{
111 struct device_node *mace = macio_get_of_node(mdev);
112 struct net_device *dev;
113 struct mace_data *mp;
114 const unsigned char *addr;
115 int j, rev, rc = -EBUSY;
116
117 if (macio_resource_count(mdev) != 3 || macio_irq_count(mdev) != 3) {
118 printk(KERN_ERR "can't use MACE %s: need 3 addrs and 3 irqs\n",
119 mace->full_name);
120 return -ENODEV;
121 }
122
123 addr = of_get_property(mace, "mac-address", NULL);
124 if (addr == NULL) {
125 addr = of_get_property(mace, "local-mac-address", NULL);
126 if (addr == NULL) {
127 printk(KERN_ERR "Can't get mac-address for MACE %s\n",
128 mace->full_name);
129 return -ENODEV;
130 }
131 }
132
133 /*
134 * lazy allocate the driver-wide dummy buffer. (Note that we
135 * never have more than one MACE in the system anyway)
136 */
137 if (dummy_buf == NULL) {
138 dummy_buf = kmalloc(RX_BUFLEN+2, GFP_KERNEL);
139 if (dummy_buf == NULL) {
140 printk(KERN_ERR "MACE: couldn't allocate dummy buffer\n");
141 return -ENOMEM;
142 }
143 }
144
145 if (macio_request_resources(mdev, "mace")) {
146 printk(KERN_ERR "MACE: can't request IO resources !\n");
147 return -EBUSY;
148 }
149
150 dev = alloc_etherdev(PRIV_BYTES);
151 if (!dev) {
152 printk(KERN_ERR "MACE: can't allocate ethernet device !\n");
153 rc = -ENOMEM;
154 goto err_release;
155 }
156 SET_NETDEV_DEV(dev, &mdev->ofdev.dev);
157
158 mp = netdev_priv(dev);
159 mp->mdev = mdev;
160 macio_set_drvdata(mdev, dev);
161
162 dev->base_addr = macio_resource_start(mdev, 0);
163 mp->mace = ioremap(dev->base_addr, 0x1000);
164 if (mp->mace == NULL) {
165 printk(KERN_ERR "MACE: can't map IO resources !\n");
166 rc = -ENOMEM;
167 goto err_free;
168 }
169 dev->irq = macio_irq(mdev, 0);
170
171 rev = addr[0] == 0 && addr[1] == 0xA0;
172 for (j = 0; j < 6; ++j) {
173 dev->dev_addr[j] = rev ? bitrev8(addr[j]): addr[j];
174 }
175 mp->chipid = (in_8(&mp->mace->chipid_hi) << 8) |
176 in_8(&mp->mace->chipid_lo);
177
178
179 mp = netdev_priv(dev);
180 mp->maccc = ENXMT | ENRCV;
181
182 mp->tx_dma = ioremap(macio_resource_start(mdev, 1), 0x1000);
183 if (mp->tx_dma == NULL) {
184 printk(KERN_ERR "MACE: can't map TX DMA resources !\n");
185 rc = -ENOMEM;
186 goto err_unmap_io;
187 }
188 mp->tx_dma_intr = macio_irq(mdev, 1);
189
190 mp->rx_dma = ioremap(macio_resource_start(mdev, 2), 0x1000);
191 if (mp->rx_dma == NULL) {
192 printk(KERN_ERR "MACE: can't map RX DMA resources !\n");
193 rc = -ENOMEM;
194 goto err_unmap_tx_dma;
195 }
196 mp->rx_dma_intr = macio_irq(mdev, 2);
197
198 mp->tx_cmds = (volatile struct dbdma_cmd *) DBDMA_ALIGN(mp + 1);
199 mp->rx_cmds = mp->tx_cmds + NCMDS_TX * N_TX_RING + 1;
200
201 memset((char *) mp->tx_cmds, 0,
202 (NCMDS_TX*N_TX_RING + N_RX_RING + 2) * sizeof(struct dbdma_cmd));
203 init_timer(&mp->tx_timeout);
204 spin_lock_init(&mp->lock);
205 mp->timeout_active = 0;
206
207 if (port_aaui >= 0)
208 mp->port_aaui = port_aaui;
209 else {
210 /* Apple Network Server uses the AAUI port */
211 if (of_machine_is_compatible("AAPL,ShinerESB"))
212 mp->port_aaui = 1;
213 else {
214#ifdef CONFIG_MACE_AAUI_PORT
215 mp->port_aaui = 1;
216#else
217 mp->port_aaui = 0;
218#endif
219 }
220 }
221
222 dev->netdev_ops = &mace_netdev_ops;
223
224 /*
225 * Most of what is below could be moved to mace_open()
226 */
227 mace_reset(dev);
228
229 rc = request_irq(dev->irq, mace_interrupt, 0, "MACE", dev);
230 if (rc) {
231 printk(KERN_ERR "MACE: can't get irq %d\n", dev->irq);
232 goto err_unmap_rx_dma;
233 }
234 rc = request_irq(mp->tx_dma_intr, mace_txdma_intr, 0, "MACE-txdma", dev);
235 if (rc) {
236 printk(KERN_ERR "MACE: can't get irq %d\n", mp->tx_dma_intr);
237 goto err_free_irq;
238 }
239 rc = request_irq(mp->rx_dma_intr, mace_rxdma_intr, 0, "MACE-rxdma", dev);
240 if (rc) {
241 printk(KERN_ERR "MACE: can't get irq %d\n", mp->rx_dma_intr);
242 goto err_free_tx_irq;
243 }
244
245 rc = register_netdev(dev);
246 if (rc) {
247 printk(KERN_ERR "MACE: Cannot register net device, aborting.\n");
248 goto err_free_rx_irq;
249 }
250
251 printk(KERN_INFO "%s: MACE at %pM, chip revision %d.%d\n",
252 dev->name, dev->dev_addr,
253 mp->chipid >> 8, mp->chipid & 0xff);
254
255 return 0;
256
257 err_free_rx_irq:
258 free_irq(macio_irq(mdev, 2), dev);
259 err_free_tx_irq:
260 free_irq(macio_irq(mdev, 1), dev);
261 err_free_irq:
262 free_irq(macio_irq(mdev, 0), dev);
263 err_unmap_rx_dma:
264 iounmap(mp->rx_dma);
265 err_unmap_tx_dma:
266 iounmap(mp->tx_dma);
267 err_unmap_io:
268 iounmap(mp->mace);
269 err_free:
270 free_netdev(dev);
271 err_release:
272 macio_release_resources(mdev);
273
274 return rc;
275}
276
277static int __devexit mace_remove(struct macio_dev *mdev)
278{
279 struct net_device *dev = macio_get_drvdata(mdev);
280 struct mace_data *mp;
281
282 BUG_ON(dev == NULL);
283
284 macio_set_drvdata(mdev, NULL);
285
286 mp = netdev_priv(dev);
287
288 unregister_netdev(dev);
289
290 free_irq(dev->irq, dev);
291 free_irq(mp->tx_dma_intr, dev);
292 free_irq(mp->rx_dma_intr, dev);
293
294 iounmap(mp->rx_dma);
295 iounmap(mp->tx_dma);
296 iounmap(mp->mace);
297
298 free_netdev(dev);
299
300 macio_release_resources(mdev);
301
302 return 0;
303}
304
305static void dbdma_reset(volatile struct dbdma_regs __iomem *dma)
306{
307 int i;
308
309 out_le32(&dma->control, (WAKE|FLUSH|PAUSE|RUN) << 16);
310
311 /*
312 * Yes this looks peculiar, but apparently it needs to be this
313 * way on some machines.
314 */
315 for (i = 200; i > 0; --i)
316 if (ld_le32(&dma->control) & RUN)
317 udelay(1);
318}
319
320static void mace_reset(struct net_device *dev)
321{
322 struct mace_data *mp = netdev_priv(dev);
323 volatile struct mace __iomem *mb = mp->mace;
324 int i;
325
326 /* soft-reset the chip */
327 i = 200;
328 while (--i) {
329 out_8(&mb->biucc, SWRST);
330 if (in_8(&mb->biucc) & SWRST) {
331 udelay(10);
332 continue;
333 }
334 break;
335 }
336 if (!i) {
337 printk(KERN_ERR "mace: cannot reset chip!\n");
338 return;
339 }
340
341 out_8(&mb->imr, 0xff); /* disable all intrs for now */
342 i = in_8(&mb->ir);
343 out_8(&mb->maccc, 0); /* turn off tx, rx */
344
345 out_8(&mb->biucc, XMTSP_64);
346 out_8(&mb->utr, RTRD);
347 out_8(&mb->fifocc, RCVFW_32 | XMTFW_16 | XMTFWU | RCVFWU | XMTBRST);
348 out_8(&mb->xmtfc, AUTO_PAD_XMIT); /* auto-pad short frames */
349 out_8(&mb->rcvfc, 0);
350
351 /* load up the hardware address */
352 __mace_set_address(dev, dev->dev_addr);
353
354 /* clear the multicast filter */
355 if (mp->chipid == BROKEN_ADDRCHG_REV)
356 out_8(&mb->iac, LOGADDR);
357 else {
358 out_8(&mb->iac, ADDRCHG | LOGADDR);
359 while ((in_8(&mb->iac) & ADDRCHG) != 0)
360 ;
361 }
362 for (i = 0; i < 8; ++i)
363 out_8(&mb->ladrf, 0);
364
365 /* done changing address */
366 if (mp->chipid != BROKEN_ADDRCHG_REV)
367 out_8(&mb->iac, 0);
368
369 if (mp->port_aaui)
370 out_8(&mb->plscc, PORTSEL_AUI + ENPLSIO);
371 else
372 out_8(&mb->plscc, PORTSEL_GPSI + ENPLSIO);
373}
374
375static void __mace_set_address(struct net_device *dev, void *addr)
376{
377 struct mace_data *mp = netdev_priv(dev);
378 volatile struct mace __iomem *mb = mp->mace;
379 unsigned char *p = addr;
380 int i;
381
382 /* load up the hardware address */
383 if (mp->chipid == BROKEN_ADDRCHG_REV)
384 out_8(&mb->iac, PHYADDR);
385 else {
386 out_8(&mb->iac, ADDRCHG | PHYADDR);
387 while ((in_8(&mb->iac) & ADDRCHG) != 0)
388 ;
389 }
390 for (i = 0; i < 6; ++i)
391 out_8(&mb->padr, dev->dev_addr[i] = p[i]);
392 if (mp->chipid != BROKEN_ADDRCHG_REV)
393 out_8(&mb->iac, 0);
394}
395
396static int mace_set_address(struct net_device *dev, void *addr)
397{
398 struct mace_data *mp = netdev_priv(dev);
399 volatile struct mace __iomem *mb = mp->mace;
400 unsigned long flags;
401
402 spin_lock_irqsave(&mp->lock, flags);
403
404 __mace_set_address(dev, addr);
405
406 /* note: setting ADDRCHG clears ENRCV */
407 out_8(&mb->maccc, mp->maccc);
408
409 spin_unlock_irqrestore(&mp->lock, flags);
410 return 0;
411}
412
413static inline void mace_clean_rings(struct mace_data *mp)
414{
415 int i;
416
417 /* free some skb's */
418 for (i = 0; i < N_RX_RING; ++i) {
419 if (mp->rx_bufs[i] != NULL) {
420 dev_kfree_skb(mp->rx_bufs[i]);
421 mp->rx_bufs[i] = NULL;
422 }
423 }
424 for (i = mp->tx_empty; i != mp->tx_fill; ) {
425 dev_kfree_skb(mp->tx_bufs[i]);
426 if (++i >= N_TX_RING)
427 i = 0;
428 }
429}
430
431static int mace_open(struct net_device *dev)
432{
433 struct mace_data *mp = netdev_priv(dev);
434 volatile struct mace __iomem *mb = mp->mace;
435 volatile struct dbdma_regs __iomem *rd = mp->rx_dma;
436 volatile struct dbdma_regs __iomem *td = mp->tx_dma;
437 volatile struct dbdma_cmd *cp;
438 int i;
439 struct sk_buff *skb;
440 unsigned char *data;
441
442 /* reset the chip */
443 mace_reset(dev);
444
445 /* initialize list of sk_buffs for receiving and set up recv dma */
446 mace_clean_rings(mp);
447 memset((char *)mp->rx_cmds, 0, N_RX_RING * sizeof(struct dbdma_cmd));
448 cp = mp->rx_cmds;
449 for (i = 0; i < N_RX_RING - 1; ++i) {
450 skb = dev_alloc_skb(RX_BUFLEN + 2);
451 if (!skb) {
452 data = dummy_buf;
453 } else {
454 skb_reserve(skb, 2); /* so IP header lands on 4-byte bdry */
455 data = skb->data;
456 }
457 mp->rx_bufs[i] = skb;
458 st_le16(&cp->req_count, RX_BUFLEN);
459 st_le16(&cp->command, INPUT_LAST + INTR_ALWAYS);
460 st_le32(&cp->phy_addr, virt_to_bus(data));
461 cp->xfer_status = 0;
462 ++cp;
463 }
464 mp->rx_bufs[i] = NULL;
465 st_le16(&cp->command, DBDMA_STOP);
466 mp->rx_fill = i;
467 mp->rx_empty = 0;
468
469 /* Put a branch back to the beginning of the receive command list */
470 ++cp;
471 st_le16(&cp->command, DBDMA_NOP + BR_ALWAYS);
472 st_le32(&cp->cmd_dep, virt_to_bus(mp->rx_cmds));
473
474 /* start rx dma */
475 out_le32(&rd->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */
476 out_le32(&rd->cmdptr, virt_to_bus(mp->rx_cmds));
477 out_le32(&rd->control, (RUN << 16) | RUN);
478
479 /* put a branch at the end of the tx command list */
480 cp = mp->tx_cmds + NCMDS_TX * N_TX_RING;
481 st_le16(&cp->command, DBDMA_NOP + BR_ALWAYS);
482 st_le32(&cp->cmd_dep, virt_to_bus(mp->tx_cmds));
483
484 /* reset tx dma */
485 out_le32(&td->control, (RUN|PAUSE|FLUSH|WAKE) << 16);
486 out_le32(&td->cmdptr, virt_to_bus(mp->tx_cmds));
487 mp->tx_fill = 0;
488 mp->tx_empty = 0;
489 mp->tx_fullup = 0;
490 mp->tx_active = 0;
491 mp->tx_bad_runt = 0;
492
493 /* turn it on! */
494 out_8(&mb->maccc, mp->maccc);
495 /* enable all interrupts except receive interrupts */
496 out_8(&mb->imr, RCVINT);
497
498 return 0;
499}
500
501static int mace_close(struct net_device *dev)
502{
503 struct mace_data *mp = netdev_priv(dev);
504 volatile struct mace __iomem *mb = mp->mace;
505 volatile struct dbdma_regs __iomem *rd = mp->rx_dma;
506 volatile struct dbdma_regs __iomem *td = mp->tx_dma;
507
508 /* disable rx and tx */
509 out_8(&mb->maccc, 0);
510 out_8(&mb->imr, 0xff); /* disable all intrs */
511
512 /* disable rx and tx dma */
513 st_le32(&rd->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */
514 st_le32(&td->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */
515
516 mace_clean_rings(mp);
517
518 return 0;
519}
520
521static inline void mace_set_timeout(struct net_device *dev)
522{
523 struct mace_data *mp = netdev_priv(dev);
524
525 if (mp->timeout_active)
526 del_timer(&mp->tx_timeout);
527 mp->tx_timeout.expires = jiffies + TX_TIMEOUT;
528 mp->tx_timeout.function = mace_tx_timeout;
529 mp->tx_timeout.data = (unsigned long) dev;
530 add_timer(&mp->tx_timeout);
531 mp->timeout_active = 1;
532}
533
534static int mace_xmit_start(struct sk_buff *skb, struct net_device *dev)
535{
536 struct mace_data *mp = netdev_priv(dev);
537 volatile struct dbdma_regs __iomem *td = mp->tx_dma;
538 volatile struct dbdma_cmd *cp, *np;
539 unsigned long flags;
540 int fill, next, len;
541
542 /* see if there's a free slot in the tx ring */
543 spin_lock_irqsave(&mp->lock, flags);
544 fill = mp->tx_fill;
545 next = fill + 1;
546 if (next >= N_TX_RING)
547 next = 0;
548 if (next == mp->tx_empty) {
549 netif_stop_queue(dev);
550 mp->tx_fullup = 1;
551 spin_unlock_irqrestore(&mp->lock, flags);
552 return NETDEV_TX_BUSY; /* can't take it at the moment */
553 }
554 spin_unlock_irqrestore(&mp->lock, flags);
555
556 /* partially fill in the dma command block */
557 len = skb->len;
558 if (len > ETH_FRAME_LEN) {
559 printk(KERN_DEBUG "mace: xmit frame too long (%d)\n", len);
560 len = ETH_FRAME_LEN;
561 }
562 mp->tx_bufs[fill] = skb;
563 cp = mp->tx_cmds + NCMDS_TX * fill;
564 st_le16(&cp->req_count, len);
565 st_le32(&cp->phy_addr, virt_to_bus(skb->data));
566
567 np = mp->tx_cmds + NCMDS_TX * next;
568 out_le16(&np->command, DBDMA_STOP);
569
570 /* poke the tx dma channel */
571 spin_lock_irqsave(&mp->lock, flags);
572 mp->tx_fill = next;
573 if (!mp->tx_bad_runt && mp->tx_active < MAX_TX_ACTIVE) {
574 out_le16(&cp->xfer_status, 0);
575 out_le16(&cp->command, OUTPUT_LAST);
576 out_le32(&td->control, ((RUN|WAKE) << 16) + (RUN|WAKE));
577 ++mp->tx_active;
578 mace_set_timeout(dev);
579 }
580 if (++next >= N_TX_RING)
581 next = 0;
582 if (next == mp->tx_empty)
583 netif_stop_queue(dev);
584 spin_unlock_irqrestore(&mp->lock, flags);
585
586 return NETDEV_TX_OK;
587}
588
589static void mace_set_multicast(struct net_device *dev)
590{
591 struct mace_data *mp = netdev_priv(dev);
592 volatile struct mace __iomem *mb = mp->mace;
593 int i;
594 u32 crc;
595 unsigned long flags;
596
597 spin_lock_irqsave(&mp->lock, flags);
598 mp->maccc &= ~PROM;
599 if (dev->flags & IFF_PROMISC) {
600 mp->maccc |= PROM;
601 } else {
602 unsigned char multicast_filter[8];
603 struct netdev_hw_addr *ha;
604
605 if (dev->flags & IFF_ALLMULTI) {
606 for (i = 0; i < 8; i++)
607 multicast_filter[i] = 0xff;
608 } else {
609 for (i = 0; i < 8; i++)
610 multicast_filter[i] = 0;
611 netdev_for_each_mc_addr(ha, dev) {
612 crc = ether_crc_le(6, ha->addr);
613 i = crc >> 26; /* bit number in multicast_filter */
614 multicast_filter[i >> 3] |= 1 << (i & 7);
615 }
616 }
617#if 0
618 printk("Multicast filter :");
619 for (i = 0; i < 8; i++)
620 printk("%02x ", multicast_filter[i]);
621 printk("\n");
622#endif
623
624 if (mp->chipid == BROKEN_ADDRCHG_REV)
625 out_8(&mb->iac, LOGADDR);
626 else {
627 out_8(&mb->iac, ADDRCHG | LOGADDR);
628 while ((in_8(&mb->iac) & ADDRCHG) != 0)
629 ;
630 }
631 for (i = 0; i < 8; ++i)
632 out_8(&mb->ladrf, multicast_filter[i]);
633 if (mp->chipid != BROKEN_ADDRCHG_REV)
634 out_8(&mb->iac, 0);
635 }
636 /* reset maccc */
637 out_8(&mb->maccc, mp->maccc);
638 spin_unlock_irqrestore(&mp->lock, flags);
639}
640
641static void mace_handle_misc_intrs(struct mace_data *mp, int intr, struct net_device *dev)
642{
643 volatile struct mace __iomem *mb = mp->mace;
644 static int mace_babbles, mace_jabbers;
645
646 if (intr & MPCO)
647 dev->stats.rx_missed_errors += 256;
648 dev->stats.rx_missed_errors += in_8(&mb->mpc); /* reading clears it */
649 if (intr & RNTPCO)
650 dev->stats.rx_length_errors += 256;
651 dev->stats.rx_length_errors += in_8(&mb->rntpc); /* reading clears it */
652 if (intr & CERR)
653 ++dev->stats.tx_heartbeat_errors;
654 if (intr & BABBLE)
655 if (mace_babbles++ < 4)
656 printk(KERN_DEBUG "mace: babbling transmitter\n");
657 if (intr & JABBER)
658 if (mace_jabbers++ < 4)
659 printk(KERN_DEBUG "mace: jabbering transceiver\n");
660}
661
662static irqreturn_t mace_interrupt(int irq, void *dev_id)
663{
664 struct net_device *dev = (struct net_device *) dev_id;
665 struct mace_data *mp = netdev_priv(dev);
666 volatile struct mace __iomem *mb = mp->mace;
667 volatile struct dbdma_regs __iomem *td = mp->tx_dma;
668 volatile struct dbdma_cmd *cp;
669 int intr, fs, i, stat, x;
670 int xcount, dstat;
671 unsigned long flags;
672 /* static int mace_last_fs, mace_last_xcount; */
673
674 spin_lock_irqsave(&mp->lock, flags);
675 intr = in_8(&mb->ir); /* read interrupt register */
676 in_8(&mb->xmtrc); /* get retries */
677 mace_handle_misc_intrs(mp, intr, dev);
678
679 i = mp->tx_empty;
680 while (in_8(&mb->pr) & XMTSV) {
681 del_timer(&mp->tx_timeout);
682 mp->timeout_active = 0;
683 /*
684 * Clear any interrupt indication associated with this status
685 * word. This appears to unlatch any error indication from
686 * the DMA controller.
687 */
688 intr = in_8(&mb->ir);
689 if (intr != 0)
690 mace_handle_misc_intrs(mp, intr, dev);
691 if (mp->tx_bad_runt) {
692 fs = in_8(&mb->xmtfs);
693 mp->tx_bad_runt = 0;
694 out_8(&mb->xmtfc, AUTO_PAD_XMIT);
695 continue;
696 }
697 dstat = ld_le32(&td->status);
698 /* stop DMA controller */
699 out_le32(&td->control, RUN << 16);
700 /*
701 * xcount is the number of complete frames which have been
702 * written to the fifo but for which status has not been read.
703 */
704 xcount = (in_8(&mb->fifofc) >> XMTFC_SH) & XMTFC_MASK;
705 if (xcount == 0 || (dstat & DEAD)) {
706 /*
707 * If a packet was aborted before the DMA controller has
708 * finished transferring it, it seems that there are 2 bytes
709 * which are stuck in some buffer somewhere. These will get
710 * transmitted as soon as we read the frame status (which
711 * reenables the transmit data transfer request). Turning
712 * off the DMA controller and/or resetting the MACE doesn't
713 * help. So we disable auto-padding and FCS transmission
714 * so the two bytes will only be a runt packet which should
715 * be ignored by other stations.
716 */
717 out_8(&mb->xmtfc, DXMTFCS);
718 }
719 fs = in_8(&mb->xmtfs);
720 if ((fs & XMTSV) == 0) {
721 printk(KERN_ERR "mace: xmtfs not valid! (fs=%x xc=%d ds=%x)\n",
722 fs, xcount, dstat);
723 mace_reset(dev);
724 /*
725 * XXX mace likes to hang the machine after a xmtfs error.
726 * This is hard to reproduce, reseting *may* help
727 */
728 }
729 cp = mp->tx_cmds + NCMDS_TX * i;
730 stat = ld_le16(&cp->xfer_status);
731 if ((fs & (UFLO|LCOL|LCAR|RTRY)) || (dstat & DEAD) || xcount == 0) {
732 /*
733 * Check whether there were in fact 2 bytes written to
734 * the transmit FIFO.
735 */
736 udelay(1);
737 x = (in_8(&mb->fifofc) >> XMTFC_SH) & XMTFC_MASK;
738 if (x != 0) {
739 /* there were two bytes with an end-of-packet indication */
740 mp->tx_bad_runt = 1;
741 mace_set_timeout(dev);
742 } else {
743 /*
744 * Either there weren't the two bytes buffered up, or they
745 * didn't have an end-of-packet indication.
746 * We flush the transmit FIFO just in case (by setting the
747 * XMTFWU bit with the transmitter disabled).
748 */
749 out_8(&mb->maccc, in_8(&mb->maccc) & ~ENXMT);
750 out_8(&mb->fifocc, in_8(&mb->fifocc) | XMTFWU);
751 udelay(1);
752 out_8(&mb->maccc, in_8(&mb->maccc) | ENXMT);
753 out_8(&mb->xmtfc, AUTO_PAD_XMIT);
754 }
755 }
756 /* dma should have finished */
757 if (i == mp->tx_fill) {
758 printk(KERN_DEBUG "mace: tx ring ran out? (fs=%x xc=%d ds=%x)\n",
759 fs, xcount, dstat);
760 continue;
761 }
762 /* Update stats */
763 if (fs & (UFLO|LCOL|LCAR|RTRY)) {
764 ++dev->stats.tx_errors;
765 if (fs & LCAR)
766 ++dev->stats.tx_carrier_errors;
767 if (fs & (UFLO|LCOL|RTRY))
768 ++dev->stats.tx_aborted_errors;
769 } else {
770 dev->stats.tx_bytes += mp->tx_bufs[i]->len;
771 ++dev->stats.tx_packets;
772 }
773 dev_kfree_skb_irq(mp->tx_bufs[i]);
774 --mp->tx_active;
775 if (++i >= N_TX_RING)
776 i = 0;
777#if 0
778 mace_last_fs = fs;
779 mace_last_xcount = xcount;
780#endif
781 }
782
783 if (i != mp->tx_empty) {
784 mp->tx_fullup = 0;
785 netif_wake_queue(dev);
786 }
787 mp->tx_empty = i;
788 i += mp->tx_active;
789 if (i >= N_TX_RING)
790 i -= N_TX_RING;
791 if (!mp->tx_bad_runt && i != mp->tx_fill && mp->tx_active < MAX_TX_ACTIVE) {
792 do {
793 /* set up the next one */
794 cp = mp->tx_cmds + NCMDS_TX * i;
795 out_le16(&cp->xfer_status, 0);
796 out_le16(&cp->command, OUTPUT_LAST);
797 ++mp->tx_active;
798 if (++i >= N_TX_RING)
799 i = 0;
800 } while (i != mp->tx_fill && mp->tx_active < MAX_TX_ACTIVE);
801 out_le32(&td->control, ((RUN|WAKE) << 16) + (RUN|WAKE));
802 mace_set_timeout(dev);
803 }
804 spin_unlock_irqrestore(&mp->lock, flags);
805 return IRQ_HANDLED;
806}
807
808static void mace_tx_timeout(unsigned long data)
809{
810 struct net_device *dev = (struct net_device *) data;
811 struct mace_data *mp = netdev_priv(dev);
812 volatile struct mace __iomem *mb = mp->mace;
813 volatile struct dbdma_regs __iomem *td = mp->tx_dma;
814 volatile struct dbdma_regs __iomem *rd = mp->rx_dma;
815 volatile struct dbdma_cmd *cp;
816 unsigned long flags;
817 int i;
818
819 spin_lock_irqsave(&mp->lock, flags);
820 mp->timeout_active = 0;
821 if (mp->tx_active == 0 && !mp->tx_bad_runt)
822 goto out;
823
824 /* update various counters */
825 mace_handle_misc_intrs(mp, in_8(&mb->ir), dev);
826
827 cp = mp->tx_cmds + NCMDS_TX * mp->tx_empty;
828
829 /* turn off both tx and rx and reset the chip */
830 out_8(&mb->maccc, 0);
831 printk(KERN_ERR "mace: transmit timeout - resetting\n");
832 dbdma_reset(td);
833 mace_reset(dev);
834
835 /* restart rx dma */
836 cp = bus_to_virt(ld_le32(&rd->cmdptr));
837 dbdma_reset(rd);
838 out_le16(&cp->xfer_status, 0);
839 out_le32(&rd->cmdptr, virt_to_bus(cp));
840 out_le32(&rd->control, (RUN << 16) | RUN);
841
842 /* fix up the transmit side */
843 i = mp->tx_empty;
844 mp->tx_active = 0;
845 ++dev->stats.tx_errors;
846 if (mp->tx_bad_runt) {
847 mp->tx_bad_runt = 0;
848 } else if (i != mp->tx_fill) {
849 dev_kfree_skb(mp->tx_bufs[i]);
850 if (++i >= N_TX_RING)
851 i = 0;
852 mp->tx_empty = i;
853 }
854 mp->tx_fullup = 0;
855 netif_wake_queue(dev);
856 if (i != mp->tx_fill) {
857 cp = mp->tx_cmds + NCMDS_TX * i;
858 out_le16(&cp->xfer_status, 0);
859 out_le16(&cp->command, OUTPUT_LAST);
860 out_le32(&td->cmdptr, virt_to_bus(cp));
861 out_le32(&td->control, (RUN << 16) | RUN);
862 ++mp->tx_active;
863 mace_set_timeout(dev);
864 }
865
866 /* turn it back on */
867 out_8(&mb->imr, RCVINT);
868 out_8(&mb->maccc, mp->maccc);
869
870out:
871 spin_unlock_irqrestore(&mp->lock, flags);
872}
873
874static irqreturn_t mace_txdma_intr(int irq, void *dev_id)
875{
876 return IRQ_HANDLED;
877}
878
879static irqreturn_t mace_rxdma_intr(int irq, void *dev_id)
880{
881 struct net_device *dev = (struct net_device *) dev_id;
882 struct mace_data *mp = netdev_priv(dev);
883 volatile struct dbdma_regs __iomem *rd = mp->rx_dma;
884 volatile struct dbdma_cmd *cp, *np;
885 int i, nb, stat, next;
886 struct sk_buff *skb;
887 unsigned frame_status;
888 static int mace_lost_status;
889 unsigned char *data;
890 unsigned long flags;
891
892 spin_lock_irqsave(&mp->lock, flags);
893 for (i = mp->rx_empty; i != mp->rx_fill; ) {
894 cp = mp->rx_cmds + i;
895 stat = ld_le16(&cp->xfer_status);
896 if ((stat & ACTIVE) == 0) {
897 next = i + 1;
898 if (next >= N_RX_RING)
899 next = 0;
900 np = mp->rx_cmds + next;
901 if (next != mp->rx_fill &&
902 (ld_le16(&np->xfer_status) & ACTIVE) != 0) {
903 printk(KERN_DEBUG "mace: lost a status word\n");
904 ++mace_lost_status;
905 } else
906 break;
907 }
908 nb = ld_le16(&cp->req_count) - ld_le16(&cp->res_count);
909 out_le16(&cp->command, DBDMA_STOP);
910 /* got a packet, have a look at it */
911 skb = mp->rx_bufs[i];
912 if (!skb) {
913 ++dev->stats.rx_dropped;
914 } else if (nb > 8) {
915 data = skb->data;
916 frame_status = (data[nb-3] << 8) + data[nb-4];
917 if (frame_status & (RS_OFLO|RS_CLSN|RS_FRAMERR|RS_FCSERR)) {
918 ++dev->stats.rx_errors;
919 if (frame_status & RS_OFLO)
920 ++dev->stats.rx_over_errors;
921 if (frame_status & RS_FRAMERR)
922 ++dev->stats.rx_frame_errors;
923 if (frame_status & RS_FCSERR)
924 ++dev->stats.rx_crc_errors;
925 } else {
926 /* Mace feature AUTO_STRIP_RCV is on by default, dropping the
927 * FCS on frames with 802.3 headers. This means that Ethernet
928 * frames have 8 extra octets at the end, while 802.3 frames
929 * have only 4. We need to correctly account for this. */
930 if (*(unsigned short *)(data+12) < 1536) /* 802.3 header */
931 nb -= 4;
932 else /* Ethernet header; mace includes FCS */
933 nb -= 8;
934 skb_put(skb, nb);
935 skb->protocol = eth_type_trans(skb, dev);
936 dev->stats.rx_bytes += skb->len;
937 netif_rx(skb);
938 mp->rx_bufs[i] = NULL;
939 ++dev->stats.rx_packets;
940 }
941 } else {
942 ++dev->stats.rx_errors;
943 ++dev->stats.rx_length_errors;
944 }
945
946 /* advance to next */
947 if (++i >= N_RX_RING)
948 i = 0;
949 }
950 mp->rx_empty = i;
951
952 i = mp->rx_fill;
953 for (;;) {
954 next = i + 1;
955 if (next >= N_RX_RING)
956 next = 0;
957 if (next == mp->rx_empty)
958 break;
959 cp = mp->rx_cmds + i;
960 skb = mp->rx_bufs[i];
961 if (!skb) {
962 skb = dev_alloc_skb(RX_BUFLEN + 2);
963 if (skb) {
964 skb_reserve(skb, 2);
965 mp->rx_bufs[i] = skb;
966 }
967 }
968 st_le16(&cp->req_count, RX_BUFLEN);
969 data = skb? skb->data: dummy_buf;
970 st_le32(&cp->phy_addr, virt_to_bus(data));
971 out_le16(&cp->xfer_status, 0);
972 out_le16(&cp->command, INPUT_LAST + INTR_ALWAYS);
973#if 0
974 if ((ld_le32(&rd->status) & ACTIVE) != 0) {
975 out_le32(&rd->control, (PAUSE << 16) | PAUSE);
976 while ((in_le32(&rd->status) & ACTIVE) != 0)
977 ;
978 }
979#endif
980 i = next;
981 }
982 if (i != mp->rx_fill) {
983 out_le32(&rd->control, ((RUN|WAKE) << 16) | (RUN|WAKE));
984 mp->rx_fill = i;
985 }
986 spin_unlock_irqrestore(&mp->lock, flags);
987 return IRQ_HANDLED;
988}
989
990static struct of_device_id mace_match[] =
991{
992 {
993 .name = "mace",
994 },
995 {},
996};
997MODULE_DEVICE_TABLE (of, mace_match);
998
999static struct macio_driver mace_driver =
1000{
1001 .driver = {
1002 .name = "mace",
1003 .owner = THIS_MODULE,
1004 .of_match_table = mace_match,
1005 },
1006 .probe = mace_probe,
1007 .remove = mace_remove,
1008};
1009
1010
1011static int __init mace_init(void)
1012{
1013 return macio_register_driver(&mace_driver);
1014}
1015
1016static void __exit mace_cleanup(void)
1017{
1018 macio_unregister_driver(&mace_driver);
1019
1020 kfree(dummy_buf);
1021 dummy_buf = NULL;
1022}
1023
1024MODULE_AUTHOR("Paul Mackerras");
1025MODULE_DESCRIPTION("PowerMac MACE driver.");
1026module_param(port_aaui, int, 0);
1027MODULE_PARM_DESC(port_aaui, "MACE uses AAUI port (0-1)");
1028MODULE_LICENSE("GPL");
1029
1030module_init(mace_init);
1031module_exit(mace_cleanup);