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1/****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2010 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11#include <linux/bitops.h>
12#include <linux/delay.h>
13#include <linux/pci.h>
14#include <linux/module.h>
15#include <linux/slab.h>
16#include <linux/random.h>
17#include "net_driver.h"
18#include "bitfield.h"
19#include "efx.h"
20#include "nic.h"
21#include "spi.h"
22#include "regs.h"
23#include "io.h"
24#include "phy.h"
25#include "workarounds.h"
26#include "mcdi.h"
27#include "mcdi_pcol.h"
28
29/* Hardware control for SFC9000 family including SFL9021 (aka Siena). */
30
31static void siena_init_wol(struct efx_nic *efx);
32
33
34static void siena_push_irq_moderation(struct efx_channel *channel)
35{
36 efx_dword_t timer_cmd;
37
38 if (channel->irq_moderation)
39 EFX_POPULATE_DWORD_2(timer_cmd,
40 FRF_CZ_TC_TIMER_MODE,
41 FFE_CZ_TIMER_MODE_INT_HLDOFF,
42 FRF_CZ_TC_TIMER_VAL,
43 channel->irq_moderation - 1);
44 else
45 EFX_POPULATE_DWORD_2(timer_cmd,
46 FRF_CZ_TC_TIMER_MODE,
47 FFE_CZ_TIMER_MODE_DIS,
48 FRF_CZ_TC_TIMER_VAL, 0);
49 efx_writed_page_locked(channel->efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
50 channel->channel);
51}
52
53static int siena_mdio_write(struct net_device *net_dev,
54 int prtad, int devad, u16 addr, u16 value)
55{
56 struct efx_nic *efx = netdev_priv(net_dev);
57 uint32_t status;
58 int rc;
59
60 rc = efx_mcdi_mdio_write(efx, efx->mdio_bus, prtad, devad,
61 addr, value, &status);
62 if (rc)
63 return rc;
64 if (status != MC_CMD_MDIO_STATUS_GOOD)
65 return -EIO;
66
67 return 0;
68}
69
70static int siena_mdio_read(struct net_device *net_dev,
71 int prtad, int devad, u16 addr)
72{
73 struct efx_nic *efx = netdev_priv(net_dev);
74 uint16_t value;
75 uint32_t status;
76 int rc;
77
78 rc = efx_mcdi_mdio_read(efx, efx->mdio_bus, prtad, devad,
79 addr, &value, &status);
80 if (rc)
81 return rc;
82 if (status != MC_CMD_MDIO_STATUS_GOOD)
83 return -EIO;
84
85 return (int)value;
86}
87
88/* This call is responsible for hooking in the MAC and PHY operations */
89static int siena_probe_port(struct efx_nic *efx)
90{
91 int rc;
92
93 /* Hook in PHY operations table */
94 efx->phy_op = &efx_mcdi_phy_ops;
95
96 /* Set up MDIO structure for PHY */
97 efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
98 efx->mdio.mdio_read = siena_mdio_read;
99 efx->mdio.mdio_write = siena_mdio_write;
100
101 /* Fill out MDIO structure, loopback modes, and initial link state */
102 rc = efx->phy_op->probe(efx);
103 if (rc != 0)
104 return rc;
105
106 /* Allocate buffer for stats */
107 rc = efx_nic_alloc_buffer(efx, &efx->stats_buffer,
108 MC_CMD_MAC_NSTATS * sizeof(u64));
109 if (rc)
110 return rc;
111 netif_dbg(efx, probe, efx->net_dev,
112 "stats buffer at %llx (virt %p phys %llx)\n",
113 (u64)efx->stats_buffer.dma_addr,
114 efx->stats_buffer.addr,
115 (u64)virt_to_phys(efx->stats_buffer.addr));
116
117 efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr, 0, 0, 1);
118
119 return 0;
120}
121
122static void siena_remove_port(struct efx_nic *efx)
123{
124 efx->phy_op->remove(efx);
125 efx_nic_free_buffer(efx, &efx->stats_buffer);
126}
127
128static const struct efx_nic_register_test siena_register_tests[] = {
129 { FR_AZ_ADR_REGION,
130 EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
131 { FR_CZ_USR_EV_CFG,
132 EFX_OWORD32(0x000103FF, 0x00000000, 0x00000000, 0x00000000) },
133 { FR_AZ_RX_CFG,
134 EFX_OWORD32(0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000) },
135 { FR_AZ_TX_CFG,
136 EFX_OWORD32(0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF) },
137 { FR_AZ_TX_RESERVED,
138 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
139 { FR_AZ_SRM_TX_DC_CFG,
140 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
141 { FR_AZ_RX_DC_CFG,
142 EFX_OWORD32(0x00000003, 0x00000000, 0x00000000, 0x00000000) },
143 { FR_AZ_RX_DC_PF_WM,
144 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
145 { FR_BZ_DP_CTRL,
146 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
147 { FR_BZ_RX_RSS_TKEY,
148 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
149 { FR_CZ_RX_RSS_IPV6_REG1,
150 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
151 { FR_CZ_RX_RSS_IPV6_REG2,
152 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
153 { FR_CZ_RX_RSS_IPV6_REG3,
154 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000) },
155};
156
157static int siena_test_registers(struct efx_nic *efx)
158{
159 return efx_nic_test_registers(efx, siena_register_tests,
160 ARRAY_SIZE(siena_register_tests));
161}
162
163/**************************************************************************
164 *
165 * Device reset
166 *
167 **************************************************************************
168 */
169
170static enum reset_type siena_map_reset_reason(enum reset_type reason)
171{
172 return RESET_TYPE_ALL;
173}
174
175static int siena_map_reset_flags(u32 *flags)
176{
177 enum {
178 SIENA_RESET_PORT = (ETH_RESET_DMA | ETH_RESET_FILTER |
179 ETH_RESET_OFFLOAD | ETH_RESET_MAC |
180 ETH_RESET_PHY),
181 SIENA_RESET_MC = (SIENA_RESET_PORT |
182 ETH_RESET_MGMT << ETH_RESET_SHARED_SHIFT),
183 };
184
185 if ((*flags & SIENA_RESET_MC) == SIENA_RESET_MC) {
186 *flags &= ~SIENA_RESET_MC;
187 return RESET_TYPE_WORLD;
188 }
189
190 if ((*flags & SIENA_RESET_PORT) == SIENA_RESET_PORT) {
191 *flags &= ~SIENA_RESET_PORT;
192 return RESET_TYPE_ALL;
193 }
194
195 /* no invisible reset implemented */
196
197 return -EINVAL;
198}
199
200static int siena_reset_hw(struct efx_nic *efx, enum reset_type method)
201{
202 int rc;
203
204 /* Recover from a failed assertion pre-reset */
205 rc = efx_mcdi_handle_assertion(efx);
206 if (rc)
207 return rc;
208
209 if (method == RESET_TYPE_WORLD)
210 return efx_mcdi_reset_mc(efx);
211 else
212 return efx_mcdi_reset_port(efx);
213}
214
215static int siena_probe_nvconfig(struct efx_nic *efx)
216{
217 u32 caps = 0;
218 int rc;
219
220 rc = efx_mcdi_get_board_cfg(efx, efx->net_dev->perm_addr, NULL, &caps);
221
222 efx->timer_quantum_ns =
223 (caps & (1 << MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN)) ?
224 3072 : 6144; /* 768 cycles */
225 return rc;
226}
227
228static void siena_dimension_resources(struct efx_nic *efx)
229{
230 /* Each port has a small block of internal SRAM dedicated to
231 * the buffer table and descriptor caches. In theory we can
232 * map both blocks to one port, but we don't.
233 */
234 efx_nic_dimension_resources(efx, FR_CZ_BUF_FULL_TBL_ROWS / 2);
235}
236
237static int siena_probe_nic(struct efx_nic *efx)
238{
239 struct siena_nic_data *nic_data;
240 bool already_attached = false;
241 efx_oword_t reg;
242 int rc;
243
244 /* Allocate storage for hardware specific data */
245 nic_data = kzalloc(sizeof(struct siena_nic_data), GFP_KERNEL);
246 if (!nic_data)
247 return -ENOMEM;
248 efx->nic_data = nic_data;
249
250 if (efx_nic_fpga_ver(efx) != 0) {
251 netif_err(efx, probe, efx->net_dev,
252 "Siena FPGA not supported\n");
253 rc = -ENODEV;
254 goto fail1;
255 }
256
257 efx_reado(efx, ®, FR_AZ_CS_DEBUG);
258 efx->net_dev->dev_id = EFX_OWORD_FIELD(reg, FRF_CZ_CS_PORT_NUM) - 1;
259
260 efx_mcdi_init(efx);
261
262 /* Recover from a failed assertion before probing */
263 rc = efx_mcdi_handle_assertion(efx);
264 if (rc)
265 goto fail1;
266
267 /* Let the BMC know that the driver is now in charge of link and
268 * filter settings. We must do this before we reset the NIC */
269 rc = efx_mcdi_drv_attach(efx, true, &already_attached);
270 if (rc) {
271 netif_err(efx, probe, efx->net_dev,
272 "Unable to register driver with MCPU\n");
273 goto fail2;
274 }
275 if (already_attached)
276 /* Not a fatal error */
277 netif_err(efx, probe, efx->net_dev,
278 "Host already registered with MCPU\n");
279
280 /* Now we can reset the NIC */
281 rc = siena_reset_hw(efx, RESET_TYPE_ALL);
282 if (rc) {
283 netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n");
284 goto fail3;
285 }
286
287 siena_init_wol(efx);
288
289 /* Allocate memory for INT_KER */
290 rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
291 if (rc)
292 goto fail4;
293 BUG_ON(efx->irq_status.dma_addr & 0x0f);
294
295 netif_dbg(efx, probe, efx->net_dev,
296 "INT_KER at %llx (virt %p phys %llx)\n",
297 (unsigned long long)efx->irq_status.dma_addr,
298 efx->irq_status.addr,
299 (unsigned long long)virt_to_phys(efx->irq_status.addr));
300
301 /* Read in the non-volatile configuration */
302 rc = siena_probe_nvconfig(efx);
303 if (rc == -EINVAL) {
304 netif_err(efx, probe, efx->net_dev,
305 "NVRAM is invalid therefore using defaults\n");
306 efx->phy_type = PHY_TYPE_NONE;
307 efx->mdio.prtad = MDIO_PRTAD_NONE;
308 } else if (rc) {
309 goto fail5;
310 }
311
312 rc = efx_mcdi_mon_probe(efx);
313 if (rc)
314 goto fail5;
315
316 efx_sriov_probe(efx);
317
318 return 0;
319
320fail5:
321 efx_nic_free_buffer(efx, &efx->irq_status);
322fail4:
323fail3:
324 efx_mcdi_drv_attach(efx, false, NULL);
325fail2:
326fail1:
327 kfree(efx->nic_data);
328 return rc;
329}
330
331/* This call performs hardware-specific global initialisation, such as
332 * defining the descriptor cache sizes and number of RSS channels.
333 * It does not set up any buffers, descriptor rings or event queues.
334 */
335static int siena_init_nic(struct efx_nic *efx)
336{
337 efx_oword_t temp;
338 int rc;
339
340 /* Recover from a failed assertion post-reset */
341 rc = efx_mcdi_handle_assertion(efx);
342 if (rc)
343 return rc;
344
345 /* Squash TX of packets of 16 bytes or less */
346 efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
347 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
348 efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
349
350 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
351 * descriptors (which is bad).
352 */
353 efx_reado(efx, &temp, FR_AZ_TX_CFG);
354 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
355 EFX_SET_OWORD_FIELD(temp, FRF_CZ_TX_FILTER_EN_BIT, 1);
356 efx_writeo(efx, &temp, FR_AZ_TX_CFG);
357
358 efx_reado(efx, &temp, FR_AZ_RX_CFG);
359 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_DESC_PUSH_EN, 0);
360 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_INGR_EN, 1);
361 /* Enable hash insertion. This is broken for the 'Falcon' hash
362 * if IPv6 hashing is also enabled, so also select Toeplitz
363 * TCP/IPv4 and IPv4 hashes. */
364 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_INSRT_HDR, 1);
365 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_ALG, 1);
366 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_IP_HASH, 1);
367 efx_writeo(efx, &temp, FR_AZ_RX_CFG);
368
369 /* Set hash key for IPv4 */
370 memcpy(&temp, efx->rx_hash_key, sizeof(temp));
371 efx_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY);
372
373 /* Enable IPv6 RSS */
374 BUILD_BUG_ON(sizeof(efx->rx_hash_key) <
375 2 * sizeof(temp) + FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8 ||
376 FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN != 0);
377 memcpy(&temp, efx->rx_hash_key, sizeof(temp));
378 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG1);
379 memcpy(&temp, efx->rx_hash_key + sizeof(temp), sizeof(temp));
380 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG2);
381 EFX_POPULATE_OWORD_2(temp, FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1,
382 FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, 1);
383 memcpy(&temp, efx->rx_hash_key + 2 * sizeof(temp),
384 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8);
385 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG3);
386
387 /* Enable event logging */
388 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
389 if (rc)
390 return rc;
391
392 /* Set destination of both TX and RX Flush events */
393 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
394 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
395
396 EFX_POPULATE_OWORD_1(temp, FRF_CZ_USREV_DIS, 1);
397 efx_writeo(efx, &temp, FR_CZ_USR_EV_CFG);
398
399 efx_nic_init_common(efx);
400 return 0;
401}
402
403static void siena_remove_nic(struct efx_nic *efx)
404{
405 efx_mcdi_mon_remove(efx);
406
407 efx_nic_free_buffer(efx, &efx->irq_status);
408
409 siena_reset_hw(efx, RESET_TYPE_ALL);
410
411 /* Relinquish the device back to the BMC */
412 efx_mcdi_drv_attach(efx, false, NULL);
413
414 /* Tear down the private nic state */
415 kfree(efx->nic_data);
416 efx->nic_data = NULL;
417}
418
419#define STATS_GENERATION_INVALID ((__force __le64)(-1))
420
421static int siena_try_update_nic_stats(struct efx_nic *efx)
422{
423 __le64 *dma_stats;
424 struct efx_mac_stats *mac_stats;
425 __le64 generation_start, generation_end;
426
427 mac_stats = &efx->mac_stats;
428 dma_stats = efx->stats_buffer.addr;
429
430 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
431 if (generation_end == STATS_GENERATION_INVALID)
432 return 0;
433 rmb();
434
435#define MAC_STAT(M, D) \
436 mac_stats->M = le64_to_cpu(dma_stats[MC_CMD_MAC_ ## D])
437
438 MAC_STAT(tx_bytes, TX_BYTES);
439 MAC_STAT(tx_bad_bytes, TX_BAD_BYTES);
440 mac_stats->tx_good_bytes = (mac_stats->tx_bytes -
441 mac_stats->tx_bad_bytes);
442 MAC_STAT(tx_packets, TX_PKTS);
443 MAC_STAT(tx_bad, TX_BAD_FCS_PKTS);
444 MAC_STAT(tx_pause, TX_PAUSE_PKTS);
445 MAC_STAT(tx_control, TX_CONTROL_PKTS);
446 MAC_STAT(tx_unicast, TX_UNICAST_PKTS);
447 MAC_STAT(tx_multicast, TX_MULTICAST_PKTS);
448 MAC_STAT(tx_broadcast, TX_BROADCAST_PKTS);
449 MAC_STAT(tx_lt64, TX_LT64_PKTS);
450 MAC_STAT(tx_64, TX_64_PKTS);
451 MAC_STAT(tx_65_to_127, TX_65_TO_127_PKTS);
452 MAC_STAT(tx_128_to_255, TX_128_TO_255_PKTS);
453 MAC_STAT(tx_256_to_511, TX_256_TO_511_PKTS);
454 MAC_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS);
455 MAC_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS);
456 MAC_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS);
457 MAC_STAT(tx_gtjumbo, TX_GTJUMBO_PKTS);
458 mac_stats->tx_collision = 0;
459 MAC_STAT(tx_single_collision, TX_SINGLE_COLLISION_PKTS);
460 MAC_STAT(tx_multiple_collision, TX_MULTIPLE_COLLISION_PKTS);
461 MAC_STAT(tx_excessive_collision, TX_EXCESSIVE_COLLISION_PKTS);
462 MAC_STAT(tx_deferred, TX_DEFERRED_PKTS);
463 MAC_STAT(tx_late_collision, TX_LATE_COLLISION_PKTS);
464 mac_stats->tx_collision = (mac_stats->tx_single_collision +
465 mac_stats->tx_multiple_collision +
466 mac_stats->tx_excessive_collision +
467 mac_stats->tx_late_collision);
468 MAC_STAT(tx_excessive_deferred, TX_EXCESSIVE_DEFERRED_PKTS);
469 MAC_STAT(tx_non_tcpudp, TX_NON_TCPUDP_PKTS);
470 MAC_STAT(tx_mac_src_error, TX_MAC_SRC_ERR_PKTS);
471 MAC_STAT(tx_ip_src_error, TX_IP_SRC_ERR_PKTS);
472 MAC_STAT(rx_bytes, RX_BYTES);
473 MAC_STAT(rx_bad_bytes, RX_BAD_BYTES);
474 mac_stats->rx_good_bytes = (mac_stats->rx_bytes -
475 mac_stats->rx_bad_bytes);
476 MAC_STAT(rx_packets, RX_PKTS);
477 MAC_STAT(rx_good, RX_GOOD_PKTS);
478 MAC_STAT(rx_bad, RX_BAD_FCS_PKTS);
479 MAC_STAT(rx_pause, RX_PAUSE_PKTS);
480 MAC_STAT(rx_control, RX_CONTROL_PKTS);
481 MAC_STAT(rx_unicast, RX_UNICAST_PKTS);
482 MAC_STAT(rx_multicast, RX_MULTICAST_PKTS);
483 MAC_STAT(rx_broadcast, RX_BROADCAST_PKTS);
484 MAC_STAT(rx_lt64, RX_UNDERSIZE_PKTS);
485 MAC_STAT(rx_64, RX_64_PKTS);
486 MAC_STAT(rx_65_to_127, RX_65_TO_127_PKTS);
487 MAC_STAT(rx_128_to_255, RX_128_TO_255_PKTS);
488 MAC_STAT(rx_256_to_511, RX_256_TO_511_PKTS);
489 MAC_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS);
490 MAC_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS);
491 MAC_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS);
492 MAC_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS);
493 mac_stats->rx_bad_lt64 = 0;
494 mac_stats->rx_bad_64_to_15xx = 0;
495 mac_stats->rx_bad_15xx_to_jumbo = 0;
496 MAC_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS);
497 MAC_STAT(rx_overflow, RX_OVERFLOW_PKTS);
498 mac_stats->rx_missed = 0;
499 MAC_STAT(rx_false_carrier, RX_FALSE_CARRIER_PKTS);
500 MAC_STAT(rx_symbol_error, RX_SYMBOL_ERROR_PKTS);
501 MAC_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS);
502 MAC_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS);
503 MAC_STAT(rx_internal_error, RX_INTERNAL_ERROR_PKTS);
504 mac_stats->rx_good_lt64 = 0;
505
506 efx->n_rx_nodesc_drop_cnt =
507 le64_to_cpu(dma_stats[MC_CMD_MAC_RX_NODESC_DROPS]);
508
509#undef MAC_STAT
510
511 rmb();
512 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
513 if (generation_end != generation_start)
514 return -EAGAIN;
515
516 return 0;
517}
518
519static void siena_update_nic_stats(struct efx_nic *efx)
520{
521 int retry;
522
523 /* If we're unlucky enough to read statistics wduring the DMA, wait
524 * up to 10ms for it to finish (typically takes <500us) */
525 for (retry = 0; retry < 100; ++retry) {
526 if (siena_try_update_nic_stats(efx) == 0)
527 return;
528 udelay(100);
529 }
530
531 /* Use the old values instead */
532}
533
534static void siena_start_nic_stats(struct efx_nic *efx)
535{
536 __le64 *dma_stats = efx->stats_buffer.addr;
537
538 dma_stats[MC_CMD_MAC_GENERATION_END] = STATS_GENERATION_INVALID;
539
540 efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr,
541 MC_CMD_MAC_NSTATS * sizeof(u64), 1, 0);
542}
543
544static void siena_stop_nic_stats(struct efx_nic *efx)
545{
546 efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr, 0, 0, 0);
547}
548
549/**************************************************************************
550 *
551 * Wake on LAN
552 *
553 **************************************************************************
554 */
555
556static void siena_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
557{
558 struct siena_nic_data *nic_data = efx->nic_data;
559
560 wol->supported = WAKE_MAGIC;
561 if (nic_data->wol_filter_id != -1)
562 wol->wolopts = WAKE_MAGIC;
563 else
564 wol->wolopts = 0;
565 memset(&wol->sopass, 0, sizeof(wol->sopass));
566}
567
568
569static int siena_set_wol(struct efx_nic *efx, u32 type)
570{
571 struct siena_nic_data *nic_data = efx->nic_data;
572 int rc;
573
574 if (type & ~WAKE_MAGIC)
575 return -EINVAL;
576
577 if (type & WAKE_MAGIC) {
578 if (nic_data->wol_filter_id != -1)
579 efx_mcdi_wol_filter_remove(efx,
580 nic_data->wol_filter_id);
581 rc = efx_mcdi_wol_filter_set_magic(efx, efx->net_dev->dev_addr,
582 &nic_data->wol_filter_id);
583 if (rc)
584 goto fail;
585
586 pci_wake_from_d3(efx->pci_dev, true);
587 } else {
588 rc = efx_mcdi_wol_filter_reset(efx);
589 nic_data->wol_filter_id = -1;
590 pci_wake_from_d3(efx->pci_dev, false);
591 if (rc)
592 goto fail;
593 }
594
595 return 0;
596 fail:
597 netif_err(efx, hw, efx->net_dev, "%s failed: type=%d rc=%d\n",
598 __func__, type, rc);
599 return rc;
600}
601
602
603static void siena_init_wol(struct efx_nic *efx)
604{
605 struct siena_nic_data *nic_data = efx->nic_data;
606 int rc;
607
608 rc = efx_mcdi_wol_filter_get_magic(efx, &nic_data->wol_filter_id);
609
610 if (rc != 0) {
611 /* If it failed, attempt to get into a synchronised
612 * state with MC by resetting any set WoL filters */
613 efx_mcdi_wol_filter_reset(efx);
614 nic_data->wol_filter_id = -1;
615 } else if (nic_data->wol_filter_id != -1) {
616 pci_wake_from_d3(efx->pci_dev, true);
617 }
618}
619
620
621/**************************************************************************
622 *
623 * Revision-dependent attributes used by efx.c and nic.c
624 *
625 **************************************************************************
626 */
627
628const struct efx_nic_type siena_a0_nic_type = {
629 .probe = siena_probe_nic,
630 .remove = siena_remove_nic,
631 .init = siena_init_nic,
632 .dimension_resources = siena_dimension_resources,
633 .fini = efx_port_dummy_op_void,
634 .monitor = NULL,
635 .map_reset_reason = siena_map_reset_reason,
636 .map_reset_flags = siena_map_reset_flags,
637 .reset = siena_reset_hw,
638 .probe_port = siena_probe_port,
639 .remove_port = siena_remove_port,
640 .prepare_flush = efx_port_dummy_op_void,
641 .update_stats = siena_update_nic_stats,
642 .start_stats = siena_start_nic_stats,
643 .stop_stats = siena_stop_nic_stats,
644 .set_id_led = efx_mcdi_set_id_led,
645 .push_irq_moderation = siena_push_irq_moderation,
646 .reconfigure_mac = efx_mcdi_mac_reconfigure,
647 .check_mac_fault = efx_mcdi_mac_check_fault,
648 .reconfigure_port = efx_mcdi_phy_reconfigure,
649 .get_wol = siena_get_wol,
650 .set_wol = siena_set_wol,
651 .resume_wol = siena_init_wol,
652 .test_registers = siena_test_registers,
653 .test_nvram = efx_mcdi_nvram_test_all,
654
655 .revision = EFX_REV_SIENA_A0,
656 .mem_map_size = (FR_CZ_MC_TREG_SMEM +
657 FR_CZ_MC_TREG_SMEM_STEP * FR_CZ_MC_TREG_SMEM_ROWS),
658 .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
659 .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
660 .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
661 .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
662 .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
663 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
664 .rx_buffer_hash_size = 0x10,
665 .rx_buffer_padding = 0,
666 .max_interrupt_mode = EFX_INT_MODE_MSIX,
667 .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
668 * interrupt handler only supports 32
669 * channels */
670 .timer_period_max = 1 << FRF_CZ_TC_TIMER_VAL_WIDTH,
671 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
672 NETIF_F_RXHASH | NETIF_F_NTUPLE),
673};