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1/*
2 * Copyright 2009 Advanced Micro Devices, Inc.
3 * Copyright 2009 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 * Jerome Glisse
26 */
27#ifndef R600D_H
28#define R600D_H
29
30#define CP_PACKET2 0x80000000
31#define PACKET2_PAD_SHIFT 0
32#define PACKET2_PAD_MASK (0x3fffffff << 0)
33
34#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
35
36#define R6XX_MAX_SH_GPRS 256
37#define R6XX_MAX_TEMP_GPRS 16
38#define R6XX_MAX_SH_THREADS 256
39#define R6XX_MAX_SH_STACK_ENTRIES 4096
40#define R6XX_MAX_BACKENDS 8
41#define R6XX_MAX_BACKENDS_MASK 0xff
42#define R6XX_MAX_SIMDS 8
43#define R6XX_MAX_SIMDS_MASK 0xff
44#define R6XX_MAX_PIPES 8
45#define R6XX_MAX_PIPES_MASK 0xff
46
47/* PTE flags */
48#define PTE_VALID (1 << 0)
49#define PTE_SYSTEM (1 << 1)
50#define PTE_SNOOPED (1 << 2)
51#define PTE_READABLE (1 << 5)
52#define PTE_WRITEABLE (1 << 6)
53
54/* tiling bits */
55#define ARRAY_LINEAR_GENERAL 0x00000000
56#define ARRAY_LINEAR_ALIGNED 0x00000001
57#define ARRAY_1D_TILED_THIN1 0x00000002
58#define ARRAY_2D_TILED_THIN1 0x00000004
59
60/* Registers */
61#define ARB_POP 0x2418
62#define ENABLE_TC128 (1 << 30)
63#define ARB_GDEC_RD_CNTL 0x246C
64
65#define CC_GC_SHADER_PIPE_CONFIG 0x8950
66#define CC_RB_BACKEND_DISABLE 0x98F4
67#define BACKEND_DISABLE(x) ((x) << 16)
68
69#define CB_COLOR0_BASE 0x28040
70#define CB_COLOR1_BASE 0x28044
71#define CB_COLOR2_BASE 0x28048
72#define CB_COLOR3_BASE 0x2804C
73#define CB_COLOR4_BASE 0x28050
74#define CB_COLOR5_BASE 0x28054
75#define CB_COLOR6_BASE 0x28058
76#define CB_COLOR7_BASE 0x2805C
77#define CB_COLOR7_FRAG 0x280FC
78
79#define CB_COLOR0_SIZE 0x28060
80#define CB_COLOR0_VIEW 0x28080
81#define CB_COLOR0_INFO 0x280a0
82#define CB_COLOR0_TILE 0x280c0
83#define CB_COLOR0_FRAG 0x280e0
84#define CB_COLOR0_MASK 0x28100
85
86#define SQ_ALU_CONST_CACHE_PS_0 0x28940
87#define SQ_ALU_CONST_CACHE_PS_1 0x28944
88#define SQ_ALU_CONST_CACHE_PS_2 0x28948
89#define SQ_ALU_CONST_CACHE_PS_3 0x2894c
90#define SQ_ALU_CONST_CACHE_PS_4 0x28950
91#define SQ_ALU_CONST_CACHE_PS_5 0x28954
92#define SQ_ALU_CONST_CACHE_PS_6 0x28958
93#define SQ_ALU_CONST_CACHE_PS_7 0x2895c
94#define SQ_ALU_CONST_CACHE_PS_8 0x28960
95#define SQ_ALU_CONST_CACHE_PS_9 0x28964
96#define SQ_ALU_CONST_CACHE_PS_10 0x28968
97#define SQ_ALU_CONST_CACHE_PS_11 0x2896c
98#define SQ_ALU_CONST_CACHE_PS_12 0x28970
99#define SQ_ALU_CONST_CACHE_PS_13 0x28974
100#define SQ_ALU_CONST_CACHE_PS_14 0x28978
101#define SQ_ALU_CONST_CACHE_PS_15 0x2897c
102#define SQ_ALU_CONST_CACHE_VS_0 0x28980
103#define SQ_ALU_CONST_CACHE_VS_1 0x28984
104#define SQ_ALU_CONST_CACHE_VS_2 0x28988
105#define SQ_ALU_CONST_CACHE_VS_3 0x2898c
106#define SQ_ALU_CONST_CACHE_VS_4 0x28990
107#define SQ_ALU_CONST_CACHE_VS_5 0x28994
108#define SQ_ALU_CONST_CACHE_VS_6 0x28998
109#define SQ_ALU_CONST_CACHE_VS_7 0x2899c
110#define SQ_ALU_CONST_CACHE_VS_8 0x289a0
111#define SQ_ALU_CONST_CACHE_VS_9 0x289a4
112#define SQ_ALU_CONST_CACHE_VS_10 0x289a8
113#define SQ_ALU_CONST_CACHE_VS_11 0x289ac
114#define SQ_ALU_CONST_CACHE_VS_12 0x289b0
115#define SQ_ALU_CONST_CACHE_VS_13 0x289b4
116#define SQ_ALU_CONST_CACHE_VS_14 0x289b8
117#define SQ_ALU_CONST_CACHE_VS_15 0x289bc
118#define SQ_ALU_CONST_CACHE_GS_0 0x289c0
119#define SQ_ALU_CONST_CACHE_GS_1 0x289c4
120#define SQ_ALU_CONST_CACHE_GS_2 0x289c8
121#define SQ_ALU_CONST_CACHE_GS_3 0x289cc
122#define SQ_ALU_CONST_CACHE_GS_4 0x289d0
123#define SQ_ALU_CONST_CACHE_GS_5 0x289d4
124#define SQ_ALU_CONST_CACHE_GS_6 0x289d8
125#define SQ_ALU_CONST_CACHE_GS_7 0x289dc
126#define SQ_ALU_CONST_CACHE_GS_8 0x289e0
127#define SQ_ALU_CONST_CACHE_GS_9 0x289e4
128#define SQ_ALU_CONST_CACHE_GS_10 0x289e8
129#define SQ_ALU_CONST_CACHE_GS_11 0x289ec
130#define SQ_ALU_CONST_CACHE_GS_12 0x289f0
131#define SQ_ALU_CONST_CACHE_GS_13 0x289f4
132#define SQ_ALU_CONST_CACHE_GS_14 0x289f8
133#define SQ_ALU_CONST_CACHE_GS_15 0x289fc
134
135#define CONFIG_MEMSIZE 0x5428
136#define CONFIG_CNTL 0x5424
137#define CP_STAT 0x8680
138#define CP_COHER_BASE 0x85F8
139#define CP_DEBUG 0xC1FC
140#define R_0086D8_CP_ME_CNTL 0x86D8
141#define S_0086D8_CP_ME_HALT(x) (((x) & 1)<<28)
142#define C_0086D8_CP_ME_HALT(x) ((x) & 0xEFFFFFFF)
143#define CP_ME_RAM_DATA 0xC160
144#define CP_ME_RAM_RADDR 0xC158
145#define CP_ME_RAM_WADDR 0xC15C
146#define CP_MEQ_THRESHOLDS 0x8764
147#define MEQ_END(x) ((x) << 16)
148#define ROQ_END(x) ((x) << 24)
149#define CP_PERFMON_CNTL 0x87FC
150#define CP_PFP_UCODE_ADDR 0xC150
151#define CP_PFP_UCODE_DATA 0xC154
152#define CP_QUEUE_THRESHOLDS 0x8760
153#define ROQ_IB1_START(x) ((x) << 0)
154#define ROQ_IB2_START(x) ((x) << 8)
155#define CP_RB_BASE 0xC100
156#define CP_RB_CNTL 0xC104
157#define RB_BUFSZ(x) ((x) << 0)
158#define RB_BLKSZ(x) ((x) << 8)
159#define RB_NO_UPDATE (1 << 27)
160#define RB_RPTR_WR_ENA (1 << 31)
161#define BUF_SWAP_32BIT (2 << 16)
162#define CP_RB_RPTR 0x8700
163#define CP_RB_RPTR_ADDR 0xC10C
164#define RB_RPTR_SWAP(x) ((x) << 0)
165#define CP_RB_RPTR_ADDR_HI 0xC110
166#define CP_RB_RPTR_WR 0xC108
167#define CP_RB_WPTR 0xC114
168#define CP_RB_WPTR_ADDR 0xC118
169#define CP_RB_WPTR_ADDR_HI 0xC11C
170#define CP_RB_WPTR_DELAY 0x8704
171#define CP_ROQ_IB1_STAT 0x8784
172#define CP_ROQ_IB2_STAT 0x8788
173#define CP_SEM_WAIT_TIMER 0x85BC
174
175#define DB_DEBUG 0x9830
176#define PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31)
177#define DB_DEPTH_BASE 0x2800C
178#define DB_HTILE_DATA_BASE 0x28014
179#define DB_WATERMARKS 0x9838
180#define DEPTH_FREE(x) ((x) << 0)
181#define DEPTH_FLUSH(x) ((x) << 5)
182#define DEPTH_PENDING_FREE(x) ((x) << 15)
183#define DEPTH_CACHELINE_FREE(x) ((x) << 20)
184
185#define DCP_TILING_CONFIG 0x6CA0
186#define PIPE_TILING(x) ((x) << 1)
187#define BANK_TILING(x) ((x) << 4)
188#define GROUP_SIZE(x) ((x) << 6)
189#define ROW_TILING(x) ((x) << 8)
190#define BANK_SWAPS(x) ((x) << 11)
191#define SAMPLE_SPLIT(x) ((x) << 14)
192#define BACKEND_MAP(x) ((x) << 16)
193
194#define GB_TILING_CONFIG 0x98F0
195
196#define GC_USER_SHADER_PIPE_CONFIG 0x8954
197#define INACTIVE_QD_PIPES(x) ((x) << 8)
198#define INACTIVE_QD_PIPES_MASK 0x0000FF00
199#define INACTIVE_SIMDS(x) ((x) << 16)
200#define INACTIVE_SIMDS_MASK 0x00FF0000
201
202#define SQ_CONFIG 0x8c00
203# define VC_ENABLE (1 << 0)
204# define EXPORT_SRC_C (1 << 1)
205# define DX9_CONSTS (1 << 2)
206# define ALU_INST_PREFER_VECTOR (1 << 3)
207# define DX10_CLAMP (1 << 4)
208# define CLAUSE_SEQ_PRIO(x) ((x) << 8)
209# define PS_PRIO(x) ((x) << 24)
210# define VS_PRIO(x) ((x) << 26)
211# define GS_PRIO(x) ((x) << 28)
212# define ES_PRIO(x) ((x) << 30)
213#define SQ_GPR_RESOURCE_MGMT_1 0x8c04
214# define NUM_PS_GPRS(x) ((x) << 0)
215# define NUM_VS_GPRS(x) ((x) << 16)
216# define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28)
217#define SQ_GPR_RESOURCE_MGMT_2 0x8c08
218# define NUM_GS_GPRS(x) ((x) << 0)
219# define NUM_ES_GPRS(x) ((x) << 16)
220#define SQ_THREAD_RESOURCE_MGMT 0x8c0c
221# define NUM_PS_THREADS(x) ((x) << 0)
222# define NUM_VS_THREADS(x) ((x) << 8)
223# define NUM_GS_THREADS(x) ((x) << 16)
224# define NUM_ES_THREADS(x) ((x) << 24)
225#define SQ_STACK_RESOURCE_MGMT_1 0x8c10
226# define NUM_PS_STACK_ENTRIES(x) ((x) << 0)
227# define NUM_VS_STACK_ENTRIES(x) ((x) << 16)
228#define SQ_STACK_RESOURCE_MGMT_2 0x8c14
229# define NUM_GS_STACK_ENTRIES(x) ((x) << 0)
230# define NUM_ES_STACK_ENTRIES(x) ((x) << 16)
231#define SQ_ESGS_RING_BASE 0x8c40
232#define SQ_GSVS_RING_BASE 0x8c48
233#define SQ_ESTMP_RING_BASE 0x8c50
234#define SQ_GSTMP_RING_BASE 0x8c58
235#define SQ_VSTMP_RING_BASE 0x8c60
236#define SQ_PSTMP_RING_BASE 0x8c68
237#define SQ_FBUF_RING_BASE 0x8c70
238#define SQ_REDUC_RING_BASE 0x8c78
239
240#define GRBM_CNTL 0x8000
241# define GRBM_READ_TIMEOUT(x) ((x) << 0)
242#define GRBM_STATUS 0x8010
243#define CMDFIFO_AVAIL_MASK 0x0000001F
244#define GUI_ACTIVE (1<<31)
245#define GRBM_STATUS2 0x8014
246#define GRBM_SOFT_RESET 0x8020
247#define SOFT_RESET_CP (1<<0)
248
249#define CG_THERMAL_STATUS 0x7F4
250#define ASIC_T(x) ((x) << 0)
251#define ASIC_T_MASK 0x1FF
252#define ASIC_T_SHIFT 0
253
254#define HDP_HOST_PATH_CNTL 0x2C00
255#define HDP_NONSURFACE_BASE 0x2C04
256#define HDP_NONSURFACE_INFO 0x2C08
257#define HDP_NONSURFACE_SIZE 0x2C0C
258#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
259#define HDP_TILING_CONFIG 0x2F3C
260#define HDP_DEBUG1 0x2F34
261
262#define MC_VM_AGP_TOP 0x2184
263#define MC_VM_AGP_BOT 0x2188
264#define MC_VM_AGP_BASE 0x218C
265#define MC_VM_FB_LOCATION 0x2180
266#define MC_VM_L1_TLB_MCD_RD_A_CNTL 0x219C
267#define ENABLE_L1_TLB (1 << 0)
268#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
269#define ENABLE_L1_STRICT_ORDERING (1 << 2)
270#define SYSTEM_ACCESS_MODE_MASK 0x000000C0
271#define SYSTEM_ACCESS_MODE_SHIFT 6
272#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 6)
273#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 6)
274#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 6)
275#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 6)
276#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 8)
277#define SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 8)
278#define ENABLE_SEMAPHORE_MODE (1 << 10)
279#define ENABLE_WAIT_L2_QUERY (1 << 11)
280#define EFFECTIVE_L1_TLB_SIZE(x) (((x) & 7) << 12)
281#define EFFECTIVE_L1_TLB_SIZE_MASK 0x00007000
282#define EFFECTIVE_L1_TLB_SIZE_SHIFT 12
283#define EFFECTIVE_L1_QUEUE_SIZE(x) (((x) & 7) << 15)
284#define EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00038000
285#define EFFECTIVE_L1_QUEUE_SIZE_SHIFT 15
286#define MC_VM_L1_TLB_MCD_RD_B_CNTL 0x21A0
287#define MC_VM_L1_TLB_MCB_RD_GFX_CNTL 0x21FC
288#define MC_VM_L1_TLB_MCB_RD_HDP_CNTL 0x2204
289#define MC_VM_L1_TLB_MCB_RD_PDMA_CNTL 0x2208
290#define MC_VM_L1_TLB_MCB_RD_SEM_CNTL 0x220C
291#define MC_VM_L1_TLB_MCB_RD_SYS_CNTL 0x2200
292#define MC_VM_L1_TLB_MCD_WR_A_CNTL 0x21A4
293#define MC_VM_L1_TLB_MCD_WR_B_CNTL 0x21A8
294#define MC_VM_L1_TLB_MCB_WR_GFX_CNTL 0x2210
295#define MC_VM_L1_TLB_MCB_WR_HDP_CNTL 0x2218
296#define MC_VM_L1_TLB_MCB_WR_PDMA_CNTL 0x221C
297#define MC_VM_L1_TLB_MCB_WR_SEM_CNTL 0x2220
298#define MC_VM_L1_TLB_MCB_WR_SYS_CNTL 0x2214
299#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190
300#define LOGICAL_PAGE_NUMBER_MASK 0x000FFFFF
301#define LOGICAL_PAGE_NUMBER_SHIFT 0
302#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194
303#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198
304
305#define PA_CL_ENHANCE 0x8A14
306#define CLIP_VTX_REORDER_ENA (1 << 0)
307#define NUM_CLIP_SEQ(x) ((x) << 1)
308#define PA_SC_AA_CONFIG 0x28C04
309#define PA_SC_AA_SAMPLE_LOCS_2S 0x8B40
310#define PA_SC_AA_SAMPLE_LOCS_4S 0x8B44
311#define PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x8B48
312#define PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x8B4C
313#define S0_X(x) ((x) << 0)
314#define S0_Y(x) ((x) << 4)
315#define S1_X(x) ((x) << 8)
316#define S1_Y(x) ((x) << 12)
317#define S2_X(x) ((x) << 16)
318#define S2_Y(x) ((x) << 20)
319#define S3_X(x) ((x) << 24)
320#define S3_Y(x) ((x) << 28)
321#define S4_X(x) ((x) << 0)
322#define S4_Y(x) ((x) << 4)
323#define S5_X(x) ((x) << 8)
324#define S5_Y(x) ((x) << 12)
325#define S6_X(x) ((x) << 16)
326#define S6_Y(x) ((x) << 20)
327#define S7_X(x) ((x) << 24)
328#define S7_Y(x) ((x) << 28)
329#define PA_SC_CLIPRECT_RULE 0x2820c
330#define PA_SC_ENHANCE 0x8BF0
331#define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
332#define FORCE_EOV_MAX_TILE_CNT(x) ((x) << 12)
333#define PA_SC_LINE_STIPPLE 0x28A0C
334#define PA_SC_LINE_STIPPLE_STATE 0x8B10
335#define PA_SC_MODE_CNTL 0x28A4C
336#define PA_SC_MULTI_CHIP_CNTL 0x8B20
337
338#define PA_SC_SCREEN_SCISSOR_TL 0x28030
339#define PA_SC_GENERIC_SCISSOR_TL 0x28240
340#define PA_SC_WINDOW_SCISSOR_TL 0x28204
341
342#define PCIE_PORT_INDEX 0x0038
343#define PCIE_PORT_DATA 0x003C
344
345#define CHMAP 0x2004
346#define NOOFCHAN_SHIFT 12
347#define NOOFCHAN_MASK 0x00003000
348
349#define RAMCFG 0x2408
350#define NOOFBANK_SHIFT 0
351#define NOOFBANK_MASK 0x00000001
352#define NOOFRANK_SHIFT 1
353#define NOOFRANK_MASK 0x00000002
354#define NOOFROWS_SHIFT 2
355#define NOOFROWS_MASK 0x0000001C
356#define NOOFCOLS_SHIFT 5
357#define NOOFCOLS_MASK 0x00000060
358#define CHANSIZE_SHIFT 7
359#define CHANSIZE_MASK 0x00000080
360#define BURSTLENGTH_SHIFT 8
361#define BURSTLENGTH_MASK 0x00000100
362#define CHANSIZE_OVERRIDE (1 << 10)
363
364#define SCRATCH_REG0 0x8500
365#define SCRATCH_REG1 0x8504
366#define SCRATCH_REG2 0x8508
367#define SCRATCH_REG3 0x850C
368#define SCRATCH_REG4 0x8510
369#define SCRATCH_REG5 0x8514
370#define SCRATCH_REG6 0x8518
371#define SCRATCH_REG7 0x851C
372#define SCRATCH_UMSK 0x8540
373#define SCRATCH_ADDR 0x8544
374
375#define SPI_CONFIG_CNTL 0x9100
376#define GPR_WRITE_PRIORITY(x) ((x) << 0)
377#define DISABLE_INTERP_1 (1 << 5)
378#define SPI_CONFIG_CNTL_1 0x913C
379#define VTX_DONE_DELAY(x) ((x) << 0)
380#define INTERP_ONE_PRIM_PER_ROW (1 << 4)
381#define SPI_INPUT_Z 0x286D8
382#define SPI_PS_IN_CONTROL_0 0x286CC
383#define NUM_INTERP(x) ((x)<<0)
384#define POSITION_ENA (1<<8)
385#define POSITION_CENTROID (1<<9)
386#define POSITION_ADDR(x) ((x)<<10)
387#define PARAM_GEN(x) ((x)<<15)
388#define PARAM_GEN_ADDR(x) ((x)<<19)
389#define BARYC_SAMPLE_CNTL(x) ((x)<<26)
390#define PERSP_GRADIENT_ENA (1<<28)
391#define LINEAR_GRADIENT_ENA (1<<29)
392#define POSITION_SAMPLE (1<<30)
393#define BARYC_AT_SAMPLE_ENA (1<<31)
394#define SPI_PS_IN_CONTROL_1 0x286D0
395#define GEN_INDEX_PIX (1<<0)
396#define GEN_INDEX_PIX_ADDR(x) ((x)<<1)
397#define FRONT_FACE_ENA (1<<8)
398#define FRONT_FACE_CHAN(x) ((x)<<9)
399#define FRONT_FACE_ALL_BITS (1<<11)
400#define FRONT_FACE_ADDR(x) ((x)<<12)
401#define FOG_ADDR(x) ((x)<<17)
402#define FIXED_PT_POSITION_ENA (1<<24)
403#define FIXED_PT_POSITION_ADDR(x) ((x)<<25)
404
405#define SQ_MS_FIFO_SIZES 0x8CF0
406#define CACHE_FIFO_SIZE(x) ((x) << 0)
407#define FETCH_FIFO_HIWATER(x) ((x) << 8)
408#define DONE_FIFO_HIWATER(x) ((x) << 16)
409#define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24)
410#define SQ_PGM_START_ES 0x28880
411#define SQ_PGM_START_FS 0x28894
412#define SQ_PGM_START_GS 0x2886C
413#define SQ_PGM_START_PS 0x28840
414#define SQ_PGM_RESOURCES_PS 0x28850
415#define SQ_PGM_EXPORTS_PS 0x28854
416#define SQ_PGM_CF_OFFSET_PS 0x288cc
417#define SQ_PGM_START_VS 0x28858
418#define SQ_PGM_RESOURCES_VS 0x28868
419#define SQ_PGM_CF_OFFSET_VS 0x288d0
420#define SQ_VTX_CONSTANT_WORD6_0 0x38018
421#define S__SQ_VTX_CONSTANT_TYPE(x) (((x) & 3) << 30)
422#define G__SQ_VTX_CONSTANT_TYPE(x) (((x) >> 30) & 3)
423#define SQ_TEX_VTX_INVALID_TEXTURE 0x0
424#define SQ_TEX_VTX_INVALID_BUFFER 0x1
425#define SQ_TEX_VTX_VALID_TEXTURE 0x2
426#define SQ_TEX_VTX_VALID_BUFFER 0x3
427
428
429#define SX_MISC 0x28350
430#define SX_MEMORY_EXPORT_BASE 0x9010
431#define SX_DEBUG_1 0x9054
432#define SMX_EVENT_RELEASE (1 << 0)
433#define ENABLE_NEW_SMX_ADDRESS (1 << 16)
434
435#define TA_CNTL_AUX 0x9508
436#define DISABLE_CUBE_WRAP (1 << 0)
437#define DISABLE_CUBE_ANISO (1 << 1)
438#define SYNC_GRADIENT (1 << 24)
439#define SYNC_WALKER (1 << 25)
440#define SYNC_ALIGNER (1 << 26)
441#define BILINEAR_PRECISION_6_BIT (0 << 31)
442#define BILINEAR_PRECISION_8_BIT (1 << 31)
443
444#define TC_CNTL 0x9608
445#define TC_L2_SIZE(x) ((x)<<5)
446#define L2_DISABLE_LATE_HIT (1<<9)
447
448
449#define VGT_CACHE_INVALIDATION 0x88C4
450#define CACHE_INVALIDATION(x) ((x)<<0)
451#define VC_ONLY 0
452#define TC_ONLY 1
453#define VC_AND_TC 2
454#define VGT_DMA_BASE 0x287E8
455#define VGT_DMA_BASE_HI 0x287E4
456#define VGT_ES_PER_GS 0x88CC
457#define VGT_GS_PER_ES 0x88C8
458#define VGT_GS_PER_VS 0x88E8
459#define VGT_GS_VERTEX_REUSE 0x88D4
460#define VGT_PRIMITIVE_TYPE 0x8958
461#define VGT_NUM_INSTANCES 0x8974
462#define VGT_OUT_DEALLOC_CNTL 0x28C5C
463#define DEALLOC_DIST_MASK 0x0000007F
464#define VGT_STRMOUT_BASE_OFFSET_0 0x28B10
465#define VGT_STRMOUT_BASE_OFFSET_1 0x28B14
466#define VGT_STRMOUT_BASE_OFFSET_2 0x28B18
467#define VGT_STRMOUT_BASE_OFFSET_3 0x28B1c
468#define VGT_STRMOUT_BASE_OFFSET_HI_0 0x28B44
469#define VGT_STRMOUT_BASE_OFFSET_HI_1 0x28B48
470#define VGT_STRMOUT_BASE_OFFSET_HI_2 0x28B4c
471#define VGT_STRMOUT_BASE_OFFSET_HI_3 0x28B50
472#define VGT_STRMOUT_BUFFER_BASE_0 0x28AD8
473#define VGT_STRMOUT_BUFFER_BASE_1 0x28AE8
474#define VGT_STRMOUT_BUFFER_BASE_2 0x28AF8
475#define VGT_STRMOUT_BUFFER_BASE_3 0x28B08
476#define VGT_STRMOUT_BUFFER_OFFSET_0 0x28ADC
477#define VGT_STRMOUT_BUFFER_OFFSET_1 0x28AEC
478#define VGT_STRMOUT_BUFFER_OFFSET_2 0x28AFC
479#define VGT_STRMOUT_BUFFER_OFFSET_3 0x28B0C
480#define VGT_STRMOUT_EN 0x28AB0
481#define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58
482#define VTX_REUSE_DEPTH_MASK 0x000000FF
483#define VGT_EVENT_INITIATOR 0x28a90
484# define CACHE_FLUSH_AND_INV_EVENT_TS (0x14 << 0)
485# define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0)
486
487#define VM_CONTEXT0_CNTL 0x1410
488#define ENABLE_CONTEXT (1 << 0)
489#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
490#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
491#define VM_CONTEXT0_INVALIDATION_LOW_ADDR 0x1490
492#define VM_CONTEXT0_INVALIDATION_HIGH_ADDR 0x14B0
493#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x1574
494#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x1594
495#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x15B4
496#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1554
497#define VM_CONTEXT0_REQUEST_RESPONSE 0x1470
498#define REQUEST_TYPE(x) (((x) & 0xf) << 0)
499#define RESPONSE_TYPE_MASK 0x000000F0
500#define RESPONSE_TYPE_SHIFT 4
501#define VM_L2_CNTL 0x1400
502#define ENABLE_L2_CACHE (1 << 0)
503#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
504#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
505#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 13)
506#define VM_L2_CNTL2 0x1404
507#define INVALIDATE_ALL_L1_TLBS (1 << 0)
508#define INVALIDATE_L2_CACHE (1 << 1)
509#define VM_L2_CNTL3 0x1408
510#define BANK_SELECT_0(x) (((x) & 0x1f) << 0)
511#define BANK_SELECT_1(x) (((x) & 0x1f) << 5)
512#define L2_CACHE_UPDATE_MODE(x) (((x) & 3) << 10)
513#define VM_L2_STATUS 0x140C
514#define L2_BUSY (1 << 0)
515
516#define WAIT_UNTIL 0x8040
517#define WAIT_2D_IDLE_bit (1 << 14)
518#define WAIT_3D_IDLE_bit (1 << 15)
519#define WAIT_2D_IDLECLEAN_bit (1 << 16)
520#define WAIT_3D_IDLECLEAN_bit (1 << 17)
521
522#define IH_RB_CNTL 0x3e00
523# define IH_RB_ENABLE (1 << 0)
524# define IH_IB_SIZE(x) ((x) << 1) /* log2 */
525# define IH_RB_FULL_DRAIN_ENABLE (1 << 6)
526# define IH_WPTR_WRITEBACK_ENABLE (1 << 8)
527# define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */
528# define IH_WPTR_OVERFLOW_ENABLE (1 << 16)
529# define IH_WPTR_OVERFLOW_CLEAR (1 << 31)
530#define IH_RB_BASE 0x3e04
531#define IH_RB_RPTR 0x3e08
532#define IH_RB_WPTR 0x3e0c
533# define RB_OVERFLOW (1 << 0)
534# define WPTR_OFFSET_MASK 0x3fffc
535#define IH_RB_WPTR_ADDR_HI 0x3e10
536#define IH_RB_WPTR_ADDR_LO 0x3e14
537#define IH_CNTL 0x3e18
538# define ENABLE_INTR (1 << 0)
539# define IH_MC_SWAP(x) ((x) << 1)
540# define IH_MC_SWAP_NONE 0
541# define IH_MC_SWAP_16BIT 1
542# define IH_MC_SWAP_32BIT 2
543# define IH_MC_SWAP_64BIT 3
544# define RPTR_REARM (1 << 4)
545# define MC_WRREQ_CREDIT(x) ((x) << 15)
546# define MC_WR_CLEAN_CNT(x) ((x) << 20)
547
548#define RLC_CNTL 0x3f00
549# define RLC_ENABLE (1 << 0)
550#define RLC_HB_BASE 0x3f10
551#define RLC_HB_CNTL 0x3f0c
552#define RLC_HB_RPTR 0x3f20
553#define RLC_HB_WPTR 0x3f1c
554#define RLC_HB_WPTR_LSB_ADDR 0x3f14
555#define RLC_HB_WPTR_MSB_ADDR 0x3f18
556#define RLC_MC_CNTL 0x3f44
557#define RLC_UCODE_CNTL 0x3f48
558#define RLC_UCODE_ADDR 0x3f2c
559#define RLC_UCODE_DATA 0x3f30
560
561#define SRBM_SOFT_RESET 0xe60
562# define SOFT_RESET_RLC (1 << 13)
563
564#define CP_INT_CNTL 0xc124
565# define CNTX_BUSY_INT_ENABLE (1 << 19)
566# define CNTX_EMPTY_INT_ENABLE (1 << 20)
567# define SCRATCH_INT_ENABLE (1 << 25)
568# define TIME_STAMP_INT_ENABLE (1 << 26)
569# define IB2_INT_ENABLE (1 << 29)
570# define IB1_INT_ENABLE (1 << 30)
571# define RB_INT_ENABLE (1 << 31)
572#define CP_INT_STATUS 0xc128
573# define SCRATCH_INT_STAT (1 << 25)
574# define TIME_STAMP_INT_STAT (1 << 26)
575# define IB2_INT_STAT (1 << 29)
576# define IB1_INT_STAT (1 << 30)
577# define RB_INT_STAT (1 << 31)
578
579#define GRBM_INT_CNTL 0x8060
580# define RDERR_INT_ENABLE (1 << 0)
581# define WAIT_COUNT_TIMEOUT_INT_ENABLE (1 << 1)
582# define GUI_IDLE_INT_ENABLE (1 << 19)
583
584#define INTERRUPT_CNTL 0x5468
585# define IH_DUMMY_RD_OVERRIDE (1 << 0)
586# define IH_DUMMY_RD_EN (1 << 1)
587# define IH_REQ_NONSNOOP_EN (1 << 3)
588# define GEN_IH_INT_EN (1 << 8)
589#define INTERRUPT_CNTL2 0x546c
590
591#define D1MODE_VBLANK_STATUS 0x6534
592#define D2MODE_VBLANK_STATUS 0x6d34
593# define DxMODE_VBLANK_OCCURRED (1 << 0)
594# define DxMODE_VBLANK_ACK (1 << 4)
595# define DxMODE_VBLANK_STAT (1 << 12)
596# define DxMODE_VBLANK_INTERRUPT (1 << 16)
597# define DxMODE_VBLANK_INTERRUPT_TYPE (1 << 17)
598#define D1MODE_VLINE_STATUS 0x653c
599#define D2MODE_VLINE_STATUS 0x6d3c
600# define DxMODE_VLINE_OCCURRED (1 << 0)
601# define DxMODE_VLINE_ACK (1 << 4)
602# define DxMODE_VLINE_STAT (1 << 12)
603# define DxMODE_VLINE_INTERRUPT (1 << 16)
604# define DxMODE_VLINE_INTERRUPT_TYPE (1 << 17)
605#define DxMODE_INT_MASK 0x6540
606# define D1MODE_VBLANK_INT_MASK (1 << 0)
607# define D1MODE_VLINE_INT_MASK (1 << 4)
608# define D2MODE_VBLANK_INT_MASK (1 << 8)
609# define D2MODE_VLINE_INT_MASK (1 << 12)
610#define DCE3_DISP_INTERRUPT_STATUS 0x7ddc
611# define DC_HPD1_INTERRUPT (1 << 18)
612# define DC_HPD2_INTERRUPT (1 << 19)
613#define DISP_INTERRUPT_STATUS 0x7edc
614# define LB_D1_VLINE_INTERRUPT (1 << 2)
615# define LB_D2_VLINE_INTERRUPT (1 << 3)
616# define LB_D1_VBLANK_INTERRUPT (1 << 4)
617# define LB_D2_VBLANK_INTERRUPT (1 << 5)
618# define DACA_AUTODETECT_INTERRUPT (1 << 16)
619# define DACB_AUTODETECT_INTERRUPT (1 << 17)
620# define DC_HOT_PLUG_DETECT1_INTERRUPT (1 << 18)
621# define DC_HOT_PLUG_DETECT2_INTERRUPT (1 << 19)
622# define DC_I2C_SW_DONE_INTERRUPT (1 << 20)
623# define DC_I2C_HW_DONE_INTERRUPT (1 << 21)
624#define DISP_INTERRUPT_STATUS_CONTINUE 0x7ee8
625#define DCE3_DISP_INTERRUPT_STATUS_CONTINUE 0x7de8
626# define DC_HPD4_INTERRUPT (1 << 14)
627# define DC_HPD4_RX_INTERRUPT (1 << 15)
628# define DC_HPD3_INTERRUPT (1 << 28)
629# define DC_HPD1_RX_INTERRUPT (1 << 29)
630# define DC_HPD2_RX_INTERRUPT (1 << 30)
631#define DCE3_DISP_INTERRUPT_STATUS_CONTINUE2 0x7dec
632# define DC_HPD3_RX_INTERRUPT (1 << 0)
633# define DIGA_DP_VID_STREAM_DISABLE_INTERRUPT (1 << 1)
634# define DIGA_DP_STEER_FIFO_OVERFLOW_INTERRUPT (1 << 2)
635# define DIGB_DP_VID_STREAM_DISABLE_INTERRUPT (1 << 3)
636# define DIGB_DP_STEER_FIFO_OVERFLOW_INTERRUPT (1 << 4)
637# define AUX1_SW_DONE_INTERRUPT (1 << 5)
638# define AUX1_LS_DONE_INTERRUPT (1 << 6)
639# define AUX2_SW_DONE_INTERRUPT (1 << 7)
640# define AUX2_LS_DONE_INTERRUPT (1 << 8)
641# define AUX3_SW_DONE_INTERRUPT (1 << 9)
642# define AUX3_LS_DONE_INTERRUPT (1 << 10)
643# define AUX4_SW_DONE_INTERRUPT (1 << 11)
644# define AUX4_LS_DONE_INTERRUPT (1 << 12)
645# define DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT (1 << 13)
646# define DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT (1 << 14)
647/* DCE 3.2 */
648# define AUX5_SW_DONE_INTERRUPT (1 << 15)
649# define AUX5_LS_DONE_INTERRUPT (1 << 16)
650# define AUX6_SW_DONE_INTERRUPT (1 << 17)
651# define AUX6_LS_DONE_INTERRUPT (1 << 18)
652# define DC_HPD5_INTERRUPT (1 << 19)
653# define DC_HPD5_RX_INTERRUPT (1 << 20)
654# define DC_HPD6_INTERRUPT (1 << 21)
655# define DC_HPD6_RX_INTERRUPT (1 << 22)
656
657#define DACA_AUTO_DETECT_CONTROL 0x7828
658#define DACB_AUTO_DETECT_CONTROL 0x7a28
659#define DCE3_DACA_AUTO_DETECT_CONTROL 0x7028
660#define DCE3_DACB_AUTO_DETECT_CONTROL 0x7128
661# define DACx_AUTODETECT_MODE(x) ((x) << 0)
662# define DACx_AUTODETECT_MODE_NONE 0
663# define DACx_AUTODETECT_MODE_CONNECT 1
664# define DACx_AUTODETECT_MODE_DISCONNECT 2
665# define DACx_AUTODETECT_FRAME_TIME_COUNTER(x) ((x) << 8)
666/* bit 18 = R/C, 17 = G/Y, 16 = B/Comp */
667# define DACx_AUTODETECT_CHECK_MASK(x) ((x) << 16)
668
669#define DCE3_DACA_AUTODETECT_INT_CONTROL 0x7038
670#define DCE3_DACB_AUTODETECT_INT_CONTROL 0x7138
671#define DACA_AUTODETECT_INT_CONTROL 0x7838
672#define DACB_AUTODETECT_INT_CONTROL 0x7a38
673# define DACx_AUTODETECT_ACK (1 << 0)
674# define DACx_AUTODETECT_INT_ENABLE (1 << 16)
675
676#define DC_HOT_PLUG_DETECT1_CONTROL 0x7d00
677#define DC_HOT_PLUG_DETECT2_CONTROL 0x7d10
678#define DC_HOT_PLUG_DETECT3_CONTROL 0x7d24
679# define DC_HOT_PLUG_DETECTx_EN (1 << 0)
680
681#define DC_HOT_PLUG_DETECT1_INT_STATUS 0x7d04
682#define DC_HOT_PLUG_DETECT2_INT_STATUS 0x7d14
683#define DC_HOT_PLUG_DETECT3_INT_STATUS 0x7d28
684# define DC_HOT_PLUG_DETECTx_INT_STATUS (1 << 0)
685# define DC_HOT_PLUG_DETECTx_SENSE (1 << 1)
686
687/* DCE 3.0 */
688#define DC_HPD1_INT_STATUS 0x7d00
689#define DC_HPD2_INT_STATUS 0x7d0c
690#define DC_HPD3_INT_STATUS 0x7d18
691#define DC_HPD4_INT_STATUS 0x7d24
692/* DCE 3.2 */
693#define DC_HPD5_INT_STATUS 0x7dc0
694#define DC_HPD6_INT_STATUS 0x7df4
695# define DC_HPDx_INT_STATUS (1 << 0)
696# define DC_HPDx_SENSE (1 << 1)
697# define DC_HPDx_RX_INT_STATUS (1 << 8)
698
699#define DC_HOT_PLUG_DETECT1_INT_CONTROL 0x7d08
700#define DC_HOT_PLUG_DETECT2_INT_CONTROL 0x7d18
701#define DC_HOT_PLUG_DETECT3_INT_CONTROL 0x7d2c
702# define DC_HOT_PLUG_DETECTx_INT_ACK (1 << 0)
703# define DC_HOT_PLUG_DETECTx_INT_POLARITY (1 << 8)
704# define DC_HOT_PLUG_DETECTx_INT_EN (1 << 16)
705/* DCE 3.0 */
706#define DC_HPD1_INT_CONTROL 0x7d04
707#define DC_HPD2_INT_CONTROL 0x7d10
708#define DC_HPD3_INT_CONTROL 0x7d1c
709#define DC_HPD4_INT_CONTROL 0x7d28
710/* DCE 3.2 */
711#define DC_HPD5_INT_CONTROL 0x7dc4
712#define DC_HPD6_INT_CONTROL 0x7df8
713# define DC_HPDx_INT_ACK (1 << 0)
714# define DC_HPDx_INT_POLARITY (1 << 8)
715# define DC_HPDx_INT_EN (1 << 16)
716# define DC_HPDx_RX_INT_ACK (1 << 20)
717# define DC_HPDx_RX_INT_EN (1 << 24)
718
719/* DCE 3.0 */
720#define DC_HPD1_CONTROL 0x7d08
721#define DC_HPD2_CONTROL 0x7d14
722#define DC_HPD3_CONTROL 0x7d20
723#define DC_HPD4_CONTROL 0x7d2c
724/* DCE 3.2 */
725#define DC_HPD5_CONTROL 0x7dc8
726#define DC_HPD6_CONTROL 0x7dfc
727# define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0)
728# define DC_HPDx_RX_INT_TIMER(x) ((x) << 16)
729/* DCE 3.2 */
730# define DC_HPDx_EN (1 << 28)
731
732#define D1GRPH_INTERRUPT_STATUS 0x6158
733#define D2GRPH_INTERRUPT_STATUS 0x6958
734# define DxGRPH_PFLIP_INT_OCCURRED (1 << 0)
735# define DxGRPH_PFLIP_INT_CLEAR (1 << 8)
736#define D1GRPH_INTERRUPT_CONTROL 0x615c
737#define D2GRPH_INTERRUPT_CONTROL 0x695c
738# define DxGRPH_PFLIP_INT_MASK (1 << 0)
739# define DxGRPH_PFLIP_INT_TYPE (1 << 8)
740
741/* PCIE link stuff */
742#define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */
743# define LC_POINT_7_PLUS_EN (1 << 6)
744#define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */
745# define LC_LINK_WIDTH_SHIFT 0
746# define LC_LINK_WIDTH_MASK 0x7
747# define LC_LINK_WIDTH_X0 0
748# define LC_LINK_WIDTH_X1 1
749# define LC_LINK_WIDTH_X2 2
750# define LC_LINK_WIDTH_X4 3
751# define LC_LINK_WIDTH_X8 4
752# define LC_LINK_WIDTH_X16 6
753# define LC_LINK_WIDTH_RD_SHIFT 4
754# define LC_LINK_WIDTH_RD_MASK 0x70
755# define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
756# define LC_RECONFIG_NOW (1 << 8)
757# define LC_RENEGOTIATION_SUPPORT (1 << 9)
758# define LC_RENEGOTIATE_EN (1 << 10)
759# define LC_SHORT_RECONFIG_EN (1 << 11)
760# define LC_UPCONFIGURE_SUPPORT (1 << 12)
761# define LC_UPCONFIGURE_DIS (1 << 13)
762#define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */
763# define LC_GEN2_EN_STRAP (1 << 0)
764# define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1)
765# define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5)
766# define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6)
767# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8)
768# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3
769# define LC_CURRENT_DATA_RATE (1 << 11)
770# define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14)
771# define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21)
772# define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23)
773# define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24)
774#define MM_CFGREGS_CNTL 0x544c
775# define MM_WR_TO_CFG_EN (1 << 3)
776#define LINK_CNTL2 0x88 /* F0 */
777# define TARGET_LINK_SPEED_MASK (0xf << 0)
778# define SELECTABLE_DEEMPHASIS (1 << 6)
779
780/*
781 * PM4
782 */
783#define PACKET_TYPE0 0
784#define PACKET_TYPE1 1
785#define PACKET_TYPE2 2
786#define PACKET_TYPE3 3
787
788#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
789#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
790#define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)
791#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
792#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
793 (((reg) >> 2) & 0xFFFF) | \
794 ((n) & 0x3FFF) << 16)
795#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
796 (((op) & 0xFF) << 8) | \
797 ((n) & 0x3FFF) << 16)
798
799/* Packet 3 types */
800#define PACKET3_NOP 0x10
801#define PACKET3_INDIRECT_BUFFER_END 0x17
802#define PACKET3_SET_PREDICATION 0x20
803#define PACKET3_REG_RMW 0x21
804#define PACKET3_COND_EXEC 0x22
805#define PACKET3_PRED_EXEC 0x23
806#define PACKET3_START_3D_CMDBUF 0x24
807#define PACKET3_DRAW_INDEX_2 0x27
808#define PACKET3_CONTEXT_CONTROL 0x28
809#define PACKET3_DRAW_INDEX_IMMD_BE 0x29
810#define PACKET3_INDEX_TYPE 0x2A
811#define PACKET3_DRAW_INDEX 0x2B
812#define PACKET3_DRAW_INDEX_AUTO 0x2D
813#define PACKET3_DRAW_INDEX_IMMD 0x2E
814#define PACKET3_NUM_INSTANCES 0x2F
815#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
816#define PACKET3_INDIRECT_BUFFER_MP 0x38
817#define PACKET3_MEM_SEMAPHORE 0x39
818#define PACKET3_MPEG_INDEX 0x3A
819#define PACKET3_WAIT_REG_MEM 0x3C
820#define PACKET3_MEM_WRITE 0x3D
821#define PACKET3_INDIRECT_BUFFER 0x32
822#define PACKET3_SURFACE_SYNC 0x43
823# define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
824# define PACKET3_TC_ACTION_ENA (1 << 23)
825# define PACKET3_VC_ACTION_ENA (1 << 24)
826# define PACKET3_CB_ACTION_ENA (1 << 25)
827# define PACKET3_DB_ACTION_ENA (1 << 26)
828# define PACKET3_SH_ACTION_ENA (1 << 27)
829# define PACKET3_SMX_ACTION_ENA (1 << 28)
830#define PACKET3_ME_INITIALIZE 0x44
831#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
832#define PACKET3_COND_WRITE 0x45
833#define PACKET3_EVENT_WRITE 0x46
834#define EVENT_TYPE(x) ((x) << 0)
835#define EVENT_INDEX(x) ((x) << 8)
836 /* 0 - any non-TS event
837 * 1 - ZPASS_DONE
838 * 2 - SAMPLE_PIPELINESTAT
839 * 3 - SAMPLE_STREAMOUTSTAT*
840 * 4 - *S_PARTIAL_FLUSH
841 * 5 - TS events
842 */
843#define PACKET3_EVENT_WRITE_EOP 0x47
844#define DATA_SEL(x) ((x) << 29)
845 /* 0 - discard
846 * 1 - send low 32bit data
847 * 2 - send 64bit data
848 * 3 - send 64bit counter value
849 */
850#define INT_SEL(x) ((x) << 24)
851 /* 0 - none
852 * 1 - interrupt only (DATA_SEL = 0)
853 * 2 - interrupt when data write is confirmed
854 */
855#define PACKET3_ONE_REG_WRITE 0x57
856#define PACKET3_SET_CONFIG_REG 0x68
857#define PACKET3_SET_CONFIG_REG_OFFSET 0x00008000
858#define PACKET3_SET_CONFIG_REG_END 0x0000ac00
859#define PACKET3_SET_CONTEXT_REG 0x69
860#define PACKET3_SET_CONTEXT_REG_OFFSET 0x00028000
861#define PACKET3_SET_CONTEXT_REG_END 0x00029000
862#define PACKET3_SET_ALU_CONST 0x6A
863#define PACKET3_SET_ALU_CONST_OFFSET 0x00030000
864#define PACKET3_SET_ALU_CONST_END 0x00032000
865#define PACKET3_SET_BOOL_CONST 0x6B
866#define PACKET3_SET_BOOL_CONST_OFFSET 0x0003e380
867#define PACKET3_SET_BOOL_CONST_END 0x00040000
868#define PACKET3_SET_LOOP_CONST 0x6C
869#define PACKET3_SET_LOOP_CONST_OFFSET 0x0003e200
870#define PACKET3_SET_LOOP_CONST_END 0x0003e380
871#define PACKET3_SET_RESOURCE 0x6D
872#define PACKET3_SET_RESOURCE_OFFSET 0x00038000
873#define PACKET3_SET_RESOURCE_END 0x0003c000
874#define PACKET3_SET_SAMPLER 0x6E
875#define PACKET3_SET_SAMPLER_OFFSET 0x0003c000
876#define PACKET3_SET_SAMPLER_END 0x0003cff0
877#define PACKET3_SET_CTL_CONST 0x6F
878#define PACKET3_SET_CTL_CONST_OFFSET 0x0003cff0
879#define PACKET3_SET_CTL_CONST_END 0x0003e200
880#define PACKET3_SURFACE_BASE_UPDATE 0x73
881
882
883#define R_008020_GRBM_SOFT_RESET 0x8020
884#define S_008020_SOFT_RESET_CP(x) (((x) & 1) << 0)
885#define S_008020_SOFT_RESET_CB(x) (((x) & 1) << 1)
886#define S_008020_SOFT_RESET_CR(x) (((x) & 1) << 2)
887#define S_008020_SOFT_RESET_DB(x) (((x) & 1) << 3)
888#define S_008020_SOFT_RESET_PA(x) (((x) & 1) << 5)
889#define S_008020_SOFT_RESET_SC(x) (((x) & 1) << 6)
890#define S_008020_SOFT_RESET_SMX(x) (((x) & 1) << 7)
891#define S_008020_SOFT_RESET_SPI(x) (((x) & 1) << 8)
892#define S_008020_SOFT_RESET_SH(x) (((x) & 1) << 9)
893#define S_008020_SOFT_RESET_SX(x) (((x) & 1) << 10)
894#define S_008020_SOFT_RESET_TC(x) (((x) & 1) << 11)
895#define S_008020_SOFT_RESET_TA(x) (((x) & 1) << 12)
896#define S_008020_SOFT_RESET_VC(x) (((x) & 1) << 13)
897#define S_008020_SOFT_RESET_VGT(x) (((x) & 1) << 14)
898#define R_008010_GRBM_STATUS 0x8010
899#define S_008010_CMDFIFO_AVAIL(x) (((x) & 0x1F) << 0)
900#define S_008010_CP_RQ_PENDING(x) (((x) & 1) << 6)
901#define S_008010_CF_RQ_PENDING(x) (((x) & 1) << 7)
902#define S_008010_PF_RQ_PENDING(x) (((x) & 1) << 8)
903#define S_008010_GRBM_EE_BUSY(x) (((x) & 1) << 10)
904#define S_008010_VC_BUSY(x) (((x) & 1) << 11)
905#define S_008010_DB03_CLEAN(x) (((x) & 1) << 12)
906#define S_008010_CB03_CLEAN(x) (((x) & 1) << 13)
907#define S_008010_VGT_BUSY_NO_DMA(x) (((x) & 1) << 16)
908#define S_008010_VGT_BUSY(x) (((x) & 1) << 17)
909#define S_008010_TA03_BUSY(x) (((x) & 1) << 18)
910#define S_008010_TC_BUSY(x) (((x) & 1) << 19)
911#define S_008010_SX_BUSY(x) (((x) & 1) << 20)
912#define S_008010_SH_BUSY(x) (((x) & 1) << 21)
913#define S_008010_SPI03_BUSY(x) (((x) & 1) << 22)
914#define S_008010_SMX_BUSY(x) (((x) & 1) << 23)
915#define S_008010_SC_BUSY(x) (((x) & 1) << 24)
916#define S_008010_PA_BUSY(x) (((x) & 1) << 25)
917#define S_008010_DB03_BUSY(x) (((x) & 1) << 26)
918#define S_008010_CR_BUSY(x) (((x) & 1) << 27)
919#define S_008010_CP_COHERENCY_BUSY(x) (((x) & 1) << 28)
920#define S_008010_CP_BUSY(x) (((x) & 1) << 29)
921#define S_008010_CB03_BUSY(x) (((x) & 1) << 30)
922#define S_008010_GUI_ACTIVE(x) (((x) & 1) << 31)
923#define G_008010_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x1F)
924#define G_008010_CP_RQ_PENDING(x) (((x) >> 6) & 1)
925#define G_008010_CF_RQ_PENDING(x) (((x) >> 7) & 1)
926#define G_008010_PF_RQ_PENDING(x) (((x) >> 8) & 1)
927#define G_008010_GRBM_EE_BUSY(x) (((x) >> 10) & 1)
928#define G_008010_VC_BUSY(x) (((x) >> 11) & 1)
929#define G_008010_DB03_CLEAN(x) (((x) >> 12) & 1)
930#define G_008010_CB03_CLEAN(x) (((x) >> 13) & 1)
931#define G_008010_VGT_BUSY_NO_DMA(x) (((x) >> 16) & 1)
932#define G_008010_VGT_BUSY(x) (((x) >> 17) & 1)
933#define G_008010_TA03_BUSY(x) (((x) >> 18) & 1)
934#define G_008010_TC_BUSY(x) (((x) >> 19) & 1)
935#define G_008010_SX_BUSY(x) (((x) >> 20) & 1)
936#define G_008010_SH_BUSY(x) (((x) >> 21) & 1)
937#define G_008010_SPI03_BUSY(x) (((x) >> 22) & 1)
938#define G_008010_SMX_BUSY(x) (((x) >> 23) & 1)
939#define G_008010_SC_BUSY(x) (((x) >> 24) & 1)
940#define G_008010_PA_BUSY(x) (((x) >> 25) & 1)
941#define G_008010_DB03_BUSY(x) (((x) >> 26) & 1)
942#define G_008010_CR_BUSY(x) (((x) >> 27) & 1)
943#define G_008010_CP_COHERENCY_BUSY(x) (((x) >> 28) & 1)
944#define G_008010_CP_BUSY(x) (((x) >> 29) & 1)
945#define G_008010_CB03_BUSY(x) (((x) >> 30) & 1)
946#define G_008010_GUI_ACTIVE(x) (((x) >> 31) & 1)
947#define R_008014_GRBM_STATUS2 0x8014
948#define S_008014_CR_CLEAN(x) (((x) & 1) << 0)
949#define S_008014_SMX_CLEAN(x) (((x) & 1) << 1)
950#define S_008014_SPI0_BUSY(x) (((x) & 1) << 8)
951#define S_008014_SPI1_BUSY(x) (((x) & 1) << 9)
952#define S_008014_SPI2_BUSY(x) (((x) & 1) << 10)
953#define S_008014_SPI3_BUSY(x) (((x) & 1) << 11)
954#define S_008014_TA0_BUSY(x) (((x) & 1) << 12)
955#define S_008014_TA1_BUSY(x) (((x) & 1) << 13)
956#define S_008014_TA2_BUSY(x) (((x) & 1) << 14)
957#define S_008014_TA3_BUSY(x) (((x) & 1) << 15)
958#define S_008014_DB0_BUSY(x) (((x) & 1) << 16)
959#define S_008014_DB1_BUSY(x) (((x) & 1) << 17)
960#define S_008014_DB2_BUSY(x) (((x) & 1) << 18)
961#define S_008014_DB3_BUSY(x) (((x) & 1) << 19)
962#define S_008014_CB0_BUSY(x) (((x) & 1) << 20)
963#define S_008014_CB1_BUSY(x) (((x) & 1) << 21)
964#define S_008014_CB2_BUSY(x) (((x) & 1) << 22)
965#define S_008014_CB3_BUSY(x) (((x) & 1) << 23)
966#define G_008014_CR_CLEAN(x) (((x) >> 0) & 1)
967#define G_008014_SMX_CLEAN(x) (((x) >> 1) & 1)
968#define G_008014_SPI0_BUSY(x) (((x) >> 8) & 1)
969#define G_008014_SPI1_BUSY(x) (((x) >> 9) & 1)
970#define G_008014_SPI2_BUSY(x) (((x) >> 10) & 1)
971#define G_008014_SPI3_BUSY(x) (((x) >> 11) & 1)
972#define G_008014_TA0_BUSY(x) (((x) >> 12) & 1)
973#define G_008014_TA1_BUSY(x) (((x) >> 13) & 1)
974#define G_008014_TA2_BUSY(x) (((x) >> 14) & 1)
975#define G_008014_TA3_BUSY(x) (((x) >> 15) & 1)
976#define G_008014_DB0_BUSY(x) (((x) >> 16) & 1)
977#define G_008014_DB1_BUSY(x) (((x) >> 17) & 1)
978#define G_008014_DB2_BUSY(x) (((x) >> 18) & 1)
979#define G_008014_DB3_BUSY(x) (((x) >> 19) & 1)
980#define G_008014_CB0_BUSY(x) (((x) >> 20) & 1)
981#define G_008014_CB1_BUSY(x) (((x) >> 21) & 1)
982#define G_008014_CB2_BUSY(x) (((x) >> 22) & 1)
983#define G_008014_CB3_BUSY(x) (((x) >> 23) & 1)
984#define R_000E50_SRBM_STATUS 0x0E50
985#define G_000E50_RLC_RQ_PENDING(x) (((x) >> 3) & 1)
986#define G_000E50_RCU_RQ_PENDING(x) (((x) >> 4) & 1)
987#define G_000E50_GRBM_RQ_PENDING(x) (((x) >> 5) & 1)
988#define G_000E50_HI_RQ_PENDING(x) (((x) >> 6) & 1)
989#define G_000E50_IO_EXTERN_SIGNAL(x) (((x) >> 7) & 1)
990#define G_000E50_VMC_BUSY(x) (((x) >> 8) & 1)
991#define G_000E50_MCB_BUSY(x) (((x) >> 9) & 1)
992#define G_000E50_MCDZ_BUSY(x) (((x) >> 10) & 1)
993#define G_000E50_MCDY_BUSY(x) (((x) >> 11) & 1)
994#define G_000E50_MCDX_BUSY(x) (((x) >> 12) & 1)
995#define G_000E50_MCDW_BUSY(x) (((x) >> 13) & 1)
996#define G_000E50_SEM_BUSY(x) (((x) >> 14) & 1)
997#define G_000E50_RLC_BUSY(x) (((x) >> 15) & 1)
998#define G_000E50_BIF_BUSY(x) (((x) >> 29) & 1)
999#define R_000E60_SRBM_SOFT_RESET 0x0E60
1000#define S_000E60_SOFT_RESET_BIF(x) (((x) & 1) << 1)
1001#define S_000E60_SOFT_RESET_CG(x) (((x) & 1) << 2)
1002#define S_000E60_SOFT_RESET_CMC(x) (((x) & 1) << 3)
1003#define S_000E60_SOFT_RESET_CSC(x) (((x) & 1) << 4)
1004#define S_000E60_SOFT_RESET_DC(x) (((x) & 1) << 5)
1005#define S_000E60_SOFT_RESET_GRBM(x) (((x) & 1) << 8)
1006#define S_000E60_SOFT_RESET_HDP(x) (((x) & 1) << 9)
1007#define S_000E60_SOFT_RESET_IH(x) (((x) & 1) << 10)
1008#define S_000E60_SOFT_RESET_MC(x) (((x) & 1) << 11)
1009#define S_000E60_SOFT_RESET_RLC(x) (((x) & 1) << 13)
1010#define S_000E60_SOFT_RESET_ROM(x) (((x) & 1) << 14)
1011#define S_000E60_SOFT_RESET_SEM(x) (((x) & 1) << 15)
1012#define S_000E60_SOFT_RESET_TSC(x) (((x) & 1) << 16)
1013#define S_000E60_SOFT_RESET_VMC(x) (((x) & 1) << 17)
1014
1015#define R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480
1016
1017#define R_028C04_PA_SC_AA_CONFIG 0x028C04
1018#define S_028C04_MSAA_NUM_SAMPLES(x) (((x) & 0x3) << 0)
1019#define G_028C04_MSAA_NUM_SAMPLES(x) (((x) >> 0) & 0x3)
1020#define C_028C04_MSAA_NUM_SAMPLES 0xFFFFFFFC
1021#define S_028C04_AA_MASK_CENTROID_DTMN(x) (((x) & 0x1) << 4)
1022#define G_028C04_AA_MASK_CENTROID_DTMN(x) (((x) >> 4) & 0x1)
1023#define C_028C04_AA_MASK_CENTROID_DTMN 0xFFFFFFEF
1024#define S_028C04_MAX_SAMPLE_DIST(x) (((x) & 0xF) << 13)
1025#define G_028C04_MAX_SAMPLE_DIST(x) (((x) >> 13) & 0xF)
1026#define C_028C04_MAX_SAMPLE_DIST 0xFFFE1FFF
1027#define R_0280E0_CB_COLOR0_FRAG 0x0280E0
1028#define S_0280E0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0)
1029#define G_0280E0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF)
1030#define C_0280E0_BASE_256B 0x00000000
1031#define R_0280E4_CB_COLOR1_FRAG 0x0280E4
1032#define R_0280E8_CB_COLOR2_FRAG 0x0280E8
1033#define R_0280EC_CB_COLOR3_FRAG 0x0280EC
1034#define R_0280F0_CB_COLOR4_FRAG 0x0280F0
1035#define R_0280F4_CB_COLOR5_FRAG 0x0280F4
1036#define R_0280F8_CB_COLOR6_FRAG 0x0280F8
1037#define R_0280FC_CB_COLOR7_FRAG 0x0280FC
1038#define R_0280C0_CB_COLOR0_TILE 0x0280C0
1039#define S_0280C0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0)
1040#define G_0280C0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF)
1041#define C_0280C0_BASE_256B 0x00000000
1042#define R_0280C4_CB_COLOR1_TILE 0x0280C4
1043#define R_0280C8_CB_COLOR2_TILE 0x0280C8
1044#define R_0280CC_CB_COLOR3_TILE 0x0280CC
1045#define R_0280D0_CB_COLOR4_TILE 0x0280D0
1046#define R_0280D4_CB_COLOR5_TILE 0x0280D4
1047#define R_0280D8_CB_COLOR6_TILE 0x0280D8
1048#define R_0280DC_CB_COLOR7_TILE 0x0280DC
1049#define R_0280A0_CB_COLOR0_INFO 0x0280A0
1050#define S_0280A0_ENDIAN(x) (((x) & 0x3) << 0)
1051#define G_0280A0_ENDIAN(x) (((x) >> 0) & 0x3)
1052#define C_0280A0_ENDIAN 0xFFFFFFFC
1053#define S_0280A0_FORMAT(x) (((x) & 0x3F) << 2)
1054#define G_0280A0_FORMAT(x) (((x) >> 2) & 0x3F)
1055#define C_0280A0_FORMAT 0xFFFFFF03
1056#define V_0280A0_COLOR_INVALID 0x00000000
1057#define V_0280A0_COLOR_8 0x00000001
1058#define V_0280A0_COLOR_4_4 0x00000002
1059#define V_0280A0_COLOR_3_3_2 0x00000003
1060#define V_0280A0_COLOR_16 0x00000005
1061#define V_0280A0_COLOR_16_FLOAT 0x00000006
1062#define V_0280A0_COLOR_8_8 0x00000007
1063#define V_0280A0_COLOR_5_6_5 0x00000008
1064#define V_0280A0_COLOR_6_5_5 0x00000009
1065#define V_0280A0_COLOR_1_5_5_5 0x0000000A
1066#define V_0280A0_COLOR_4_4_4_4 0x0000000B
1067#define V_0280A0_COLOR_5_5_5_1 0x0000000C
1068#define V_0280A0_COLOR_32 0x0000000D
1069#define V_0280A0_COLOR_32_FLOAT 0x0000000E
1070#define V_0280A0_COLOR_16_16 0x0000000F
1071#define V_0280A0_COLOR_16_16_FLOAT 0x00000010
1072#define V_0280A0_COLOR_8_24 0x00000011
1073#define V_0280A0_COLOR_8_24_FLOAT 0x00000012
1074#define V_0280A0_COLOR_24_8 0x00000013
1075#define V_0280A0_COLOR_24_8_FLOAT 0x00000014
1076#define V_0280A0_COLOR_10_11_11 0x00000015
1077#define V_0280A0_COLOR_10_11_11_FLOAT 0x00000016
1078#define V_0280A0_COLOR_11_11_10 0x00000017
1079#define V_0280A0_COLOR_11_11_10_FLOAT 0x00000018
1080#define V_0280A0_COLOR_2_10_10_10 0x00000019
1081#define V_0280A0_COLOR_8_8_8_8 0x0000001A
1082#define V_0280A0_COLOR_10_10_10_2 0x0000001B
1083#define V_0280A0_COLOR_X24_8_32_FLOAT 0x0000001C
1084#define V_0280A0_COLOR_32_32 0x0000001D
1085#define V_0280A0_COLOR_32_32_FLOAT 0x0000001E
1086#define V_0280A0_COLOR_16_16_16_16 0x0000001F
1087#define V_0280A0_COLOR_16_16_16_16_FLOAT 0x00000020
1088#define V_0280A0_COLOR_32_32_32_32 0x00000022
1089#define V_0280A0_COLOR_32_32_32_32_FLOAT 0x00000023
1090#define S_0280A0_ARRAY_MODE(x) (((x) & 0xF) << 8)
1091#define G_0280A0_ARRAY_MODE(x) (((x) >> 8) & 0xF)
1092#define C_0280A0_ARRAY_MODE 0xFFFFF0FF
1093#define V_0280A0_ARRAY_LINEAR_GENERAL 0x00000000
1094#define V_0280A0_ARRAY_LINEAR_ALIGNED 0x00000001
1095#define V_0280A0_ARRAY_1D_TILED_THIN1 0x00000002
1096#define V_0280A0_ARRAY_2D_TILED_THIN1 0x00000004
1097#define S_0280A0_NUMBER_TYPE(x) (((x) & 0x7) << 12)
1098#define G_0280A0_NUMBER_TYPE(x) (((x) >> 12) & 0x7)
1099#define C_0280A0_NUMBER_TYPE 0xFFFF8FFF
1100#define S_0280A0_READ_SIZE(x) (((x) & 0x1) << 15)
1101#define G_0280A0_READ_SIZE(x) (((x) >> 15) & 0x1)
1102#define C_0280A0_READ_SIZE 0xFFFF7FFF
1103#define S_0280A0_COMP_SWAP(x) (((x) & 0x3) << 16)
1104#define G_0280A0_COMP_SWAP(x) (((x) >> 16) & 0x3)
1105#define C_0280A0_COMP_SWAP 0xFFFCFFFF
1106#define S_0280A0_TILE_MODE(x) (((x) & 0x3) << 18)
1107#define G_0280A0_TILE_MODE(x) (((x) >> 18) & 0x3)
1108#define C_0280A0_TILE_MODE 0xFFF3FFFF
1109#define S_0280A0_BLEND_CLAMP(x) (((x) & 0x1) << 20)
1110#define G_0280A0_BLEND_CLAMP(x) (((x) >> 20) & 0x1)
1111#define C_0280A0_BLEND_CLAMP 0xFFEFFFFF
1112#define S_0280A0_CLEAR_COLOR(x) (((x) & 0x1) << 21)
1113#define G_0280A0_CLEAR_COLOR(x) (((x) >> 21) & 0x1)
1114#define C_0280A0_CLEAR_COLOR 0xFFDFFFFF
1115#define S_0280A0_BLEND_BYPASS(x) (((x) & 0x1) << 22)
1116#define G_0280A0_BLEND_BYPASS(x) (((x) >> 22) & 0x1)
1117#define C_0280A0_BLEND_BYPASS 0xFFBFFFFF
1118#define S_0280A0_BLEND_FLOAT32(x) (((x) & 0x1) << 23)
1119#define G_0280A0_BLEND_FLOAT32(x) (((x) >> 23) & 0x1)
1120#define C_0280A0_BLEND_FLOAT32 0xFF7FFFFF
1121#define S_0280A0_SIMPLE_FLOAT(x) (((x) & 0x1) << 24)
1122#define G_0280A0_SIMPLE_FLOAT(x) (((x) >> 24) & 0x1)
1123#define C_0280A0_SIMPLE_FLOAT 0xFEFFFFFF
1124#define S_0280A0_ROUND_MODE(x) (((x) & 0x1) << 25)
1125#define G_0280A0_ROUND_MODE(x) (((x) >> 25) & 0x1)
1126#define C_0280A0_ROUND_MODE 0xFDFFFFFF
1127#define S_0280A0_TILE_COMPACT(x) (((x) & 0x1) << 26)
1128#define G_0280A0_TILE_COMPACT(x) (((x) >> 26) & 0x1)
1129#define C_0280A0_TILE_COMPACT 0xFBFFFFFF
1130#define S_0280A0_SOURCE_FORMAT(x) (((x) & 0x1) << 27)
1131#define G_0280A0_SOURCE_FORMAT(x) (((x) >> 27) & 0x1)
1132#define C_0280A0_SOURCE_FORMAT 0xF7FFFFFF
1133#define R_0280A4_CB_COLOR1_INFO 0x0280A4
1134#define R_0280A8_CB_COLOR2_INFO 0x0280A8
1135#define R_0280AC_CB_COLOR3_INFO 0x0280AC
1136#define R_0280B0_CB_COLOR4_INFO 0x0280B0
1137#define R_0280B4_CB_COLOR5_INFO 0x0280B4
1138#define R_0280B8_CB_COLOR6_INFO 0x0280B8
1139#define R_0280BC_CB_COLOR7_INFO 0x0280BC
1140#define R_028060_CB_COLOR0_SIZE 0x028060
1141#define S_028060_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0)
1142#define G_028060_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF)
1143#define C_028060_PITCH_TILE_MAX 0xFFFFFC00
1144#define S_028060_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10)
1145#define G_028060_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF)
1146#define C_028060_SLICE_TILE_MAX 0xC00003FF
1147#define R_028064_CB_COLOR1_SIZE 0x028064
1148#define R_028068_CB_COLOR2_SIZE 0x028068
1149#define R_02806C_CB_COLOR3_SIZE 0x02806C
1150#define R_028070_CB_COLOR4_SIZE 0x028070
1151#define R_028074_CB_COLOR5_SIZE 0x028074
1152#define R_028078_CB_COLOR6_SIZE 0x028078
1153#define R_02807C_CB_COLOR7_SIZE 0x02807C
1154#define R_028238_CB_TARGET_MASK 0x028238
1155#define S_028238_TARGET0_ENABLE(x) (((x) & 0xF) << 0)
1156#define G_028238_TARGET0_ENABLE(x) (((x) >> 0) & 0xF)
1157#define C_028238_TARGET0_ENABLE 0xFFFFFFF0
1158#define S_028238_TARGET1_ENABLE(x) (((x) & 0xF) << 4)
1159#define G_028238_TARGET1_ENABLE(x) (((x) >> 4) & 0xF)
1160#define C_028238_TARGET1_ENABLE 0xFFFFFF0F
1161#define S_028238_TARGET2_ENABLE(x) (((x) & 0xF) << 8)
1162#define G_028238_TARGET2_ENABLE(x) (((x) >> 8) & 0xF)
1163#define C_028238_TARGET2_ENABLE 0xFFFFF0FF
1164#define S_028238_TARGET3_ENABLE(x) (((x) & 0xF) << 12)
1165#define G_028238_TARGET3_ENABLE(x) (((x) >> 12) & 0xF)
1166#define C_028238_TARGET3_ENABLE 0xFFFF0FFF
1167#define S_028238_TARGET4_ENABLE(x) (((x) & 0xF) << 16)
1168#define G_028238_TARGET4_ENABLE(x) (((x) >> 16) & 0xF)
1169#define C_028238_TARGET4_ENABLE 0xFFF0FFFF
1170#define S_028238_TARGET5_ENABLE(x) (((x) & 0xF) << 20)
1171#define G_028238_TARGET5_ENABLE(x) (((x) >> 20) & 0xF)
1172#define C_028238_TARGET5_ENABLE 0xFF0FFFFF
1173#define S_028238_TARGET6_ENABLE(x) (((x) & 0xF) << 24)
1174#define G_028238_TARGET6_ENABLE(x) (((x) >> 24) & 0xF)
1175#define C_028238_TARGET6_ENABLE 0xF0FFFFFF
1176#define S_028238_TARGET7_ENABLE(x) (((x) & 0xF) << 28)
1177#define G_028238_TARGET7_ENABLE(x) (((x) >> 28) & 0xF)
1178#define C_028238_TARGET7_ENABLE 0x0FFFFFFF
1179#define R_02823C_CB_SHADER_MASK 0x02823C
1180#define S_02823C_OUTPUT0_ENABLE(x) (((x) & 0xF) << 0)
1181#define G_02823C_OUTPUT0_ENABLE(x) (((x) >> 0) & 0xF)
1182#define C_02823C_OUTPUT0_ENABLE 0xFFFFFFF0
1183#define S_02823C_OUTPUT1_ENABLE(x) (((x) & 0xF) << 4)
1184#define G_02823C_OUTPUT1_ENABLE(x) (((x) >> 4) & 0xF)
1185#define C_02823C_OUTPUT1_ENABLE 0xFFFFFF0F
1186#define S_02823C_OUTPUT2_ENABLE(x) (((x) & 0xF) << 8)
1187#define G_02823C_OUTPUT2_ENABLE(x) (((x) >> 8) & 0xF)
1188#define C_02823C_OUTPUT2_ENABLE 0xFFFFF0FF
1189#define S_02823C_OUTPUT3_ENABLE(x) (((x) & 0xF) << 12)
1190#define G_02823C_OUTPUT3_ENABLE(x) (((x) >> 12) & 0xF)
1191#define C_02823C_OUTPUT3_ENABLE 0xFFFF0FFF
1192#define S_02823C_OUTPUT4_ENABLE(x) (((x) & 0xF) << 16)
1193#define G_02823C_OUTPUT4_ENABLE(x) (((x) >> 16) & 0xF)
1194#define C_02823C_OUTPUT4_ENABLE 0xFFF0FFFF
1195#define S_02823C_OUTPUT5_ENABLE(x) (((x) & 0xF) << 20)
1196#define G_02823C_OUTPUT5_ENABLE(x) (((x) >> 20) & 0xF)
1197#define C_02823C_OUTPUT5_ENABLE 0xFF0FFFFF
1198#define S_02823C_OUTPUT6_ENABLE(x) (((x) & 0xF) << 24)
1199#define G_02823C_OUTPUT6_ENABLE(x) (((x) >> 24) & 0xF)
1200#define C_02823C_OUTPUT6_ENABLE 0xF0FFFFFF
1201#define S_02823C_OUTPUT7_ENABLE(x) (((x) & 0xF) << 28)
1202#define G_02823C_OUTPUT7_ENABLE(x) (((x) >> 28) & 0xF)
1203#define C_02823C_OUTPUT7_ENABLE 0x0FFFFFFF
1204#define R_028AB0_VGT_STRMOUT_EN 0x028AB0
1205#define S_028AB0_STREAMOUT(x) (((x) & 0x1) << 0)
1206#define G_028AB0_STREAMOUT(x) (((x) >> 0) & 0x1)
1207#define C_028AB0_STREAMOUT 0xFFFFFFFE
1208#define R_028B20_VGT_STRMOUT_BUFFER_EN 0x028B20
1209#define S_028B20_BUFFER_0_EN(x) (((x) & 0x1) << 0)
1210#define G_028B20_BUFFER_0_EN(x) (((x) >> 0) & 0x1)
1211#define C_028B20_BUFFER_0_EN 0xFFFFFFFE
1212#define S_028B20_BUFFER_1_EN(x) (((x) & 0x1) << 1)
1213#define G_028B20_BUFFER_1_EN(x) (((x) >> 1) & 0x1)
1214#define C_028B20_BUFFER_1_EN 0xFFFFFFFD
1215#define S_028B20_BUFFER_2_EN(x) (((x) & 0x1) << 2)
1216#define G_028B20_BUFFER_2_EN(x) (((x) >> 2) & 0x1)
1217#define C_028B20_BUFFER_2_EN 0xFFFFFFFB
1218#define S_028B20_BUFFER_3_EN(x) (((x) & 0x1) << 3)
1219#define G_028B20_BUFFER_3_EN(x) (((x) >> 3) & 0x1)
1220#define C_028B20_BUFFER_3_EN 0xFFFFFFF7
1221#define S_028B20_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
1222#define G_028B20_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
1223#define C_028B20_SIZE 0x00000000
1224#define R_038000_SQ_TEX_RESOURCE_WORD0_0 0x038000
1225#define S_038000_DIM(x) (((x) & 0x7) << 0)
1226#define G_038000_DIM(x) (((x) >> 0) & 0x7)
1227#define C_038000_DIM 0xFFFFFFF8
1228#define V_038000_SQ_TEX_DIM_1D 0x00000000
1229#define V_038000_SQ_TEX_DIM_2D 0x00000001
1230#define V_038000_SQ_TEX_DIM_3D 0x00000002
1231#define V_038000_SQ_TEX_DIM_CUBEMAP 0x00000003
1232#define V_038000_SQ_TEX_DIM_1D_ARRAY 0x00000004
1233#define V_038000_SQ_TEX_DIM_2D_ARRAY 0x00000005
1234#define V_038000_SQ_TEX_DIM_2D_MSAA 0x00000006
1235#define V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA 0x00000007
1236#define S_038000_TILE_MODE(x) (((x) & 0xF) << 3)
1237#define G_038000_TILE_MODE(x) (((x) >> 3) & 0xF)
1238#define C_038000_TILE_MODE 0xFFFFFF87
1239#define V_038000_ARRAY_LINEAR_GENERAL 0x00000000
1240#define V_038000_ARRAY_LINEAR_ALIGNED 0x00000001
1241#define V_038000_ARRAY_1D_TILED_THIN1 0x00000002
1242#define V_038000_ARRAY_2D_TILED_THIN1 0x00000004
1243#define S_038000_TILE_TYPE(x) (((x) & 0x1) << 7)
1244#define G_038000_TILE_TYPE(x) (((x) >> 7) & 0x1)
1245#define C_038000_TILE_TYPE 0xFFFFFF7F
1246#define S_038000_PITCH(x) (((x) & 0x7FF) << 8)
1247#define G_038000_PITCH(x) (((x) >> 8) & 0x7FF)
1248#define C_038000_PITCH 0xFFF800FF
1249#define S_038000_TEX_WIDTH(x) (((x) & 0x1FFF) << 19)
1250#define G_038000_TEX_WIDTH(x) (((x) >> 19) & 0x1FFF)
1251#define C_038000_TEX_WIDTH 0x0007FFFF
1252#define R_038004_SQ_TEX_RESOURCE_WORD1_0 0x038004
1253#define S_038004_TEX_HEIGHT(x) (((x) & 0x1FFF) << 0)
1254#define G_038004_TEX_HEIGHT(x) (((x) >> 0) & 0x1FFF)
1255#define C_038004_TEX_HEIGHT 0xFFFFE000
1256#define S_038004_TEX_DEPTH(x) (((x) & 0x1FFF) << 13)
1257#define G_038004_TEX_DEPTH(x) (((x) >> 13) & 0x1FFF)
1258#define C_038004_TEX_DEPTH 0xFC001FFF
1259#define S_038004_DATA_FORMAT(x) (((x) & 0x3F) << 26)
1260#define G_038004_DATA_FORMAT(x) (((x) >> 26) & 0x3F)
1261#define C_038004_DATA_FORMAT 0x03FFFFFF
1262#define V_038004_COLOR_INVALID 0x00000000
1263#define V_038004_COLOR_8 0x00000001
1264#define V_038004_COLOR_4_4 0x00000002
1265#define V_038004_COLOR_3_3_2 0x00000003
1266#define V_038004_COLOR_16 0x00000005
1267#define V_038004_COLOR_16_FLOAT 0x00000006
1268#define V_038004_COLOR_8_8 0x00000007
1269#define V_038004_COLOR_5_6_5 0x00000008
1270#define V_038004_COLOR_6_5_5 0x00000009
1271#define V_038004_COLOR_1_5_5_5 0x0000000A
1272#define V_038004_COLOR_4_4_4_4 0x0000000B
1273#define V_038004_COLOR_5_5_5_1 0x0000000C
1274#define V_038004_COLOR_32 0x0000000D
1275#define V_038004_COLOR_32_FLOAT 0x0000000E
1276#define V_038004_COLOR_16_16 0x0000000F
1277#define V_038004_COLOR_16_16_FLOAT 0x00000010
1278#define V_038004_COLOR_8_24 0x00000011
1279#define V_038004_COLOR_8_24_FLOAT 0x00000012
1280#define V_038004_COLOR_24_8 0x00000013
1281#define V_038004_COLOR_24_8_FLOAT 0x00000014
1282#define V_038004_COLOR_10_11_11 0x00000015
1283#define V_038004_COLOR_10_11_11_FLOAT 0x00000016
1284#define V_038004_COLOR_11_11_10 0x00000017
1285#define V_038004_COLOR_11_11_10_FLOAT 0x00000018
1286#define V_038004_COLOR_2_10_10_10 0x00000019
1287#define V_038004_COLOR_8_8_8_8 0x0000001A
1288#define V_038004_COLOR_10_10_10_2 0x0000001B
1289#define V_038004_COLOR_X24_8_32_FLOAT 0x0000001C
1290#define V_038004_COLOR_32_32 0x0000001D
1291#define V_038004_COLOR_32_32_FLOAT 0x0000001E
1292#define V_038004_COLOR_16_16_16_16 0x0000001F
1293#define V_038004_COLOR_16_16_16_16_FLOAT 0x00000020
1294#define V_038004_COLOR_32_32_32_32 0x00000022
1295#define V_038004_COLOR_32_32_32_32_FLOAT 0x00000023
1296#define V_038004_FMT_1 0x00000025
1297#define V_038004_FMT_GB_GR 0x00000027
1298#define V_038004_FMT_BG_RG 0x00000028
1299#define V_038004_FMT_32_AS_8 0x00000029
1300#define V_038004_FMT_32_AS_8_8 0x0000002A
1301#define V_038004_FMT_5_9_9_9_SHAREDEXP 0x0000002B
1302#define V_038004_FMT_8_8_8 0x0000002C
1303#define V_038004_FMT_16_16_16 0x0000002D
1304#define V_038004_FMT_16_16_16_FLOAT 0x0000002E
1305#define V_038004_FMT_32_32_32 0x0000002F
1306#define V_038004_FMT_32_32_32_FLOAT 0x00000030
1307#define V_038004_FMT_BC1 0x00000031
1308#define V_038004_FMT_BC2 0x00000032
1309#define V_038004_FMT_BC3 0x00000033
1310#define V_038004_FMT_BC4 0x00000034
1311#define V_038004_FMT_BC5 0x00000035
1312#define V_038004_FMT_BC6 0x00000036
1313#define V_038004_FMT_BC7 0x00000037
1314#define V_038004_FMT_32_AS_32_32_32_32 0x00000038
1315#define R_038010_SQ_TEX_RESOURCE_WORD4_0 0x038010
1316#define S_038010_FORMAT_COMP_X(x) (((x) & 0x3) << 0)
1317#define G_038010_FORMAT_COMP_X(x) (((x) >> 0) & 0x3)
1318#define C_038010_FORMAT_COMP_X 0xFFFFFFFC
1319#define S_038010_FORMAT_COMP_Y(x) (((x) & 0x3) << 2)
1320#define G_038010_FORMAT_COMP_Y(x) (((x) >> 2) & 0x3)
1321#define C_038010_FORMAT_COMP_Y 0xFFFFFFF3
1322#define S_038010_FORMAT_COMP_Z(x) (((x) & 0x3) << 4)
1323#define G_038010_FORMAT_COMP_Z(x) (((x) >> 4) & 0x3)
1324#define C_038010_FORMAT_COMP_Z 0xFFFFFFCF
1325#define S_038010_FORMAT_COMP_W(x) (((x) & 0x3) << 6)
1326#define G_038010_FORMAT_COMP_W(x) (((x) >> 6) & 0x3)
1327#define C_038010_FORMAT_COMP_W 0xFFFFFF3F
1328#define S_038010_NUM_FORMAT_ALL(x) (((x) & 0x3) << 8)
1329#define G_038010_NUM_FORMAT_ALL(x) (((x) >> 8) & 0x3)
1330#define C_038010_NUM_FORMAT_ALL 0xFFFFFCFF
1331#define S_038010_SRF_MODE_ALL(x) (((x) & 0x1) << 10)
1332#define G_038010_SRF_MODE_ALL(x) (((x) >> 10) & 0x1)
1333#define C_038010_SRF_MODE_ALL 0xFFFFFBFF
1334#define S_038010_FORCE_DEGAMMA(x) (((x) & 0x1) << 11)
1335#define G_038010_FORCE_DEGAMMA(x) (((x) >> 11) & 0x1)
1336#define C_038010_FORCE_DEGAMMA 0xFFFFF7FF
1337#define S_038010_ENDIAN_SWAP(x) (((x) & 0x3) << 12)
1338#define G_038010_ENDIAN_SWAP(x) (((x) >> 12) & 0x3)
1339#define C_038010_ENDIAN_SWAP 0xFFFFCFFF
1340#define S_038010_REQUEST_SIZE(x) (((x) & 0x3) << 14)
1341#define G_038010_REQUEST_SIZE(x) (((x) >> 14) & 0x3)
1342#define C_038010_REQUEST_SIZE 0xFFFF3FFF
1343#define S_038010_DST_SEL_X(x) (((x) & 0x7) << 16)
1344#define G_038010_DST_SEL_X(x) (((x) >> 16) & 0x7)
1345#define C_038010_DST_SEL_X 0xFFF8FFFF
1346#define S_038010_DST_SEL_Y(x) (((x) & 0x7) << 19)
1347#define G_038010_DST_SEL_Y(x) (((x) >> 19) & 0x7)
1348#define C_038010_DST_SEL_Y 0xFFC7FFFF
1349#define S_038010_DST_SEL_Z(x) (((x) & 0x7) << 22)
1350#define G_038010_DST_SEL_Z(x) (((x) >> 22) & 0x7)
1351#define C_038010_DST_SEL_Z 0xFE3FFFFF
1352#define S_038010_DST_SEL_W(x) (((x) & 0x7) << 25)
1353#define G_038010_DST_SEL_W(x) (((x) >> 25) & 0x7)
1354#define C_038010_DST_SEL_W 0xF1FFFFFF
1355#define S_038010_BASE_LEVEL(x) (((x) & 0xF) << 28)
1356#define G_038010_BASE_LEVEL(x) (((x) >> 28) & 0xF)
1357#define C_038010_BASE_LEVEL 0x0FFFFFFF
1358#define R_038014_SQ_TEX_RESOURCE_WORD5_0 0x038014
1359#define S_038014_LAST_LEVEL(x) (((x) & 0xF) << 0)
1360#define G_038014_LAST_LEVEL(x) (((x) >> 0) & 0xF)
1361#define C_038014_LAST_LEVEL 0xFFFFFFF0
1362#define S_038014_BASE_ARRAY(x) (((x) & 0x1FFF) << 4)
1363#define G_038014_BASE_ARRAY(x) (((x) >> 4) & 0x1FFF)
1364#define C_038014_BASE_ARRAY 0xFFFE000F
1365#define S_038014_LAST_ARRAY(x) (((x) & 0x1FFF) << 17)
1366#define G_038014_LAST_ARRAY(x) (((x) >> 17) & 0x1FFF)
1367#define C_038014_LAST_ARRAY 0xC001FFFF
1368#define R_0288A8_SQ_ESGS_RING_ITEMSIZE 0x0288A8
1369#define S_0288A8_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
1370#define G_0288A8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
1371#define C_0288A8_ITEMSIZE 0xFFFF8000
1372#define R_008C44_SQ_ESGS_RING_SIZE 0x008C44
1373#define S_008C44_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
1374#define G_008C44_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
1375#define C_008C44_MEM_SIZE 0x00000000
1376#define R_0288B0_SQ_ESTMP_RING_ITEMSIZE 0x0288B0
1377#define S_0288B0_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
1378#define G_0288B0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
1379#define C_0288B0_ITEMSIZE 0xFFFF8000
1380#define R_008C54_SQ_ESTMP_RING_SIZE 0x008C54
1381#define S_008C54_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
1382#define G_008C54_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
1383#define C_008C54_MEM_SIZE 0x00000000
1384#define R_0288C0_SQ_FBUF_RING_ITEMSIZE 0x0288C0
1385#define S_0288C0_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
1386#define G_0288C0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
1387#define C_0288C0_ITEMSIZE 0xFFFF8000
1388#define R_008C74_SQ_FBUF_RING_SIZE 0x008C74
1389#define S_008C74_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
1390#define G_008C74_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
1391#define C_008C74_MEM_SIZE 0x00000000
1392#define R_0288B4_SQ_GSTMP_RING_ITEMSIZE 0x0288B4
1393#define S_0288B4_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
1394#define G_0288B4_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
1395#define C_0288B4_ITEMSIZE 0xFFFF8000
1396#define R_008C5C_SQ_GSTMP_RING_SIZE 0x008C5C
1397#define S_008C5C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
1398#define G_008C5C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
1399#define C_008C5C_MEM_SIZE 0x00000000
1400#define R_0288AC_SQ_GSVS_RING_ITEMSIZE 0x0288AC
1401#define S_0288AC_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
1402#define G_0288AC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
1403#define C_0288AC_ITEMSIZE 0xFFFF8000
1404#define R_008C4C_SQ_GSVS_RING_SIZE 0x008C4C
1405#define S_008C4C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
1406#define G_008C4C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
1407#define C_008C4C_MEM_SIZE 0x00000000
1408#define R_0288BC_SQ_PSTMP_RING_ITEMSIZE 0x0288BC
1409#define S_0288BC_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
1410#define G_0288BC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
1411#define C_0288BC_ITEMSIZE 0xFFFF8000
1412#define R_008C6C_SQ_PSTMP_RING_SIZE 0x008C6C
1413#define S_008C6C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
1414#define G_008C6C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
1415#define C_008C6C_MEM_SIZE 0x00000000
1416#define R_0288C4_SQ_REDUC_RING_ITEMSIZE 0x0288C4
1417#define S_0288C4_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
1418#define G_0288C4_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
1419#define C_0288C4_ITEMSIZE 0xFFFF8000
1420#define R_008C7C_SQ_REDUC_RING_SIZE 0x008C7C
1421#define S_008C7C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
1422#define G_008C7C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
1423#define C_008C7C_MEM_SIZE 0x00000000
1424#define R_0288B8_SQ_VSTMP_RING_ITEMSIZE 0x0288B8
1425#define S_0288B8_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
1426#define G_0288B8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
1427#define C_0288B8_ITEMSIZE 0xFFFF8000
1428#define R_008C64_SQ_VSTMP_RING_SIZE 0x008C64
1429#define S_008C64_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
1430#define G_008C64_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
1431#define C_008C64_MEM_SIZE 0x00000000
1432#define R_0288C8_SQ_GS_VERT_ITEMSIZE 0x0288C8
1433#define S_0288C8_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
1434#define G_0288C8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
1435#define C_0288C8_ITEMSIZE 0xFFFF8000
1436#define R_028010_DB_DEPTH_INFO 0x028010
1437#define S_028010_FORMAT(x) (((x) & 0x7) << 0)
1438#define G_028010_FORMAT(x) (((x) >> 0) & 0x7)
1439#define C_028010_FORMAT 0xFFFFFFF8
1440#define V_028010_DEPTH_INVALID 0x00000000
1441#define V_028010_DEPTH_16 0x00000001
1442#define V_028010_DEPTH_X8_24 0x00000002
1443#define V_028010_DEPTH_8_24 0x00000003
1444#define V_028010_DEPTH_X8_24_FLOAT 0x00000004
1445#define V_028010_DEPTH_8_24_FLOAT 0x00000005
1446#define V_028010_DEPTH_32_FLOAT 0x00000006
1447#define V_028010_DEPTH_X24_8_32_FLOAT 0x00000007
1448#define S_028010_READ_SIZE(x) (((x) & 0x1) << 3)
1449#define G_028010_READ_SIZE(x) (((x) >> 3) & 0x1)
1450#define C_028010_READ_SIZE 0xFFFFFFF7
1451#define S_028010_ARRAY_MODE(x) (((x) & 0xF) << 15)
1452#define G_028010_ARRAY_MODE(x) (((x) >> 15) & 0xF)
1453#define C_028010_ARRAY_MODE 0xFFF87FFF
1454#define V_028010_ARRAY_1D_TILED_THIN1 0x00000002
1455#define V_028010_ARRAY_2D_TILED_THIN1 0x00000004
1456#define S_028010_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 25)
1457#define G_028010_TILE_SURFACE_ENABLE(x) (((x) >> 25) & 0x1)
1458#define C_028010_TILE_SURFACE_ENABLE 0xFDFFFFFF
1459#define S_028010_TILE_COMPACT(x) (((x) & 0x1) << 26)
1460#define G_028010_TILE_COMPACT(x) (((x) >> 26) & 0x1)
1461#define C_028010_TILE_COMPACT 0xFBFFFFFF
1462#define S_028010_ZRANGE_PRECISION(x) (((x) & 0x1) << 31)
1463#define G_028010_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1)
1464#define C_028010_ZRANGE_PRECISION 0x7FFFFFFF
1465#define R_028000_DB_DEPTH_SIZE 0x028000
1466#define S_028000_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0)
1467#define G_028000_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF)
1468#define C_028000_PITCH_TILE_MAX 0xFFFFFC00
1469#define S_028000_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10)
1470#define G_028000_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF)
1471#define C_028000_SLICE_TILE_MAX 0xC00003FF
1472#define R_028004_DB_DEPTH_VIEW 0x028004
1473#define S_028004_SLICE_START(x) (((x) & 0x7FF) << 0)
1474#define G_028004_SLICE_START(x) (((x) >> 0) & 0x7FF)
1475#define C_028004_SLICE_START 0xFFFFF800
1476#define S_028004_SLICE_MAX(x) (((x) & 0x7FF) << 13)
1477#define G_028004_SLICE_MAX(x) (((x) >> 13) & 0x7FF)
1478#define C_028004_SLICE_MAX 0xFF001FFF
1479#define R_028800_DB_DEPTH_CONTROL 0x028800
1480#define S_028800_STENCIL_ENABLE(x) (((x) & 0x1) << 0)
1481#define G_028800_STENCIL_ENABLE(x) (((x) >> 0) & 0x1)
1482#define C_028800_STENCIL_ENABLE 0xFFFFFFFE
1483#define S_028800_Z_ENABLE(x) (((x) & 0x1) << 1)
1484#define G_028800_Z_ENABLE(x) (((x) >> 1) & 0x1)
1485#define C_028800_Z_ENABLE 0xFFFFFFFD
1486#define S_028800_Z_WRITE_ENABLE(x) (((x) & 0x1) << 2)
1487#define G_028800_Z_WRITE_ENABLE(x) (((x) >> 2) & 0x1)
1488#define C_028800_Z_WRITE_ENABLE 0xFFFFFFFB
1489#define S_028800_ZFUNC(x) (((x) & 0x7) << 4)
1490#define G_028800_ZFUNC(x) (((x) >> 4) & 0x7)
1491#define C_028800_ZFUNC 0xFFFFFF8F
1492#define S_028800_BACKFACE_ENABLE(x) (((x) & 0x1) << 7)
1493#define G_028800_BACKFACE_ENABLE(x) (((x) >> 7) & 0x1)
1494#define C_028800_BACKFACE_ENABLE 0xFFFFFF7F
1495#define S_028800_STENCILFUNC(x) (((x) & 0x7) << 8)
1496#define G_028800_STENCILFUNC(x) (((x) >> 8) & 0x7)
1497#define C_028800_STENCILFUNC 0xFFFFF8FF
1498#define S_028800_STENCILFAIL(x) (((x) & 0x7) << 11)
1499#define G_028800_STENCILFAIL(x) (((x) >> 11) & 0x7)
1500#define C_028800_STENCILFAIL 0xFFFFC7FF
1501#define S_028800_STENCILZPASS(x) (((x) & 0x7) << 14)
1502#define G_028800_STENCILZPASS(x) (((x) >> 14) & 0x7)
1503#define C_028800_STENCILZPASS 0xFFFE3FFF
1504#define S_028800_STENCILZFAIL(x) (((x) & 0x7) << 17)
1505#define G_028800_STENCILZFAIL(x) (((x) >> 17) & 0x7)
1506#define C_028800_STENCILZFAIL 0xFFF1FFFF
1507#define S_028800_STENCILFUNC_BF(x) (((x) & 0x7) << 20)
1508#define G_028800_STENCILFUNC_BF(x) (((x) >> 20) & 0x7)
1509#define C_028800_STENCILFUNC_BF 0xFF8FFFFF
1510#define S_028800_STENCILFAIL_BF(x) (((x) & 0x7) << 23)
1511#define G_028800_STENCILFAIL_BF(x) (((x) >> 23) & 0x7)
1512#define C_028800_STENCILFAIL_BF 0xFC7FFFFF
1513#define S_028800_STENCILZPASS_BF(x) (((x) & 0x7) << 26)
1514#define G_028800_STENCILZPASS_BF(x) (((x) >> 26) & 0x7)
1515#define C_028800_STENCILZPASS_BF 0xE3FFFFFF
1516#define S_028800_STENCILZFAIL_BF(x) (((x) & 0x7) << 29)
1517#define G_028800_STENCILZFAIL_BF(x) (((x) >> 29) & 0x7)
1518#define C_028800_STENCILZFAIL_BF 0x1FFFFFFF
1519
1520#endif
1/*
2 * Copyright 2009 Advanced Micro Devices, Inc.
3 * Copyright 2009 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 * Jerome Glisse
26 */
27#ifndef R600D_H
28#define R600D_H
29
30#define CP_PACKET2 0x80000000
31#define PACKET2_PAD_SHIFT 0
32#define PACKET2_PAD_MASK (0x3fffffff << 0)
33
34#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
35
36#define R6XX_MAX_SH_GPRS 256
37#define R6XX_MAX_TEMP_GPRS 16
38#define R6XX_MAX_SH_THREADS 256
39#define R6XX_MAX_SH_STACK_ENTRIES 4096
40#define R6XX_MAX_BACKENDS 8
41#define R6XX_MAX_BACKENDS_MASK 0xff
42#define R6XX_MAX_SIMDS 8
43#define R6XX_MAX_SIMDS_MASK 0xff
44#define R6XX_MAX_PIPES 8
45#define R6XX_MAX_PIPES_MASK 0xff
46
47/* PTE flags */
48#define PTE_VALID (1 << 0)
49#define PTE_SYSTEM (1 << 1)
50#define PTE_SNOOPED (1 << 2)
51#define PTE_READABLE (1 << 5)
52#define PTE_WRITEABLE (1 << 6)
53
54/* tiling bits */
55#define ARRAY_LINEAR_GENERAL 0x00000000
56#define ARRAY_LINEAR_ALIGNED 0x00000001
57#define ARRAY_1D_TILED_THIN1 0x00000002
58#define ARRAY_2D_TILED_THIN1 0x00000004
59
60/* Registers */
61#define ARB_POP 0x2418
62#define ENABLE_TC128 (1 << 30)
63#define ARB_GDEC_RD_CNTL 0x246C
64
65#define CC_GC_SHADER_PIPE_CONFIG 0x8950
66#define CC_RB_BACKEND_DISABLE 0x98F4
67#define BACKEND_DISABLE(x) ((x) << 16)
68
69#define CB_COLOR0_BASE 0x28040
70#define CB_COLOR1_BASE 0x28044
71#define CB_COLOR2_BASE 0x28048
72#define CB_COLOR3_BASE 0x2804C
73#define CB_COLOR4_BASE 0x28050
74#define CB_COLOR5_BASE 0x28054
75#define CB_COLOR6_BASE 0x28058
76#define CB_COLOR7_BASE 0x2805C
77#define CB_COLOR7_FRAG 0x280FC
78
79#define CB_COLOR0_SIZE 0x28060
80#define CB_COLOR0_VIEW 0x28080
81#define R_028080_CB_COLOR0_VIEW 0x028080
82#define S_028080_SLICE_START(x) (((x) & 0x7FF) << 0)
83#define G_028080_SLICE_START(x) (((x) >> 0) & 0x7FF)
84#define C_028080_SLICE_START 0xFFFFF800
85#define S_028080_SLICE_MAX(x) (((x) & 0x7FF) << 13)
86#define G_028080_SLICE_MAX(x) (((x) >> 13) & 0x7FF)
87#define C_028080_SLICE_MAX 0xFF001FFF
88#define R_028084_CB_COLOR1_VIEW 0x028084
89#define R_028088_CB_COLOR2_VIEW 0x028088
90#define R_02808C_CB_COLOR3_VIEW 0x02808C
91#define R_028090_CB_COLOR4_VIEW 0x028090
92#define R_028094_CB_COLOR5_VIEW 0x028094
93#define R_028098_CB_COLOR6_VIEW 0x028098
94#define R_02809C_CB_COLOR7_VIEW 0x02809C
95#define CB_COLOR0_INFO 0x280a0
96# define CB_FORMAT(x) ((x) << 2)
97# define CB_ARRAY_MODE(x) ((x) << 8)
98# define CB_SOURCE_FORMAT(x) ((x) << 27)
99# define CB_SF_EXPORT_FULL 0
100# define CB_SF_EXPORT_NORM 1
101#define CB_COLOR0_TILE 0x280c0
102#define CB_COLOR0_FRAG 0x280e0
103#define CB_COLOR0_MASK 0x28100
104
105#define SQ_ALU_CONST_CACHE_PS_0 0x28940
106#define SQ_ALU_CONST_CACHE_PS_1 0x28944
107#define SQ_ALU_CONST_CACHE_PS_2 0x28948
108#define SQ_ALU_CONST_CACHE_PS_3 0x2894c
109#define SQ_ALU_CONST_CACHE_PS_4 0x28950
110#define SQ_ALU_CONST_CACHE_PS_5 0x28954
111#define SQ_ALU_CONST_CACHE_PS_6 0x28958
112#define SQ_ALU_CONST_CACHE_PS_7 0x2895c
113#define SQ_ALU_CONST_CACHE_PS_8 0x28960
114#define SQ_ALU_CONST_CACHE_PS_9 0x28964
115#define SQ_ALU_CONST_CACHE_PS_10 0x28968
116#define SQ_ALU_CONST_CACHE_PS_11 0x2896c
117#define SQ_ALU_CONST_CACHE_PS_12 0x28970
118#define SQ_ALU_CONST_CACHE_PS_13 0x28974
119#define SQ_ALU_CONST_CACHE_PS_14 0x28978
120#define SQ_ALU_CONST_CACHE_PS_15 0x2897c
121#define SQ_ALU_CONST_CACHE_VS_0 0x28980
122#define SQ_ALU_CONST_CACHE_VS_1 0x28984
123#define SQ_ALU_CONST_CACHE_VS_2 0x28988
124#define SQ_ALU_CONST_CACHE_VS_3 0x2898c
125#define SQ_ALU_CONST_CACHE_VS_4 0x28990
126#define SQ_ALU_CONST_CACHE_VS_5 0x28994
127#define SQ_ALU_CONST_CACHE_VS_6 0x28998
128#define SQ_ALU_CONST_CACHE_VS_7 0x2899c
129#define SQ_ALU_CONST_CACHE_VS_8 0x289a0
130#define SQ_ALU_CONST_CACHE_VS_9 0x289a4
131#define SQ_ALU_CONST_CACHE_VS_10 0x289a8
132#define SQ_ALU_CONST_CACHE_VS_11 0x289ac
133#define SQ_ALU_CONST_CACHE_VS_12 0x289b0
134#define SQ_ALU_CONST_CACHE_VS_13 0x289b4
135#define SQ_ALU_CONST_CACHE_VS_14 0x289b8
136#define SQ_ALU_CONST_CACHE_VS_15 0x289bc
137#define SQ_ALU_CONST_CACHE_GS_0 0x289c0
138#define SQ_ALU_CONST_CACHE_GS_1 0x289c4
139#define SQ_ALU_CONST_CACHE_GS_2 0x289c8
140#define SQ_ALU_CONST_CACHE_GS_3 0x289cc
141#define SQ_ALU_CONST_CACHE_GS_4 0x289d0
142#define SQ_ALU_CONST_CACHE_GS_5 0x289d4
143#define SQ_ALU_CONST_CACHE_GS_6 0x289d8
144#define SQ_ALU_CONST_CACHE_GS_7 0x289dc
145#define SQ_ALU_CONST_CACHE_GS_8 0x289e0
146#define SQ_ALU_CONST_CACHE_GS_9 0x289e4
147#define SQ_ALU_CONST_CACHE_GS_10 0x289e8
148#define SQ_ALU_CONST_CACHE_GS_11 0x289ec
149#define SQ_ALU_CONST_CACHE_GS_12 0x289f0
150#define SQ_ALU_CONST_CACHE_GS_13 0x289f4
151#define SQ_ALU_CONST_CACHE_GS_14 0x289f8
152#define SQ_ALU_CONST_CACHE_GS_15 0x289fc
153
154#define CONFIG_MEMSIZE 0x5428
155#define CONFIG_CNTL 0x5424
156#define CP_STAT 0x8680
157#define CP_COHER_BASE 0x85F8
158#define CP_DEBUG 0xC1FC
159#define R_0086D8_CP_ME_CNTL 0x86D8
160#define S_0086D8_CP_ME_HALT(x) (((x) & 1)<<28)
161#define C_0086D8_CP_ME_HALT(x) ((x) & 0xEFFFFFFF)
162#define CP_ME_RAM_DATA 0xC160
163#define CP_ME_RAM_RADDR 0xC158
164#define CP_ME_RAM_WADDR 0xC15C
165#define CP_MEQ_THRESHOLDS 0x8764
166#define MEQ_END(x) ((x) << 16)
167#define ROQ_END(x) ((x) << 24)
168#define CP_PERFMON_CNTL 0x87FC
169#define CP_PFP_UCODE_ADDR 0xC150
170#define CP_PFP_UCODE_DATA 0xC154
171#define CP_QUEUE_THRESHOLDS 0x8760
172#define ROQ_IB1_START(x) ((x) << 0)
173#define ROQ_IB2_START(x) ((x) << 8)
174#define CP_RB_BASE 0xC100
175#define CP_RB_CNTL 0xC104
176#define RB_BUFSZ(x) ((x) << 0)
177#define RB_BLKSZ(x) ((x) << 8)
178#define RB_NO_UPDATE (1 << 27)
179#define RB_RPTR_WR_ENA (1 << 31)
180#define BUF_SWAP_32BIT (2 << 16)
181#define CP_RB_RPTR 0x8700
182#define CP_RB_RPTR_ADDR 0xC10C
183#define RB_RPTR_SWAP(x) ((x) << 0)
184#define CP_RB_RPTR_ADDR_HI 0xC110
185#define CP_RB_RPTR_WR 0xC108
186#define CP_RB_WPTR 0xC114
187#define CP_RB_WPTR_ADDR 0xC118
188#define CP_RB_WPTR_ADDR_HI 0xC11C
189#define CP_RB_WPTR_DELAY 0x8704
190#define CP_ROQ_IB1_STAT 0x8784
191#define CP_ROQ_IB2_STAT 0x8788
192#define CP_SEM_WAIT_TIMER 0x85BC
193
194#define DB_DEBUG 0x9830
195#define PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31)
196#define DB_DEPTH_BASE 0x2800C
197#define DB_HTILE_DATA_BASE 0x28014
198#define DB_HTILE_SURFACE 0x28D24
199#define S_028D24_HTILE_WIDTH(x) (((x) & 0x1) << 0)
200#define G_028D24_HTILE_WIDTH(x) (((x) >> 0) & 0x1)
201#define C_028D24_HTILE_WIDTH 0xFFFFFFFE
202#define S_028D24_HTILE_HEIGHT(x) (((x) & 0x1) << 1)
203#define G_028D24_HTILE_HEIGHT(x) (((x) >> 1) & 0x1)
204#define C_028D24_HTILE_HEIGHT 0xFFFFFFFD
205#define G_028D24_LINEAR(x) (((x) >> 2) & 0x1)
206#define DB_WATERMARKS 0x9838
207#define DEPTH_FREE(x) ((x) << 0)
208#define DEPTH_FLUSH(x) ((x) << 5)
209#define DEPTH_PENDING_FREE(x) ((x) << 15)
210#define DEPTH_CACHELINE_FREE(x) ((x) << 20)
211
212#define DCP_TILING_CONFIG 0x6CA0
213#define PIPE_TILING(x) ((x) << 1)
214#define BANK_TILING(x) ((x) << 4)
215#define GROUP_SIZE(x) ((x) << 6)
216#define ROW_TILING(x) ((x) << 8)
217#define BANK_SWAPS(x) ((x) << 11)
218#define SAMPLE_SPLIT(x) ((x) << 14)
219#define BACKEND_MAP(x) ((x) << 16)
220
221#define GB_TILING_CONFIG 0x98F0
222#define PIPE_TILING__SHIFT 1
223#define PIPE_TILING__MASK 0x0000000e
224
225#define GC_USER_SHADER_PIPE_CONFIG 0x8954
226#define INACTIVE_QD_PIPES(x) ((x) << 8)
227#define INACTIVE_QD_PIPES_MASK 0x0000FF00
228#define INACTIVE_SIMDS(x) ((x) << 16)
229#define INACTIVE_SIMDS_MASK 0x00FF0000
230
231#define SQ_CONFIG 0x8c00
232# define VC_ENABLE (1 << 0)
233# define EXPORT_SRC_C (1 << 1)
234# define DX9_CONSTS (1 << 2)
235# define ALU_INST_PREFER_VECTOR (1 << 3)
236# define DX10_CLAMP (1 << 4)
237# define CLAUSE_SEQ_PRIO(x) ((x) << 8)
238# define PS_PRIO(x) ((x) << 24)
239# define VS_PRIO(x) ((x) << 26)
240# define GS_PRIO(x) ((x) << 28)
241# define ES_PRIO(x) ((x) << 30)
242#define SQ_GPR_RESOURCE_MGMT_1 0x8c04
243# define NUM_PS_GPRS(x) ((x) << 0)
244# define NUM_VS_GPRS(x) ((x) << 16)
245# define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28)
246#define SQ_GPR_RESOURCE_MGMT_2 0x8c08
247# define NUM_GS_GPRS(x) ((x) << 0)
248# define NUM_ES_GPRS(x) ((x) << 16)
249#define SQ_THREAD_RESOURCE_MGMT 0x8c0c
250# define NUM_PS_THREADS(x) ((x) << 0)
251# define NUM_VS_THREADS(x) ((x) << 8)
252# define NUM_GS_THREADS(x) ((x) << 16)
253# define NUM_ES_THREADS(x) ((x) << 24)
254#define SQ_STACK_RESOURCE_MGMT_1 0x8c10
255# define NUM_PS_STACK_ENTRIES(x) ((x) << 0)
256# define NUM_VS_STACK_ENTRIES(x) ((x) << 16)
257#define SQ_STACK_RESOURCE_MGMT_2 0x8c14
258# define NUM_GS_STACK_ENTRIES(x) ((x) << 0)
259# define NUM_ES_STACK_ENTRIES(x) ((x) << 16)
260#define SQ_ESGS_RING_BASE 0x8c40
261#define SQ_GSVS_RING_BASE 0x8c48
262#define SQ_ESTMP_RING_BASE 0x8c50
263#define SQ_GSTMP_RING_BASE 0x8c58
264#define SQ_VSTMP_RING_BASE 0x8c60
265#define SQ_PSTMP_RING_BASE 0x8c68
266#define SQ_FBUF_RING_BASE 0x8c70
267#define SQ_REDUC_RING_BASE 0x8c78
268
269#define GRBM_CNTL 0x8000
270# define GRBM_READ_TIMEOUT(x) ((x) << 0)
271#define GRBM_STATUS 0x8010
272#define CMDFIFO_AVAIL_MASK 0x0000001F
273#define GUI_ACTIVE (1<<31)
274#define GRBM_STATUS2 0x8014
275#define GRBM_SOFT_RESET 0x8020
276#define SOFT_RESET_CP (1<<0)
277
278#define CG_THERMAL_STATUS 0x7F4
279#define ASIC_T(x) ((x) << 0)
280#define ASIC_T_MASK 0x1FF
281#define ASIC_T_SHIFT 0
282
283#define HDP_HOST_PATH_CNTL 0x2C00
284#define HDP_NONSURFACE_BASE 0x2C04
285#define HDP_NONSURFACE_INFO 0x2C08
286#define HDP_NONSURFACE_SIZE 0x2C0C
287#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
288#define HDP_TILING_CONFIG 0x2F3C
289#define HDP_DEBUG1 0x2F34
290
291#define MC_VM_AGP_TOP 0x2184
292#define MC_VM_AGP_BOT 0x2188
293#define MC_VM_AGP_BASE 0x218C
294#define MC_VM_FB_LOCATION 0x2180
295#define MC_VM_L1_TLB_MCD_RD_A_CNTL 0x219C
296#define ENABLE_L1_TLB (1 << 0)
297#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
298#define ENABLE_L1_STRICT_ORDERING (1 << 2)
299#define SYSTEM_ACCESS_MODE_MASK 0x000000C0
300#define SYSTEM_ACCESS_MODE_SHIFT 6
301#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 6)
302#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 6)
303#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 6)
304#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 6)
305#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 8)
306#define SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 8)
307#define ENABLE_SEMAPHORE_MODE (1 << 10)
308#define ENABLE_WAIT_L2_QUERY (1 << 11)
309#define EFFECTIVE_L1_TLB_SIZE(x) (((x) & 7) << 12)
310#define EFFECTIVE_L1_TLB_SIZE_MASK 0x00007000
311#define EFFECTIVE_L1_TLB_SIZE_SHIFT 12
312#define EFFECTIVE_L1_QUEUE_SIZE(x) (((x) & 7) << 15)
313#define EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00038000
314#define EFFECTIVE_L1_QUEUE_SIZE_SHIFT 15
315#define MC_VM_L1_TLB_MCD_RD_B_CNTL 0x21A0
316#define MC_VM_L1_TLB_MCB_RD_GFX_CNTL 0x21FC
317#define MC_VM_L1_TLB_MCB_RD_HDP_CNTL 0x2204
318#define MC_VM_L1_TLB_MCB_RD_PDMA_CNTL 0x2208
319#define MC_VM_L1_TLB_MCB_RD_SEM_CNTL 0x220C
320#define MC_VM_L1_TLB_MCB_RD_SYS_CNTL 0x2200
321#define MC_VM_L1_TLB_MCD_WR_A_CNTL 0x21A4
322#define MC_VM_L1_TLB_MCD_WR_B_CNTL 0x21A8
323#define MC_VM_L1_TLB_MCB_WR_GFX_CNTL 0x2210
324#define MC_VM_L1_TLB_MCB_WR_HDP_CNTL 0x2218
325#define MC_VM_L1_TLB_MCB_WR_PDMA_CNTL 0x221C
326#define MC_VM_L1_TLB_MCB_WR_SEM_CNTL 0x2220
327#define MC_VM_L1_TLB_MCB_WR_SYS_CNTL 0x2214
328#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190
329#define LOGICAL_PAGE_NUMBER_MASK 0x000FFFFF
330#define LOGICAL_PAGE_NUMBER_SHIFT 0
331#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194
332#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198
333
334#define PA_CL_ENHANCE 0x8A14
335#define CLIP_VTX_REORDER_ENA (1 << 0)
336#define NUM_CLIP_SEQ(x) ((x) << 1)
337#define PA_SC_AA_CONFIG 0x28C04
338#define PA_SC_AA_SAMPLE_LOCS_2S 0x8B40
339#define PA_SC_AA_SAMPLE_LOCS_4S 0x8B44
340#define PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x8B48
341#define PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x8B4C
342#define S0_X(x) ((x) << 0)
343#define S0_Y(x) ((x) << 4)
344#define S1_X(x) ((x) << 8)
345#define S1_Y(x) ((x) << 12)
346#define S2_X(x) ((x) << 16)
347#define S2_Y(x) ((x) << 20)
348#define S3_X(x) ((x) << 24)
349#define S3_Y(x) ((x) << 28)
350#define S4_X(x) ((x) << 0)
351#define S4_Y(x) ((x) << 4)
352#define S5_X(x) ((x) << 8)
353#define S5_Y(x) ((x) << 12)
354#define S6_X(x) ((x) << 16)
355#define S6_Y(x) ((x) << 20)
356#define S7_X(x) ((x) << 24)
357#define S7_Y(x) ((x) << 28)
358#define PA_SC_CLIPRECT_RULE 0x2820c
359#define PA_SC_ENHANCE 0x8BF0
360#define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
361#define FORCE_EOV_MAX_TILE_CNT(x) ((x) << 12)
362#define PA_SC_LINE_STIPPLE 0x28A0C
363#define PA_SC_LINE_STIPPLE_STATE 0x8B10
364#define PA_SC_MODE_CNTL 0x28A4C
365#define PA_SC_MULTI_CHIP_CNTL 0x8B20
366
367#define PA_SC_SCREEN_SCISSOR_TL 0x28030
368#define PA_SC_GENERIC_SCISSOR_TL 0x28240
369#define PA_SC_WINDOW_SCISSOR_TL 0x28204
370
371#define PCIE_PORT_INDEX 0x0038
372#define PCIE_PORT_DATA 0x003C
373
374#define CHMAP 0x2004
375#define NOOFCHAN_SHIFT 12
376#define NOOFCHAN_MASK 0x00003000
377
378#define RAMCFG 0x2408
379#define NOOFBANK_SHIFT 0
380#define NOOFBANK_MASK 0x00000001
381#define NOOFRANK_SHIFT 1
382#define NOOFRANK_MASK 0x00000002
383#define NOOFROWS_SHIFT 2
384#define NOOFROWS_MASK 0x0000001C
385#define NOOFCOLS_SHIFT 5
386#define NOOFCOLS_MASK 0x00000060
387#define CHANSIZE_SHIFT 7
388#define CHANSIZE_MASK 0x00000080
389#define BURSTLENGTH_SHIFT 8
390#define BURSTLENGTH_MASK 0x00000100
391#define CHANSIZE_OVERRIDE (1 << 10)
392
393#define SCRATCH_REG0 0x8500
394#define SCRATCH_REG1 0x8504
395#define SCRATCH_REG2 0x8508
396#define SCRATCH_REG3 0x850C
397#define SCRATCH_REG4 0x8510
398#define SCRATCH_REG5 0x8514
399#define SCRATCH_REG6 0x8518
400#define SCRATCH_REG7 0x851C
401#define SCRATCH_UMSK 0x8540
402#define SCRATCH_ADDR 0x8544
403
404#define SPI_CONFIG_CNTL 0x9100
405#define GPR_WRITE_PRIORITY(x) ((x) << 0)
406#define DISABLE_INTERP_1 (1 << 5)
407#define SPI_CONFIG_CNTL_1 0x913C
408#define VTX_DONE_DELAY(x) ((x) << 0)
409#define INTERP_ONE_PRIM_PER_ROW (1 << 4)
410#define SPI_INPUT_Z 0x286D8
411#define SPI_PS_IN_CONTROL_0 0x286CC
412#define NUM_INTERP(x) ((x)<<0)
413#define POSITION_ENA (1<<8)
414#define POSITION_CENTROID (1<<9)
415#define POSITION_ADDR(x) ((x)<<10)
416#define PARAM_GEN(x) ((x)<<15)
417#define PARAM_GEN_ADDR(x) ((x)<<19)
418#define BARYC_SAMPLE_CNTL(x) ((x)<<26)
419#define PERSP_GRADIENT_ENA (1<<28)
420#define LINEAR_GRADIENT_ENA (1<<29)
421#define POSITION_SAMPLE (1<<30)
422#define BARYC_AT_SAMPLE_ENA (1<<31)
423#define SPI_PS_IN_CONTROL_1 0x286D0
424#define GEN_INDEX_PIX (1<<0)
425#define GEN_INDEX_PIX_ADDR(x) ((x)<<1)
426#define FRONT_FACE_ENA (1<<8)
427#define FRONT_FACE_CHAN(x) ((x)<<9)
428#define FRONT_FACE_ALL_BITS (1<<11)
429#define FRONT_FACE_ADDR(x) ((x)<<12)
430#define FOG_ADDR(x) ((x)<<17)
431#define FIXED_PT_POSITION_ENA (1<<24)
432#define FIXED_PT_POSITION_ADDR(x) ((x)<<25)
433
434#define SQ_MS_FIFO_SIZES 0x8CF0
435#define CACHE_FIFO_SIZE(x) ((x) << 0)
436#define FETCH_FIFO_HIWATER(x) ((x) << 8)
437#define DONE_FIFO_HIWATER(x) ((x) << 16)
438#define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24)
439#define SQ_PGM_START_ES 0x28880
440#define SQ_PGM_START_FS 0x28894
441#define SQ_PGM_START_GS 0x2886C
442#define SQ_PGM_START_PS 0x28840
443#define SQ_PGM_RESOURCES_PS 0x28850
444#define SQ_PGM_EXPORTS_PS 0x28854
445#define SQ_PGM_CF_OFFSET_PS 0x288cc
446#define SQ_PGM_START_VS 0x28858
447#define SQ_PGM_RESOURCES_VS 0x28868
448#define SQ_PGM_CF_OFFSET_VS 0x288d0
449
450#define SQ_VTX_CONSTANT_WORD0_0 0x30000
451#define SQ_VTX_CONSTANT_WORD1_0 0x30004
452#define SQ_VTX_CONSTANT_WORD2_0 0x30008
453# define SQ_VTXC_BASE_ADDR_HI(x) ((x) << 0)
454# define SQ_VTXC_STRIDE(x) ((x) << 8)
455# define SQ_VTXC_ENDIAN_SWAP(x) ((x) << 30)
456# define SQ_ENDIAN_NONE 0
457# define SQ_ENDIAN_8IN16 1
458# define SQ_ENDIAN_8IN32 2
459#define SQ_VTX_CONSTANT_WORD3_0 0x3000c
460#define SQ_VTX_CONSTANT_WORD6_0 0x38018
461#define S__SQ_VTX_CONSTANT_TYPE(x) (((x) & 3) << 30)
462#define G__SQ_VTX_CONSTANT_TYPE(x) (((x) >> 30) & 3)
463#define SQ_TEX_VTX_INVALID_TEXTURE 0x0
464#define SQ_TEX_VTX_INVALID_BUFFER 0x1
465#define SQ_TEX_VTX_VALID_TEXTURE 0x2
466#define SQ_TEX_VTX_VALID_BUFFER 0x3
467
468
469#define SX_MISC 0x28350
470#define SX_MEMORY_EXPORT_BASE 0x9010
471#define SX_DEBUG_1 0x9054
472#define SMX_EVENT_RELEASE (1 << 0)
473#define ENABLE_NEW_SMX_ADDRESS (1 << 16)
474
475#define TA_CNTL_AUX 0x9508
476#define DISABLE_CUBE_WRAP (1 << 0)
477#define DISABLE_CUBE_ANISO (1 << 1)
478#define SYNC_GRADIENT (1 << 24)
479#define SYNC_WALKER (1 << 25)
480#define SYNC_ALIGNER (1 << 26)
481#define BILINEAR_PRECISION_6_BIT (0 << 31)
482#define BILINEAR_PRECISION_8_BIT (1 << 31)
483
484#define TC_CNTL 0x9608
485#define TC_L2_SIZE(x) ((x)<<5)
486#define L2_DISABLE_LATE_HIT (1<<9)
487
488#define VC_ENHANCE 0x9714
489
490#define VGT_CACHE_INVALIDATION 0x88C4
491#define CACHE_INVALIDATION(x) ((x)<<0)
492#define VC_ONLY 0
493#define TC_ONLY 1
494#define VC_AND_TC 2
495#define VGT_DMA_BASE 0x287E8
496#define VGT_DMA_BASE_HI 0x287E4
497#define VGT_ES_PER_GS 0x88CC
498#define VGT_GS_PER_ES 0x88C8
499#define VGT_GS_PER_VS 0x88E8
500#define VGT_GS_VERTEX_REUSE 0x88D4
501#define VGT_PRIMITIVE_TYPE 0x8958
502#define VGT_NUM_INSTANCES 0x8974
503#define VGT_OUT_DEALLOC_CNTL 0x28C5C
504#define DEALLOC_DIST_MASK 0x0000007F
505#define VGT_STRMOUT_BASE_OFFSET_0 0x28B10
506#define VGT_STRMOUT_BASE_OFFSET_1 0x28B14
507#define VGT_STRMOUT_BASE_OFFSET_2 0x28B18
508#define VGT_STRMOUT_BASE_OFFSET_3 0x28B1c
509#define VGT_STRMOUT_BASE_OFFSET_HI_0 0x28B44
510#define VGT_STRMOUT_BASE_OFFSET_HI_1 0x28B48
511#define VGT_STRMOUT_BASE_OFFSET_HI_2 0x28B4c
512#define VGT_STRMOUT_BASE_OFFSET_HI_3 0x28B50
513#define VGT_STRMOUT_BUFFER_BASE_0 0x28AD8
514#define VGT_STRMOUT_BUFFER_BASE_1 0x28AE8
515#define VGT_STRMOUT_BUFFER_BASE_2 0x28AF8
516#define VGT_STRMOUT_BUFFER_BASE_3 0x28B08
517#define VGT_STRMOUT_BUFFER_OFFSET_0 0x28ADC
518#define VGT_STRMOUT_BUFFER_OFFSET_1 0x28AEC
519#define VGT_STRMOUT_BUFFER_OFFSET_2 0x28AFC
520#define VGT_STRMOUT_BUFFER_OFFSET_3 0x28B0C
521#define VGT_STRMOUT_BUFFER_SIZE_0 0x28AD0
522#define VGT_STRMOUT_BUFFER_SIZE_1 0x28AE0
523#define VGT_STRMOUT_BUFFER_SIZE_2 0x28AF0
524#define VGT_STRMOUT_BUFFER_SIZE_3 0x28B00
525
526#define VGT_STRMOUT_EN 0x28AB0
527#define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58
528#define VTX_REUSE_DEPTH_MASK 0x000000FF
529#define VGT_EVENT_INITIATOR 0x28a90
530# define CACHE_FLUSH_AND_INV_EVENT_TS (0x14 << 0)
531# define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0)
532
533#define VM_CONTEXT0_CNTL 0x1410
534#define ENABLE_CONTEXT (1 << 0)
535#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
536#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
537#define VM_CONTEXT0_INVALIDATION_LOW_ADDR 0x1490
538#define VM_CONTEXT0_INVALIDATION_HIGH_ADDR 0x14B0
539#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x1574
540#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x1594
541#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x15B4
542#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1554
543#define VM_CONTEXT0_REQUEST_RESPONSE 0x1470
544#define REQUEST_TYPE(x) (((x) & 0xf) << 0)
545#define RESPONSE_TYPE_MASK 0x000000F0
546#define RESPONSE_TYPE_SHIFT 4
547#define VM_L2_CNTL 0x1400
548#define ENABLE_L2_CACHE (1 << 0)
549#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
550#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
551#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 13)
552#define VM_L2_CNTL2 0x1404
553#define INVALIDATE_ALL_L1_TLBS (1 << 0)
554#define INVALIDATE_L2_CACHE (1 << 1)
555#define VM_L2_CNTL3 0x1408
556#define BANK_SELECT_0(x) (((x) & 0x1f) << 0)
557#define BANK_SELECT_1(x) (((x) & 0x1f) << 5)
558#define L2_CACHE_UPDATE_MODE(x) (((x) & 3) << 10)
559#define VM_L2_STATUS 0x140C
560#define L2_BUSY (1 << 0)
561
562#define WAIT_UNTIL 0x8040
563#define WAIT_2D_IDLE_bit (1 << 14)
564#define WAIT_3D_IDLE_bit (1 << 15)
565#define WAIT_2D_IDLECLEAN_bit (1 << 16)
566#define WAIT_3D_IDLECLEAN_bit (1 << 17)
567
568#define IH_RB_CNTL 0x3e00
569# define IH_RB_ENABLE (1 << 0)
570# define IH_IB_SIZE(x) ((x) << 1) /* log2 */
571# define IH_RB_FULL_DRAIN_ENABLE (1 << 6)
572# define IH_WPTR_WRITEBACK_ENABLE (1 << 8)
573# define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */
574# define IH_WPTR_OVERFLOW_ENABLE (1 << 16)
575# define IH_WPTR_OVERFLOW_CLEAR (1 << 31)
576#define IH_RB_BASE 0x3e04
577#define IH_RB_RPTR 0x3e08
578#define IH_RB_WPTR 0x3e0c
579# define RB_OVERFLOW (1 << 0)
580# define WPTR_OFFSET_MASK 0x3fffc
581#define IH_RB_WPTR_ADDR_HI 0x3e10
582#define IH_RB_WPTR_ADDR_LO 0x3e14
583#define IH_CNTL 0x3e18
584# define ENABLE_INTR (1 << 0)
585# define IH_MC_SWAP(x) ((x) << 1)
586# define IH_MC_SWAP_NONE 0
587# define IH_MC_SWAP_16BIT 1
588# define IH_MC_SWAP_32BIT 2
589# define IH_MC_SWAP_64BIT 3
590# define RPTR_REARM (1 << 4)
591# define MC_WRREQ_CREDIT(x) ((x) << 15)
592# define MC_WR_CLEAN_CNT(x) ((x) << 20)
593
594#define RLC_CNTL 0x3f00
595# define RLC_ENABLE (1 << 0)
596#define RLC_HB_BASE 0x3f10
597#define RLC_HB_CNTL 0x3f0c
598#define RLC_HB_RPTR 0x3f20
599#define RLC_HB_WPTR 0x3f1c
600#define RLC_HB_WPTR_LSB_ADDR 0x3f14
601#define RLC_HB_WPTR_MSB_ADDR 0x3f18
602#define RLC_MC_CNTL 0x3f44
603#define RLC_UCODE_CNTL 0x3f48
604#define RLC_UCODE_ADDR 0x3f2c
605#define RLC_UCODE_DATA 0x3f30
606
607/* new for TN */
608#define TN_RLC_SAVE_AND_RESTORE_BASE 0x3f10
609#define TN_RLC_CLEAR_STATE_RESTORE_BASE 0x3f20
610
611#define SRBM_SOFT_RESET 0xe60
612# define SOFT_RESET_RLC (1 << 13)
613
614#define CP_INT_CNTL 0xc124
615# define CNTX_BUSY_INT_ENABLE (1 << 19)
616# define CNTX_EMPTY_INT_ENABLE (1 << 20)
617# define SCRATCH_INT_ENABLE (1 << 25)
618# define TIME_STAMP_INT_ENABLE (1 << 26)
619# define IB2_INT_ENABLE (1 << 29)
620# define IB1_INT_ENABLE (1 << 30)
621# define RB_INT_ENABLE (1 << 31)
622#define CP_INT_STATUS 0xc128
623# define SCRATCH_INT_STAT (1 << 25)
624# define TIME_STAMP_INT_STAT (1 << 26)
625# define IB2_INT_STAT (1 << 29)
626# define IB1_INT_STAT (1 << 30)
627# define RB_INT_STAT (1 << 31)
628
629#define GRBM_INT_CNTL 0x8060
630# define RDERR_INT_ENABLE (1 << 0)
631# define WAIT_COUNT_TIMEOUT_INT_ENABLE (1 << 1)
632# define GUI_IDLE_INT_ENABLE (1 << 19)
633
634#define INTERRUPT_CNTL 0x5468
635# define IH_DUMMY_RD_OVERRIDE (1 << 0)
636# define IH_DUMMY_RD_EN (1 << 1)
637# define IH_REQ_NONSNOOP_EN (1 << 3)
638# define GEN_IH_INT_EN (1 << 8)
639#define INTERRUPT_CNTL2 0x546c
640
641#define D1MODE_VBLANK_STATUS 0x6534
642#define D2MODE_VBLANK_STATUS 0x6d34
643# define DxMODE_VBLANK_OCCURRED (1 << 0)
644# define DxMODE_VBLANK_ACK (1 << 4)
645# define DxMODE_VBLANK_STAT (1 << 12)
646# define DxMODE_VBLANK_INTERRUPT (1 << 16)
647# define DxMODE_VBLANK_INTERRUPT_TYPE (1 << 17)
648#define D1MODE_VLINE_STATUS 0x653c
649#define D2MODE_VLINE_STATUS 0x6d3c
650# define DxMODE_VLINE_OCCURRED (1 << 0)
651# define DxMODE_VLINE_ACK (1 << 4)
652# define DxMODE_VLINE_STAT (1 << 12)
653# define DxMODE_VLINE_INTERRUPT (1 << 16)
654# define DxMODE_VLINE_INTERRUPT_TYPE (1 << 17)
655#define DxMODE_INT_MASK 0x6540
656# define D1MODE_VBLANK_INT_MASK (1 << 0)
657# define D1MODE_VLINE_INT_MASK (1 << 4)
658# define D2MODE_VBLANK_INT_MASK (1 << 8)
659# define D2MODE_VLINE_INT_MASK (1 << 12)
660#define DCE3_DISP_INTERRUPT_STATUS 0x7ddc
661# define DC_HPD1_INTERRUPT (1 << 18)
662# define DC_HPD2_INTERRUPT (1 << 19)
663#define DISP_INTERRUPT_STATUS 0x7edc
664# define LB_D1_VLINE_INTERRUPT (1 << 2)
665# define LB_D2_VLINE_INTERRUPT (1 << 3)
666# define LB_D1_VBLANK_INTERRUPT (1 << 4)
667# define LB_D2_VBLANK_INTERRUPT (1 << 5)
668# define DACA_AUTODETECT_INTERRUPT (1 << 16)
669# define DACB_AUTODETECT_INTERRUPT (1 << 17)
670# define DC_HOT_PLUG_DETECT1_INTERRUPT (1 << 18)
671# define DC_HOT_PLUG_DETECT2_INTERRUPT (1 << 19)
672# define DC_I2C_SW_DONE_INTERRUPT (1 << 20)
673# define DC_I2C_HW_DONE_INTERRUPT (1 << 21)
674#define DISP_INTERRUPT_STATUS_CONTINUE 0x7ee8
675#define DCE3_DISP_INTERRUPT_STATUS_CONTINUE 0x7de8
676# define DC_HPD4_INTERRUPT (1 << 14)
677# define DC_HPD4_RX_INTERRUPT (1 << 15)
678# define DC_HPD3_INTERRUPT (1 << 28)
679# define DC_HPD1_RX_INTERRUPT (1 << 29)
680# define DC_HPD2_RX_INTERRUPT (1 << 30)
681#define DCE3_DISP_INTERRUPT_STATUS_CONTINUE2 0x7dec
682# define DC_HPD3_RX_INTERRUPT (1 << 0)
683# define DIGA_DP_VID_STREAM_DISABLE_INTERRUPT (1 << 1)
684# define DIGA_DP_STEER_FIFO_OVERFLOW_INTERRUPT (1 << 2)
685# define DIGB_DP_VID_STREAM_DISABLE_INTERRUPT (1 << 3)
686# define DIGB_DP_STEER_FIFO_OVERFLOW_INTERRUPT (1 << 4)
687# define AUX1_SW_DONE_INTERRUPT (1 << 5)
688# define AUX1_LS_DONE_INTERRUPT (1 << 6)
689# define AUX2_SW_DONE_INTERRUPT (1 << 7)
690# define AUX2_LS_DONE_INTERRUPT (1 << 8)
691# define AUX3_SW_DONE_INTERRUPT (1 << 9)
692# define AUX3_LS_DONE_INTERRUPT (1 << 10)
693# define AUX4_SW_DONE_INTERRUPT (1 << 11)
694# define AUX4_LS_DONE_INTERRUPT (1 << 12)
695# define DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT (1 << 13)
696# define DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT (1 << 14)
697/* DCE 3.2 */
698# define AUX5_SW_DONE_INTERRUPT (1 << 15)
699# define AUX5_LS_DONE_INTERRUPT (1 << 16)
700# define AUX6_SW_DONE_INTERRUPT (1 << 17)
701# define AUX6_LS_DONE_INTERRUPT (1 << 18)
702# define DC_HPD5_INTERRUPT (1 << 19)
703# define DC_HPD5_RX_INTERRUPT (1 << 20)
704# define DC_HPD6_INTERRUPT (1 << 21)
705# define DC_HPD6_RX_INTERRUPT (1 << 22)
706
707#define DACA_AUTO_DETECT_CONTROL 0x7828
708#define DACB_AUTO_DETECT_CONTROL 0x7a28
709#define DCE3_DACA_AUTO_DETECT_CONTROL 0x7028
710#define DCE3_DACB_AUTO_DETECT_CONTROL 0x7128
711# define DACx_AUTODETECT_MODE(x) ((x) << 0)
712# define DACx_AUTODETECT_MODE_NONE 0
713# define DACx_AUTODETECT_MODE_CONNECT 1
714# define DACx_AUTODETECT_MODE_DISCONNECT 2
715# define DACx_AUTODETECT_FRAME_TIME_COUNTER(x) ((x) << 8)
716/* bit 18 = R/C, 17 = G/Y, 16 = B/Comp */
717# define DACx_AUTODETECT_CHECK_MASK(x) ((x) << 16)
718
719#define DCE3_DACA_AUTODETECT_INT_CONTROL 0x7038
720#define DCE3_DACB_AUTODETECT_INT_CONTROL 0x7138
721#define DACA_AUTODETECT_INT_CONTROL 0x7838
722#define DACB_AUTODETECT_INT_CONTROL 0x7a38
723# define DACx_AUTODETECT_ACK (1 << 0)
724# define DACx_AUTODETECT_INT_ENABLE (1 << 16)
725
726#define DC_HOT_PLUG_DETECT1_CONTROL 0x7d00
727#define DC_HOT_PLUG_DETECT2_CONTROL 0x7d10
728#define DC_HOT_PLUG_DETECT3_CONTROL 0x7d24
729# define DC_HOT_PLUG_DETECTx_EN (1 << 0)
730
731#define DC_HOT_PLUG_DETECT1_INT_STATUS 0x7d04
732#define DC_HOT_PLUG_DETECT2_INT_STATUS 0x7d14
733#define DC_HOT_PLUG_DETECT3_INT_STATUS 0x7d28
734# define DC_HOT_PLUG_DETECTx_INT_STATUS (1 << 0)
735# define DC_HOT_PLUG_DETECTx_SENSE (1 << 1)
736
737/* DCE 3.0 */
738#define DC_HPD1_INT_STATUS 0x7d00
739#define DC_HPD2_INT_STATUS 0x7d0c
740#define DC_HPD3_INT_STATUS 0x7d18
741#define DC_HPD4_INT_STATUS 0x7d24
742/* DCE 3.2 */
743#define DC_HPD5_INT_STATUS 0x7dc0
744#define DC_HPD6_INT_STATUS 0x7df4
745# define DC_HPDx_INT_STATUS (1 << 0)
746# define DC_HPDx_SENSE (1 << 1)
747# define DC_HPDx_RX_INT_STATUS (1 << 8)
748
749#define DC_HOT_PLUG_DETECT1_INT_CONTROL 0x7d08
750#define DC_HOT_PLUG_DETECT2_INT_CONTROL 0x7d18
751#define DC_HOT_PLUG_DETECT3_INT_CONTROL 0x7d2c
752# define DC_HOT_PLUG_DETECTx_INT_ACK (1 << 0)
753# define DC_HOT_PLUG_DETECTx_INT_POLARITY (1 << 8)
754# define DC_HOT_PLUG_DETECTx_INT_EN (1 << 16)
755/* DCE 3.0 */
756#define DC_HPD1_INT_CONTROL 0x7d04
757#define DC_HPD2_INT_CONTROL 0x7d10
758#define DC_HPD3_INT_CONTROL 0x7d1c
759#define DC_HPD4_INT_CONTROL 0x7d28
760/* DCE 3.2 */
761#define DC_HPD5_INT_CONTROL 0x7dc4
762#define DC_HPD6_INT_CONTROL 0x7df8
763# define DC_HPDx_INT_ACK (1 << 0)
764# define DC_HPDx_INT_POLARITY (1 << 8)
765# define DC_HPDx_INT_EN (1 << 16)
766# define DC_HPDx_RX_INT_ACK (1 << 20)
767# define DC_HPDx_RX_INT_EN (1 << 24)
768
769/* DCE 3.0 */
770#define DC_HPD1_CONTROL 0x7d08
771#define DC_HPD2_CONTROL 0x7d14
772#define DC_HPD3_CONTROL 0x7d20
773#define DC_HPD4_CONTROL 0x7d2c
774/* DCE 3.2 */
775#define DC_HPD5_CONTROL 0x7dc8
776#define DC_HPD6_CONTROL 0x7dfc
777# define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0)
778# define DC_HPDx_RX_INT_TIMER(x) ((x) << 16)
779/* DCE 3.2 */
780# define DC_HPDx_EN (1 << 28)
781
782#define D1GRPH_INTERRUPT_STATUS 0x6158
783#define D2GRPH_INTERRUPT_STATUS 0x6958
784# define DxGRPH_PFLIP_INT_OCCURRED (1 << 0)
785# define DxGRPH_PFLIP_INT_CLEAR (1 << 8)
786#define D1GRPH_INTERRUPT_CONTROL 0x615c
787#define D2GRPH_INTERRUPT_CONTROL 0x695c
788# define DxGRPH_PFLIP_INT_MASK (1 << 0)
789# define DxGRPH_PFLIP_INT_TYPE (1 << 8)
790
791/* PCIE link stuff */
792#define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */
793# define LC_POINT_7_PLUS_EN (1 << 6)
794#define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */
795# define LC_LINK_WIDTH_SHIFT 0
796# define LC_LINK_WIDTH_MASK 0x7
797# define LC_LINK_WIDTH_X0 0
798# define LC_LINK_WIDTH_X1 1
799# define LC_LINK_WIDTH_X2 2
800# define LC_LINK_WIDTH_X4 3
801# define LC_LINK_WIDTH_X8 4
802# define LC_LINK_WIDTH_X16 6
803# define LC_LINK_WIDTH_RD_SHIFT 4
804# define LC_LINK_WIDTH_RD_MASK 0x70
805# define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
806# define LC_RECONFIG_NOW (1 << 8)
807# define LC_RENEGOTIATION_SUPPORT (1 << 9)
808# define LC_RENEGOTIATE_EN (1 << 10)
809# define LC_SHORT_RECONFIG_EN (1 << 11)
810# define LC_UPCONFIGURE_SUPPORT (1 << 12)
811# define LC_UPCONFIGURE_DIS (1 << 13)
812#define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */
813# define LC_GEN2_EN_STRAP (1 << 0)
814# define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1)
815# define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5)
816# define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6)
817# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8)
818# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3
819# define LC_CURRENT_DATA_RATE (1 << 11)
820# define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14)
821# define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21)
822# define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23)
823# define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24)
824#define MM_CFGREGS_CNTL 0x544c
825# define MM_WR_TO_CFG_EN (1 << 3)
826#define LINK_CNTL2 0x88 /* F0 */
827# define TARGET_LINK_SPEED_MASK (0xf << 0)
828# define SELECTABLE_DEEMPHASIS (1 << 6)
829
830/* Audio clocks */
831#define DCCG_AUDIO_DTO0_PHASE 0x0514
832#define DCCG_AUDIO_DTO0_MODULE 0x0518
833#define DCCG_AUDIO_DTO0_LOAD 0x051c
834# define DTO_LOAD (1 << 31)
835#define DCCG_AUDIO_DTO0_CNTL 0x0520
836
837#define DCCG_AUDIO_DTO1_PHASE 0x0524
838#define DCCG_AUDIO_DTO1_MODULE 0x0528
839#define DCCG_AUDIO_DTO1_LOAD 0x052c
840#define DCCG_AUDIO_DTO1_CNTL 0x0530
841
842#define DCCG_AUDIO_DTO_SELECT 0x0534
843
844/* digital blocks */
845#define TMDSA_CNTL 0x7880
846# define TMDSA_HDMI_EN (1 << 2)
847#define LVTMA_CNTL 0x7a80
848# define LVTMA_HDMI_EN (1 << 2)
849#define DDIA_CNTL 0x7200
850# define DDIA_HDMI_EN (1 << 2)
851#define DIG0_CNTL 0x75a0
852# define DIG_MODE(x) (((x) & 7) << 8)
853# define DIG_MODE_DP 0
854# define DIG_MODE_LVDS 1
855# define DIG_MODE_TMDS_DVI 2
856# define DIG_MODE_TMDS_HDMI 3
857# define DIG_MODE_SDVO 4
858#define DIG1_CNTL 0x79a0
859
860/* rs6xx/rs740 and r6xx share the same HDMI blocks, however, rs6xx has only one
861 * instance of the blocks while r6xx has 2. DCE 3.0 cards are slightly
862 * different due to the new DIG blocks, but also have 2 instances.
863 * DCE 3.0 HDMI blocks are part of each DIG encoder.
864 */
865
866/* rs6xx/rs740/r6xx/dce3 */
867#define HDMI0_CONTROL 0x7400
868/* rs6xx/rs740/r6xx */
869# define HDMI0_ENABLE (1 << 0)
870# define HDMI0_STREAM(x) (((x) & 3) << 2)
871# define HDMI0_STREAM_TMDSA 0
872# define HDMI0_STREAM_LVTMA 1
873# define HDMI0_STREAM_DVOA 2
874# define HDMI0_STREAM_DDIA 3
875/* rs6xx/r6xx/dce3 */
876# define HDMI0_ERROR_ACK (1 << 8)
877# define HDMI0_ERROR_MASK (1 << 9)
878#define HDMI0_STATUS 0x7404
879# define HDMI0_ACTIVE_AVMUTE (1 << 0)
880# define HDMI0_AUDIO_ENABLE (1 << 4)
881# define HDMI0_AZ_FORMAT_WTRIG (1 << 28)
882# define HDMI0_AZ_FORMAT_WTRIG_INT (1 << 29)
883#define HDMI0_AUDIO_PACKET_CONTROL 0x7408
884# define HDMI0_AUDIO_SAMPLE_SEND (1 << 0)
885# define HDMI0_AUDIO_DELAY_EN(x) (((x) & 3) << 4)
886# define HDMI0_AUDIO_SEND_MAX_PACKETS (1 << 8)
887# define HDMI0_AUDIO_TEST_EN (1 << 12)
888# define HDMI0_AUDIO_PACKETS_PER_LINE(x) (((x) & 0x1f) << 16)
889# define HDMI0_AUDIO_CHANNEL_SWAP (1 << 24)
890# define HDMI0_60958_CS_UPDATE (1 << 26)
891# define HDMI0_AZ_FORMAT_WTRIG_MASK (1 << 28)
892# define HDMI0_AZ_FORMAT_WTRIG_ACK (1 << 29)
893#define HDMI0_AUDIO_CRC_CONTROL 0x740c
894# define HDMI0_AUDIO_CRC_EN (1 << 0)
895#define HDMI0_VBI_PACKET_CONTROL 0x7410
896# define HDMI0_NULL_SEND (1 << 0)
897# define HDMI0_GC_SEND (1 << 4)
898# define HDMI0_GC_CONT (1 << 5) /* 0 - once; 1 - every frame */
899#define HDMI0_INFOFRAME_CONTROL0 0x7414
900# define HDMI0_AVI_INFO_SEND (1 << 0)
901# define HDMI0_AVI_INFO_CONT (1 << 1)
902# define HDMI0_AUDIO_INFO_SEND (1 << 4)
903# define HDMI0_AUDIO_INFO_CONT (1 << 5)
904# define HDMI0_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - hmdi regs */
905# define HDMI0_AUDIO_INFO_UPDATE (1 << 7)
906# define HDMI0_MPEG_INFO_SEND (1 << 8)
907# define HDMI0_MPEG_INFO_CONT (1 << 9)
908# define HDMI0_MPEG_INFO_UPDATE (1 << 10)
909#define HDMI0_INFOFRAME_CONTROL1 0x7418
910# define HDMI0_AVI_INFO_LINE(x) (((x) & 0x3f) << 0)
911# define HDMI0_AUDIO_INFO_LINE(x) (((x) & 0x3f) << 8)
912# define HDMI0_MPEG_INFO_LINE(x) (((x) & 0x3f) << 16)
913#define HDMI0_GENERIC_PACKET_CONTROL 0x741c
914# define HDMI0_GENERIC0_SEND (1 << 0)
915# define HDMI0_GENERIC0_CONT (1 << 1)
916# define HDMI0_GENERIC0_UPDATE (1 << 2)
917# define HDMI0_GENERIC1_SEND (1 << 4)
918# define HDMI0_GENERIC1_CONT (1 << 5)
919# define HDMI0_GENERIC0_LINE(x) (((x) & 0x3f) << 16)
920# define HDMI0_GENERIC1_LINE(x) (((x) & 0x3f) << 24)
921#define HDMI0_GC 0x7428
922# define HDMI0_GC_AVMUTE (1 << 0)
923#define HDMI0_AVI_INFO0 0x7454
924# define HDMI0_AVI_INFO_CHECKSUM(x) (((x) & 0xff) << 0)
925# define HDMI0_AVI_INFO_S(x) (((x) & 3) << 8)
926# define HDMI0_AVI_INFO_B(x) (((x) & 3) << 10)
927# define HDMI0_AVI_INFO_A(x) (((x) & 1) << 12)
928# define HDMI0_AVI_INFO_Y(x) (((x) & 3) << 13)
929# define HDMI0_AVI_INFO_Y_RGB 0
930# define HDMI0_AVI_INFO_Y_YCBCR422 1
931# define HDMI0_AVI_INFO_Y_YCBCR444 2
932# define HDMI0_AVI_INFO_Y_A_B_S(x) (((x) & 0xff) << 8)
933# define HDMI0_AVI_INFO_R(x) (((x) & 0xf) << 16)
934# define HDMI0_AVI_INFO_M(x) (((x) & 0x3) << 20)
935# define HDMI0_AVI_INFO_C(x) (((x) & 0x3) << 22)
936# define HDMI0_AVI_INFO_C_M_R(x) (((x) & 0xff) << 16)
937# define HDMI0_AVI_INFO_SC(x) (((x) & 0x3) << 24)
938# define HDMI0_AVI_INFO_ITC_EC_Q_SC(x) (((x) & 0xff) << 24)
939#define HDMI0_AVI_INFO1 0x7458
940# define HDMI0_AVI_INFO_VIC(x) (((x) & 0x7f) << 0) /* don't use avi infoframe v1 */
941# define HDMI0_AVI_INFO_PR(x) (((x) & 0xf) << 8) /* don't use avi infoframe v1 */
942# define HDMI0_AVI_INFO_TOP(x) (((x) & 0xffff) << 16)
943#define HDMI0_AVI_INFO2 0x745c
944# define HDMI0_AVI_INFO_BOTTOM(x) (((x) & 0xffff) << 0)
945# define HDMI0_AVI_INFO_LEFT(x) (((x) & 0xffff) << 16)
946#define HDMI0_AVI_INFO3 0x7460
947# define HDMI0_AVI_INFO_RIGHT(x) (((x) & 0xffff) << 0)
948# define HDMI0_AVI_INFO_VERSION(x) (((x) & 3) << 24)
949#define HDMI0_MPEG_INFO0 0x7464
950# define HDMI0_MPEG_INFO_CHECKSUM(x) (((x) & 0xff) << 0)
951# define HDMI0_MPEG_INFO_MB0(x) (((x) & 0xff) << 8)
952# define HDMI0_MPEG_INFO_MB1(x) (((x) & 0xff) << 16)
953# define HDMI0_MPEG_INFO_MB2(x) (((x) & 0xff) << 24)
954#define HDMI0_MPEG_INFO1 0x7468
955# define HDMI0_MPEG_INFO_MB3(x) (((x) & 0xff) << 0)
956# define HDMI0_MPEG_INFO_MF(x) (((x) & 3) << 8)
957# define HDMI0_MPEG_INFO_FR(x) (((x) & 1) << 12)
958#define HDMI0_GENERIC0_HDR 0x746c
959#define HDMI0_GENERIC0_0 0x7470
960#define HDMI0_GENERIC0_1 0x7474
961#define HDMI0_GENERIC0_2 0x7478
962#define HDMI0_GENERIC0_3 0x747c
963#define HDMI0_GENERIC0_4 0x7480
964#define HDMI0_GENERIC0_5 0x7484
965#define HDMI0_GENERIC0_6 0x7488
966#define HDMI0_GENERIC1_HDR 0x748c
967#define HDMI0_GENERIC1_0 0x7490
968#define HDMI0_GENERIC1_1 0x7494
969#define HDMI0_GENERIC1_2 0x7498
970#define HDMI0_GENERIC1_3 0x749c
971#define HDMI0_GENERIC1_4 0x74a0
972#define HDMI0_GENERIC1_5 0x74a4
973#define HDMI0_GENERIC1_6 0x74a8
974#define HDMI0_ACR_32_0 0x74ac
975# define HDMI0_ACR_CTS_32(x) (((x) & 0xfffff) << 12)
976#define HDMI0_ACR_32_1 0x74b0
977# define HDMI0_ACR_N_32(x) (((x) & 0xfffff) << 0)
978#define HDMI0_ACR_44_0 0x74b4
979# define HDMI0_ACR_CTS_44(x) (((x) & 0xfffff) << 12)
980#define HDMI0_ACR_44_1 0x74b8
981# define HDMI0_ACR_N_44(x) (((x) & 0xfffff) << 0)
982#define HDMI0_ACR_48_0 0x74bc
983# define HDMI0_ACR_CTS_48(x) (((x) & 0xfffff) << 12)
984#define HDMI0_ACR_48_1 0x74c0
985# define HDMI0_ACR_N_48(x) (((x) & 0xfffff) << 0)
986#define HDMI0_ACR_STATUS_0 0x74c4
987#define HDMI0_ACR_STATUS_1 0x74c8
988#define HDMI0_AUDIO_INFO0 0x74cc
989# define HDMI0_AUDIO_INFO_CHECKSUM(x) (((x) & 0xff) << 0)
990# define HDMI0_AUDIO_INFO_CC(x) (((x) & 7) << 8)
991#define HDMI0_AUDIO_INFO1 0x74d0
992# define HDMI0_AUDIO_INFO_CA(x) (((x) & 0xff) << 0)
993# define HDMI0_AUDIO_INFO_LSV(x) (((x) & 0xf) << 11)
994# define HDMI0_AUDIO_INFO_DM_INH(x) (((x) & 1) << 15)
995# define HDMI0_AUDIO_INFO_DM_INH_LSV(x) (((x) & 0xff) << 8)
996#define HDMI0_60958_0 0x74d4
997# define HDMI0_60958_CS_A(x) (((x) & 1) << 0)
998# define HDMI0_60958_CS_B(x) (((x) & 1) << 1)
999# define HDMI0_60958_CS_C(x) (((x) & 1) << 2)
1000# define HDMI0_60958_CS_D(x) (((x) & 3) << 3)
1001# define HDMI0_60958_CS_MODE(x) (((x) & 3) << 6)
1002# define HDMI0_60958_CS_CATEGORY_CODE(x) (((x) & 0xff) << 8)
1003# define HDMI0_60958_CS_SOURCE_NUMBER(x) (((x) & 0xf) << 16)
1004# define HDMI0_60958_CS_CHANNEL_NUMBER_L(x) (((x) & 0xf) << 20)
1005# define HDMI0_60958_CS_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 24)
1006# define HDMI0_60958_CS_CLOCK_ACCURACY(x) (((x) & 3) << 28)
1007#define HDMI0_60958_1 0x74d8
1008# define HDMI0_60958_CS_WORD_LENGTH(x) (((x) & 0xf) << 0)
1009# define HDMI0_60958_CS_ORIGINAL_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 4)
1010# define HDMI0_60958_CS_VALID_L(x) (((x) & 1) << 16)
1011# define HDMI0_60958_CS_VALID_R(x) (((x) & 1) << 18)
1012# define HDMI0_60958_CS_CHANNEL_NUMBER_R(x) (((x) & 0xf) << 20)
1013#define HDMI0_ACR_PACKET_CONTROL 0x74dc
1014# define HDMI0_ACR_SEND (1 << 0)
1015# define HDMI0_ACR_CONT (1 << 1)
1016# define HDMI0_ACR_SELECT(x) (((x) & 3) << 4)
1017# define HDMI0_ACR_HW 0
1018# define HDMI0_ACR_32 1
1019# define HDMI0_ACR_44 2
1020# define HDMI0_ACR_48 3
1021# define HDMI0_ACR_SOURCE (1 << 8) /* 0 - hw; 1 - cts value */
1022# define HDMI0_ACR_AUTO_SEND (1 << 12)
1023#define HDMI0_RAMP_CONTROL0 0x74e0
1024# define HDMI0_RAMP_MAX_COUNT(x) (((x) & 0xffffff) << 0)
1025#define HDMI0_RAMP_CONTROL1 0x74e4
1026# define HDMI0_RAMP_MIN_COUNT(x) (((x) & 0xffffff) << 0)
1027#define HDMI0_RAMP_CONTROL2 0x74e8
1028# define HDMI0_RAMP_INC_COUNT(x) (((x) & 0xffffff) << 0)
1029#define HDMI0_RAMP_CONTROL3 0x74ec
1030# define HDMI0_RAMP_DEC_COUNT(x) (((x) & 0xffffff) << 0)
1031/* HDMI0_60958_2 is r7xx only */
1032#define HDMI0_60958_2 0x74f0
1033# define HDMI0_60958_CS_CHANNEL_NUMBER_2(x) (((x) & 0xf) << 0)
1034# define HDMI0_60958_CS_CHANNEL_NUMBER_3(x) (((x) & 0xf) << 4)
1035# define HDMI0_60958_CS_CHANNEL_NUMBER_4(x) (((x) & 0xf) << 8)
1036# define HDMI0_60958_CS_CHANNEL_NUMBER_5(x) (((x) & 0xf) << 12)
1037# define HDMI0_60958_CS_CHANNEL_NUMBER_6(x) (((x) & 0xf) << 16)
1038# define HDMI0_60958_CS_CHANNEL_NUMBER_7(x) (((x) & 0xf) << 20)
1039/* r6xx only; second instance starts at 0x7700 */
1040#define HDMI1_CONTROL 0x7700
1041#define HDMI1_STATUS 0x7704
1042#define HDMI1_AUDIO_PACKET_CONTROL 0x7708
1043/* DCE3; second instance starts at 0x7800 NOT 0x7700 */
1044#define DCE3_HDMI1_CONTROL 0x7800
1045#define DCE3_HDMI1_STATUS 0x7804
1046#define DCE3_HDMI1_AUDIO_PACKET_CONTROL 0x7808
1047/* DCE3.2 (for interrupts) */
1048#define AFMT_STATUS 0x7600
1049# define AFMT_AUDIO_ENABLE (1 << 4)
1050# define AFMT_AZ_FORMAT_WTRIG (1 << 28)
1051# define AFMT_AZ_FORMAT_WTRIG_INT (1 << 29)
1052# define AFMT_AZ_AUDIO_ENABLE_CHG (1 << 30)
1053#define AFMT_AUDIO_PACKET_CONTROL 0x7604
1054# define AFMT_AUDIO_SAMPLE_SEND (1 << 0)
1055# define AFMT_AUDIO_TEST_EN (1 << 12)
1056# define AFMT_AUDIO_CHANNEL_SWAP (1 << 24)
1057# define AFMT_60958_CS_UPDATE (1 << 26)
1058# define AFMT_AZ_AUDIO_ENABLE_CHG_MASK (1 << 27)
1059# define AFMT_AZ_FORMAT_WTRIG_MASK (1 << 28)
1060# define AFMT_AZ_FORMAT_WTRIG_ACK (1 << 29)
1061# define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30)
1062
1063/*
1064 * PM4
1065 */
1066#define PACKET_TYPE0 0
1067#define PACKET_TYPE1 1
1068#define PACKET_TYPE2 2
1069#define PACKET_TYPE3 3
1070
1071#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
1072#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
1073#define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)
1074#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
1075#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
1076 (((reg) >> 2) & 0xFFFF) | \
1077 ((n) & 0x3FFF) << 16)
1078#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
1079 (((op) & 0xFF) << 8) | \
1080 ((n) & 0x3FFF) << 16)
1081
1082/* Packet 3 types */
1083#define PACKET3_NOP 0x10
1084#define PACKET3_INDIRECT_BUFFER_END 0x17
1085#define PACKET3_SET_PREDICATION 0x20
1086#define PACKET3_REG_RMW 0x21
1087#define PACKET3_COND_EXEC 0x22
1088#define PACKET3_PRED_EXEC 0x23
1089#define PACKET3_START_3D_CMDBUF 0x24
1090#define PACKET3_DRAW_INDEX_2 0x27
1091#define PACKET3_CONTEXT_CONTROL 0x28
1092#define PACKET3_DRAW_INDEX_IMMD_BE 0x29
1093#define PACKET3_INDEX_TYPE 0x2A
1094#define PACKET3_DRAW_INDEX 0x2B
1095#define PACKET3_DRAW_INDEX_AUTO 0x2D
1096#define PACKET3_DRAW_INDEX_IMMD 0x2E
1097#define PACKET3_NUM_INSTANCES 0x2F
1098#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
1099#define PACKET3_INDIRECT_BUFFER_MP 0x38
1100#define PACKET3_MEM_SEMAPHORE 0x39
1101# define PACKET3_SEM_WAIT_ON_SIGNAL (0x1 << 12)
1102# define PACKET3_SEM_SEL_SIGNAL (0x6 << 29)
1103# define PACKET3_SEM_SEL_WAIT (0x7 << 29)
1104#define PACKET3_MPEG_INDEX 0x3A
1105#define PACKET3_COPY_DW 0x3B
1106#define PACKET3_WAIT_REG_MEM 0x3C
1107#define PACKET3_MEM_WRITE 0x3D
1108#define PACKET3_INDIRECT_BUFFER 0x32
1109#define PACKET3_SURFACE_SYNC 0x43
1110# define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
1111# define PACKET3_TC_ACTION_ENA (1 << 23)
1112# define PACKET3_VC_ACTION_ENA (1 << 24)
1113# define PACKET3_CB_ACTION_ENA (1 << 25)
1114# define PACKET3_DB_ACTION_ENA (1 << 26)
1115# define PACKET3_SH_ACTION_ENA (1 << 27)
1116# define PACKET3_SMX_ACTION_ENA (1 << 28)
1117#define PACKET3_ME_INITIALIZE 0x44
1118#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
1119#define PACKET3_COND_WRITE 0x45
1120#define PACKET3_EVENT_WRITE 0x46
1121#define EVENT_TYPE(x) ((x) << 0)
1122#define EVENT_INDEX(x) ((x) << 8)
1123 /* 0 - any non-TS event
1124 * 1 - ZPASS_DONE
1125 * 2 - SAMPLE_PIPELINESTAT
1126 * 3 - SAMPLE_STREAMOUTSTAT*
1127 * 4 - *S_PARTIAL_FLUSH
1128 * 5 - TS events
1129 */
1130#define PACKET3_EVENT_WRITE_EOP 0x47
1131#define DATA_SEL(x) ((x) << 29)
1132 /* 0 - discard
1133 * 1 - send low 32bit data
1134 * 2 - send 64bit data
1135 * 3 - send 64bit counter value
1136 */
1137#define INT_SEL(x) ((x) << 24)
1138 /* 0 - none
1139 * 1 - interrupt only (DATA_SEL = 0)
1140 * 2 - interrupt when data write is confirmed
1141 */
1142#define PACKET3_ONE_REG_WRITE 0x57
1143#define PACKET3_SET_CONFIG_REG 0x68
1144#define PACKET3_SET_CONFIG_REG_OFFSET 0x00008000
1145#define PACKET3_SET_CONFIG_REG_END 0x0000ac00
1146#define PACKET3_SET_CONTEXT_REG 0x69
1147#define PACKET3_SET_CONTEXT_REG_OFFSET 0x00028000
1148#define PACKET3_SET_CONTEXT_REG_END 0x00029000
1149#define PACKET3_SET_ALU_CONST 0x6A
1150#define PACKET3_SET_ALU_CONST_OFFSET 0x00030000
1151#define PACKET3_SET_ALU_CONST_END 0x00032000
1152#define PACKET3_SET_BOOL_CONST 0x6B
1153#define PACKET3_SET_BOOL_CONST_OFFSET 0x0003e380
1154#define PACKET3_SET_BOOL_CONST_END 0x00040000
1155#define PACKET3_SET_LOOP_CONST 0x6C
1156#define PACKET3_SET_LOOP_CONST_OFFSET 0x0003e200
1157#define PACKET3_SET_LOOP_CONST_END 0x0003e380
1158#define PACKET3_SET_RESOURCE 0x6D
1159#define PACKET3_SET_RESOURCE_OFFSET 0x00038000
1160#define PACKET3_SET_RESOURCE_END 0x0003c000
1161#define PACKET3_SET_SAMPLER 0x6E
1162#define PACKET3_SET_SAMPLER_OFFSET 0x0003c000
1163#define PACKET3_SET_SAMPLER_END 0x0003cff0
1164#define PACKET3_SET_CTL_CONST 0x6F
1165#define PACKET3_SET_CTL_CONST_OFFSET 0x0003cff0
1166#define PACKET3_SET_CTL_CONST_END 0x0003e200
1167#define PACKET3_STRMOUT_BASE_UPDATE 0x72 /* r7xx */
1168#define PACKET3_SURFACE_BASE_UPDATE 0x73
1169
1170
1171#define R_008020_GRBM_SOFT_RESET 0x8020
1172#define S_008020_SOFT_RESET_CP(x) (((x) & 1) << 0)
1173#define S_008020_SOFT_RESET_CB(x) (((x) & 1) << 1)
1174#define S_008020_SOFT_RESET_CR(x) (((x) & 1) << 2)
1175#define S_008020_SOFT_RESET_DB(x) (((x) & 1) << 3)
1176#define S_008020_SOFT_RESET_PA(x) (((x) & 1) << 5)
1177#define S_008020_SOFT_RESET_SC(x) (((x) & 1) << 6)
1178#define S_008020_SOFT_RESET_SMX(x) (((x) & 1) << 7)
1179#define S_008020_SOFT_RESET_SPI(x) (((x) & 1) << 8)
1180#define S_008020_SOFT_RESET_SH(x) (((x) & 1) << 9)
1181#define S_008020_SOFT_RESET_SX(x) (((x) & 1) << 10)
1182#define S_008020_SOFT_RESET_TC(x) (((x) & 1) << 11)
1183#define S_008020_SOFT_RESET_TA(x) (((x) & 1) << 12)
1184#define S_008020_SOFT_RESET_VC(x) (((x) & 1) << 13)
1185#define S_008020_SOFT_RESET_VGT(x) (((x) & 1) << 14)
1186#define R_008010_GRBM_STATUS 0x8010
1187#define S_008010_CMDFIFO_AVAIL(x) (((x) & 0x1F) << 0)
1188#define S_008010_CP_RQ_PENDING(x) (((x) & 1) << 6)
1189#define S_008010_CF_RQ_PENDING(x) (((x) & 1) << 7)
1190#define S_008010_PF_RQ_PENDING(x) (((x) & 1) << 8)
1191#define S_008010_GRBM_EE_BUSY(x) (((x) & 1) << 10)
1192#define S_008010_VC_BUSY(x) (((x) & 1) << 11)
1193#define S_008010_DB03_CLEAN(x) (((x) & 1) << 12)
1194#define S_008010_CB03_CLEAN(x) (((x) & 1) << 13)
1195#define S_008010_VGT_BUSY_NO_DMA(x) (((x) & 1) << 16)
1196#define S_008010_VGT_BUSY(x) (((x) & 1) << 17)
1197#define S_008010_TA03_BUSY(x) (((x) & 1) << 18)
1198#define S_008010_TC_BUSY(x) (((x) & 1) << 19)
1199#define S_008010_SX_BUSY(x) (((x) & 1) << 20)
1200#define S_008010_SH_BUSY(x) (((x) & 1) << 21)
1201#define S_008010_SPI03_BUSY(x) (((x) & 1) << 22)
1202#define S_008010_SMX_BUSY(x) (((x) & 1) << 23)
1203#define S_008010_SC_BUSY(x) (((x) & 1) << 24)
1204#define S_008010_PA_BUSY(x) (((x) & 1) << 25)
1205#define S_008010_DB03_BUSY(x) (((x) & 1) << 26)
1206#define S_008010_CR_BUSY(x) (((x) & 1) << 27)
1207#define S_008010_CP_COHERENCY_BUSY(x) (((x) & 1) << 28)
1208#define S_008010_CP_BUSY(x) (((x) & 1) << 29)
1209#define S_008010_CB03_BUSY(x) (((x) & 1) << 30)
1210#define S_008010_GUI_ACTIVE(x) (((x) & 1) << 31)
1211#define G_008010_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x1F)
1212#define G_008010_CP_RQ_PENDING(x) (((x) >> 6) & 1)
1213#define G_008010_CF_RQ_PENDING(x) (((x) >> 7) & 1)
1214#define G_008010_PF_RQ_PENDING(x) (((x) >> 8) & 1)
1215#define G_008010_GRBM_EE_BUSY(x) (((x) >> 10) & 1)
1216#define G_008010_VC_BUSY(x) (((x) >> 11) & 1)
1217#define G_008010_DB03_CLEAN(x) (((x) >> 12) & 1)
1218#define G_008010_CB03_CLEAN(x) (((x) >> 13) & 1)
1219#define G_008010_VGT_BUSY_NO_DMA(x) (((x) >> 16) & 1)
1220#define G_008010_VGT_BUSY(x) (((x) >> 17) & 1)
1221#define G_008010_TA03_BUSY(x) (((x) >> 18) & 1)
1222#define G_008010_TC_BUSY(x) (((x) >> 19) & 1)
1223#define G_008010_SX_BUSY(x) (((x) >> 20) & 1)
1224#define G_008010_SH_BUSY(x) (((x) >> 21) & 1)
1225#define G_008010_SPI03_BUSY(x) (((x) >> 22) & 1)
1226#define G_008010_SMX_BUSY(x) (((x) >> 23) & 1)
1227#define G_008010_SC_BUSY(x) (((x) >> 24) & 1)
1228#define G_008010_PA_BUSY(x) (((x) >> 25) & 1)
1229#define G_008010_DB03_BUSY(x) (((x) >> 26) & 1)
1230#define G_008010_CR_BUSY(x) (((x) >> 27) & 1)
1231#define G_008010_CP_COHERENCY_BUSY(x) (((x) >> 28) & 1)
1232#define G_008010_CP_BUSY(x) (((x) >> 29) & 1)
1233#define G_008010_CB03_BUSY(x) (((x) >> 30) & 1)
1234#define G_008010_GUI_ACTIVE(x) (((x) >> 31) & 1)
1235#define R_008014_GRBM_STATUS2 0x8014
1236#define S_008014_CR_CLEAN(x) (((x) & 1) << 0)
1237#define S_008014_SMX_CLEAN(x) (((x) & 1) << 1)
1238#define S_008014_SPI0_BUSY(x) (((x) & 1) << 8)
1239#define S_008014_SPI1_BUSY(x) (((x) & 1) << 9)
1240#define S_008014_SPI2_BUSY(x) (((x) & 1) << 10)
1241#define S_008014_SPI3_BUSY(x) (((x) & 1) << 11)
1242#define S_008014_TA0_BUSY(x) (((x) & 1) << 12)
1243#define S_008014_TA1_BUSY(x) (((x) & 1) << 13)
1244#define S_008014_TA2_BUSY(x) (((x) & 1) << 14)
1245#define S_008014_TA3_BUSY(x) (((x) & 1) << 15)
1246#define S_008014_DB0_BUSY(x) (((x) & 1) << 16)
1247#define S_008014_DB1_BUSY(x) (((x) & 1) << 17)
1248#define S_008014_DB2_BUSY(x) (((x) & 1) << 18)
1249#define S_008014_DB3_BUSY(x) (((x) & 1) << 19)
1250#define S_008014_CB0_BUSY(x) (((x) & 1) << 20)
1251#define S_008014_CB1_BUSY(x) (((x) & 1) << 21)
1252#define S_008014_CB2_BUSY(x) (((x) & 1) << 22)
1253#define S_008014_CB3_BUSY(x) (((x) & 1) << 23)
1254#define G_008014_CR_CLEAN(x) (((x) >> 0) & 1)
1255#define G_008014_SMX_CLEAN(x) (((x) >> 1) & 1)
1256#define G_008014_SPI0_BUSY(x) (((x) >> 8) & 1)
1257#define G_008014_SPI1_BUSY(x) (((x) >> 9) & 1)
1258#define G_008014_SPI2_BUSY(x) (((x) >> 10) & 1)
1259#define G_008014_SPI3_BUSY(x) (((x) >> 11) & 1)
1260#define G_008014_TA0_BUSY(x) (((x) >> 12) & 1)
1261#define G_008014_TA1_BUSY(x) (((x) >> 13) & 1)
1262#define G_008014_TA2_BUSY(x) (((x) >> 14) & 1)
1263#define G_008014_TA3_BUSY(x) (((x) >> 15) & 1)
1264#define G_008014_DB0_BUSY(x) (((x) >> 16) & 1)
1265#define G_008014_DB1_BUSY(x) (((x) >> 17) & 1)
1266#define G_008014_DB2_BUSY(x) (((x) >> 18) & 1)
1267#define G_008014_DB3_BUSY(x) (((x) >> 19) & 1)
1268#define G_008014_CB0_BUSY(x) (((x) >> 20) & 1)
1269#define G_008014_CB1_BUSY(x) (((x) >> 21) & 1)
1270#define G_008014_CB2_BUSY(x) (((x) >> 22) & 1)
1271#define G_008014_CB3_BUSY(x) (((x) >> 23) & 1)
1272#define R_000E50_SRBM_STATUS 0x0E50
1273#define G_000E50_RLC_RQ_PENDING(x) (((x) >> 3) & 1)
1274#define G_000E50_RCU_RQ_PENDING(x) (((x) >> 4) & 1)
1275#define G_000E50_GRBM_RQ_PENDING(x) (((x) >> 5) & 1)
1276#define G_000E50_HI_RQ_PENDING(x) (((x) >> 6) & 1)
1277#define G_000E50_IO_EXTERN_SIGNAL(x) (((x) >> 7) & 1)
1278#define G_000E50_VMC_BUSY(x) (((x) >> 8) & 1)
1279#define G_000E50_MCB_BUSY(x) (((x) >> 9) & 1)
1280#define G_000E50_MCDZ_BUSY(x) (((x) >> 10) & 1)
1281#define G_000E50_MCDY_BUSY(x) (((x) >> 11) & 1)
1282#define G_000E50_MCDX_BUSY(x) (((x) >> 12) & 1)
1283#define G_000E50_MCDW_BUSY(x) (((x) >> 13) & 1)
1284#define G_000E50_SEM_BUSY(x) (((x) >> 14) & 1)
1285#define G_000E50_RLC_BUSY(x) (((x) >> 15) & 1)
1286#define G_000E50_BIF_BUSY(x) (((x) >> 29) & 1)
1287#define R_000E60_SRBM_SOFT_RESET 0x0E60
1288#define S_000E60_SOFT_RESET_BIF(x) (((x) & 1) << 1)
1289#define S_000E60_SOFT_RESET_CG(x) (((x) & 1) << 2)
1290#define S_000E60_SOFT_RESET_CMC(x) (((x) & 1) << 3)
1291#define S_000E60_SOFT_RESET_CSC(x) (((x) & 1) << 4)
1292#define S_000E60_SOFT_RESET_DC(x) (((x) & 1) << 5)
1293#define S_000E60_SOFT_RESET_GRBM(x) (((x) & 1) << 8)
1294#define S_000E60_SOFT_RESET_HDP(x) (((x) & 1) << 9)
1295#define S_000E60_SOFT_RESET_IH(x) (((x) & 1) << 10)
1296#define S_000E60_SOFT_RESET_MC(x) (((x) & 1) << 11)
1297#define S_000E60_SOFT_RESET_RLC(x) (((x) & 1) << 13)
1298#define S_000E60_SOFT_RESET_ROM(x) (((x) & 1) << 14)
1299#define S_000E60_SOFT_RESET_SEM(x) (((x) & 1) << 15)
1300#define S_000E60_SOFT_RESET_TSC(x) (((x) & 1) << 16)
1301#define S_000E60_SOFT_RESET_VMC(x) (((x) & 1) << 17)
1302
1303#define R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480
1304
1305#define R_028C04_PA_SC_AA_CONFIG 0x028C04
1306#define S_028C04_MSAA_NUM_SAMPLES(x) (((x) & 0x3) << 0)
1307#define G_028C04_MSAA_NUM_SAMPLES(x) (((x) >> 0) & 0x3)
1308#define C_028C04_MSAA_NUM_SAMPLES 0xFFFFFFFC
1309#define S_028C04_AA_MASK_CENTROID_DTMN(x) (((x) & 0x1) << 4)
1310#define G_028C04_AA_MASK_CENTROID_DTMN(x) (((x) >> 4) & 0x1)
1311#define C_028C04_AA_MASK_CENTROID_DTMN 0xFFFFFFEF
1312#define S_028C04_MAX_SAMPLE_DIST(x) (((x) & 0xF) << 13)
1313#define G_028C04_MAX_SAMPLE_DIST(x) (((x) >> 13) & 0xF)
1314#define C_028C04_MAX_SAMPLE_DIST 0xFFFE1FFF
1315#define R_0280E0_CB_COLOR0_FRAG 0x0280E0
1316#define S_0280E0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0)
1317#define G_0280E0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF)
1318#define C_0280E0_BASE_256B 0x00000000
1319#define R_0280E4_CB_COLOR1_FRAG 0x0280E4
1320#define R_0280E8_CB_COLOR2_FRAG 0x0280E8
1321#define R_0280EC_CB_COLOR3_FRAG 0x0280EC
1322#define R_0280F0_CB_COLOR4_FRAG 0x0280F0
1323#define R_0280F4_CB_COLOR5_FRAG 0x0280F4
1324#define R_0280F8_CB_COLOR6_FRAG 0x0280F8
1325#define R_0280FC_CB_COLOR7_FRAG 0x0280FC
1326#define R_0280C0_CB_COLOR0_TILE 0x0280C0
1327#define S_0280C0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0)
1328#define G_0280C0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF)
1329#define C_0280C0_BASE_256B 0x00000000
1330#define R_0280C4_CB_COLOR1_TILE 0x0280C4
1331#define R_0280C8_CB_COLOR2_TILE 0x0280C8
1332#define R_0280CC_CB_COLOR3_TILE 0x0280CC
1333#define R_0280D0_CB_COLOR4_TILE 0x0280D0
1334#define R_0280D4_CB_COLOR5_TILE 0x0280D4
1335#define R_0280D8_CB_COLOR6_TILE 0x0280D8
1336#define R_0280DC_CB_COLOR7_TILE 0x0280DC
1337#define R_0280A0_CB_COLOR0_INFO 0x0280A0
1338#define S_0280A0_ENDIAN(x) (((x) & 0x3) << 0)
1339#define G_0280A0_ENDIAN(x) (((x) >> 0) & 0x3)
1340#define C_0280A0_ENDIAN 0xFFFFFFFC
1341#define S_0280A0_FORMAT(x) (((x) & 0x3F) << 2)
1342#define G_0280A0_FORMAT(x) (((x) >> 2) & 0x3F)
1343#define C_0280A0_FORMAT 0xFFFFFF03
1344#define V_0280A0_COLOR_INVALID 0x00000000
1345#define V_0280A0_COLOR_8 0x00000001
1346#define V_0280A0_COLOR_4_4 0x00000002
1347#define V_0280A0_COLOR_3_3_2 0x00000003
1348#define V_0280A0_COLOR_16 0x00000005
1349#define V_0280A0_COLOR_16_FLOAT 0x00000006
1350#define V_0280A0_COLOR_8_8 0x00000007
1351#define V_0280A0_COLOR_5_6_5 0x00000008
1352#define V_0280A0_COLOR_6_5_5 0x00000009
1353#define V_0280A0_COLOR_1_5_5_5 0x0000000A
1354#define V_0280A0_COLOR_4_4_4_4 0x0000000B
1355#define V_0280A0_COLOR_5_5_5_1 0x0000000C
1356#define V_0280A0_COLOR_32 0x0000000D
1357#define V_0280A0_COLOR_32_FLOAT 0x0000000E
1358#define V_0280A0_COLOR_16_16 0x0000000F
1359#define V_0280A0_COLOR_16_16_FLOAT 0x00000010
1360#define V_0280A0_COLOR_8_24 0x00000011
1361#define V_0280A0_COLOR_8_24_FLOAT 0x00000012
1362#define V_0280A0_COLOR_24_8 0x00000013
1363#define V_0280A0_COLOR_24_8_FLOAT 0x00000014
1364#define V_0280A0_COLOR_10_11_11 0x00000015
1365#define V_0280A0_COLOR_10_11_11_FLOAT 0x00000016
1366#define V_0280A0_COLOR_11_11_10 0x00000017
1367#define V_0280A0_COLOR_11_11_10_FLOAT 0x00000018
1368#define V_0280A0_COLOR_2_10_10_10 0x00000019
1369#define V_0280A0_COLOR_8_8_8_8 0x0000001A
1370#define V_0280A0_COLOR_10_10_10_2 0x0000001B
1371#define V_0280A0_COLOR_X24_8_32_FLOAT 0x0000001C
1372#define V_0280A0_COLOR_32_32 0x0000001D
1373#define V_0280A0_COLOR_32_32_FLOAT 0x0000001E
1374#define V_0280A0_COLOR_16_16_16_16 0x0000001F
1375#define V_0280A0_COLOR_16_16_16_16_FLOAT 0x00000020
1376#define V_0280A0_COLOR_32_32_32_32 0x00000022
1377#define V_0280A0_COLOR_32_32_32_32_FLOAT 0x00000023
1378#define S_0280A0_ARRAY_MODE(x) (((x) & 0xF) << 8)
1379#define G_0280A0_ARRAY_MODE(x) (((x) >> 8) & 0xF)
1380#define C_0280A0_ARRAY_MODE 0xFFFFF0FF
1381#define V_0280A0_ARRAY_LINEAR_GENERAL 0x00000000
1382#define V_0280A0_ARRAY_LINEAR_ALIGNED 0x00000001
1383#define V_0280A0_ARRAY_1D_TILED_THIN1 0x00000002
1384#define V_0280A0_ARRAY_2D_TILED_THIN1 0x00000004
1385#define S_0280A0_NUMBER_TYPE(x) (((x) & 0x7) << 12)
1386#define G_0280A0_NUMBER_TYPE(x) (((x) >> 12) & 0x7)
1387#define C_0280A0_NUMBER_TYPE 0xFFFF8FFF
1388#define S_0280A0_READ_SIZE(x) (((x) & 0x1) << 15)
1389#define G_0280A0_READ_SIZE(x) (((x) >> 15) & 0x1)
1390#define C_0280A0_READ_SIZE 0xFFFF7FFF
1391#define S_0280A0_COMP_SWAP(x) (((x) & 0x3) << 16)
1392#define G_0280A0_COMP_SWAP(x) (((x) >> 16) & 0x3)
1393#define C_0280A0_COMP_SWAP 0xFFFCFFFF
1394#define S_0280A0_TILE_MODE(x) (((x) & 0x3) << 18)
1395#define G_0280A0_TILE_MODE(x) (((x) >> 18) & 0x3)
1396#define C_0280A0_TILE_MODE 0xFFF3FFFF
1397#define S_0280A0_BLEND_CLAMP(x) (((x) & 0x1) << 20)
1398#define G_0280A0_BLEND_CLAMP(x) (((x) >> 20) & 0x1)
1399#define C_0280A0_BLEND_CLAMP 0xFFEFFFFF
1400#define S_0280A0_CLEAR_COLOR(x) (((x) & 0x1) << 21)
1401#define G_0280A0_CLEAR_COLOR(x) (((x) >> 21) & 0x1)
1402#define C_0280A0_CLEAR_COLOR 0xFFDFFFFF
1403#define S_0280A0_BLEND_BYPASS(x) (((x) & 0x1) << 22)
1404#define G_0280A0_BLEND_BYPASS(x) (((x) >> 22) & 0x1)
1405#define C_0280A0_BLEND_BYPASS 0xFFBFFFFF
1406#define S_0280A0_BLEND_FLOAT32(x) (((x) & 0x1) << 23)
1407#define G_0280A0_BLEND_FLOAT32(x) (((x) >> 23) & 0x1)
1408#define C_0280A0_BLEND_FLOAT32 0xFF7FFFFF
1409#define S_0280A0_SIMPLE_FLOAT(x) (((x) & 0x1) << 24)
1410#define G_0280A0_SIMPLE_FLOAT(x) (((x) >> 24) & 0x1)
1411#define C_0280A0_SIMPLE_FLOAT 0xFEFFFFFF
1412#define S_0280A0_ROUND_MODE(x) (((x) & 0x1) << 25)
1413#define G_0280A0_ROUND_MODE(x) (((x) >> 25) & 0x1)
1414#define C_0280A0_ROUND_MODE 0xFDFFFFFF
1415#define S_0280A0_TILE_COMPACT(x) (((x) & 0x1) << 26)
1416#define G_0280A0_TILE_COMPACT(x) (((x) >> 26) & 0x1)
1417#define C_0280A0_TILE_COMPACT 0xFBFFFFFF
1418#define S_0280A0_SOURCE_FORMAT(x) (((x) & 0x1) << 27)
1419#define G_0280A0_SOURCE_FORMAT(x) (((x) >> 27) & 0x1)
1420#define C_0280A0_SOURCE_FORMAT 0xF7FFFFFF
1421#define R_0280A4_CB_COLOR1_INFO 0x0280A4
1422#define R_0280A8_CB_COLOR2_INFO 0x0280A8
1423#define R_0280AC_CB_COLOR3_INFO 0x0280AC
1424#define R_0280B0_CB_COLOR4_INFO 0x0280B0
1425#define R_0280B4_CB_COLOR5_INFO 0x0280B4
1426#define R_0280B8_CB_COLOR6_INFO 0x0280B8
1427#define R_0280BC_CB_COLOR7_INFO 0x0280BC
1428#define R_028060_CB_COLOR0_SIZE 0x028060
1429#define S_028060_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0)
1430#define G_028060_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF)
1431#define C_028060_PITCH_TILE_MAX 0xFFFFFC00
1432#define S_028060_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10)
1433#define G_028060_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF)
1434#define C_028060_SLICE_TILE_MAX 0xC00003FF
1435#define R_028064_CB_COLOR1_SIZE 0x028064
1436#define R_028068_CB_COLOR2_SIZE 0x028068
1437#define R_02806C_CB_COLOR3_SIZE 0x02806C
1438#define R_028070_CB_COLOR4_SIZE 0x028070
1439#define R_028074_CB_COLOR5_SIZE 0x028074
1440#define R_028078_CB_COLOR6_SIZE 0x028078
1441#define R_02807C_CB_COLOR7_SIZE 0x02807C
1442#define R_028238_CB_TARGET_MASK 0x028238
1443#define S_028238_TARGET0_ENABLE(x) (((x) & 0xF) << 0)
1444#define G_028238_TARGET0_ENABLE(x) (((x) >> 0) & 0xF)
1445#define C_028238_TARGET0_ENABLE 0xFFFFFFF0
1446#define S_028238_TARGET1_ENABLE(x) (((x) & 0xF) << 4)
1447#define G_028238_TARGET1_ENABLE(x) (((x) >> 4) & 0xF)
1448#define C_028238_TARGET1_ENABLE 0xFFFFFF0F
1449#define S_028238_TARGET2_ENABLE(x) (((x) & 0xF) << 8)
1450#define G_028238_TARGET2_ENABLE(x) (((x) >> 8) & 0xF)
1451#define C_028238_TARGET2_ENABLE 0xFFFFF0FF
1452#define S_028238_TARGET3_ENABLE(x) (((x) & 0xF) << 12)
1453#define G_028238_TARGET3_ENABLE(x) (((x) >> 12) & 0xF)
1454#define C_028238_TARGET3_ENABLE 0xFFFF0FFF
1455#define S_028238_TARGET4_ENABLE(x) (((x) & 0xF) << 16)
1456#define G_028238_TARGET4_ENABLE(x) (((x) >> 16) & 0xF)
1457#define C_028238_TARGET4_ENABLE 0xFFF0FFFF
1458#define S_028238_TARGET5_ENABLE(x) (((x) & 0xF) << 20)
1459#define G_028238_TARGET5_ENABLE(x) (((x) >> 20) & 0xF)
1460#define C_028238_TARGET5_ENABLE 0xFF0FFFFF
1461#define S_028238_TARGET6_ENABLE(x) (((x) & 0xF) << 24)
1462#define G_028238_TARGET6_ENABLE(x) (((x) >> 24) & 0xF)
1463#define C_028238_TARGET6_ENABLE 0xF0FFFFFF
1464#define S_028238_TARGET7_ENABLE(x) (((x) & 0xF) << 28)
1465#define G_028238_TARGET7_ENABLE(x) (((x) >> 28) & 0xF)
1466#define C_028238_TARGET7_ENABLE 0x0FFFFFFF
1467#define R_02823C_CB_SHADER_MASK 0x02823C
1468#define S_02823C_OUTPUT0_ENABLE(x) (((x) & 0xF) << 0)
1469#define G_02823C_OUTPUT0_ENABLE(x) (((x) >> 0) & 0xF)
1470#define C_02823C_OUTPUT0_ENABLE 0xFFFFFFF0
1471#define S_02823C_OUTPUT1_ENABLE(x) (((x) & 0xF) << 4)
1472#define G_02823C_OUTPUT1_ENABLE(x) (((x) >> 4) & 0xF)
1473#define C_02823C_OUTPUT1_ENABLE 0xFFFFFF0F
1474#define S_02823C_OUTPUT2_ENABLE(x) (((x) & 0xF) << 8)
1475#define G_02823C_OUTPUT2_ENABLE(x) (((x) >> 8) & 0xF)
1476#define C_02823C_OUTPUT2_ENABLE 0xFFFFF0FF
1477#define S_02823C_OUTPUT3_ENABLE(x) (((x) & 0xF) << 12)
1478#define G_02823C_OUTPUT3_ENABLE(x) (((x) >> 12) & 0xF)
1479#define C_02823C_OUTPUT3_ENABLE 0xFFFF0FFF
1480#define S_02823C_OUTPUT4_ENABLE(x) (((x) & 0xF) << 16)
1481#define G_02823C_OUTPUT4_ENABLE(x) (((x) >> 16) & 0xF)
1482#define C_02823C_OUTPUT4_ENABLE 0xFFF0FFFF
1483#define S_02823C_OUTPUT5_ENABLE(x) (((x) & 0xF) << 20)
1484#define G_02823C_OUTPUT5_ENABLE(x) (((x) >> 20) & 0xF)
1485#define C_02823C_OUTPUT5_ENABLE 0xFF0FFFFF
1486#define S_02823C_OUTPUT6_ENABLE(x) (((x) & 0xF) << 24)
1487#define G_02823C_OUTPUT6_ENABLE(x) (((x) >> 24) & 0xF)
1488#define C_02823C_OUTPUT6_ENABLE 0xF0FFFFFF
1489#define S_02823C_OUTPUT7_ENABLE(x) (((x) & 0xF) << 28)
1490#define G_02823C_OUTPUT7_ENABLE(x) (((x) >> 28) & 0xF)
1491#define C_02823C_OUTPUT7_ENABLE 0x0FFFFFFF
1492#define R_028AB0_VGT_STRMOUT_EN 0x028AB0
1493#define S_028AB0_STREAMOUT(x) (((x) & 0x1) << 0)
1494#define G_028AB0_STREAMOUT(x) (((x) >> 0) & 0x1)
1495#define C_028AB0_STREAMOUT 0xFFFFFFFE
1496#define R_028B20_VGT_STRMOUT_BUFFER_EN 0x028B20
1497#define S_028B20_BUFFER_0_EN(x) (((x) & 0x1) << 0)
1498#define G_028B20_BUFFER_0_EN(x) (((x) >> 0) & 0x1)
1499#define C_028B20_BUFFER_0_EN 0xFFFFFFFE
1500#define S_028B20_BUFFER_1_EN(x) (((x) & 0x1) << 1)
1501#define G_028B20_BUFFER_1_EN(x) (((x) >> 1) & 0x1)
1502#define C_028B20_BUFFER_1_EN 0xFFFFFFFD
1503#define S_028B20_BUFFER_2_EN(x) (((x) & 0x1) << 2)
1504#define G_028B20_BUFFER_2_EN(x) (((x) >> 2) & 0x1)
1505#define C_028B20_BUFFER_2_EN 0xFFFFFFFB
1506#define S_028B20_BUFFER_3_EN(x) (((x) & 0x1) << 3)
1507#define G_028B20_BUFFER_3_EN(x) (((x) >> 3) & 0x1)
1508#define C_028B20_BUFFER_3_EN 0xFFFFFFF7
1509#define S_028B20_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
1510#define G_028B20_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
1511#define C_028B20_SIZE 0x00000000
1512#define R_038000_SQ_TEX_RESOURCE_WORD0_0 0x038000
1513#define S_038000_DIM(x) (((x) & 0x7) << 0)
1514#define G_038000_DIM(x) (((x) >> 0) & 0x7)
1515#define C_038000_DIM 0xFFFFFFF8
1516#define V_038000_SQ_TEX_DIM_1D 0x00000000
1517#define V_038000_SQ_TEX_DIM_2D 0x00000001
1518#define V_038000_SQ_TEX_DIM_3D 0x00000002
1519#define V_038000_SQ_TEX_DIM_CUBEMAP 0x00000003
1520#define V_038000_SQ_TEX_DIM_1D_ARRAY 0x00000004
1521#define V_038000_SQ_TEX_DIM_2D_ARRAY 0x00000005
1522#define V_038000_SQ_TEX_DIM_2D_MSAA 0x00000006
1523#define V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA 0x00000007
1524#define S_038000_TILE_MODE(x) (((x) & 0xF) << 3)
1525#define G_038000_TILE_MODE(x) (((x) >> 3) & 0xF)
1526#define C_038000_TILE_MODE 0xFFFFFF87
1527#define V_038000_ARRAY_LINEAR_GENERAL 0x00000000
1528#define V_038000_ARRAY_LINEAR_ALIGNED 0x00000001
1529#define V_038000_ARRAY_1D_TILED_THIN1 0x00000002
1530#define V_038000_ARRAY_2D_TILED_THIN1 0x00000004
1531#define S_038000_TILE_TYPE(x) (((x) & 0x1) << 7)
1532#define G_038000_TILE_TYPE(x) (((x) >> 7) & 0x1)
1533#define C_038000_TILE_TYPE 0xFFFFFF7F
1534#define S_038000_PITCH(x) (((x) & 0x7FF) << 8)
1535#define G_038000_PITCH(x) (((x) >> 8) & 0x7FF)
1536#define C_038000_PITCH 0xFFF800FF
1537#define S_038000_TEX_WIDTH(x) (((x) & 0x1FFF) << 19)
1538#define G_038000_TEX_WIDTH(x) (((x) >> 19) & 0x1FFF)
1539#define C_038000_TEX_WIDTH 0x0007FFFF
1540#define R_038004_SQ_TEX_RESOURCE_WORD1_0 0x038004
1541#define S_038004_TEX_HEIGHT(x) (((x) & 0x1FFF) << 0)
1542#define G_038004_TEX_HEIGHT(x) (((x) >> 0) & 0x1FFF)
1543#define C_038004_TEX_HEIGHT 0xFFFFE000
1544#define S_038004_TEX_DEPTH(x) (((x) & 0x1FFF) << 13)
1545#define G_038004_TEX_DEPTH(x) (((x) >> 13) & 0x1FFF)
1546#define C_038004_TEX_DEPTH 0xFC001FFF
1547#define S_038004_DATA_FORMAT(x) (((x) & 0x3F) << 26)
1548#define G_038004_DATA_FORMAT(x) (((x) >> 26) & 0x3F)
1549#define C_038004_DATA_FORMAT 0x03FFFFFF
1550#define V_038004_COLOR_INVALID 0x00000000
1551#define V_038004_COLOR_8 0x00000001
1552#define V_038004_COLOR_4_4 0x00000002
1553#define V_038004_COLOR_3_3_2 0x00000003
1554#define V_038004_COLOR_16 0x00000005
1555#define V_038004_COLOR_16_FLOAT 0x00000006
1556#define V_038004_COLOR_8_8 0x00000007
1557#define V_038004_COLOR_5_6_5 0x00000008
1558#define V_038004_COLOR_6_5_5 0x00000009
1559#define V_038004_COLOR_1_5_5_5 0x0000000A
1560#define V_038004_COLOR_4_4_4_4 0x0000000B
1561#define V_038004_COLOR_5_5_5_1 0x0000000C
1562#define V_038004_COLOR_32 0x0000000D
1563#define V_038004_COLOR_32_FLOAT 0x0000000E
1564#define V_038004_COLOR_16_16 0x0000000F
1565#define V_038004_COLOR_16_16_FLOAT 0x00000010
1566#define V_038004_COLOR_8_24 0x00000011
1567#define V_038004_COLOR_8_24_FLOAT 0x00000012
1568#define V_038004_COLOR_24_8 0x00000013
1569#define V_038004_COLOR_24_8_FLOAT 0x00000014
1570#define V_038004_COLOR_10_11_11 0x00000015
1571#define V_038004_COLOR_10_11_11_FLOAT 0x00000016
1572#define V_038004_COLOR_11_11_10 0x00000017
1573#define V_038004_COLOR_11_11_10_FLOAT 0x00000018
1574#define V_038004_COLOR_2_10_10_10 0x00000019
1575#define V_038004_COLOR_8_8_8_8 0x0000001A
1576#define V_038004_COLOR_10_10_10_2 0x0000001B
1577#define V_038004_COLOR_X24_8_32_FLOAT 0x0000001C
1578#define V_038004_COLOR_32_32 0x0000001D
1579#define V_038004_COLOR_32_32_FLOAT 0x0000001E
1580#define V_038004_COLOR_16_16_16_16 0x0000001F
1581#define V_038004_COLOR_16_16_16_16_FLOAT 0x00000020
1582#define V_038004_COLOR_32_32_32_32 0x00000022
1583#define V_038004_COLOR_32_32_32_32_FLOAT 0x00000023
1584#define V_038004_FMT_1 0x00000025
1585#define V_038004_FMT_GB_GR 0x00000027
1586#define V_038004_FMT_BG_RG 0x00000028
1587#define V_038004_FMT_32_AS_8 0x00000029
1588#define V_038004_FMT_32_AS_8_8 0x0000002A
1589#define V_038004_FMT_5_9_9_9_SHAREDEXP 0x0000002B
1590#define V_038004_FMT_8_8_8 0x0000002C
1591#define V_038004_FMT_16_16_16 0x0000002D
1592#define V_038004_FMT_16_16_16_FLOAT 0x0000002E
1593#define V_038004_FMT_32_32_32 0x0000002F
1594#define V_038004_FMT_32_32_32_FLOAT 0x00000030
1595#define V_038004_FMT_BC1 0x00000031
1596#define V_038004_FMT_BC2 0x00000032
1597#define V_038004_FMT_BC3 0x00000033
1598#define V_038004_FMT_BC4 0x00000034
1599#define V_038004_FMT_BC5 0x00000035
1600#define V_038004_FMT_BC6 0x00000036
1601#define V_038004_FMT_BC7 0x00000037
1602#define V_038004_FMT_32_AS_32_32_32_32 0x00000038
1603#define R_038010_SQ_TEX_RESOURCE_WORD4_0 0x038010
1604#define S_038010_FORMAT_COMP_X(x) (((x) & 0x3) << 0)
1605#define G_038010_FORMAT_COMP_X(x) (((x) >> 0) & 0x3)
1606#define C_038010_FORMAT_COMP_X 0xFFFFFFFC
1607#define S_038010_FORMAT_COMP_Y(x) (((x) & 0x3) << 2)
1608#define G_038010_FORMAT_COMP_Y(x) (((x) >> 2) & 0x3)
1609#define C_038010_FORMAT_COMP_Y 0xFFFFFFF3
1610#define S_038010_FORMAT_COMP_Z(x) (((x) & 0x3) << 4)
1611#define G_038010_FORMAT_COMP_Z(x) (((x) >> 4) & 0x3)
1612#define C_038010_FORMAT_COMP_Z 0xFFFFFFCF
1613#define S_038010_FORMAT_COMP_W(x) (((x) & 0x3) << 6)
1614#define G_038010_FORMAT_COMP_W(x) (((x) >> 6) & 0x3)
1615#define C_038010_FORMAT_COMP_W 0xFFFFFF3F
1616#define S_038010_NUM_FORMAT_ALL(x) (((x) & 0x3) << 8)
1617#define G_038010_NUM_FORMAT_ALL(x) (((x) >> 8) & 0x3)
1618#define C_038010_NUM_FORMAT_ALL 0xFFFFFCFF
1619#define S_038010_SRF_MODE_ALL(x) (((x) & 0x1) << 10)
1620#define G_038010_SRF_MODE_ALL(x) (((x) >> 10) & 0x1)
1621#define C_038010_SRF_MODE_ALL 0xFFFFFBFF
1622#define S_038010_FORCE_DEGAMMA(x) (((x) & 0x1) << 11)
1623#define G_038010_FORCE_DEGAMMA(x) (((x) >> 11) & 0x1)
1624#define C_038010_FORCE_DEGAMMA 0xFFFFF7FF
1625#define S_038010_ENDIAN_SWAP(x) (((x) & 0x3) << 12)
1626#define G_038010_ENDIAN_SWAP(x) (((x) >> 12) & 0x3)
1627#define C_038010_ENDIAN_SWAP 0xFFFFCFFF
1628#define S_038010_REQUEST_SIZE(x) (((x) & 0x3) << 14)
1629#define G_038010_REQUEST_SIZE(x) (((x) >> 14) & 0x3)
1630#define C_038010_REQUEST_SIZE 0xFFFF3FFF
1631#define S_038010_DST_SEL_X(x) (((x) & 0x7) << 16)
1632#define G_038010_DST_SEL_X(x) (((x) >> 16) & 0x7)
1633#define C_038010_DST_SEL_X 0xFFF8FFFF
1634#define S_038010_DST_SEL_Y(x) (((x) & 0x7) << 19)
1635#define G_038010_DST_SEL_Y(x) (((x) >> 19) & 0x7)
1636#define C_038010_DST_SEL_Y 0xFFC7FFFF
1637#define S_038010_DST_SEL_Z(x) (((x) & 0x7) << 22)
1638#define G_038010_DST_SEL_Z(x) (((x) >> 22) & 0x7)
1639#define C_038010_DST_SEL_Z 0xFE3FFFFF
1640#define S_038010_DST_SEL_W(x) (((x) & 0x7) << 25)
1641#define G_038010_DST_SEL_W(x) (((x) >> 25) & 0x7)
1642#define C_038010_DST_SEL_W 0xF1FFFFFF
1643# define SQ_SEL_X 0
1644# define SQ_SEL_Y 1
1645# define SQ_SEL_Z 2
1646# define SQ_SEL_W 3
1647# define SQ_SEL_0 4
1648# define SQ_SEL_1 5
1649#define S_038010_BASE_LEVEL(x) (((x) & 0xF) << 28)
1650#define G_038010_BASE_LEVEL(x) (((x) >> 28) & 0xF)
1651#define C_038010_BASE_LEVEL 0x0FFFFFFF
1652#define R_038014_SQ_TEX_RESOURCE_WORD5_0 0x038014
1653#define S_038014_LAST_LEVEL(x) (((x) & 0xF) << 0)
1654#define G_038014_LAST_LEVEL(x) (((x) >> 0) & 0xF)
1655#define C_038014_LAST_LEVEL 0xFFFFFFF0
1656#define S_038014_BASE_ARRAY(x) (((x) & 0x1FFF) << 4)
1657#define G_038014_BASE_ARRAY(x) (((x) >> 4) & 0x1FFF)
1658#define C_038014_BASE_ARRAY 0xFFFE000F
1659#define S_038014_LAST_ARRAY(x) (((x) & 0x1FFF) << 17)
1660#define G_038014_LAST_ARRAY(x) (((x) >> 17) & 0x1FFF)
1661#define C_038014_LAST_ARRAY 0xC001FFFF
1662#define R_0288A8_SQ_ESGS_RING_ITEMSIZE 0x0288A8
1663#define S_0288A8_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
1664#define G_0288A8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
1665#define C_0288A8_ITEMSIZE 0xFFFF8000
1666#define R_008C44_SQ_ESGS_RING_SIZE 0x008C44
1667#define S_008C44_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
1668#define G_008C44_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
1669#define C_008C44_MEM_SIZE 0x00000000
1670#define R_0288B0_SQ_ESTMP_RING_ITEMSIZE 0x0288B0
1671#define S_0288B0_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
1672#define G_0288B0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
1673#define C_0288B0_ITEMSIZE 0xFFFF8000
1674#define R_008C54_SQ_ESTMP_RING_SIZE 0x008C54
1675#define S_008C54_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
1676#define G_008C54_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
1677#define C_008C54_MEM_SIZE 0x00000000
1678#define R_0288C0_SQ_FBUF_RING_ITEMSIZE 0x0288C0
1679#define S_0288C0_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
1680#define G_0288C0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
1681#define C_0288C0_ITEMSIZE 0xFFFF8000
1682#define R_008C74_SQ_FBUF_RING_SIZE 0x008C74
1683#define S_008C74_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
1684#define G_008C74_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
1685#define C_008C74_MEM_SIZE 0x00000000
1686#define R_0288B4_SQ_GSTMP_RING_ITEMSIZE 0x0288B4
1687#define S_0288B4_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
1688#define G_0288B4_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
1689#define C_0288B4_ITEMSIZE 0xFFFF8000
1690#define R_008C5C_SQ_GSTMP_RING_SIZE 0x008C5C
1691#define S_008C5C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
1692#define G_008C5C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
1693#define C_008C5C_MEM_SIZE 0x00000000
1694#define R_0288AC_SQ_GSVS_RING_ITEMSIZE 0x0288AC
1695#define S_0288AC_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
1696#define G_0288AC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
1697#define C_0288AC_ITEMSIZE 0xFFFF8000
1698#define R_008C4C_SQ_GSVS_RING_SIZE 0x008C4C
1699#define S_008C4C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
1700#define G_008C4C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
1701#define C_008C4C_MEM_SIZE 0x00000000
1702#define R_0288BC_SQ_PSTMP_RING_ITEMSIZE 0x0288BC
1703#define S_0288BC_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
1704#define G_0288BC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
1705#define C_0288BC_ITEMSIZE 0xFFFF8000
1706#define R_008C6C_SQ_PSTMP_RING_SIZE 0x008C6C
1707#define S_008C6C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
1708#define G_008C6C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
1709#define C_008C6C_MEM_SIZE 0x00000000
1710#define R_0288C4_SQ_REDUC_RING_ITEMSIZE 0x0288C4
1711#define S_0288C4_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
1712#define G_0288C4_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
1713#define C_0288C4_ITEMSIZE 0xFFFF8000
1714#define R_008C7C_SQ_REDUC_RING_SIZE 0x008C7C
1715#define S_008C7C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
1716#define G_008C7C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
1717#define C_008C7C_MEM_SIZE 0x00000000
1718#define R_0288B8_SQ_VSTMP_RING_ITEMSIZE 0x0288B8
1719#define S_0288B8_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
1720#define G_0288B8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
1721#define C_0288B8_ITEMSIZE 0xFFFF8000
1722#define R_008C64_SQ_VSTMP_RING_SIZE 0x008C64
1723#define S_008C64_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)
1724#define G_008C64_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)
1725#define C_008C64_MEM_SIZE 0x00000000
1726#define R_0288C8_SQ_GS_VERT_ITEMSIZE 0x0288C8
1727#define S_0288C8_ITEMSIZE(x) (((x) & 0x7FFF) << 0)
1728#define G_0288C8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)
1729#define C_0288C8_ITEMSIZE 0xFFFF8000
1730#define R_028010_DB_DEPTH_INFO 0x028010
1731#define S_028010_FORMAT(x) (((x) & 0x7) << 0)
1732#define G_028010_FORMAT(x) (((x) >> 0) & 0x7)
1733#define C_028010_FORMAT 0xFFFFFFF8
1734#define V_028010_DEPTH_INVALID 0x00000000
1735#define V_028010_DEPTH_16 0x00000001
1736#define V_028010_DEPTH_X8_24 0x00000002
1737#define V_028010_DEPTH_8_24 0x00000003
1738#define V_028010_DEPTH_X8_24_FLOAT 0x00000004
1739#define V_028010_DEPTH_8_24_FLOAT 0x00000005
1740#define V_028010_DEPTH_32_FLOAT 0x00000006
1741#define V_028010_DEPTH_X24_8_32_FLOAT 0x00000007
1742#define S_028010_READ_SIZE(x) (((x) & 0x1) << 3)
1743#define G_028010_READ_SIZE(x) (((x) >> 3) & 0x1)
1744#define C_028010_READ_SIZE 0xFFFFFFF7
1745#define S_028010_ARRAY_MODE(x) (((x) & 0xF) << 15)
1746#define G_028010_ARRAY_MODE(x) (((x) >> 15) & 0xF)
1747#define C_028010_ARRAY_MODE 0xFFF87FFF
1748#define V_028010_ARRAY_1D_TILED_THIN1 0x00000002
1749#define V_028010_ARRAY_2D_TILED_THIN1 0x00000004
1750#define S_028010_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 25)
1751#define G_028010_TILE_SURFACE_ENABLE(x) (((x) >> 25) & 0x1)
1752#define C_028010_TILE_SURFACE_ENABLE 0xFDFFFFFF
1753#define S_028010_TILE_COMPACT(x) (((x) & 0x1) << 26)
1754#define G_028010_TILE_COMPACT(x) (((x) >> 26) & 0x1)
1755#define C_028010_TILE_COMPACT 0xFBFFFFFF
1756#define S_028010_ZRANGE_PRECISION(x) (((x) & 0x1) << 31)
1757#define G_028010_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1)
1758#define C_028010_ZRANGE_PRECISION 0x7FFFFFFF
1759#define R_028000_DB_DEPTH_SIZE 0x028000
1760#define S_028000_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0)
1761#define G_028000_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF)
1762#define C_028000_PITCH_TILE_MAX 0xFFFFFC00
1763#define S_028000_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10)
1764#define G_028000_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF)
1765#define C_028000_SLICE_TILE_MAX 0xC00003FF
1766#define R_028004_DB_DEPTH_VIEW 0x028004
1767#define S_028004_SLICE_START(x) (((x) & 0x7FF) << 0)
1768#define G_028004_SLICE_START(x) (((x) >> 0) & 0x7FF)
1769#define C_028004_SLICE_START 0xFFFFF800
1770#define S_028004_SLICE_MAX(x) (((x) & 0x7FF) << 13)
1771#define G_028004_SLICE_MAX(x) (((x) >> 13) & 0x7FF)
1772#define C_028004_SLICE_MAX 0xFF001FFF
1773#define R_028800_DB_DEPTH_CONTROL 0x028800
1774#define S_028800_STENCIL_ENABLE(x) (((x) & 0x1) << 0)
1775#define G_028800_STENCIL_ENABLE(x) (((x) >> 0) & 0x1)
1776#define C_028800_STENCIL_ENABLE 0xFFFFFFFE
1777#define S_028800_Z_ENABLE(x) (((x) & 0x1) << 1)
1778#define G_028800_Z_ENABLE(x) (((x) >> 1) & 0x1)
1779#define C_028800_Z_ENABLE 0xFFFFFFFD
1780#define S_028800_Z_WRITE_ENABLE(x) (((x) & 0x1) << 2)
1781#define G_028800_Z_WRITE_ENABLE(x) (((x) >> 2) & 0x1)
1782#define C_028800_Z_WRITE_ENABLE 0xFFFFFFFB
1783#define S_028800_ZFUNC(x) (((x) & 0x7) << 4)
1784#define G_028800_ZFUNC(x) (((x) >> 4) & 0x7)
1785#define C_028800_ZFUNC 0xFFFFFF8F
1786#define S_028800_BACKFACE_ENABLE(x) (((x) & 0x1) << 7)
1787#define G_028800_BACKFACE_ENABLE(x) (((x) >> 7) & 0x1)
1788#define C_028800_BACKFACE_ENABLE 0xFFFFFF7F
1789#define S_028800_STENCILFUNC(x) (((x) & 0x7) << 8)
1790#define G_028800_STENCILFUNC(x) (((x) >> 8) & 0x7)
1791#define C_028800_STENCILFUNC 0xFFFFF8FF
1792#define S_028800_STENCILFAIL(x) (((x) & 0x7) << 11)
1793#define G_028800_STENCILFAIL(x) (((x) >> 11) & 0x7)
1794#define C_028800_STENCILFAIL 0xFFFFC7FF
1795#define S_028800_STENCILZPASS(x) (((x) & 0x7) << 14)
1796#define G_028800_STENCILZPASS(x) (((x) >> 14) & 0x7)
1797#define C_028800_STENCILZPASS 0xFFFE3FFF
1798#define S_028800_STENCILZFAIL(x) (((x) & 0x7) << 17)
1799#define G_028800_STENCILZFAIL(x) (((x) >> 17) & 0x7)
1800#define C_028800_STENCILZFAIL 0xFFF1FFFF
1801#define S_028800_STENCILFUNC_BF(x) (((x) & 0x7) << 20)
1802#define G_028800_STENCILFUNC_BF(x) (((x) >> 20) & 0x7)
1803#define C_028800_STENCILFUNC_BF 0xFF8FFFFF
1804#define S_028800_STENCILFAIL_BF(x) (((x) & 0x7) << 23)
1805#define G_028800_STENCILFAIL_BF(x) (((x) >> 23) & 0x7)
1806#define C_028800_STENCILFAIL_BF 0xFC7FFFFF
1807#define S_028800_STENCILZPASS_BF(x) (((x) & 0x7) << 26)
1808#define G_028800_STENCILZPASS_BF(x) (((x) >> 26) & 0x7)
1809#define C_028800_STENCILZPASS_BF 0xE3FFFFFF
1810#define S_028800_STENCILZFAIL_BF(x) (((x) & 0x7) << 29)
1811#define G_028800_STENCILZFAIL_BF(x) (((x) >> 29) & 0x7)
1812#define C_028800_STENCILZFAIL_BF 0x1FFFFFFF
1813
1814#endif