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1/*
2 * Copyright (C) 2007 Ben Skeggs.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
26
27#ifndef __NOUVEAU_DMA_H__
28#define __NOUVEAU_DMA_H__
29
30#ifndef NOUVEAU_DMA_DEBUG
31#define NOUVEAU_DMA_DEBUG 0
32#endif
33
34void nv50_dma_push(struct nouveau_channel *, struct nouveau_bo *,
35 int delta, int length);
36
37/*
38 * There's a hw race condition where you can't jump to your PUT offset,
39 * to avoid this we jump to offset + SKIPS and fill the difference with
40 * NOPs.
41 *
42 * xf86-video-nv configures the DMA fetch size to 32 bytes, and uses
43 * a SKIPS value of 8. Lets assume that the race condition is to do
44 * with writing into the fetch area, we configure a fetch size of 128
45 * bytes so we need a larger SKIPS value.
46 */
47#define NOUVEAU_DMA_SKIPS (128 / 4)
48
49/* Hardcoded object assignments to subchannels (subchannel id). */
50enum {
51 NvSubM2MF = 0,
52 NvSubSw = 1,
53 NvSub2D = 2,
54 NvSubCtxSurf2D = 2,
55 NvSubGdiRect = 3,
56 NvSubImageBlit = 4
57};
58
59/* Object handles. */
60enum {
61 NvM2MF = 0x80000001,
62 NvDmaFB = 0x80000002,
63 NvDmaTT = 0x80000003,
64 NvNotify0 = 0x80000006,
65 Nv2D = 0x80000007,
66 NvCtxSurf2D = 0x80000008,
67 NvRop = 0x80000009,
68 NvImagePatt = 0x8000000a,
69 NvClipRect = 0x8000000b,
70 NvGdiRect = 0x8000000c,
71 NvImageBlit = 0x8000000d,
72 NvSw = 0x8000000e,
73 NvSema = 0x8000000f,
74 NvEvoSema0 = 0x80000010,
75 NvEvoSema1 = 0x80000011,
76
77 /* G80+ display objects */
78 NvEvoVRAM = 0x01000000,
79 NvEvoFB16 = 0x01000001,
80 NvEvoFB32 = 0x01000002,
81 NvEvoVRAM_LP = 0x01000003,
82 NvEvoSync = 0xcafe0000
83};
84
85#define NV_MEMORY_TO_MEMORY_FORMAT 0x00000039
86#define NV_MEMORY_TO_MEMORY_FORMAT_NAME 0x00000000
87#define NV_MEMORY_TO_MEMORY_FORMAT_SET_REF 0x00000050
88#define NV_MEMORY_TO_MEMORY_FORMAT_NOP 0x00000100
89#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY 0x00000104
90#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY_STYLE_WRITE 0x00000000
91#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY_STYLE_WRITE_LE_AWAKEN 0x00000001
92#define NV_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY 0x00000180
93#define NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE 0x00000184
94#define NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN 0x0000030c
95
96#define NV50_MEMORY_TO_MEMORY_FORMAT 0x00005039
97#define NV50_MEMORY_TO_MEMORY_FORMAT_UNK200 0x00000200
98#define NV50_MEMORY_TO_MEMORY_FORMAT_UNK21C 0x0000021c
99#define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN_HIGH 0x00000238
100#define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_OUT_HIGH 0x0000023c
101
102static __must_check inline int
103RING_SPACE(struct nouveau_channel *chan, int size)
104{
105 int ret;
106
107 ret = nouveau_dma_wait(chan, 1, size);
108 if (ret)
109 return ret;
110
111 chan->dma.free -= size;
112 return 0;
113}
114
115static inline void
116OUT_RING(struct nouveau_channel *chan, int data)
117{
118 if (NOUVEAU_DMA_DEBUG) {
119 NV_INFO(chan->dev, "Ch%d/0x%08x: 0x%08x\n",
120 chan->id, chan->dma.cur << 2, data);
121 }
122
123 nouveau_bo_wr32(chan->pushbuf_bo, chan->dma.cur++, data);
124}
125
126extern void
127OUT_RINGp(struct nouveau_channel *chan, const void *data, unsigned nr_dwords);
128
129static inline void
130BEGIN_NVC0(struct nouveau_channel *chan, int op, int subc, int mthd, int size)
131{
132 OUT_RING(chan, (op << 28) | (size << 16) | (subc << 13) | (mthd >> 2));
133}
134
135static inline void
136BEGIN_RING(struct nouveau_channel *chan, int subc, int mthd, int size)
137{
138 OUT_RING(chan, (subc << 13) | (size << 18) | mthd);
139}
140
141#define WRITE_PUT(val) do { \
142 DRM_MEMORYBARRIER(); \
143 nouveau_bo_rd32(chan->pushbuf_bo, 0); \
144 nvchan_wr32(chan, chan->user_put, ((val) << 2) + chan->pushbuf_base); \
145} while (0)
146
147static inline void
148FIRE_RING(struct nouveau_channel *chan)
149{
150 if (NOUVEAU_DMA_DEBUG) {
151 NV_INFO(chan->dev, "Ch%d/0x%08x: PUSH!\n",
152 chan->id, chan->dma.cur << 2);
153 }
154
155 if (chan->dma.cur == chan->dma.put)
156 return;
157 chan->accel_done = true;
158
159 if (chan->dma.ib_max) {
160 nv50_dma_push(chan, chan->pushbuf_bo, chan->dma.put << 2,
161 (chan->dma.cur - chan->dma.put) << 2);
162 } else {
163 WRITE_PUT(chan->dma.cur);
164 }
165
166 chan->dma.put = chan->dma.cur;
167}
168
169static inline void
170WIND_RING(struct nouveau_channel *chan)
171{
172 chan->dma.cur = chan->dma.put;
173}
174
175#endif
1/*
2 * Copyright (C) 2007 Ben Skeggs.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
26
27#ifndef __NOUVEAU_DMA_H__
28#define __NOUVEAU_DMA_H__
29
30#ifndef NOUVEAU_DMA_DEBUG
31#define NOUVEAU_DMA_DEBUG 0
32#endif
33
34void nv50_dma_push(struct nouveau_channel *, struct nouveau_bo *,
35 int delta, int length);
36
37/*
38 * There's a hw race condition where you can't jump to your PUT offset,
39 * to avoid this we jump to offset + SKIPS and fill the difference with
40 * NOPs.
41 *
42 * xf86-video-nv configures the DMA fetch size to 32 bytes, and uses
43 * a SKIPS value of 8. Lets assume that the race condition is to do
44 * with writing into the fetch area, we configure a fetch size of 128
45 * bytes so we need a larger SKIPS value.
46 */
47#define NOUVEAU_DMA_SKIPS (128 / 4)
48
49/* Hardcoded object assignments to subchannels (subchannel id). */
50enum {
51 NvSubCtxSurf2D = 0,
52 NvSubSw = 1,
53 NvSubImageBlit = 2,
54 NvSub2D = 3,
55 NvSubGdiRect = 3,
56 NvSubCopy = 4,
57};
58
59/* Object handles. */
60enum {
61 NvM2MF = 0x80000001,
62 NvDmaFB = 0x80000002,
63 NvDmaTT = 0x80000003,
64 NvNotify0 = 0x80000006,
65 Nv2D = 0x80000007,
66 NvCtxSurf2D = 0x80000008,
67 NvRop = 0x80000009,
68 NvImagePatt = 0x8000000a,
69 NvClipRect = 0x8000000b,
70 NvGdiRect = 0x8000000c,
71 NvImageBlit = 0x8000000d,
72 NvSw = 0x8000000e,
73 NvSema = 0x8000000f,
74 NvEvoSema0 = 0x80000010,
75 NvEvoSema1 = 0x80000011,
76 NvNotify1 = 0x80000012,
77
78 /* G80+ display objects */
79 NvEvoVRAM = 0x01000000,
80 NvEvoFB16 = 0x01000001,
81 NvEvoFB32 = 0x01000002,
82 NvEvoVRAM_LP = 0x01000003,
83 NvEvoSync = 0xcafe0000
84};
85
86#define NV_MEMORY_TO_MEMORY_FORMAT 0x00000039
87#define NV_MEMORY_TO_MEMORY_FORMAT_NAME 0x00000000
88#define NV_MEMORY_TO_MEMORY_FORMAT_SET_REF 0x00000050
89#define NV_MEMORY_TO_MEMORY_FORMAT_NOP 0x00000100
90#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY 0x00000104
91#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY_STYLE_WRITE 0x00000000
92#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY_STYLE_WRITE_LE_AWAKEN 0x00000001
93#define NV_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY 0x00000180
94#define NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE 0x00000184
95#define NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN 0x0000030c
96
97#define NV50_MEMORY_TO_MEMORY_FORMAT 0x00005039
98#define NV50_MEMORY_TO_MEMORY_FORMAT_UNK200 0x00000200
99#define NV50_MEMORY_TO_MEMORY_FORMAT_UNK21C 0x0000021c
100#define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN_HIGH 0x00000238
101#define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_OUT_HIGH 0x0000023c
102
103static __must_check inline int
104RING_SPACE(struct nouveau_channel *chan, int size)
105{
106 int ret;
107
108 ret = nouveau_dma_wait(chan, 1, size);
109 if (ret)
110 return ret;
111
112 chan->dma.free -= size;
113 return 0;
114}
115
116static inline void
117OUT_RING(struct nouveau_channel *chan, int data)
118{
119 if (NOUVEAU_DMA_DEBUG) {
120 NV_INFO(chan->dev, "Ch%d/0x%08x: 0x%08x\n",
121 chan->id, chan->dma.cur << 2, data);
122 }
123
124 nouveau_bo_wr32(chan->pushbuf_bo, chan->dma.cur++, data);
125}
126
127extern void
128OUT_RINGp(struct nouveau_channel *chan, const void *data, unsigned nr_dwords);
129
130static inline void
131BEGIN_NV04(struct nouveau_channel *chan, int subc, int mthd, int size)
132{
133 OUT_RING(chan, 0x00000000 | (subc << 13) | (size << 18) | mthd);
134}
135
136static inline void
137BEGIN_NI04(struct nouveau_channel *chan, int subc, int mthd, int size)
138{
139 OUT_RING(chan, 0x40000000 | (subc << 13) | (size << 18) | mthd);
140}
141
142static inline void
143BEGIN_NVC0(struct nouveau_channel *chan, int subc, int mthd, int size)
144{
145 OUT_RING(chan, 0x20000000 | (size << 16) | (subc << 13) | (mthd >> 2));
146}
147
148static inline void
149BEGIN_NIC0(struct nouveau_channel *chan, int subc, int mthd, int size)
150{
151 OUT_RING(chan, 0x60000000 | (size << 16) | (subc << 13) | (mthd >> 2));
152}
153
154static inline void
155BEGIN_IMC0(struct nouveau_channel *chan, int subc, int mthd, u16 data)
156{
157 OUT_RING(chan, 0x80000000 | (data << 16) | (subc << 13) | (mthd >> 2));
158}
159
160#define WRITE_PUT(val) do { \
161 DRM_MEMORYBARRIER(); \
162 nouveau_bo_rd32(chan->pushbuf_bo, 0); \
163 nvchan_wr32(chan, chan->user_put, ((val) << 2) + chan->pushbuf_base); \
164} while (0)
165
166static inline void
167FIRE_RING(struct nouveau_channel *chan)
168{
169 if (NOUVEAU_DMA_DEBUG) {
170 NV_INFO(chan->dev, "Ch%d/0x%08x: PUSH!\n",
171 chan->id, chan->dma.cur << 2);
172 }
173
174 if (chan->dma.cur == chan->dma.put)
175 return;
176 chan->accel_done = true;
177
178 if (chan->dma.ib_max) {
179 nv50_dma_push(chan, chan->pushbuf_bo, chan->dma.put << 2,
180 (chan->dma.cur - chan->dma.put) << 2);
181 } else {
182 WRITE_PUT(chan->dma.cur);
183 }
184
185 chan->dma.put = chan->dma.cur;
186}
187
188static inline void
189WIND_RING(struct nouveau_channel *chan)
190{
191 chan->dma.cur = chan->dma.put;
192}
193
194#endif