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1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
27 */
28
29#include <linux/i2c.h>
30#include <linux/slab.h>
31#include <linux/delay.h>
32#include "drmP.h"
33#include "drm.h"
34#include "drm_crtc.h"
35#include "drm_edid.h"
36#include "intel_drv.h"
37#include "i915_drm.h"
38#include "i915_drv.h"
39
40struct intel_hdmi {
41 struct intel_encoder base;
42 u32 sdvox_reg;
43 int ddc_bus;
44 uint32_t color_range;
45 bool has_hdmi_sink;
46 bool has_audio;
47 int force_audio;
48 void (*write_infoframe)(struct drm_encoder *encoder,
49 struct dip_infoframe *frame);
50};
51
52static struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
53{
54 return container_of(encoder, struct intel_hdmi, base.base);
55}
56
57static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
58{
59 return container_of(intel_attached_encoder(connector),
60 struct intel_hdmi, base);
61}
62
63void intel_dip_infoframe_csum(struct dip_infoframe *frame)
64{
65 uint8_t *data = (uint8_t *)frame;
66 uint8_t sum = 0;
67 unsigned i;
68
69 frame->checksum = 0;
70 frame->ecc = 0;
71
72 /* Header isn't part of the checksum */
73 for (i = 5; i < frame->len; i++)
74 sum += data[i];
75
76 frame->checksum = 0x100 - sum;
77}
78
79static u32 intel_infoframe_index(struct dip_infoframe *frame)
80{
81 u32 flags = 0;
82
83 switch (frame->type) {
84 case DIP_TYPE_AVI:
85 flags |= VIDEO_DIP_SELECT_AVI;
86 break;
87 case DIP_TYPE_SPD:
88 flags |= VIDEO_DIP_SELECT_SPD;
89 break;
90 default:
91 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
92 break;
93 }
94
95 return flags;
96}
97
98static u32 intel_infoframe_flags(struct dip_infoframe *frame)
99{
100 u32 flags = 0;
101
102 switch (frame->type) {
103 case DIP_TYPE_AVI:
104 flags |= VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_FREQ_VSYNC;
105 break;
106 case DIP_TYPE_SPD:
107 flags |= VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_FREQ_2VSYNC;
108 break;
109 default:
110 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
111 break;
112 }
113
114 return flags;
115}
116
117static void i9xx_write_infoframe(struct drm_encoder *encoder,
118 struct dip_infoframe *frame)
119{
120 uint32_t *data = (uint32_t *)frame;
121 struct drm_device *dev = encoder->dev;
122 struct drm_i915_private *dev_priv = dev->dev_private;
123 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
124 u32 port, flags, val = I915_READ(VIDEO_DIP_CTL);
125 unsigned i, len = DIP_HEADER_SIZE + frame->len;
126
127
128 /* XXX first guess at handling video port, is this corrent? */
129 if (intel_hdmi->sdvox_reg == SDVOB)
130 port = VIDEO_DIP_PORT_B;
131 else if (intel_hdmi->sdvox_reg == SDVOC)
132 port = VIDEO_DIP_PORT_C;
133 else
134 return;
135
136 flags = intel_infoframe_index(frame);
137
138 val &= ~VIDEO_DIP_SELECT_MASK;
139
140 I915_WRITE(VIDEO_DIP_CTL, val | port | flags);
141
142 for (i = 0; i < len; i += 4) {
143 I915_WRITE(VIDEO_DIP_DATA, *data);
144 data++;
145 }
146
147 flags |= intel_infoframe_flags(frame);
148
149 I915_WRITE(VIDEO_DIP_CTL, VIDEO_DIP_ENABLE | val | port | flags);
150}
151
152static void ironlake_write_infoframe(struct drm_encoder *encoder,
153 struct dip_infoframe *frame)
154{
155 uint32_t *data = (uint32_t *)frame;
156 struct drm_device *dev = encoder->dev;
157 struct drm_i915_private *dev_priv = dev->dev_private;
158 struct drm_crtc *crtc = encoder->crtc;
159 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
160 int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
161 unsigned i, len = DIP_HEADER_SIZE + frame->len;
162 u32 flags, val = I915_READ(reg);
163
164 intel_wait_for_vblank(dev, intel_crtc->pipe);
165
166 flags = intel_infoframe_index(frame);
167
168 val &= ~VIDEO_DIP_SELECT_MASK;
169
170 I915_WRITE(reg, val | flags);
171
172 for (i = 0; i < len; i += 4) {
173 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
174 data++;
175 }
176
177 flags |= intel_infoframe_flags(frame);
178
179 I915_WRITE(reg, VIDEO_DIP_ENABLE | val | flags);
180}
181static void intel_set_infoframe(struct drm_encoder *encoder,
182 struct dip_infoframe *frame)
183{
184 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
185
186 if (!intel_hdmi->has_hdmi_sink)
187 return;
188
189 intel_dip_infoframe_csum(frame);
190 intel_hdmi->write_infoframe(encoder, frame);
191}
192
193static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
194{
195 struct dip_infoframe avi_if = {
196 .type = DIP_TYPE_AVI,
197 .ver = DIP_VERSION_AVI,
198 .len = DIP_LEN_AVI,
199 };
200
201 intel_set_infoframe(encoder, &avi_if);
202}
203
204static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
205{
206 struct dip_infoframe spd_if;
207
208 memset(&spd_if, 0, sizeof(spd_if));
209 spd_if.type = DIP_TYPE_SPD;
210 spd_if.ver = DIP_VERSION_SPD;
211 spd_if.len = DIP_LEN_SPD;
212 strcpy(spd_if.body.spd.vn, "Intel");
213 strcpy(spd_if.body.spd.pd, "Integrated gfx");
214 spd_if.body.spd.sdi = DIP_SPD_PC;
215
216 intel_set_infoframe(encoder, &spd_if);
217}
218
219static void intel_hdmi_mode_set(struct drm_encoder *encoder,
220 struct drm_display_mode *mode,
221 struct drm_display_mode *adjusted_mode)
222{
223 struct drm_device *dev = encoder->dev;
224 struct drm_i915_private *dev_priv = dev->dev_private;
225 struct drm_crtc *crtc = encoder->crtc;
226 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
227 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
228 u32 sdvox;
229
230 sdvox = SDVO_ENCODING_HDMI | SDVO_BORDER_ENABLE;
231 if (!HAS_PCH_SPLIT(dev))
232 sdvox |= intel_hdmi->color_range;
233 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
234 sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
235 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
236 sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
237
238 if (intel_crtc->bpp > 24)
239 sdvox |= COLOR_FORMAT_12bpc;
240 else
241 sdvox |= COLOR_FORMAT_8bpc;
242
243 /* Required on CPT */
244 if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev))
245 sdvox |= HDMI_MODE_SELECT;
246
247 if (intel_hdmi->has_audio) {
248 sdvox |= SDVO_AUDIO_ENABLE;
249 sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC;
250 }
251
252 if (intel_crtc->pipe == 1) {
253 if (HAS_PCH_CPT(dev))
254 sdvox |= PORT_TRANS_B_SEL_CPT;
255 else
256 sdvox |= SDVO_PIPE_B_SELECT;
257 }
258
259 I915_WRITE(intel_hdmi->sdvox_reg, sdvox);
260 POSTING_READ(intel_hdmi->sdvox_reg);
261
262 intel_hdmi_set_avi_infoframe(encoder);
263 intel_hdmi_set_spd_infoframe(encoder);
264}
265
266static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode)
267{
268 struct drm_device *dev = encoder->dev;
269 struct drm_i915_private *dev_priv = dev->dev_private;
270 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
271 u32 temp;
272
273 temp = I915_READ(intel_hdmi->sdvox_reg);
274
275 /* HW workaround, need to toggle enable bit off and on for 12bpc, but
276 * we do this anyway which shows more stable in testing.
277 */
278 if (HAS_PCH_SPLIT(dev)) {
279 I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE);
280 POSTING_READ(intel_hdmi->sdvox_reg);
281 }
282
283 if (mode != DRM_MODE_DPMS_ON) {
284 temp &= ~SDVO_ENABLE;
285 } else {
286 temp |= SDVO_ENABLE;
287 }
288
289 I915_WRITE(intel_hdmi->sdvox_reg, temp);
290 POSTING_READ(intel_hdmi->sdvox_reg);
291
292 /* HW workaround, need to write this twice for issue that may result
293 * in first write getting masked.
294 */
295 if (HAS_PCH_SPLIT(dev)) {
296 I915_WRITE(intel_hdmi->sdvox_reg, temp);
297 POSTING_READ(intel_hdmi->sdvox_reg);
298 }
299}
300
301static int intel_hdmi_mode_valid(struct drm_connector *connector,
302 struct drm_display_mode *mode)
303{
304 if (mode->clock > 165000)
305 return MODE_CLOCK_HIGH;
306 if (mode->clock < 20000)
307 return MODE_CLOCK_LOW;
308
309 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
310 return MODE_NO_DBLESCAN;
311
312 return MODE_OK;
313}
314
315static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder,
316 struct drm_display_mode *mode,
317 struct drm_display_mode *adjusted_mode)
318{
319 return true;
320}
321
322static enum drm_connector_status
323intel_hdmi_detect(struct drm_connector *connector, bool force)
324{
325 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
326 struct drm_i915_private *dev_priv = connector->dev->dev_private;
327 struct edid *edid;
328 enum drm_connector_status status = connector_status_disconnected;
329
330 intel_hdmi->has_hdmi_sink = false;
331 intel_hdmi->has_audio = false;
332 edid = drm_get_edid(connector,
333 &dev_priv->gmbus[intel_hdmi->ddc_bus].adapter);
334
335 if (edid) {
336 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
337 status = connector_status_connected;
338 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
339 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
340 }
341 connector->display_info.raw_edid = NULL;
342 kfree(edid);
343 }
344
345 if (status == connector_status_connected) {
346 if (intel_hdmi->force_audio)
347 intel_hdmi->has_audio = intel_hdmi->force_audio > 0;
348 }
349
350 return status;
351}
352
353static int intel_hdmi_get_modes(struct drm_connector *connector)
354{
355 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
356 struct drm_i915_private *dev_priv = connector->dev->dev_private;
357
358 /* We should parse the EDID data and find out if it's an HDMI sink so
359 * we can send audio to it.
360 */
361
362 return intel_ddc_get_modes(connector,
363 &dev_priv->gmbus[intel_hdmi->ddc_bus].adapter);
364}
365
366static bool
367intel_hdmi_detect_audio(struct drm_connector *connector)
368{
369 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
370 struct drm_i915_private *dev_priv = connector->dev->dev_private;
371 struct edid *edid;
372 bool has_audio = false;
373
374 edid = drm_get_edid(connector,
375 &dev_priv->gmbus[intel_hdmi->ddc_bus].adapter);
376 if (edid) {
377 if (edid->input & DRM_EDID_INPUT_DIGITAL)
378 has_audio = drm_detect_monitor_audio(edid);
379
380 connector->display_info.raw_edid = NULL;
381 kfree(edid);
382 }
383
384 return has_audio;
385}
386
387static int
388intel_hdmi_set_property(struct drm_connector *connector,
389 struct drm_property *property,
390 uint64_t val)
391{
392 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
393 struct drm_i915_private *dev_priv = connector->dev->dev_private;
394 int ret;
395
396 ret = drm_connector_property_set_value(connector, property, val);
397 if (ret)
398 return ret;
399
400 if (property == dev_priv->force_audio_property) {
401 int i = val;
402 bool has_audio;
403
404 if (i == intel_hdmi->force_audio)
405 return 0;
406
407 intel_hdmi->force_audio = i;
408
409 if (i == 0)
410 has_audio = intel_hdmi_detect_audio(connector);
411 else
412 has_audio = i > 0;
413
414 if (has_audio == intel_hdmi->has_audio)
415 return 0;
416
417 intel_hdmi->has_audio = has_audio;
418 goto done;
419 }
420
421 if (property == dev_priv->broadcast_rgb_property) {
422 if (val == !!intel_hdmi->color_range)
423 return 0;
424
425 intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
426 goto done;
427 }
428
429 return -EINVAL;
430
431done:
432 if (intel_hdmi->base.base.crtc) {
433 struct drm_crtc *crtc = intel_hdmi->base.base.crtc;
434 drm_crtc_helper_set_mode(crtc, &crtc->mode,
435 crtc->x, crtc->y,
436 crtc->fb);
437 }
438
439 return 0;
440}
441
442static void intel_hdmi_destroy(struct drm_connector *connector)
443{
444 drm_sysfs_connector_remove(connector);
445 drm_connector_cleanup(connector);
446 kfree(connector);
447}
448
449static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = {
450 .dpms = intel_hdmi_dpms,
451 .mode_fixup = intel_hdmi_mode_fixup,
452 .prepare = intel_encoder_prepare,
453 .mode_set = intel_hdmi_mode_set,
454 .commit = intel_encoder_commit,
455};
456
457static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
458 .dpms = drm_helper_connector_dpms,
459 .detect = intel_hdmi_detect,
460 .fill_modes = drm_helper_probe_single_connector_modes,
461 .set_property = intel_hdmi_set_property,
462 .destroy = intel_hdmi_destroy,
463};
464
465static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
466 .get_modes = intel_hdmi_get_modes,
467 .mode_valid = intel_hdmi_mode_valid,
468 .best_encoder = intel_best_encoder,
469};
470
471static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
472 .destroy = intel_encoder_destroy,
473};
474
475static void
476intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
477{
478 intel_attach_force_audio_property(connector);
479 intel_attach_broadcast_rgb_property(connector);
480}
481
482void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
483{
484 struct drm_i915_private *dev_priv = dev->dev_private;
485 struct drm_connector *connector;
486 struct intel_encoder *intel_encoder;
487 struct intel_connector *intel_connector;
488 struct intel_hdmi *intel_hdmi;
489
490 intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL);
491 if (!intel_hdmi)
492 return;
493
494 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
495 if (!intel_connector) {
496 kfree(intel_hdmi);
497 return;
498 }
499
500 intel_encoder = &intel_hdmi->base;
501 drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
502 DRM_MODE_ENCODER_TMDS);
503
504 connector = &intel_connector->base;
505 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
506 DRM_MODE_CONNECTOR_HDMIA);
507 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
508
509 intel_encoder->type = INTEL_OUTPUT_HDMI;
510
511 connector->polled = DRM_CONNECTOR_POLL_HPD;
512 connector->interlace_allowed = 0;
513 connector->doublescan_allowed = 0;
514 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
515
516 /* Set up the DDC bus. */
517 if (sdvox_reg == SDVOB) {
518 intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT);
519 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
520 dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
521 } else if (sdvox_reg == SDVOC) {
522 intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT);
523 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
524 dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
525 } else if (sdvox_reg == HDMIB) {
526 intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT);
527 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
528 dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
529 } else if (sdvox_reg == HDMIC) {
530 intel_encoder->clone_mask = (1 << INTEL_HDMIE_CLONE_BIT);
531 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
532 dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
533 } else if (sdvox_reg == HDMID) {
534 intel_encoder->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT);
535 intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
536 dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
537 }
538
539 intel_hdmi->sdvox_reg = sdvox_reg;
540
541 if (!HAS_PCH_SPLIT(dev))
542 intel_hdmi->write_infoframe = i9xx_write_infoframe;
543 else
544 intel_hdmi->write_infoframe = ironlake_write_infoframe;
545
546 drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs);
547
548 intel_hdmi_add_properties(intel_hdmi, connector);
549
550 intel_connector_attach_encoder(intel_connector, intel_encoder);
551 drm_sysfs_connector_add(connector);
552
553 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
554 * 0xd. Failure to do so will result in spurious interrupts being
555 * generated on the port when a cable is not attached.
556 */
557 if (IS_G4X(dev) && !IS_GM45(dev)) {
558 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
559 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
560 }
561}
1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
27 */
28
29#include <linux/i2c.h>
30#include <linux/slab.h>
31#include <linux/delay.h>
32#include "drmP.h"
33#include "drm.h"
34#include "drm_crtc.h"
35#include "drm_edid.h"
36#include "intel_drv.h"
37#include "i915_drm.h"
38#include "i915_drv.h"
39
40struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
41{
42 return container_of(encoder, struct intel_hdmi, base.base);
43}
44
45static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
46{
47 return container_of(intel_attached_encoder(connector),
48 struct intel_hdmi, base);
49}
50
51void intel_dip_infoframe_csum(struct dip_infoframe *frame)
52{
53 uint8_t *data = (uint8_t *)frame;
54 uint8_t sum = 0;
55 unsigned i;
56
57 frame->checksum = 0;
58 frame->ecc = 0;
59
60 for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++)
61 sum += data[i];
62
63 frame->checksum = 0x100 - sum;
64}
65
66static u32 g4x_infoframe_index(struct dip_infoframe *frame)
67{
68 switch (frame->type) {
69 case DIP_TYPE_AVI:
70 return VIDEO_DIP_SELECT_AVI;
71 case DIP_TYPE_SPD:
72 return VIDEO_DIP_SELECT_SPD;
73 default:
74 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
75 return 0;
76 }
77}
78
79static u32 g4x_infoframe_enable(struct dip_infoframe *frame)
80{
81 switch (frame->type) {
82 case DIP_TYPE_AVI:
83 return VIDEO_DIP_ENABLE_AVI;
84 case DIP_TYPE_SPD:
85 return VIDEO_DIP_ENABLE_SPD;
86 default:
87 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
88 return 0;
89 }
90}
91
92static u32 hsw_infoframe_enable(struct dip_infoframe *frame)
93{
94 switch (frame->type) {
95 case DIP_TYPE_AVI:
96 return VIDEO_DIP_ENABLE_AVI_HSW;
97 case DIP_TYPE_SPD:
98 return VIDEO_DIP_ENABLE_SPD_HSW;
99 default:
100 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
101 return 0;
102 }
103}
104
105static u32 hsw_infoframe_data_reg(struct dip_infoframe *frame, enum pipe pipe)
106{
107 switch (frame->type) {
108 case DIP_TYPE_AVI:
109 return HSW_TVIDEO_DIP_AVI_DATA(pipe);
110 case DIP_TYPE_SPD:
111 return HSW_TVIDEO_DIP_SPD_DATA(pipe);
112 default:
113 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
114 return 0;
115 }
116}
117
118static void g4x_write_infoframe(struct drm_encoder *encoder,
119 struct dip_infoframe *frame)
120{
121 uint32_t *data = (uint32_t *)frame;
122 struct drm_device *dev = encoder->dev;
123 struct drm_i915_private *dev_priv = dev->dev_private;
124 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
125 u32 val = I915_READ(VIDEO_DIP_CTL);
126 unsigned i, len = DIP_HEADER_SIZE + frame->len;
127
128 val &= ~VIDEO_DIP_PORT_MASK;
129 if (intel_hdmi->sdvox_reg == SDVOB)
130 val |= VIDEO_DIP_PORT_B;
131 else if (intel_hdmi->sdvox_reg == SDVOC)
132 val |= VIDEO_DIP_PORT_C;
133 else
134 return;
135
136 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
137 val |= g4x_infoframe_index(frame);
138
139 val &= ~g4x_infoframe_enable(frame);
140 val |= VIDEO_DIP_ENABLE;
141
142 I915_WRITE(VIDEO_DIP_CTL, val);
143
144 for (i = 0; i < len; i += 4) {
145 I915_WRITE(VIDEO_DIP_DATA, *data);
146 data++;
147 }
148
149 val |= g4x_infoframe_enable(frame);
150 val &= ~VIDEO_DIP_FREQ_MASK;
151 val |= VIDEO_DIP_FREQ_VSYNC;
152
153 I915_WRITE(VIDEO_DIP_CTL, val);
154}
155
156static void ibx_write_infoframe(struct drm_encoder *encoder,
157 struct dip_infoframe *frame)
158{
159 uint32_t *data = (uint32_t *)frame;
160 struct drm_device *dev = encoder->dev;
161 struct drm_i915_private *dev_priv = dev->dev_private;
162 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
163 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
164 int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
165 unsigned i, len = DIP_HEADER_SIZE + frame->len;
166 u32 val = I915_READ(reg);
167
168 val &= ~VIDEO_DIP_PORT_MASK;
169 switch (intel_hdmi->sdvox_reg) {
170 case HDMIB:
171 val |= VIDEO_DIP_PORT_B;
172 break;
173 case HDMIC:
174 val |= VIDEO_DIP_PORT_C;
175 break;
176 case HDMID:
177 val |= VIDEO_DIP_PORT_D;
178 break;
179 default:
180 return;
181 }
182
183 intel_wait_for_vblank(dev, intel_crtc->pipe);
184
185 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
186 val |= g4x_infoframe_index(frame);
187
188 val &= ~g4x_infoframe_enable(frame);
189 val |= VIDEO_DIP_ENABLE;
190
191 I915_WRITE(reg, val);
192
193 for (i = 0; i < len; i += 4) {
194 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
195 data++;
196 }
197
198 val |= g4x_infoframe_enable(frame);
199 val &= ~VIDEO_DIP_FREQ_MASK;
200 val |= VIDEO_DIP_FREQ_VSYNC;
201
202 I915_WRITE(reg, val);
203}
204
205static void cpt_write_infoframe(struct drm_encoder *encoder,
206 struct dip_infoframe *frame)
207{
208 uint32_t *data = (uint32_t *)frame;
209 struct drm_device *dev = encoder->dev;
210 struct drm_i915_private *dev_priv = dev->dev_private;
211 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
212 int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
213 unsigned i, len = DIP_HEADER_SIZE + frame->len;
214 u32 val = I915_READ(reg);
215
216 intel_wait_for_vblank(dev, intel_crtc->pipe);
217
218 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
219 val |= g4x_infoframe_index(frame);
220
221 /* The DIP control register spec says that we need to update the AVI
222 * infoframe without clearing its enable bit */
223 if (frame->type == DIP_TYPE_AVI)
224 val |= VIDEO_DIP_ENABLE_AVI;
225 else
226 val &= ~g4x_infoframe_enable(frame);
227
228 val |= VIDEO_DIP_ENABLE;
229
230 I915_WRITE(reg, val);
231
232 for (i = 0; i < len; i += 4) {
233 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
234 data++;
235 }
236
237 val |= g4x_infoframe_enable(frame);
238 val &= ~VIDEO_DIP_FREQ_MASK;
239 val |= VIDEO_DIP_FREQ_VSYNC;
240
241 I915_WRITE(reg, val);
242}
243
244static void vlv_write_infoframe(struct drm_encoder *encoder,
245 struct dip_infoframe *frame)
246{
247 uint32_t *data = (uint32_t *)frame;
248 struct drm_device *dev = encoder->dev;
249 struct drm_i915_private *dev_priv = dev->dev_private;
250 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
251 int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
252 unsigned i, len = DIP_HEADER_SIZE + frame->len;
253 u32 val = I915_READ(reg);
254
255 intel_wait_for_vblank(dev, intel_crtc->pipe);
256
257 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
258 val |= g4x_infoframe_index(frame);
259
260 val &= ~g4x_infoframe_enable(frame);
261 val |= VIDEO_DIP_ENABLE;
262
263 I915_WRITE(reg, val);
264
265 for (i = 0; i < len; i += 4) {
266 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
267 data++;
268 }
269
270 val |= g4x_infoframe_enable(frame);
271 val &= ~VIDEO_DIP_FREQ_MASK;
272 val |= VIDEO_DIP_FREQ_VSYNC;
273
274 I915_WRITE(reg, val);
275}
276
277static void hsw_write_infoframe(struct drm_encoder *encoder,
278 struct dip_infoframe *frame)
279{
280 uint32_t *data = (uint32_t *)frame;
281 struct drm_device *dev = encoder->dev;
282 struct drm_i915_private *dev_priv = dev->dev_private;
283 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
284 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe);
285 u32 data_reg = hsw_infoframe_data_reg(frame, intel_crtc->pipe);
286 unsigned int i, len = DIP_HEADER_SIZE + frame->len;
287 u32 val = I915_READ(ctl_reg);
288
289 if (data_reg == 0)
290 return;
291
292 intel_wait_for_vblank(dev, intel_crtc->pipe);
293
294 val &= ~hsw_infoframe_enable(frame);
295 I915_WRITE(ctl_reg, val);
296
297 for (i = 0; i < len; i += 4) {
298 I915_WRITE(data_reg + i, *data);
299 data++;
300 }
301
302 val |= hsw_infoframe_enable(frame);
303 I915_WRITE(ctl_reg, val);
304}
305
306static void intel_set_infoframe(struct drm_encoder *encoder,
307 struct dip_infoframe *frame)
308{
309 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
310
311 if (!intel_hdmi->has_hdmi_sink)
312 return;
313
314 intel_dip_infoframe_csum(frame);
315 intel_hdmi->write_infoframe(encoder, frame);
316}
317
318void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
319 struct drm_display_mode *adjusted_mode)
320{
321 struct dip_infoframe avi_if = {
322 .type = DIP_TYPE_AVI,
323 .ver = DIP_VERSION_AVI,
324 .len = DIP_LEN_AVI,
325 };
326
327 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
328 avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2;
329
330 intel_set_infoframe(encoder, &avi_if);
331}
332
333void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
334{
335 struct dip_infoframe spd_if;
336
337 memset(&spd_if, 0, sizeof(spd_if));
338 spd_if.type = DIP_TYPE_SPD;
339 spd_if.ver = DIP_VERSION_SPD;
340 spd_if.len = DIP_LEN_SPD;
341 strcpy(spd_if.body.spd.vn, "Intel");
342 strcpy(spd_if.body.spd.pd, "Integrated gfx");
343 spd_if.body.spd.sdi = DIP_SPD_PC;
344
345 intel_set_infoframe(encoder, &spd_if);
346}
347
348static void intel_hdmi_mode_set(struct drm_encoder *encoder,
349 struct drm_display_mode *mode,
350 struct drm_display_mode *adjusted_mode)
351{
352 struct drm_device *dev = encoder->dev;
353 struct drm_i915_private *dev_priv = dev->dev_private;
354 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
355 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
356 u32 sdvox;
357
358 sdvox = SDVO_ENCODING_HDMI | SDVO_BORDER_ENABLE;
359 if (!HAS_PCH_SPLIT(dev))
360 sdvox |= intel_hdmi->color_range;
361 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
362 sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
363 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
364 sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
365
366 if (intel_crtc->bpp > 24)
367 sdvox |= COLOR_FORMAT_12bpc;
368 else
369 sdvox |= COLOR_FORMAT_8bpc;
370
371 /* Required on CPT */
372 if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev))
373 sdvox |= HDMI_MODE_SELECT;
374
375 if (intel_hdmi->has_audio) {
376 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
377 pipe_name(intel_crtc->pipe));
378 sdvox |= SDVO_AUDIO_ENABLE;
379 sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC;
380 intel_write_eld(encoder, adjusted_mode);
381 }
382
383 if (HAS_PCH_CPT(dev))
384 sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe);
385 else if (intel_crtc->pipe == 1)
386 sdvox |= SDVO_PIPE_B_SELECT;
387
388 I915_WRITE(intel_hdmi->sdvox_reg, sdvox);
389 POSTING_READ(intel_hdmi->sdvox_reg);
390
391 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
392 intel_hdmi_set_spd_infoframe(encoder);
393}
394
395static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode)
396{
397 struct drm_device *dev = encoder->dev;
398 struct drm_i915_private *dev_priv = dev->dev_private;
399 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
400 u32 temp;
401 u32 enable_bits = SDVO_ENABLE;
402
403 if (intel_hdmi->has_audio || mode != DRM_MODE_DPMS_ON)
404 enable_bits |= SDVO_AUDIO_ENABLE;
405
406 temp = I915_READ(intel_hdmi->sdvox_reg);
407
408 /* HW workaround, need to toggle enable bit off and on for 12bpc, but
409 * we do this anyway which shows more stable in testing.
410 */
411 if (HAS_PCH_SPLIT(dev)) {
412 I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE);
413 POSTING_READ(intel_hdmi->sdvox_reg);
414 }
415
416 if (mode != DRM_MODE_DPMS_ON) {
417 temp &= ~enable_bits;
418 } else {
419 temp |= enable_bits;
420 }
421
422 I915_WRITE(intel_hdmi->sdvox_reg, temp);
423 POSTING_READ(intel_hdmi->sdvox_reg);
424
425 /* HW workaround, need to write this twice for issue that may result
426 * in first write getting masked.
427 */
428 if (HAS_PCH_SPLIT(dev)) {
429 I915_WRITE(intel_hdmi->sdvox_reg, temp);
430 POSTING_READ(intel_hdmi->sdvox_reg);
431 }
432}
433
434static int intel_hdmi_mode_valid(struct drm_connector *connector,
435 struct drm_display_mode *mode)
436{
437 if (mode->clock > 165000)
438 return MODE_CLOCK_HIGH;
439 if (mode->clock < 20000)
440 return MODE_CLOCK_LOW;
441
442 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
443 return MODE_NO_DBLESCAN;
444
445 return MODE_OK;
446}
447
448static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder,
449 struct drm_display_mode *mode,
450 struct drm_display_mode *adjusted_mode)
451{
452 return true;
453}
454
455static enum drm_connector_status
456intel_hdmi_detect(struct drm_connector *connector, bool force)
457{
458 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
459 struct drm_i915_private *dev_priv = connector->dev->dev_private;
460 struct edid *edid;
461 enum drm_connector_status status = connector_status_disconnected;
462
463 intel_hdmi->has_hdmi_sink = false;
464 intel_hdmi->has_audio = false;
465 edid = drm_get_edid(connector,
466 intel_gmbus_get_adapter(dev_priv,
467 intel_hdmi->ddc_bus));
468
469 if (edid) {
470 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
471 status = connector_status_connected;
472 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
473 intel_hdmi->has_hdmi_sink =
474 drm_detect_hdmi_monitor(edid);
475 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
476 }
477 connector->display_info.raw_edid = NULL;
478 kfree(edid);
479 }
480
481 if (status == connector_status_connected) {
482 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
483 intel_hdmi->has_audio =
484 (intel_hdmi->force_audio == HDMI_AUDIO_ON);
485 }
486
487 return status;
488}
489
490static int intel_hdmi_get_modes(struct drm_connector *connector)
491{
492 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
493 struct drm_i915_private *dev_priv = connector->dev->dev_private;
494
495 /* We should parse the EDID data and find out if it's an HDMI sink so
496 * we can send audio to it.
497 */
498
499 return intel_ddc_get_modes(connector,
500 intel_gmbus_get_adapter(dev_priv,
501 intel_hdmi->ddc_bus));
502}
503
504static bool
505intel_hdmi_detect_audio(struct drm_connector *connector)
506{
507 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
508 struct drm_i915_private *dev_priv = connector->dev->dev_private;
509 struct edid *edid;
510 bool has_audio = false;
511
512 edid = drm_get_edid(connector,
513 intel_gmbus_get_adapter(dev_priv,
514 intel_hdmi->ddc_bus));
515 if (edid) {
516 if (edid->input & DRM_EDID_INPUT_DIGITAL)
517 has_audio = drm_detect_monitor_audio(edid);
518
519 connector->display_info.raw_edid = NULL;
520 kfree(edid);
521 }
522
523 return has_audio;
524}
525
526static int
527intel_hdmi_set_property(struct drm_connector *connector,
528 struct drm_property *property,
529 uint64_t val)
530{
531 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
532 struct drm_i915_private *dev_priv = connector->dev->dev_private;
533 int ret;
534
535 ret = drm_connector_property_set_value(connector, property, val);
536 if (ret)
537 return ret;
538
539 if (property == dev_priv->force_audio_property) {
540 enum hdmi_force_audio i = val;
541 bool has_audio;
542
543 if (i == intel_hdmi->force_audio)
544 return 0;
545
546 intel_hdmi->force_audio = i;
547
548 if (i == HDMI_AUDIO_AUTO)
549 has_audio = intel_hdmi_detect_audio(connector);
550 else
551 has_audio = (i == HDMI_AUDIO_ON);
552
553 if (i == HDMI_AUDIO_OFF_DVI)
554 intel_hdmi->has_hdmi_sink = 0;
555
556 intel_hdmi->has_audio = has_audio;
557 goto done;
558 }
559
560 if (property == dev_priv->broadcast_rgb_property) {
561 if (val == !!intel_hdmi->color_range)
562 return 0;
563
564 intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
565 goto done;
566 }
567
568 return -EINVAL;
569
570done:
571 if (intel_hdmi->base.base.crtc) {
572 struct drm_crtc *crtc = intel_hdmi->base.base.crtc;
573 drm_crtc_helper_set_mode(crtc, &crtc->mode,
574 crtc->x, crtc->y,
575 crtc->fb);
576 }
577
578 return 0;
579}
580
581static void intel_hdmi_destroy(struct drm_connector *connector)
582{
583 drm_sysfs_connector_remove(connector);
584 drm_connector_cleanup(connector);
585 kfree(connector);
586}
587
588static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs_hsw = {
589 .dpms = intel_ddi_dpms,
590 .mode_fixup = intel_hdmi_mode_fixup,
591 .prepare = intel_encoder_prepare,
592 .mode_set = intel_ddi_mode_set,
593 .commit = intel_encoder_commit,
594};
595
596static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = {
597 .dpms = intel_hdmi_dpms,
598 .mode_fixup = intel_hdmi_mode_fixup,
599 .prepare = intel_encoder_prepare,
600 .mode_set = intel_hdmi_mode_set,
601 .commit = intel_encoder_commit,
602};
603
604static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
605 .dpms = drm_helper_connector_dpms,
606 .detect = intel_hdmi_detect,
607 .fill_modes = drm_helper_probe_single_connector_modes,
608 .set_property = intel_hdmi_set_property,
609 .destroy = intel_hdmi_destroy,
610};
611
612static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
613 .get_modes = intel_hdmi_get_modes,
614 .mode_valid = intel_hdmi_mode_valid,
615 .best_encoder = intel_best_encoder,
616};
617
618static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
619 .destroy = intel_encoder_destroy,
620};
621
622static void
623intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
624{
625 intel_attach_force_audio_property(connector);
626 intel_attach_broadcast_rgb_property(connector);
627}
628
629void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
630{
631 struct drm_i915_private *dev_priv = dev->dev_private;
632 struct drm_connector *connector;
633 struct intel_encoder *intel_encoder;
634 struct intel_connector *intel_connector;
635 struct intel_hdmi *intel_hdmi;
636 int i;
637
638 intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL);
639 if (!intel_hdmi)
640 return;
641
642 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
643 if (!intel_connector) {
644 kfree(intel_hdmi);
645 return;
646 }
647
648 intel_encoder = &intel_hdmi->base;
649 drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
650 DRM_MODE_ENCODER_TMDS);
651
652 connector = &intel_connector->base;
653 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
654 DRM_MODE_CONNECTOR_HDMIA);
655 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
656
657 intel_encoder->type = INTEL_OUTPUT_HDMI;
658
659 connector->polled = DRM_CONNECTOR_POLL_HPD;
660 connector->interlace_allowed = 1;
661 connector->doublescan_allowed = 0;
662 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
663
664 /* Set up the DDC bus. */
665 if (sdvox_reg == SDVOB) {
666 intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT);
667 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
668 dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
669 } else if (sdvox_reg == SDVOC) {
670 intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT);
671 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
672 dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
673 } else if (sdvox_reg == HDMIB) {
674 intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT);
675 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
676 dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
677 } else if (sdvox_reg == HDMIC) {
678 intel_encoder->clone_mask = (1 << INTEL_HDMIE_CLONE_BIT);
679 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
680 dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
681 } else if (sdvox_reg == HDMID) {
682 intel_encoder->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT);
683 intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
684 dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
685 } else if (sdvox_reg == DDI_BUF_CTL(PORT_B)) {
686 DRM_DEBUG_DRIVER("LPT: detected output on DDI B\n");
687 intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT);
688 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
689 intel_hdmi->ddi_port = PORT_B;
690 dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
691 } else if (sdvox_reg == DDI_BUF_CTL(PORT_C)) {
692 DRM_DEBUG_DRIVER("LPT: detected output on DDI C\n");
693 intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT);
694 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
695 intel_hdmi->ddi_port = PORT_C;
696 dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
697 } else if (sdvox_reg == DDI_BUF_CTL(PORT_D)) {
698 DRM_DEBUG_DRIVER("LPT: detected output on DDI D\n");
699 intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT);
700 intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
701 intel_hdmi->ddi_port = PORT_D;
702 dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
703 } else {
704 /* If we got an unknown sdvox_reg, things are pretty much broken
705 * in a way that we should let the kernel know about it */
706 BUG();
707 }
708
709 intel_hdmi->sdvox_reg = sdvox_reg;
710
711 if (!HAS_PCH_SPLIT(dev)) {
712 intel_hdmi->write_infoframe = g4x_write_infoframe;
713 I915_WRITE(VIDEO_DIP_CTL, 0);
714 } else if (IS_VALLEYVIEW(dev)) {
715 intel_hdmi->write_infoframe = vlv_write_infoframe;
716 for_each_pipe(i)
717 I915_WRITE(VLV_TVIDEO_DIP_CTL(i), 0);
718 } else if (IS_HASWELL(dev)) {
719 /* FIXME: Haswell has a new set of DIP frame registers, but we are
720 * just doing the minimal required for HDMI to work at this stage.
721 */
722 intel_hdmi->write_infoframe = hsw_write_infoframe;
723 for_each_pipe(i)
724 I915_WRITE(HSW_TVIDEO_DIP_CTL(i), 0);
725 } else if (HAS_PCH_IBX(dev)) {
726 intel_hdmi->write_infoframe = ibx_write_infoframe;
727 for_each_pipe(i)
728 I915_WRITE(TVIDEO_DIP_CTL(i), 0);
729 } else {
730 intel_hdmi->write_infoframe = cpt_write_infoframe;
731 for_each_pipe(i)
732 I915_WRITE(TVIDEO_DIP_CTL(i), 0);
733 }
734
735 if (IS_HASWELL(dev))
736 drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs_hsw);
737 else
738 drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs);
739
740 intel_hdmi_add_properties(intel_hdmi, connector);
741
742 intel_connector_attach_encoder(intel_connector, intel_encoder);
743 drm_sysfs_connector_add(connector);
744
745 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
746 * 0xd. Failure to do so will result in spurious interrupts being
747 * generated on the port when a cable is not attached.
748 */
749 if (IS_G4X(dev) && !IS_GM45(dev)) {
750 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
751 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
752 }
753}