1/*
  2 * GPIOs on MPC512x/8349/8572/8610 and compatible
  3 *
  4 * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
  5 *
  6 * This file is licensed under the terms of the GNU General Public License
  7 * version 2.  This program is licensed "as is" without any warranty of any
  8 * kind, whether express or implied.
  9 */
 10
 11#include <linux/kernel.h>
 12#include <linux/init.h>
 13#include <linux/spinlock.h>
 14#include <linux/io.h>
 15#include <linux/of.h>
 16#include <linux/of_gpio.h>
 17#include <linux/gpio.h>
 18#include <linux/slab.h>
 19#include <linux/irq.h>
 20
 21#define MPC8XXX_GPIO_PINS	32
 22
 23#define GPIO_DIR		0x00
 24#define GPIO_ODR		0x04
 25#define GPIO_DAT		0x08
 26#define GPIO_IER		0x0c
 27#define GPIO_IMR		0x10
 28#define GPIO_ICR		0x14
 29#define GPIO_ICR2		0x18
 30
 31struct mpc8xxx_gpio_chip {
 32	struct of_mm_gpio_chip mm_gc;
 33	spinlock_t lock;
 34
 35	/*
 36	 * shadowed data register to be able to clear/set output pins in
 37	 * open drain mode safely
 38	 */
 39	u32 data;
 40	struct irq_domain *irq;
 41	void *of_dev_id_data;
 42};
 43
 44static inline u32 mpc8xxx_gpio2mask(unsigned int gpio)
 45{
 46	return 1u << (MPC8XXX_GPIO_PINS - 1 - gpio);
 47}
 48
 49static inline struct mpc8xxx_gpio_chip *
 50to_mpc8xxx_gpio_chip(struct of_mm_gpio_chip *mm)
 51{
 52	return container_of(mm, struct mpc8xxx_gpio_chip, mm_gc);
 53}
 54
 55static void mpc8xxx_gpio_save_regs(struct of_mm_gpio_chip *mm)
 56{
 57	struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
 58
 59	mpc8xxx_gc->data = in_be32(mm->regs + GPIO_DAT);
 60}
 61
 62/* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
 63 * defined as output cannot be determined by reading GPDAT register,
 64 * so we use shadow data register instead. The status of input pins
 65 * is determined by reading GPDAT register.
 66 */
 67static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
 68{
 69	u32 val;
 70	struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
 71	struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
 72
 73	val = in_be32(mm->regs + GPIO_DAT) & ~in_be32(mm->regs + GPIO_DIR);
 74
 75	return (val | mpc8xxx_gc->data) & mpc8xxx_gpio2mask(gpio);
 76}
 77
 78static int mpc8xxx_gpio_get(struct gpio_chip *gc, unsigned int gpio)
 79{
 80	struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
 81
 82	return in_be32(mm->regs + GPIO_DAT) & mpc8xxx_gpio2mask(gpio);
 83}
 84
 85static void mpc8xxx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
 86{
 87	struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
 88	struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
 89	unsigned long flags;
 90
 91	spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
 92
 93	if (val)
 94		mpc8xxx_gc->data |= mpc8xxx_gpio2mask(gpio);
 95	else
 96		mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(gpio);
 97
 98	out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data);
 99
100	spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
101}
102
103static int mpc8xxx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
104{
105	struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
106	struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
107	unsigned long flags;
108
109	spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
110
111	clrbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
112
113	spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
114
115	return 0;
116}
117
118static int mpc8xxx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
119{
120	struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
121	struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
122	unsigned long flags;
123
124	mpc8xxx_gpio_set(gc, gpio, val);
125
126	spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
127
128	setbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
129
130	spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
131
132	return 0;
133}
134
135static int mpc5121_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
136{
137	/* GPIO 28..31 are input only on MPC5121 */
138	if (gpio >= 28)
139		return -EINVAL;
140
141	return mpc8xxx_gpio_dir_out(gc, gpio, val);
142}
143
144static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
145{
146	struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
147	struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
148
149	if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
150		return irq_create_mapping(mpc8xxx_gc->irq, offset);
151	else
152		return -ENXIO;
153}
154
155static void mpc8xxx_gpio_irq_cascade(unsigned int irq, struct irq_desc *desc)
156{
157	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc);
158	struct irq_chip *chip = irq_desc_get_chip(desc);
159	struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
160	unsigned int mask;
161
162	mask = in_be32(mm->regs + GPIO_IER) & in_be32(mm->regs + GPIO_IMR);
163	if (mask)
164		generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq,
165						     32 - ffs(mask)));
166	if (chip->irq_eoi)
167		chip->irq_eoi(&desc->irq_data);
168}
169
170static void mpc8xxx_irq_unmask(struct irq_data *d)
171{
172	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
173	struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
174	unsigned long flags;
175
176	spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
177
178	setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
179
180	spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
181}
182
183static void mpc8xxx_irq_mask(struct irq_data *d)
184{
185	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
186	struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
187	unsigned long flags;
188
189	spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
190
191	clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
192
193	spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
194}
195
196static void mpc8xxx_irq_ack(struct irq_data *d)
197{
198	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
199	struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
200
201	out_be32(mm->regs + GPIO_IER, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
202}
203
204static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
205{
206	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
207	struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
208	unsigned long flags;
209
210	switch (flow_type) {
211	case IRQ_TYPE_EDGE_FALLING:
212		spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
213		setbits32(mm->regs + GPIO_ICR,
214			  mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
215		spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
216		break;
217
218	case IRQ_TYPE_EDGE_BOTH:
219		spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
220		clrbits32(mm->regs + GPIO_ICR,
221			  mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
222		spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
223		break;
224
225	default:
226		return -EINVAL;
227	}
228
229	return 0;
230}
231
232static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
233{
234	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
235	struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
236	unsigned long gpio = irqd_to_hwirq(d);
237	void __iomem *reg;
238	unsigned int shift;
239	unsigned long flags;
240
241	if (gpio < 16) {
242		reg = mm->regs + GPIO_ICR;
243		shift = (15 - gpio) * 2;
244	} else {
245		reg = mm->regs + GPIO_ICR2;
246		shift = (15 - (gpio % 16)) * 2;
247	}
248
249	switch (flow_type) {
250	case IRQ_TYPE_EDGE_FALLING:
251	case IRQ_TYPE_LEVEL_LOW:
252		spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
253		clrsetbits_be32(reg, 3 << shift, 2 << shift);
254		spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
255		break;
256
257	case IRQ_TYPE_EDGE_RISING:
258	case IRQ_TYPE_LEVEL_HIGH:
259		spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
260		clrsetbits_be32(reg, 3 << shift, 1 << shift);
261		spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
262		break;
263
264	case IRQ_TYPE_EDGE_BOTH:
265		spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
266		clrbits32(reg, 3 << shift);
267		spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
268		break;
269
270	default:
271		return -EINVAL;
272	}
273
274	return 0;
275}
276
277static struct irq_chip mpc8xxx_irq_chip = {
278	.name		= "mpc8xxx-gpio",
279	.irq_unmask	= mpc8xxx_irq_unmask,
280	.irq_mask	= mpc8xxx_irq_mask,
281	.irq_ack	= mpc8xxx_irq_ack,
282	.irq_set_type	= mpc8xxx_irq_set_type,
283};
284
285static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int virq,
286				irq_hw_number_t hw)
287{
288	struct mpc8xxx_gpio_chip *mpc8xxx_gc = h->host_data;
289
290	if (mpc8xxx_gc->of_dev_id_data)
291		mpc8xxx_irq_chip.irq_set_type = mpc8xxx_gc->of_dev_id_data;
292
293	irq_set_chip_data(virq, h->host_data);
294	irq_set_chip_and_handler(virq, &mpc8xxx_irq_chip, handle_level_irq);
295	irq_set_irq_type(virq, IRQ_TYPE_NONE);
296
297	return 0;
298}
299
300static struct irq_domain_ops mpc8xxx_gpio_irq_ops = {
301	.map	= mpc8xxx_gpio_irq_map,
302	.xlate	= irq_domain_xlate_twocell,
303};
304
305static struct of_device_id mpc8xxx_gpio_ids[] __initdata = {
306	{ .compatible = "fsl,mpc8349-gpio", },
307	{ .compatible = "fsl,mpc8572-gpio", },
308	{ .compatible = "fsl,mpc8610-gpio", },
309	{ .compatible = "fsl,mpc5121-gpio", .data = mpc512x_irq_set_type, },
310	{ .compatible = "fsl,pq3-gpio",     },
311	{ .compatible = "fsl,qoriq-gpio",   },
312	{}
313};
314
315static void __init mpc8xxx_add_controller(struct device_node *np)
316{
317	struct mpc8xxx_gpio_chip *mpc8xxx_gc;
318	struct of_mm_gpio_chip *mm_gc;
319	struct gpio_chip *gc;
320	const struct of_device_id *id;
321	unsigned hwirq;
322	int ret;
323
324	mpc8xxx_gc = kzalloc(sizeof(*mpc8xxx_gc), GFP_KERNEL);
325	if (!mpc8xxx_gc) {
326		ret = -ENOMEM;
327		goto err;
328	}
329
330	spin_lock_init(&mpc8xxx_gc->lock);
331
332	mm_gc = &mpc8xxx_gc->mm_gc;
333	gc = &mm_gc->gc;
334
335	mm_gc->save_regs = mpc8xxx_gpio_save_regs;
336	gc->ngpio = MPC8XXX_GPIO_PINS;
337	gc->direction_input = mpc8xxx_gpio_dir_in;
338	gc->direction_output = of_device_is_compatible(np, "fsl,mpc5121-gpio") ?
339		mpc5121_gpio_dir_out : mpc8xxx_gpio_dir_out;
340	gc->get = of_device_is_compatible(np, "fsl,mpc8572-gpio") ?
341		mpc8572_gpio_get : mpc8xxx_gpio_get;
342	gc->set = mpc8xxx_gpio_set;
343	gc->to_irq = mpc8xxx_gpio_to_irq;
344
345	ret = of_mm_gpiochip_add(np, mm_gc);
346	if (ret)
347		goto err;
348
349	hwirq = irq_of_parse_and_map(np, 0);
350	if (hwirq == NO_IRQ)
351		goto skip_irq;
352
353	mpc8xxx_gc->irq = irq_domain_add_linear(np, MPC8XXX_GPIO_PINS,
354					&mpc8xxx_gpio_irq_ops, mpc8xxx_gc);
355	if (!mpc8xxx_gc->irq)
356		goto skip_irq;
357
358	id = of_match_node(mpc8xxx_gpio_ids, np);
359	if (id)
360		mpc8xxx_gc->of_dev_id_data = id->data;
361
362	/* ack and mask all irqs */
363	out_be32(mm_gc->regs + GPIO_IER, 0xffffffff);
364	out_be32(mm_gc->regs + GPIO_IMR, 0);
365
366	irq_set_handler_data(hwirq, mpc8xxx_gc);
367	irq_set_chained_handler(hwirq, mpc8xxx_gpio_irq_cascade);
368
369skip_irq:
370	return;
371
372err:
373	pr_err("%s: registration failed with status %d\n",
374	       np->full_name, ret);
375	kfree(mpc8xxx_gc);
376
377	return;
378}
379
380static int __init mpc8xxx_add_gpiochips(void)
381{
382	struct device_node *np;
383
384	for_each_matching_node(np, mpc8xxx_gpio_ids)
385		mpc8xxx_add_controller(np);
386
387	return 0;
388}
389arch_initcall(mpc8xxx_add_gpiochips);