1/*
   2 *	Local APIC handling, local APIC timers
   3 *
   4 *	(c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
   5 *
   6 *	Fixes
   7 *	Maciej W. Rozycki	:	Bits for genuine 82489DX APICs;
   8 *					thanks to Eric Gilmore
   9 *					and Rolf G. Tews
  10 *					for testing these extensively.
  11 *	Maciej W. Rozycki	:	Various updates and fixes.
  12 *	Mikael Pettersson	:	Power Management for UP-APIC.
  13 *	Pavel Machek and
  14 *	Mikael Pettersson	:	PM converted to driver model.
  15 */
  16
  17#include <linux/perf_event.h>
  18#include <linux/kernel_stat.h>
  19#include <linux/mc146818rtc.h>
  20#include <linux/acpi_pmtmr.h>
  21#include <linux/clockchips.h>
  22#include <linux/interrupt.h>
  23#include <linux/bootmem.h>
  24#include <linux/ftrace.h>
  25#include <linux/ioport.h>
  26#include <linux/module.h>
  27#include <linux/syscore_ops.h>
  28#include <linux/delay.h>
  29#include <linux/timex.h>
  30#include <linux/i8253.h>
  31#include <linux/dmar.h>
  32#include <linux/init.h>
  33#include <linux/cpu.h>
  34#include <linux/dmi.h>
  35#include <linux/smp.h>
  36#include <linux/mm.h>
  37
 
  38#include <asm/perf_event.h>
  39#include <asm/x86_init.h>
  40#include <asm/pgalloc.h>
  41#include <linux/atomic.h>
  42#include <asm/mpspec.h>
  43#include <asm/i8259.h>
  44#include <asm/proto.h>
  45#include <asm/apic.h>
  46#include <asm/io_apic.h>
  47#include <asm/desc.h>
  48#include <asm/hpet.h>
  49#include <asm/idle.h>
  50#include <asm/mtrr.h>
  51#include <asm/time.h>
  52#include <asm/smp.h>
  53#include <asm/mce.h>
  54#include <asm/tsc.h>
  55#include <asm/hypervisor.h>
  56
  57unsigned int num_processors;
  58
  59unsigned disabled_cpus __cpuinitdata;
  60
  61/* Processor that is doing the boot up */
  62unsigned int boot_cpu_physical_apicid = -1U;
  63
  64/*
  65 * The highest APIC ID seen during enumeration.
  66 */
  67unsigned int max_physical_apicid;
  68
  69/*
  70 * Bitmask of physically existing CPUs:
  71 */
  72physid_mask_t phys_cpu_present_map;
  73
  74/*
  75 * Map cpu index to physical APIC ID
  76 */
  77DEFINE_EARLY_PER_CPU(u16, x86_cpu_to_apicid, BAD_APICID);
  78DEFINE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid, BAD_APICID);
  79EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
  80EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
  81
  82#ifdef CONFIG_X86_32
  83
  84/*
  85 * On x86_32, the mapping between cpu and logical apicid may vary
  86 * depending on apic in use.  The following early percpu variable is
  87 * used for the mapping.  This is where the behaviors of x86_64 and 32
  88 * actually diverge.  Let's keep it ugly for now.
  89 */
  90DEFINE_EARLY_PER_CPU(int, x86_cpu_to_logical_apicid, BAD_APICID);
  91
  92/*
  93 * Knob to control our willingness to enable the local APIC.
  94 *
  95 * +1=force-enable
  96 */
  97static int force_enable_local_apic __initdata;
  98/*
  99 * APIC command line parameters
 100 */
 101static int __init parse_lapic(char *arg)
 102{
 103	force_enable_local_apic = 1;
 104	return 0;
 105}
 106early_param("lapic", parse_lapic);
 107/* Local APIC was disabled by the BIOS and enabled by the kernel */
 108static int enabled_via_apicbase;
 109
 110/*
 111 * Handle interrupt mode configuration register (IMCR).
 112 * This register controls whether the interrupt signals
 113 * that reach the BSP come from the master PIC or from the
 114 * local APIC. Before entering Symmetric I/O Mode, either
 115 * the BIOS or the operating system must switch out of
 116 * PIC Mode by changing the IMCR.
 117 */
 118static inline void imcr_pic_to_apic(void)
 119{
 120	/* select IMCR register */
 121	outb(0x70, 0x22);
 122	/* NMI and 8259 INTR go through APIC */
 123	outb(0x01, 0x23);
 124}
 125
 126static inline void imcr_apic_to_pic(void)
 127{
 128	/* select IMCR register */
 129	outb(0x70, 0x22);
 130	/* NMI and 8259 INTR go directly to BSP */
 131	outb(0x00, 0x23);
 132}
 133#endif
 134
 135#ifdef CONFIG_X86_64
 136static int apic_calibrate_pmtmr __initdata;
 137static __init int setup_apicpmtimer(char *s)
 138{
 139	apic_calibrate_pmtmr = 1;
 140	notsc_setup(NULL);
 141	return 0;
 142}
 143__setup("apicpmtimer", setup_apicpmtimer);
 144#endif
 145
 146int x2apic_mode;
 147#ifdef CONFIG_X86_X2APIC
 148/* x2apic enabled before OS handover */
 149static int x2apic_preenabled;
 
 
 150static __init int setup_nox2apic(char *str)
 151{
 152	if (x2apic_enabled()) {
 153		pr_warning("Bios already enabled x2apic, "
 154			   "can't enforce nox2apic");
 155		return 0;
 156	}
 
 
 
 
 
 
 
 
 
 157
 158	setup_clear_cpu_cap(X86_FEATURE_X2APIC);
 159	return 0;
 160}
 161early_param("nox2apic", setup_nox2apic);
 162#endif
 163
 164unsigned long mp_lapic_addr;
 165int disable_apic;
 166/* Disable local APIC timer from the kernel commandline or via dmi quirk */
 167static int disable_apic_timer __initdata;
 168/* Local APIC timer works in C2 */
 169int local_apic_timer_c2_ok;
 170EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
 171
 172int first_system_vector = 0xfe;
 173
 174/*
 175 * Debug level, exported for io_apic.c
 176 */
 177unsigned int apic_verbosity;
 178
 179int pic_mode;
 180
 181/* Have we found an MP table */
 182int smp_found_config;
 183
 184static struct resource lapic_resource = {
 185	.name = "Local APIC",
 186	.flags = IORESOURCE_MEM | IORESOURCE_BUSY,
 187};
 188
 189static unsigned int calibration_result;
 190
 191static void apic_pm_activate(void);
 192
 193static unsigned long apic_phys;
 194
 195/*
 196 * Get the LAPIC version
 197 */
 198static inline int lapic_get_version(void)
 199{
 200	return GET_APIC_VERSION(apic_read(APIC_LVR));
 201}
 202
 203/*
 204 * Check, if the APIC is integrated or a separate chip
 205 */
 206static inline int lapic_is_integrated(void)
 207{
 208#ifdef CONFIG_X86_64
 209	return 1;
 210#else
 211	return APIC_INTEGRATED(lapic_get_version());
 212#endif
 213}
 214
 215/*
 216 * Check, whether this is a modern or a first generation APIC
 217 */
 218static int modern_apic(void)
 219{
 220	/* AMD systems use old APIC versions, so check the CPU */
 221	if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
 222	    boot_cpu_data.x86 >= 0xf)
 223		return 1;
 224	return lapic_get_version() >= 0x14;
 225}
 226
 227/*
 228 * right after this call apic become NOOP driven
 229 * so apic->write/read doesn't do anything
 230 */
 231static void __init apic_disable(void)
 232{
 233	pr_info("APIC: switched to apic NOOP\n");
 234	apic = &apic_noop;
 235}
 236
 237void native_apic_wait_icr_idle(void)
 238{
 239	while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
 240		cpu_relax();
 241}
 242
 243u32 native_safe_apic_wait_icr_idle(void)
 244{
 245	u32 send_status;
 246	int timeout;
 247
 248	timeout = 0;
 249	do {
 250		send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
 251		if (!send_status)
 252			break;
 
 253		udelay(100);
 254	} while (timeout++ < 1000);
 255
 256	return send_status;
 257}
 258
 259void native_apic_icr_write(u32 low, u32 id)
 260{
 261	apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
 262	apic_write(APIC_ICR, low);
 263}
 264
 265u64 native_apic_icr_read(void)
 266{
 267	u32 icr1, icr2;
 268
 269	icr2 = apic_read(APIC_ICR2);
 270	icr1 = apic_read(APIC_ICR);
 271
 272	return icr1 | ((u64)icr2 << 32);
 273}
 274
 275#ifdef CONFIG_X86_32
 276/**
 277 * get_physical_broadcast - Get number of physical broadcast IDs
 278 */
 279int get_physical_broadcast(void)
 280{
 281	return modern_apic() ? 0xff : 0xf;
 282}
 283#endif
 284
 285/**
 286 * lapic_get_maxlvt - get the maximum number of local vector table entries
 287 */
 288int lapic_get_maxlvt(void)
 289{
 290	unsigned int v;
 291
 292	v = apic_read(APIC_LVR);
 293	/*
 294	 * - we always have APIC integrated on 64bit mode
 295	 * - 82489DXs do not report # of LVT entries
 296	 */
 297	return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
 298}
 299
 300/*
 301 * Local APIC timer
 302 */
 303
 304/* Clock divisor */
 305#define APIC_DIVISOR 16
 306
 307/*
 308 * This function sets up the local APIC timer, with a timeout of
 309 * 'clocks' APIC bus clock. During calibration we actually call
 310 * this function twice on the boot CPU, once with a bogus timeout
 311 * value, second time for real. The other (noncalibrating) CPUs
 312 * call this function only once, with the real, calibrated value.
 313 *
 314 * We do reads before writes even if unnecessary, to get around the
 315 * P5 APIC double write bug.
 316 */
 317static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
 318{
 319	unsigned int lvtt_value, tmp_value;
 320
 321	lvtt_value = LOCAL_TIMER_VECTOR;
 322	if (!oneshot)
 323		lvtt_value |= APIC_LVT_TIMER_PERIODIC;
 324	if (!lapic_is_integrated())
 325		lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
 326
 327	if (!irqen)
 328		lvtt_value |= APIC_LVT_MASKED;
 329
 330	apic_write(APIC_LVTT, lvtt_value);
 331
 332	/*
 333	 * Divide PICLK by 16
 334	 */
 335	tmp_value = apic_read(APIC_TDCR);
 336	apic_write(APIC_TDCR,
 337		(tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
 338		APIC_TDR_DIV_16);
 339
 340	if (!oneshot)
 341		apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
 342}
 343
 344/*
 345 * Setup extended LVT, AMD specific
 346 *
 347 * Software should use the LVT offsets the BIOS provides.  The offsets
 348 * are determined by the subsystems using it like those for MCE
 349 * threshold or IBS.  On K8 only offset 0 (APIC500) and MCE interrupts
 350 * are supported. Beginning with family 10h at least 4 offsets are
 351 * available.
 352 *
 353 * Since the offsets must be consistent for all cores, we keep track
 354 * of the LVT offsets in software and reserve the offset for the same
 355 * vector also to be used on other cores. An offset is freed by
 356 * setting the entry to APIC_EILVT_MASKED.
 357 *
 358 * If the BIOS is right, there should be no conflicts. Otherwise a
 359 * "[Firmware Bug]: ..." error message is generated. However, if
 360 * software does not properly determines the offsets, it is not
 361 * necessarily a BIOS bug.
 362 */
 363
 364static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX];
 365
 366static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new)
 367{
 368	return (old & APIC_EILVT_MASKED)
 369		|| (new == APIC_EILVT_MASKED)
 370		|| ((new & ~APIC_EILVT_MASKED) == old);
 371}
 372
 373static unsigned int reserve_eilvt_offset(int offset, unsigned int new)
 374{
 375	unsigned int rsvd;			/* 0: uninitialized */
 376
 377	if (offset >= APIC_EILVT_NR_MAX)
 378		return ~0;
 379
 380	rsvd = atomic_read(&eilvt_offsets[offset]) & ~APIC_EILVT_MASKED;
 381	do {
 382		if (rsvd &&
 383		    !eilvt_entry_is_changeable(rsvd, new))
 384			/* may not change if vectors are different */
 385			return rsvd;
 386		rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new);
 387	} while (rsvd != new);
 388
 
 
 
 
 
 389	return new;
 390}
 391
 392/*
 393 * If mask=1, the LVT entry does not generate interrupts while mask=0
 394 * enables the vector. See also the BKDGs. Must be called with
 395 * preemption disabled.
 396 */
 397
 398int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask)
 399{
 400	unsigned long reg = APIC_EILVTn(offset);
 401	unsigned int new, old, reserved;
 402
 403	new = (mask << 16) | (msg_type << 8) | vector;
 404	old = apic_read(reg);
 405	reserved = reserve_eilvt_offset(offset, new);
 406
 407	if (reserved != new) {
 408		pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
 409		       "vector 0x%x, but the register is already in use for "
 410		       "vector 0x%x on another cpu\n",
 411		       smp_processor_id(), reg, offset, new, reserved);
 412		return -EINVAL;
 413	}
 414
 415	if (!eilvt_entry_is_changeable(old, new)) {
 416		pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
 417		       "vector 0x%x, but the register is already in use for "
 418		       "vector 0x%x on this cpu\n",
 419		       smp_processor_id(), reg, offset, new, old);
 420		return -EBUSY;
 421	}
 422
 423	apic_write(reg, new);
 424
 425	return 0;
 426}
 427EXPORT_SYMBOL_GPL(setup_APIC_eilvt);
 428
 429/*
 430 * Program the next event, relative to now
 431 */
 432static int lapic_next_event(unsigned long delta,
 433			    struct clock_event_device *evt)
 434{
 435	apic_write(APIC_TMICT, delta);
 436	return 0;
 437}
 438
 439/*
 440 * Setup the lapic timer in periodic or oneshot mode
 441 */
 442static void lapic_timer_setup(enum clock_event_mode mode,
 443			      struct clock_event_device *evt)
 444{
 445	unsigned long flags;
 446	unsigned int v;
 447
 448	/* Lapic used as dummy for broadcast ? */
 449	if (evt->features & CLOCK_EVT_FEAT_DUMMY)
 450		return;
 451
 452	local_irq_save(flags);
 453
 454	switch (mode) {
 455	case CLOCK_EVT_MODE_PERIODIC:
 456	case CLOCK_EVT_MODE_ONESHOT:
 457		__setup_APIC_LVTT(calibration_result,
 458				  mode != CLOCK_EVT_MODE_PERIODIC, 1);
 459		break;
 460	case CLOCK_EVT_MODE_UNUSED:
 461	case CLOCK_EVT_MODE_SHUTDOWN:
 462		v = apic_read(APIC_LVTT);
 463		v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
 464		apic_write(APIC_LVTT, v);
 465		apic_write(APIC_TMICT, 0);
 466		break;
 467	case CLOCK_EVT_MODE_RESUME:
 468		/* Nothing to do here */
 469		break;
 470	}
 471
 472	local_irq_restore(flags);
 473}
 474
 475/*
 476 * Local APIC timer broadcast function
 477 */
 478static void lapic_timer_broadcast(const struct cpumask *mask)
 479{
 480#ifdef CONFIG_SMP
 481	apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
 482#endif
 483}
 484
 485
 486/*
 487 * The local apic timer can be used for any function which is CPU local.
 488 */
 489static struct clock_event_device lapic_clockevent = {
 490	.name		= "lapic",
 491	.features	= CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
 492			| CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
 493	.shift		= 32,
 494	.set_mode	= lapic_timer_setup,
 495	.set_next_event	= lapic_next_event,
 496	.broadcast	= lapic_timer_broadcast,
 497	.rating		= 100,
 498	.irq		= -1,
 499};
 500static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
 501
 502/*
 503 * Setup the local APIC timer for this CPU. Copy the initialized values
 504 * of the boot CPU and register the clock event in the framework.
 505 */
 506static void __cpuinit setup_APIC_timer(void)
 507{
 508	struct clock_event_device *levt = &__get_cpu_var(lapic_events);
 509
 510	if (this_cpu_has(X86_FEATURE_ARAT)) {
 511		lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP;
 512		/* Make LAPIC timer preferrable over percpu HPET */
 513		lapic_clockevent.rating = 150;
 514	}
 515
 516	memcpy(levt, &lapic_clockevent, sizeof(*levt));
 517	levt->cpumask = cpumask_of(smp_processor_id());
 518
 519	clockevents_register_device(levt);
 520}
 521
 522/*
 523 * In this functions we calibrate APIC bus clocks to the external timer.
 524 *
 525 * We want to do the calibration only once since we want to have local timer
 526 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
 527 * frequency.
 528 *
 529 * This was previously done by reading the PIT/HPET and waiting for a wrap
 530 * around to find out, that a tick has elapsed. I have a box, where the PIT
 531 * readout is broken, so it never gets out of the wait loop again. This was
 532 * also reported by others.
 533 *
 534 * Monitoring the jiffies value is inaccurate and the clockevents
 535 * infrastructure allows us to do a simple substitution of the interrupt
 536 * handler.
 537 *
 538 * The calibration routine also uses the pm_timer when possible, as the PIT
 539 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
 540 * back to normal later in the boot process).
 541 */
 542
 543#define LAPIC_CAL_LOOPS		(HZ/10)
 544
 545static __initdata int lapic_cal_loops = -1;
 546static __initdata long lapic_cal_t1, lapic_cal_t2;
 547static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
 548static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
 549static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
 550
 551/*
 552 * Temporary interrupt handler.
 553 */
 554static void __init lapic_cal_handler(struct clock_event_device *dev)
 555{
 556	unsigned long long tsc = 0;
 557	long tapic = apic_read(APIC_TMCCT);
 558	unsigned long pm = acpi_pm_read_early();
 559
 560	if (cpu_has_tsc)
 561		rdtscll(tsc);
 562
 563	switch (lapic_cal_loops++) {
 564	case 0:
 565		lapic_cal_t1 = tapic;
 566		lapic_cal_tsc1 = tsc;
 567		lapic_cal_pm1 = pm;
 568		lapic_cal_j1 = jiffies;
 569		break;
 570
 571	case LAPIC_CAL_LOOPS:
 572		lapic_cal_t2 = tapic;
 573		lapic_cal_tsc2 = tsc;
 574		if (pm < lapic_cal_pm1)
 575			pm += ACPI_PM_OVRRUN;
 576		lapic_cal_pm2 = pm;
 577		lapic_cal_j2 = jiffies;
 578		break;
 579	}
 580}
 581
 582static int __init
 583calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc)
 584{
 585	const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
 586	const long pm_thresh = pm_100ms / 100;
 587	unsigned long mult;
 588	u64 res;
 589
 590#ifndef CONFIG_X86_PM_TIMER
 591	return -1;
 592#endif
 593
 594	apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm);
 595
 596	/* Check, if the PM timer is available */
 597	if (!deltapm)
 598		return -1;
 599
 600	mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
 601
 602	if (deltapm > (pm_100ms - pm_thresh) &&
 603	    deltapm < (pm_100ms + pm_thresh)) {
 604		apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n");
 605		return 0;
 606	}
 607
 608	res = (((u64)deltapm) *  mult) >> 22;
 609	do_div(res, 1000000);
 610	pr_warning("APIC calibration not consistent "
 611		   "with PM-Timer: %ldms instead of 100ms\n",(long)res);
 612
 613	/* Correct the lapic counter value */
 614	res = (((u64)(*delta)) * pm_100ms);
 615	do_div(res, deltapm);
 616	pr_info("APIC delta adjusted to PM-Timer: "
 617		"%lu (%ld)\n", (unsigned long)res, *delta);
 618	*delta = (long)res;
 619
 620	/* Correct the tsc counter value */
 621	if (cpu_has_tsc) {
 622		res = (((u64)(*deltatsc)) * pm_100ms);
 623		do_div(res, deltapm);
 624		apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
 625					  "PM-Timer: %lu (%ld)\n",
 626					(unsigned long)res, *deltatsc);
 627		*deltatsc = (long)res;
 628	}
 629
 630	return 0;
 631}
 632
 633static int __init calibrate_APIC_clock(void)
 634{
 635	struct clock_event_device *levt = &__get_cpu_var(lapic_events);
 636	void (*real_handler)(struct clock_event_device *dev);
 637	unsigned long deltaj;
 638	long delta, deltatsc;
 639	int pm_referenced = 0;
 640
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 641	local_irq_disable();
 642
 643	/* Replace the global interrupt handler */
 644	real_handler = global_clock_event->event_handler;
 645	global_clock_event->event_handler = lapic_cal_handler;
 646
 647	/*
 648	 * Setup the APIC counter to maximum. There is no way the lapic
 649	 * can underflow in the 100ms detection time frame
 650	 */
 651	__setup_APIC_LVTT(0xffffffff, 0, 0);
 652
 653	/* Let the interrupts run */
 654	local_irq_enable();
 655
 656	while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
 657		cpu_relax();
 658
 659	local_irq_disable();
 660
 661	/* Restore the real event handler */
 662	global_clock_event->event_handler = real_handler;
 663
 664	/* Build delta t1-t2 as apic timer counts down */
 665	delta = lapic_cal_t1 - lapic_cal_t2;
 666	apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
 667
 668	deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
 669
 670	/* we trust the PM based calibration if possible */
 671	pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
 672					&delta, &deltatsc);
 673
 674	/* Calculate the scaled math multiplication factor */
 675	lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
 676				       lapic_clockevent.shift);
 677	lapic_clockevent.max_delta_ns =
 678		clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent);
 679	lapic_clockevent.min_delta_ns =
 680		clockevent_delta2ns(0xF, &lapic_clockevent);
 681
 682	calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
 683
 684	apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
 685	apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult);
 686	apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
 687		    calibration_result);
 688
 689	if (cpu_has_tsc) {
 690		apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
 691			    "%ld.%04ld MHz.\n",
 692			    (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ),
 693			    (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ));
 694	}
 695
 696	apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
 697		    "%u.%04u MHz.\n",
 698		    calibration_result / (1000000 / HZ),
 699		    calibration_result % (1000000 / HZ));
 700
 701	/*
 702	 * Do a sanity check on the APIC calibration result
 703	 */
 704	if (calibration_result < (1000000 / HZ)) {
 705		local_irq_enable();
 706		pr_warning("APIC frequency too slow, disabling apic timer\n");
 707		return -1;
 708	}
 709
 710	levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
 711
 712	/*
 713	 * PM timer calibration failed or not turned on
 714	 * so lets try APIC timer based calibration
 715	 */
 716	if (!pm_referenced) {
 717		apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
 718
 719		/*
 720		 * Setup the apic timer manually
 721		 */
 722		levt->event_handler = lapic_cal_handler;
 723		lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt);
 724		lapic_cal_loops = -1;
 725
 726		/* Let the interrupts run */
 727		local_irq_enable();
 728
 729		while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
 730			cpu_relax();
 731
 732		/* Stop the lapic timer */
 733		lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt);
 734
 735		/* Jiffies delta */
 736		deltaj = lapic_cal_j2 - lapic_cal_j1;
 737		apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
 738
 739		/* Check, if the jiffies result is consistent */
 740		if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
 741			apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
 742		else
 743			levt->features |= CLOCK_EVT_FEAT_DUMMY;
 744	} else
 745		local_irq_enable();
 746
 747	if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
 748		pr_warning("APIC timer disabled due to verification failure\n");
 749			return -1;
 750	}
 751
 752	return 0;
 753}
 754
 755/*
 756 * Setup the boot APIC
 757 *
 758 * Calibrate and verify the result.
 759 */
 760void __init setup_boot_APIC_clock(void)
 761{
 762	/*
 763	 * The local apic timer can be disabled via the kernel
 764	 * commandline or from the CPU detection code. Register the lapic
 765	 * timer as a dummy clock event source on SMP systems, so the
 766	 * broadcast mechanism is used. On UP systems simply ignore it.
 767	 */
 768	if (disable_apic_timer) {
 769		pr_info("Disabling APIC timer\n");
 770		/* No broadcast on UP ! */
 771		if (num_possible_cpus() > 1) {
 772			lapic_clockevent.mult = 1;
 773			setup_APIC_timer();
 774		}
 775		return;
 776	}
 777
 778	apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
 779		    "calibrating APIC timer ...\n");
 780
 781	if (calibrate_APIC_clock()) {
 782		/* No broadcast on UP ! */
 783		if (num_possible_cpus() > 1)
 784			setup_APIC_timer();
 785		return;
 786	}
 787
 788	/*
 789	 * If nmi_watchdog is set to IO_APIC, we need the
 790	 * PIT/HPET going.  Otherwise register lapic as a dummy
 791	 * device.
 792	 */
 793	lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
 794
 795	/* Setup the lapic or request the broadcast */
 796	setup_APIC_timer();
 797}
 798
 799void __cpuinit setup_secondary_APIC_clock(void)
 800{
 801	setup_APIC_timer();
 802}
 803
 804/*
 805 * The guts of the apic timer interrupt
 806 */
 807static void local_apic_timer_interrupt(void)
 808{
 809	int cpu = smp_processor_id();
 810	struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
 811
 812	/*
 813	 * Normally we should not be here till LAPIC has been initialized but
 814	 * in some cases like kdump, its possible that there is a pending LAPIC
 815	 * timer interrupt from previous kernel's context and is delivered in
 816	 * new kernel the moment interrupts are enabled.
 817	 *
 818	 * Interrupts are enabled early and LAPIC is setup much later, hence
 819	 * its possible that when we get here evt->event_handler is NULL.
 820	 * Check for event_handler being NULL and discard the interrupt as
 821	 * spurious.
 822	 */
 823	if (!evt->event_handler) {
 824		pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu);
 825		/* Switch it off */
 826		lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
 827		return;
 828	}
 829
 830	/*
 831	 * the NMI deadlock-detector uses this.
 832	 */
 833	inc_irq_stat(apic_timer_irqs);
 834
 835	evt->event_handler(evt);
 836}
 837
 838/*
 839 * Local APIC timer interrupt. This is the most natural way for doing
 840 * local interrupts, but local timer interrupts can be emulated by
 841 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
 842 *
 843 * [ if a single-CPU system runs an SMP kernel then we call the local
 844 *   interrupt as well. Thus we cannot inline the local irq ... ]
 845 */
 846void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
 847{
 848	struct pt_regs *old_regs = set_irq_regs(regs);
 849
 850	/*
 851	 * NOTE! We'd better ACK the irq immediately,
 852	 * because timer handling can be slow.
 853	 */
 854	ack_APIC_irq();
 855	/*
 856	 * update_process_times() expects us to have done irq_enter().
 857	 * Besides, if we don't timer interrupts ignore the global
 858	 * interrupt lock, which is the WrongThing (tm) to do.
 859	 */
 860	exit_idle();
 861	irq_enter();
 
 862	local_apic_timer_interrupt();
 863	irq_exit();
 864
 865	set_irq_regs(old_regs);
 866}
 867
 868int setup_profiling_timer(unsigned int multiplier)
 869{
 870	return -EINVAL;
 871}
 872
 873/*
 874 * Local APIC start and shutdown
 875 */
 876
 877/**
 878 * clear_local_APIC - shutdown the local APIC
 879 *
 880 * This is called, when a CPU is disabled and before rebooting, so the state of
 881 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
 882 * leftovers during boot.
 883 */
 884void clear_local_APIC(void)
 885{
 886	int maxlvt;
 887	u32 v;
 888
 889	/* APIC hasn't been mapped yet */
 890	if (!x2apic_mode && !apic_phys)
 891		return;
 892
 893	maxlvt = lapic_get_maxlvt();
 894	/*
 895	 * Masking an LVT entry can trigger a local APIC error
 896	 * if the vector is zero. Mask LVTERR first to prevent this.
 897	 */
 898	if (maxlvt >= 3) {
 899		v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
 900		apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
 901	}
 902	/*
 903	 * Careful: we have to set masks only first to deassert
 904	 * any level-triggered sources.
 905	 */
 906	v = apic_read(APIC_LVTT);
 907	apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
 908	v = apic_read(APIC_LVT0);
 909	apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
 910	v = apic_read(APIC_LVT1);
 911	apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
 912	if (maxlvt >= 4) {
 913		v = apic_read(APIC_LVTPC);
 914		apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
 915	}
 916
 917	/* lets not touch this if we didn't frob it */
 918#ifdef CONFIG_X86_THERMAL_VECTOR
 919	if (maxlvt >= 5) {
 920		v = apic_read(APIC_LVTTHMR);
 921		apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
 922	}
 923#endif
 924#ifdef CONFIG_X86_MCE_INTEL
 925	if (maxlvt >= 6) {
 926		v = apic_read(APIC_LVTCMCI);
 927		if (!(v & APIC_LVT_MASKED))
 928			apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED);
 929	}
 930#endif
 931
 932	/*
 933	 * Clean APIC state for other OSs:
 934	 */
 935	apic_write(APIC_LVTT, APIC_LVT_MASKED);
 936	apic_write(APIC_LVT0, APIC_LVT_MASKED);
 937	apic_write(APIC_LVT1, APIC_LVT_MASKED);
 938	if (maxlvt >= 3)
 939		apic_write(APIC_LVTERR, APIC_LVT_MASKED);
 940	if (maxlvt >= 4)
 941		apic_write(APIC_LVTPC, APIC_LVT_MASKED);
 942
 943	/* Integrated APIC (!82489DX) ? */
 944	if (lapic_is_integrated()) {
 945		if (maxlvt > 3)
 946			/* Clear ESR due to Pentium errata 3AP and 11AP */
 947			apic_write(APIC_ESR, 0);
 948		apic_read(APIC_ESR);
 949	}
 950}
 951
 952/**
 953 * disable_local_APIC - clear and disable the local APIC
 954 */
 955void disable_local_APIC(void)
 956{
 957	unsigned int value;
 958
 959	/* APIC hasn't been mapped yet */
 960	if (!x2apic_mode && !apic_phys)
 961		return;
 962
 963	clear_local_APIC();
 964
 965	/*
 966	 * Disable APIC (implies clearing of registers
 967	 * for 82489DX!).
 968	 */
 969	value = apic_read(APIC_SPIV);
 970	value &= ~APIC_SPIV_APIC_ENABLED;
 971	apic_write(APIC_SPIV, value);
 972
 973#ifdef CONFIG_X86_32
 974	/*
 975	 * When LAPIC was disabled by the BIOS and enabled by the kernel,
 976	 * restore the disabled state.
 977	 */
 978	if (enabled_via_apicbase) {
 979		unsigned int l, h;
 980
 981		rdmsr(MSR_IA32_APICBASE, l, h);
 982		l &= ~MSR_IA32_APICBASE_ENABLE;
 983		wrmsr(MSR_IA32_APICBASE, l, h);
 984	}
 985#endif
 986}
 987
 988/*
 989 * If Linux enabled the LAPIC against the BIOS default disable it down before
 990 * re-entering the BIOS on shutdown.  Otherwise the BIOS may get confused and
 991 * not power-off.  Additionally clear all LVT entries before disable_local_APIC
 992 * for the case where Linux didn't enable the LAPIC.
 993 */
 994void lapic_shutdown(void)
 995{
 996	unsigned long flags;
 997
 998	if (!cpu_has_apic && !apic_from_smp_config())
 999		return;
1000
1001	local_irq_save(flags);
1002
1003#ifdef CONFIG_X86_32
1004	if (!enabled_via_apicbase)
1005		clear_local_APIC();
1006	else
1007#endif
1008		disable_local_APIC();
1009
1010
1011	local_irq_restore(flags);
1012}
1013
1014/*
1015 * This is to verify that we're looking at a real local APIC.
1016 * Check these against your board if the CPUs aren't getting
1017 * started for no apparent reason.
1018 */
1019int __init verify_local_APIC(void)
1020{
1021	unsigned int reg0, reg1;
1022
1023	/*
1024	 * The version register is read-only in a real APIC.
1025	 */
1026	reg0 = apic_read(APIC_LVR);
1027	apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
1028	apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
1029	reg1 = apic_read(APIC_LVR);
1030	apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
1031
1032	/*
1033	 * The two version reads above should print the same
1034	 * numbers.  If the second one is different, then we
1035	 * poke at a non-APIC.
1036	 */
1037	if (reg1 != reg0)
1038		return 0;
1039
1040	/*
1041	 * Check if the version looks reasonably.
1042	 */
1043	reg1 = GET_APIC_VERSION(reg0);
1044	if (reg1 == 0x00 || reg1 == 0xff)
1045		return 0;
1046	reg1 = lapic_get_maxlvt();
1047	if (reg1 < 0x02 || reg1 == 0xff)
1048		return 0;
1049
1050	/*
1051	 * The ID register is read/write in a real APIC.
1052	 */
1053	reg0 = apic_read(APIC_ID);
1054	apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
1055	apic_write(APIC_ID, reg0 ^ apic->apic_id_mask);
1056	reg1 = apic_read(APIC_ID);
1057	apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
1058	apic_write(APIC_ID, reg0);
1059	if (reg1 != (reg0 ^ apic->apic_id_mask))
1060		return 0;
1061
1062	/*
1063	 * The next two are just to see if we have sane values.
1064	 * They're only really relevant if we're in Virtual Wire
1065	 * compatibility mode, but most boxes are anymore.
1066	 */
1067	reg0 = apic_read(APIC_LVT0);
1068	apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
1069	reg1 = apic_read(APIC_LVT1);
1070	apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
1071
1072	return 1;
1073}
1074
1075/**
1076 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1077 */
1078void __init sync_Arb_IDs(void)
1079{
1080	/*
1081	 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1082	 * needed on AMD.
1083	 */
1084	if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1085		return;
1086
1087	/*
1088	 * Wait for idle.
1089	 */
1090	apic_wait_icr_idle();
1091
1092	apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1093	apic_write(APIC_ICR, APIC_DEST_ALLINC |
1094			APIC_INT_LEVELTRIG | APIC_DM_INIT);
1095}
1096
1097/*
1098 * An initial setup of the virtual wire mode.
1099 */
1100void __init init_bsp_APIC(void)
1101{
1102	unsigned int value;
1103
1104	/*
1105	 * Don't do the setup now if we have a SMP BIOS as the
1106	 * through-I/O-APIC virtual wire mode might be active.
1107	 */
1108	if (smp_found_config || !cpu_has_apic)
1109		return;
1110
1111	/*
1112	 * Do not trust the local APIC being empty at bootup.
1113	 */
1114	clear_local_APIC();
1115
1116	/*
1117	 * Enable APIC.
1118	 */
1119	value = apic_read(APIC_SPIV);
1120	value &= ~APIC_VECTOR_MASK;
1121	value |= APIC_SPIV_APIC_ENABLED;
1122
1123#ifdef CONFIG_X86_32
1124	/* This bit is reserved on P4/Xeon and should be cleared */
1125	if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1126	    (boot_cpu_data.x86 == 15))
1127		value &= ~APIC_SPIV_FOCUS_DISABLED;
1128	else
1129#endif
1130		value |= APIC_SPIV_FOCUS_DISABLED;
1131	value |= SPURIOUS_APIC_VECTOR;
1132	apic_write(APIC_SPIV, value);
1133
1134	/*
1135	 * Set up the virtual wire mode.
1136	 */
1137	apic_write(APIC_LVT0, APIC_DM_EXTINT);
1138	value = APIC_DM_NMI;
1139	if (!lapic_is_integrated())		/* 82489DX */
1140		value |= APIC_LVT_LEVEL_TRIGGER;
1141	apic_write(APIC_LVT1, value);
1142}
1143
1144static void __cpuinit lapic_setup_esr(void)
1145{
1146	unsigned int oldvalue, value, maxlvt;
1147
1148	if (!lapic_is_integrated()) {
1149		pr_info("No ESR for 82489DX.\n");
1150		return;
1151	}
1152
1153	if (apic->disable_esr) {
1154		/*
1155		 * Something untraceable is creating bad interrupts on
1156		 * secondary quads ... for the moment, just leave the
1157		 * ESR disabled - we can't do anything useful with the
1158		 * errors anyway - mbligh
1159		 */
1160		pr_info("Leaving ESR disabled.\n");
1161		return;
1162	}
1163
1164	maxlvt = lapic_get_maxlvt();
1165	if (maxlvt > 3)		/* Due to the Pentium erratum 3AP. */
1166		apic_write(APIC_ESR, 0);
1167	oldvalue = apic_read(APIC_ESR);
1168
1169	/* enables sending errors */
1170	value = ERROR_APIC_VECTOR;
1171	apic_write(APIC_LVTERR, value);
1172
1173	/*
1174	 * spec says clear errors after enabling vector.
1175	 */
1176	if (maxlvt > 3)
1177		apic_write(APIC_ESR, 0);
1178	value = apic_read(APIC_ESR);
1179	if (value != oldvalue)
1180		apic_printk(APIC_VERBOSE, "ESR value before enabling "
1181			"vector: 0x%08x  after: 0x%08x\n",
1182			oldvalue, value);
1183}
1184
1185/**
1186 * setup_local_APIC - setup the local APIC
1187 *
1188 * Used to setup local APIC while initializing BSP or bringin up APs.
1189 * Always called with preemption disabled.
1190 */
1191void __cpuinit setup_local_APIC(void)
1192{
1193	int cpu = smp_processor_id();
1194	unsigned int value, queued;
1195	int i, j, acked = 0;
1196	unsigned long long tsc = 0, ntsc;
1197	long long max_loops = cpu_khz;
1198
1199	if (cpu_has_tsc)
1200		rdtscll(tsc);
1201
1202	if (disable_apic) {
1203		disable_ioapic_support();
1204		return;
1205	}
1206
1207#ifdef CONFIG_X86_32
1208	/* Pound the ESR really hard over the head with a big hammer - mbligh */
1209	if (lapic_is_integrated() && apic->disable_esr) {
1210		apic_write(APIC_ESR, 0);
1211		apic_write(APIC_ESR, 0);
1212		apic_write(APIC_ESR, 0);
1213		apic_write(APIC_ESR, 0);
1214	}
1215#endif
1216	perf_events_lapic_init();
1217
1218	/*
1219	 * Double-check whether this APIC is really registered.
1220	 * This is meaningless in clustered apic mode, so we skip it.
1221	 */
1222	BUG_ON(!apic->apic_id_registered());
1223
1224	/*
1225	 * Intel recommends to set DFR, LDR and TPR before enabling
1226	 * an APIC.  See e.g. "AP-388 82489DX User's Manual" (Intel
1227	 * document number 292116).  So here it goes...
1228	 */
1229	apic->init_apic_ldr();
1230
1231#ifdef CONFIG_X86_32
1232	/*
1233	 * APIC LDR is initialized.  If logical_apicid mapping was
1234	 * initialized during get_smp_config(), make sure it matches the
1235	 * actual value.
1236	 */
1237	i = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
1238	WARN_ON(i != BAD_APICID && i != logical_smp_processor_id());
1239	/* always use the value from LDR */
1240	early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
1241		logical_smp_processor_id();
1242
1243	/*
1244	 * Some NUMA implementations (NUMAQ) don't initialize apicid to
1245	 * node mapping during NUMA init.  Now that logical apicid is
1246	 * guaranteed to be known, give it another chance.  This is already
1247	 * a bit too late - percpu allocation has already happened without
1248	 * proper NUMA affinity.
1249	 */
1250	if (apic->x86_32_numa_cpu_node)
1251		set_apicid_to_node(early_per_cpu(x86_cpu_to_apicid, cpu),
1252				   apic->x86_32_numa_cpu_node(cpu));
1253#endif
1254
1255	/*
1256	 * Set Task Priority to 'accept all'. We never change this
1257	 * later on.
1258	 */
1259	value = apic_read(APIC_TASKPRI);
1260	value &= ~APIC_TPRI_MASK;
1261	apic_write(APIC_TASKPRI, value);
1262
1263	/*
1264	 * After a crash, we no longer service the interrupts and a pending
1265	 * interrupt from previous kernel might still have ISR bit set.
1266	 *
1267	 * Most probably by now CPU has serviced that pending interrupt and
1268	 * it might not have done the ack_APIC_irq() because it thought,
1269	 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1270	 * does not clear the ISR bit and cpu thinks it has already serivced
1271	 * the interrupt. Hence a vector might get locked. It was noticed
1272	 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1273	 */
1274	do {
1275		queued = 0;
1276		for (i = APIC_ISR_NR - 1; i >= 0; i--)
1277			queued |= apic_read(APIC_IRR + i*0x10);
1278
1279		for (i = APIC_ISR_NR - 1; i >= 0; i--) {
1280			value = apic_read(APIC_ISR + i*0x10);
1281			for (j = 31; j >= 0; j--) {
1282				if (value & (1<<j)) {
1283					ack_APIC_irq();
1284					acked++;
1285				}
1286			}
1287		}
1288		if (acked > 256) {
1289			printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n",
1290			       acked);
1291			break;
1292		}
1293		if (cpu_has_tsc) {
1294			rdtscll(ntsc);
1295			max_loops = (cpu_khz << 10) - (ntsc - tsc);
1296		} else
1297			max_loops--;
 
 
1298	} while (queued && max_loops > 0);
1299	WARN_ON(max_loops <= 0);
1300
1301	/*
1302	 * Now that we are all set up, enable the APIC
1303	 */
1304	value = apic_read(APIC_SPIV);
1305	value &= ~APIC_VECTOR_MASK;
1306	/*
1307	 * Enable APIC
1308	 */
1309	value |= APIC_SPIV_APIC_ENABLED;
1310
1311#ifdef CONFIG_X86_32
1312	/*
1313	 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1314	 * certain networking cards. If high frequency interrupts are
1315	 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1316	 * entry is masked/unmasked at a high rate as well then sooner or
1317	 * later IOAPIC line gets 'stuck', no more interrupts are received
1318	 * from the device. If focus CPU is disabled then the hang goes
1319	 * away, oh well :-(
1320	 *
1321	 * [ This bug can be reproduced easily with a level-triggered
1322	 *   PCI Ne2000 networking cards and PII/PIII processors, dual
1323	 *   BX chipset. ]
1324	 */
1325	/*
1326	 * Actually disabling the focus CPU check just makes the hang less
1327	 * frequent as it makes the interrupt distributon model be more
1328	 * like LRU than MRU (the short-term load is more even across CPUs).
1329	 * See also the comment in end_level_ioapic_irq().  --macro
1330	 */
1331
1332	/*
1333	 * - enable focus processor (bit==0)
1334	 * - 64bit mode always use processor focus
1335	 *   so no need to set it
1336	 */
1337	value &= ~APIC_SPIV_FOCUS_DISABLED;
1338#endif
1339
1340	/*
1341	 * Set spurious IRQ vector
1342	 */
1343	value |= SPURIOUS_APIC_VECTOR;
1344	apic_write(APIC_SPIV, value);
1345
1346	/*
1347	 * Set up LVT0, LVT1:
1348	 *
1349	 * set up through-local-APIC on the BP's LINT0. This is not
1350	 * strictly necessary in pure symmetric-IO mode, but sometimes
1351	 * we delegate interrupts to the 8259A.
1352	 */
1353	/*
1354	 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1355	 */
1356	value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1357	if (!cpu && (pic_mode || !value)) {
1358		value = APIC_DM_EXTINT;
1359		apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu);
1360	} else {
1361		value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1362		apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu);
1363	}
1364	apic_write(APIC_LVT0, value);
1365
1366	/*
1367	 * only the BP should see the LINT1 NMI signal, obviously.
1368	 */
1369	if (!cpu)
1370		value = APIC_DM_NMI;
1371	else
1372		value = APIC_DM_NMI | APIC_LVT_MASKED;
1373	if (!lapic_is_integrated())		/* 82489DX */
1374		value |= APIC_LVT_LEVEL_TRIGGER;
1375	apic_write(APIC_LVT1, value);
1376
1377#ifdef CONFIG_X86_MCE_INTEL
1378	/* Recheck CMCI information after local APIC is up on CPU #0 */
1379	if (!cpu)
1380		cmci_recheck();
1381#endif
1382}
1383
1384void __cpuinit end_local_APIC_setup(void)
1385{
1386	lapic_setup_esr();
1387
1388#ifdef CONFIG_X86_32
1389	{
1390		unsigned int value;
1391		/* Disable the local apic timer */
1392		value = apic_read(APIC_LVTT);
1393		value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1394		apic_write(APIC_LVTT, value);
1395	}
1396#endif
1397
1398	apic_pm_activate();
1399}
1400
1401void __init bsp_end_local_APIC_setup(void)
1402{
1403	end_local_APIC_setup();
1404
1405	/*
1406	 * Now that local APIC setup is completed for BP, configure the fault
1407	 * handling for interrupt remapping.
1408	 */
1409	if (intr_remapping_enabled)
1410		enable_drhd_fault_handling();
1411
1412}
1413
1414#ifdef CONFIG_X86_X2APIC
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1415void check_x2apic(void)
1416{
1417	if (x2apic_enabled()) {
1418		pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
1419		x2apic_preenabled = x2apic_mode = 1;
1420	}
1421}
1422
1423void enable_x2apic(void)
1424{
1425	int msr, msr2;
 
 
 
 
 
 
1426
1427	if (!x2apic_mode)
1428		return;
1429
1430	rdmsr(MSR_IA32_APICBASE, msr, msr2);
1431	if (!(msr & X2APIC_ENABLE)) {
1432		printk_once(KERN_INFO "Enabling x2apic\n");
1433		wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, msr2);
1434	}
1435}
1436#endif /* CONFIG_X86_X2APIC */
1437
1438int __init enable_IR(void)
1439{
1440#ifdef CONFIG_INTR_REMAP
1441	if (!intr_remapping_supported()) {
1442		pr_debug("intr-remapping not supported\n");
1443		return 0;
1444	}
1445
1446	if (!x2apic_preenabled && skip_ioapic_setup) {
1447		pr_info("Skipped enabling intr-remap because of skipping "
1448			"io-apic setup\n");
1449		return 0;
1450	}
1451
1452	if (enable_intr_remapping(x2apic_supported()))
1453		return 0;
1454
1455	pr_info("Enabled Interrupt-remapping\n");
1456
1457	return 1;
1458
1459#endif
1460	return 0;
1461}
1462
1463void __init enable_IR_x2apic(void)
1464{
1465	unsigned long flags;
1466	int ret, x2apic_enabled = 0;
1467	int dmar_table_init_ret;
1468
1469	dmar_table_init_ret = dmar_table_init();
1470	if (dmar_table_init_ret && !x2apic_supported())
 
 
 
1471		return;
1472
1473	ret = save_ioapic_entries();
1474	if (ret) {
1475		pr_info("Saving IO-APIC state failed: %d\n", ret);
1476		goto out;
1477	}
1478
1479	local_irq_save(flags);
1480	legacy_pic->mask_all();
1481	mask_ioapic_entries();
1482
1483	if (dmar_table_init_ret)
1484		ret = 0;
 
 
 
1485	else
1486		ret = enable_IR();
1487
1488	if (!ret) {
 
 
 
1489		/* IR is required if there is APIC ID > 255 even when running
1490		 * under KVM
1491		 */
1492		if (max_physical_apicid > 255 ||
1493		    !hypervisor_x2apic_available())
1494			goto nox2apic;
 
 
 
1495		/*
1496		 * without IR all CPUs can be addressed by IOAPIC/MSI
1497		 * only in physical mode
1498		 */
1499		x2apic_force_phys();
1500	}
1501
 
 
 
 
 
1502	x2apic_enabled = 1;
1503
1504	if (x2apic_supported() && !x2apic_mode) {
1505		x2apic_mode = 1;
1506		enable_x2apic();
1507		pr_info("Enabled x2apic\n");
1508	}
1509
1510nox2apic:
1511	if (!ret) /* IR enabling failed */
1512		restore_ioapic_entries();
1513	legacy_pic->restore_mask();
1514	local_irq_restore(flags);
1515
1516out:
1517	if (x2apic_enabled)
1518		return;
1519
1520	if (x2apic_preenabled)
1521		panic("x2apic: enabled by BIOS but kernel init failed.");
1522	else if (cpu_has_x2apic)
1523		pr_info("Not enabling x2apic, Intr-remapping init failed.\n");
1524}
1525
1526#ifdef CONFIG_X86_64
1527/*
1528 * Detect and enable local APICs on non-SMP boards.
1529 * Original code written by Keir Fraser.
1530 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1531 * not correctly set up (usually the APIC timer won't work etc.)
1532 */
1533static int __init detect_init_APIC(void)
1534{
1535	if (!cpu_has_apic) {
1536		pr_info("No local APIC present\n");
1537		return -1;
1538	}
1539
1540	mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1541	return 0;
1542}
1543#else
1544
1545static int __init apic_verify(void)
1546{
1547	u32 features, h, l;
1548
1549	/*
1550	 * The APIC feature bit should now be enabled
1551	 * in `cpuid'
1552	 */
1553	features = cpuid_edx(1);
1554	if (!(features & (1 << X86_FEATURE_APIC))) {
1555		pr_warning("Could not enable APIC!\n");
1556		return -1;
1557	}
1558	set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1559	mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1560
1561	/* The BIOS may have set up the APIC at some other address */
1562	rdmsr(MSR_IA32_APICBASE, l, h);
1563	if (l & MSR_IA32_APICBASE_ENABLE)
1564		mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
 
 
1565
1566	pr_info("Found and enabled local APIC!\n");
1567	return 0;
1568}
1569
1570int __init apic_force_enable(unsigned long addr)
1571{
1572	u32 h, l;
1573
1574	if (disable_apic)
1575		return -1;
1576
1577	/*
1578	 * Some BIOSes disable the local APIC in the APIC_BASE
1579	 * MSR. This can only be done in software for Intel P6 or later
1580	 * and AMD K7 (Model > 1) or later.
1581	 */
1582	rdmsr(MSR_IA32_APICBASE, l, h);
1583	if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1584		pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1585		l &= ~MSR_IA32_APICBASE_BASE;
1586		l |= MSR_IA32_APICBASE_ENABLE | addr;
1587		wrmsr(MSR_IA32_APICBASE, l, h);
1588		enabled_via_apicbase = 1;
 
 
1589	}
1590	return apic_verify();
1591}
1592
1593/*
1594 * Detect and initialize APIC
1595 */
1596static int __init detect_init_APIC(void)
1597{
1598	/* Disabled by kernel option? */
1599	if (disable_apic)
1600		return -1;
1601
1602	switch (boot_cpu_data.x86_vendor) {
1603	case X86_VENDOR_AMD:
1604		if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1605		    (boot_cpu_data.x86 >= 15))
1606			break;
1607		goto no_apic;
1608	case X86_VENDOR_INTEL:
1609		if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1610		    (boot_cpu_data.x86 == 5 && cpu_has_apic))
1611			break;
1612		goto no_apic;
1613	default:
1614		goto no_apic;
1615	}
1616
1617	if (!cpu_has_apic) {
1618		/*
1619		 * Over-ride BIOS and try to enable the local APIC only if
1620		 * "lapic" specified.
1621		 */
1622		if (!force_enable_local_apic) {
1623			pr_info("Local APIC disabled by BIOS -- "
1624				"you can enable it with \"lapic\"\n");
1625			return -1;
1626		}
1627		if (apic_force_enable(APIC_DEFAULT_PHYS_BASE))
1628			return -1;
1629	} else {
1630		if (apic_verify())
1631			return -1;
1632	}
1633
1634	apic_pm_activate();
1635
1636	return 0;
1637
1638no_apic:
1639	pr_info("No local APIC present or hardware disabled\n");
1640	return -1;
1641}
1642#endif
1643
1644/**
1645 * init_apic_mappings - initialize APIC mappings
1646 */
1647void __init init_apic_mappings(void)
1648{
1649	unsigned int new_apicid;
1650
1651	if (x2apic_mode) {
1652		boot_cpu_physical_apicid = read_apic_id();
1653		return;
1654	}
1655
1656	/* If no local APIC can be found return early */
1657	if (!smp_found_config && detect_init_APIC()) {
1658		/* lets NOP'ify apic operations */
1659		pr_info("APIC: disable apic facility\n");
1660		apic_disable();
1661	} else {
1662		apic_phys = mp_lapic_addr;
1663
1664		/*
1665		 * acpi lapic path already maps that address in
1666		 * acpi_register_lapic_address()
1667		 */
1668		if (!acpi_lapic && !smp_found_config)
1669			register_lapic_address(apic_phys);
1670	}
1671
1672	/*
1673	 * Fetch the APIC ID of the BSP in case we have a
1674	 * default configuration (or the MP table is broken).
1675	 */
1676	new_apicid = read_apic_id();
1677	if (boot_cpu_physical_apicid != new_apicid) {
1678		boot_cpu_physical_apicid = new_apicid;
1679		/*
1680		 * yeah -- we lie about apic_version
1681		 * in case if apic was disabled via boot option
1682		 * but it's not a problem for SMP compiled kernel
1683		 * since smp_sanity_check is prepared for such a case
1684		 * and disable smp mode
1685		 */
1686		apic_version[new_apicid] =
1687			 GET_APIC_VERSION(apic_read(APIC_LVR));
1688	}
1689}
1690
1691void __init register_lapic_address(unsigned long address)
1692{
1693	mp_lapic_addr = address;
1694
1695	if (!x2apic_mode) {
1696		set_fixmap_nocache(FIX_APIC_BASE, address);
1697		apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1698			    APIC_BASE, mp_lapic_addr);
1699	}
1700	if (boot_cpu_physical_apicid == -1U) {
1701		boot_cpu_physical_apicid  = read_apic_id();
1702		apic_version[boot_cpu_physical_apicid] =
1703			 GET_APIC_VERSION(apic_read(APIC_LVR));
1704	}
1705}
1706
1707/*
1708 * This initializes the IO-APIC and APIC hardware if this is
1709 * a UP kernel.
1710 */
1711int apic_version[MAX_LOCAL_APIC];
1712
1713int __init APIC_init_uniprocessor(void)
1714{
1715	if (disable_apic) {
1716		pr_info("Apic disabled\n");
1717		return -1;
1718	}
1719#ifdef CONFIG_X86_64
1720	if (!cpu_has_apic) {
1721		disable_apic = 1;
1722		pr_info("Apic disabled by BIOS\n");
1723		return -1;
1724	}
1725#else
1726	if (!smp_found_config && !cpu_has_apic)
1727		return -1;
1728
1729	/*
1730	 * Complain if the BIOS pretends there is one.
1731	 */
1732	if (!cpu_has_apic &&
1733	    APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
1734		pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
1735			boot_cpu_physical_apicid);
1736		return -1;
1737	}
1738#endif
1739
1740	default_setup_apic_routing();
1741
1742	verify_local_APIC();
1743	connect_bsp_APIC();
1744
1745#ifdef CONFIG_X86_64
1746	apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
1747#else
1748	/*
1749	 * Hack: In case of kdump, after a crash, kernel might be booting
1750	 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1751	 * might be zero if read from MP tables. Get it from LAPIC.
1752	 */
1753# ifdef CONFIG_CRASH_DUMP
1754	boot_cpu_physical_apicid = read_apic_id();
1755# endif
1756#endif
1757	physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1758	setup_local_APIC();
1759
1760#ifdef CONFIG_X86_IO_APIC
1761	/*
1762	 * Now enable IO-APICs, actually call clear_IO_APIC
1763	 * We need clear_IO_APIC before enabling error vector
1764	 */
1765	if (!skip_ioapic_setup && nr_ioapics)
1766		enable_IO_APIC();
1767#endif
1768
1769	bsp_end_local_APIC_setup();
1770
1771#ifdef CONFIG_X86_IO_APIC
1772	if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
1773		setup_IO_APIC();
1774	else {
1775		nr_ioapics = 0;
1776	}
1777#endif
1778
1779	x86_init.timers.setup_percpu_clockev();
1780	return 0;
1781}
1782
1783/*
1784 * Local APIC interrupts
1785 */
1786
1787/*
1788 * This interrupt should _never_ happen with our APIC/SMP architecture
1789 */
1790void smp_spurious_interrupt(struct pt_regs *regs)
1791{
1792	u32 v;
1793
1794	exit_idle();
1795	irq_enter();
 
1796	/*
1797	 * Check if this really is a spurious interrupt and ACK it
1798	 * if it is a vectored one.  Just in case...
1799	 * Spurious interrupts should not be ACKed.
1800	 */
1801	v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1802	if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1803		ack_APIC_irq();
1804
1805	inc_irq_stat(irq_spurious_count);
1806
1807	/* see sw-dev-man vol 3, chapter 7.4.13.5 */
1808	pr_info("spurious APIC interrupt on CPU#%d, "
1809		"should never happen.\n", smp_processor_id());
1810	irq_exit();
1811}
1812
1813/*
1814 * This interrupt should never happen with our APIC/SMP architecture
1815 */
1816void smp_error_interrupt(struct pt_regs *regs)
1817{
1818	u32 v0, v1;
1819	u32 i = 0;
1820	static const char * const error_interrupt_reason[] = {
1821		"Send CS error",		/* APIC Error Bit 0 */
1822		"Receive CS error",		/* APIC Error Bit 1 */
1823		"Send accept error",		/* APIC Error Bit 2 */
1824		"Receive accept error",		/* APIC Error Bit 3 */
1825		"Redirectable IPI",		/* APIC Error Bit 4 */
1826		"Send illegal vector",		/* APIC Error Bit 5 */
1827		"Received illegal vector",	/* APIC Error Bit 6 */
1828		"Illegal register address",	/* APIC Error Bit 7 */
1829	};
1830
1831	exit_idle();
1832	irq_enter();
 
1833	/* First tickle the hardware, only then report what went on. -- REW */
1834	v0 = apic_read(APIC_ESR);
1835	apic_write(APIC_ESR, 0);
1836	v1 = apic_read(APIC_ESR);
1837	ack_APIC_irq();
1838	atomic_inc(&irq_err_count);
1839
1840	apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x(%02x)",
1841		    smp_processor_id(), v0 , v1);
1842
1843	v1 = v1 & 0xff;
1844	while (v1) {
1845		if (v1 & 0x1)
1846			apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]);
1847		i++;
1848		v1 >>= 1;
1849	};
1850
1851	apic_printk(APIC_DEBUG, KERN_CONT "\n");
1852
1853	irq_exit();
1854}
1855
1856/**
1857 * connect_bsp_APIC - attach the APIC to the interrupt system
1858 */
1859void __init connect_bsp_APIC(void)
1860{
1861#ifdef CONFIG_X86_32
1862	if (pic_mode) {
1863		/*
1864		 * Do not trust the local APIC being empty at bootup.
1865		 */
1866		clear_local_APIC();
1867		/*
1868		 * PIC mode, enable APIC mode in the IMCR, i.e.  connect BSP's
1869		 * local APIC to INT and NMI lines.
1870		 */
1871		apic_printk(APIC_VERBOSE, "leaving PIC mode, "
1872				"enabling APIC mode.\n");
1873		imcr_pic_to_apic();
1874	}
1875#endif
1876	if (apic->enable_apic_mode)
1877		apic->enable_apic_mode();
1878}
1879
1880/**
1881 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1882 * @virt_wire_setup:	indicates, whether virtual wire mode is selected
1883 *
1884 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1885 * APIC is disabled.
1886 */
1887void disconnect_bsp_APIC(int virt_wire_setup)
1888{
1889	unsigned int value;
1890
1891#ifdef CONFIG_X86_32
1892	if (pic_mode) {
1893		/*
1894		 * Put the board back into PIC mode (has an effect only on
1895		 * certain older boards).  Note that APIC interrupts, including
1896		 * IPIs, won't work beyond this point!  The only exception are
1897		 * INIT IPIs.
1898		 */
1899		apic_printk(APIC_VERBOSE, "disabling APIC mode, "
1900				"entering PIC mode.\n");
1901		imcr_apic_to_pic();
1902		return;
1903	}
1904#endif
1905
1906	/* Go back to Virtual Wire compatibility mode */
1907
1908	/* For the spurious interrupt use vector F, and enable it */
1909	value = apic_read(APIC_SPIV);
1910	value &= ~APIC_VECTOR_MASK;
1911	value |= APIC_SPIV_APIC_ENABLED;
1912	value |= 0xf;
1913	apic_write(APIC_SPIV, value);
1914
1915	if (!virt_wire_setup) {
1916		/*
1917		 * For LVT0 make it edge triggered, active high,
1918		 * external and enabled
1919		 */
1920		value = apic_read(APIC_LVT0);
1921		value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1922			APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1923			APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1924		value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1925		value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
1926		apic_write(APIC_LVT0, value);
1927	} else {
1928		/* Disable LVT0 */
1929		apic_write(APIC_LVT0, APIC_LVT_MASKED);
1930	}
1931
1932	/*
1933	 * For LVT1 make it edge triggered, active high,
1934	 * nmi and enabled
1935	 */
1936	value = apic_read(APIC_LVT1);
1937	value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1938			APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1939			APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1940	value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1941	value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
1942	apic_write(APIC_LVT1, value);
1943}
1944
1945void __cpuinit generic_processor_info(int apicid, int version)
1946{
1947	int cpu, max = nr_cpu_ids;
1948	bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid,
1949				phys_cpu_present_map);
1950
1951	/*
1952	 * If boot cpu has not been detected yet, then only allow upto
1953	 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu
1954	 */
1955	if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 &&
1956	    apicid != boot_cpu_physical_apicid) {
1957		int thiscpu = max + disabled_cpus - 1;
1958
1959		pr_warning(
1960			"ACPI: NR_CPUS/possible_cpus limit of %i almost"
1961			" reached. Keeping one slot for boot cpu."
1962			"  Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
1963
1964		disabled_cpus++;
1965		return;
1966	}
1967
1968	if (num_processors >= nr_cpu_ids) {
1969		int thiscpu = max + disabled_cpus;
1970
1971		pr_warning(
1972			"ACPI: NR_CPUS/possible_cpus limit of %i reached."
1973			"  Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
1974
1975		disabled_cpus++;
1976		return;
1977	}
1978
1979	num_processors++;
1980	if (apicid == boot_cpu_physical_apicid) {
1981		/*
1982		 * x86_bios_cpu_apicid is required to have processors listed
1983		 * in same order as logical cpu numbers. Hence the first
1984		 * entry is BSP, and so on.
1985		 * boot_cpu_init() already hold bit 0 in cpu_present_mask
1986		 * for BSP.
1987		 */
1988		cpu = 0;
1989	} else
1990		cpu = cpumask_next_zero(-1, cpu_present_mask);
1991
1992	/*
1993	 * Validate version
1994	 */
1995	if (version == 0x0) {
1996		pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n",
1997			   cpu, apicid);
1998		version = 0x10;
1999	}
2000	apic_version[apicid] = version;
2001
2002	if (version != apic_version[boot_cpu_physical_apicid]) {
2003		pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n",
2004			apic_version[boot_cpu_physical_apicid], cpu, version);
2005	}
2006
2007	physid_set(apicid, phys_cpu_present_map);
2008	if (apicid > max_physical_apicid)
2009		max_physical_apicid = apicid;
2010
2011#if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
2012	early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
2013	early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
2014#endif
2015#ifdef CONFIG_X86_32
2016	early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
2017		apic->x86_32_early_logical_apicid(cpu);
2018#endif
2019	set_cpu_possible(cpu, true);
2020	set_cpu_present(cpu, true);
2021}
2022
2023int hard_smp_processor_id(void)
2024{
2025	return read_apic_id();
2026}
2027
2028void default_init_apic_ldr(void)
2029{
2030	unsigned long val;
2031
2032	apic_write(APIC_DFR, APIC_DFR_VALUE);
2033	val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
2034	val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
2035	apic_write(APIC_LDR, val);
2036}
2037
2038/*
2039 * Power management
2040 */
2041#ifdef CONFIG_PM
2042
2043static struct {
2044	/*
2045	 * 'active' is true if the local APIC was enabled by us and
2046	 * not the BIOS; this signifies that we are also responsible
2047	 * for disabling it before entering apm/acpi suspend
2048	 */
2049	int active;
2050	/* r/w apic fields */
2051	unsigned int apic_id;
2052	unsigned int apic_taskpri;
2053	unsigned int apic_ldr;
2054	unsigned int apic_dfr;
2055	unsigned int apic_spiv;
2056	unsigned int apic_lvtt;
2057	unsigned int apic_lvtpc;
2058	unsigned int apic_lvt0;
2059	unsigned int apic_lvt1;
2060	unsigned int apic_lvterr;
2061	unsigned int apic_tmict;
2062	unsigned int apic_tdcr;
2063	unsigned int apic_thmr;
2064} apic_pm_state;
2065
2066static int lapic_suspend(void)
2067{
2068	unsigned long flags;
2069	int maxlvt;
2070
2071	if (!apic_pm_state.active)
2072		return 0;
2073
2074	maxlvt = lapic_get_maxlvt();
2075
2076	apic_pm_state.apic_id = apic_read(APIC_ID);
2077	apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
2078	apic_pm_state.apic_ldr = apic_read(APIC_LDR);
2079	apic_pm_state.apic_dfr = apic_read(APIC_DFR);
2080	apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
2081	apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
2082	if (maxlvt >= 4)
2083		apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
2084	apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
2085	apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
2086	apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
2087	apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
2088	apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
2089#ifdef CONFIG_X86_THERMAL_VECTOR
2090	if (maxlvt >= 5)
2091		apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
2092#endif
2093
2094	local_irq_save(flags);
2095	disable_local_APIC();
2096
2097	if (intr_remapping_enabled)
2098		disable_intr_remapping();
2099
2100	local_irq_restore(flags);
2101	return 0;
2102}
2103
2104static void lapic_resume(void)
2105{
2106	unsigned int l, h;
2107	unsigned long flags;
2108	int maxlvt;
2109
2110	if (!apic_pm_state.active)
2111		return;
2112
2113	local_irq_save(flags);
2114	if (intr_remapping_enabled) {
2115		/*
2116		 * IO-APIC and PIC have their own resume routines.
2117		 * We just mask them here to make sure the interrupt
2118		 * subsystem is completely quiet while we enable x2apic
2119		 * and interrupt-remapping.
2120		 */
2121		mask_ioapic_entries();
2122		legacy_pic->mask_all();
2123	}
2124
2125	if (x2apic_mode)
2126		enable_x2apic();
2127	else {
2128		/*
2129		 * Make sure the APICBASE points to the right address
2130		 *
2131		 * FIXME! This will be wrong if we ever support suspend on
2132		 * SMP! We'll need to do this as part of the CPU restore!
2133		 */
2134		rdmsr(MSR_IA32_APICBASE, l, h);
2135		l &= ~MSR_IA32_APICBASE_BASE;
2136		l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
2137		wrmsr(MSR_IA32_APICBASE, l, h);
 
 
2138	}
2139
2140	maxlvt = lapic_get_maxlvt();
2141	apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
2142	apic_write(APIC_ID, apic_pm_state.apic_id);
2143	apic_write(APIC_DFR, apic_pm_state.apic_dfr);
2144	apic_write(APIC_LDR, apic_pm_state.apic_ldr);
2145	apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
2146	apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
2147	apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
2148	apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
2149#if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2150	if (maxlvt >= 5)
2151		apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
2152#endif
2153	if (maxlvt >= 4)
2154		apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
2155	apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
2156	apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
2157	apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
2158	apic_write(APIC_ESR, 0);
2159	apic_read(APIC_ESR);
2160	apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
2161	apic_write(APIC_ESR, 0);
2162	apic_read(APIC_ESR);
2163
2164	if (intr_remapping_enabled)
2165		reenable_intr_remapping(x2apic_mode);
2166
2167	local_irq_restore(flags);
2168}
2169
2170/*
2171 * This device has no shutdown method - fully functioning local APICs
2172 * are needed on every CPU up until machine_halt/restart/poweroff.
2173 */
2174
2175static struct syscore_ops lapic_syscore_ops = {
2176	.resume		= lapic_resume,
2177	.suspend	= lapic_suspend,
2178};
2179
2180static void __cpuinit apic_pm_activate(void)
2181{
2182	apic_pm_state.active = 1;
2183}
2184
2185static int __init init_lapic_sysfs(void)
2186{
2187	/* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2188	if (cpu_has_apic)
2189		register_syscore_ops(&lapic_syscore_ops);
2190
2191	return 0;
2192}
2193
2194/* local apic needs to resume before other devices access its registers. */
2195core_initcall(init_lapic_sysfs);
2196
2197#else	/* CONFIG_PM */
2198
2199static void apic_pm_activate(void) { }
2200
2201#endif	/* CONFIG_PM */
2202
2203#ifdef CONFIG_X86_64
2204
2205static int __cpuinit apic_cluster_num(void)
2206{
2207	int i, clusters, zeros;
2208	unsigned id;
2209	u16 *bios_cpu_apicid;
2210	DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
2211
2212	bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
2213	bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
2214
2215	for (i = 0; i < nr_cpu_ids; i++) {
2216		/* are we being called early in kernel startup? */
2217		if (bios_cpu_apicid) {
2218			id = bios_cpu_apicid[i];
2219		} else if (i < nr_cpu_ids) {
2220			if (cpu_present(i))
2221				id = per_cpu(x86_bios_cpu_apicid, i);
2222			else
2223				continue;
2224		} else
2225			break;
2226
2227		if (id != BAD_APICID)
2228			__set_bit(APIC_CLUSTERID(id), clustermap);
2229	}
2230
2231	/* Problem:  Partially populated chassis may not have CPUs in some of
2232	 * the APIC clusters they have been allocated.  Only present CPUs have
2233	 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2234	 * Since clusters are allocated sequentially, count zeros only if
2235	 * they are bounded by ones.
2236	 */
2237	clusters = 0;
2238	zeros = 0;
2239	for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
2240		if (test_bit(i, clustermap)) {
2241			clusters += 1 + zeros;
2242			zeros = 0;
2243		} else
2244			++zeros;
2245	}
2246
2247	return clusters;
2248}
2249
2250static int __cpuinitdata multi_checked;
2251static int __cpuinitdata multi;
2252
2253static int __cpuinit set_multi(const struct dmi_system_id *d)
2254{
2255	if (multi)
2256		return 0;
2257	pr_info("APIC: %s detected, Multi Chassis\n", d->ident);
2258	multi = 1;
2259	return 0;
2260}
2261
2262static const __cpuinitconst struct dmi_system_id multi_dmi_table[] = {
2263	{
2264		.callback = set_multi,
2265		.ident = "IBM System Summit2",
2266		.matches = {
2267			DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
2268			DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"),
2269		},
2270	},
2271	{}
2272};
2273
2274static void __cpuinit dmi_check_multi(void)
2275{
2276	if (multi_checked)
2277		return;
2278
2279	dmi_check_system(multi_dmi_table);
2280	multi_checked = 1;
2281}
2282
2283/*
2284 * apic_is_clustered_box() -- Check if we can expect good TSC
2285 *
2286 * Thus far, the major user of this is IBM's Summit2 series:
2287 * Clustered boxes may have unsynced TSC problems if they are
2288 * multi-chassis.
2289 * Use DMI to check them
2290 */
2291__cpuinit int apic_is_clustered_box(void)
2292{
2293	dmi_check_multi();
2294	if (multi)
2295		return 1;
2296
2297	if (!is_vsmp_box())
2298		return 0;
2299
2300	/*
2301	 * ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2302	 * not guaranteed to be synced between boards
2303	 */
2304	if (apic_cluster_num() > 1)
2305		return 1;
2306
2307	return 0;
2308}
2309#endif
2310
2311/*
2312 * APIC command line parameters
2313 */
2314static int __init setup_disableapic(char *arg)
2315{
2316	disable_apic = 1;
2317	setup_clear_cpu_cap(X86_FEATURE_APIC);
2318	return 0;
2319}
2320early_param("disableapic", setup_disableapic);
2321
2322/* same as disableapic, for compatibility */
2323static int __init setup_nolapic(char *arg)
2324{
2325	return setup_disableapic(arg);
2326}
2327early_param("nolapic", setup_nolapic);
2328
2329static int __init parse_lapic_timer_c2_ok(char *arg)
2330{
2331	local_apic_timer_c2_ok = 1;
2332	return 0;
2333}
2334early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
2335
2336static int __init parse_disable_apic_timer(char *arg)
2337{
2338	disable_apic_timer = 1;
2339	return 0;
2340}
2341early_param("noapictimer", parse_disable_apic_timer);
2342
2343static int __init parse_nolapic_timer(char *arg)
2344{
2345	disable_apic_timer = 1;
2346	return 0;
2347}
2348early_param("nolapic_timer", parse_nolapic_timer);
2349
2350static int __init apic_set_verbosity(char *arg)
2351{
2352	if (!arg)  {
2353#ifdef CONFIG_X86_64
2354		skip_ioapic_setup = 0;
2355		return 0;
2356#endif
2357		return -EINVAL;
2358	}
2359
2360	if (strcmp("debug", arg) == 0)
2361		apic_verbosity = APIC_DEBUG;
2362	else if (strcmp("verbose", arg) == 0)
2363		apic_verbosity = APIC_VERBOSE;
2364	else {
2365		pr_warning("APIC Verbosity level %s not recognised"
2366			" use apic=verbose or apic=debug\n", arg);
2367		return -EINVAL;
2368	}
2369
2370	return 0;
2371}
2372early_param("apic", apic_set_verbosity);
2373
2374static int __init lapic_insert_resource(void)
2375{
2376	if (!apic_phys)
2377		return -1;
2378
2379	/* Put local APIC into the resource map. */
2380	lapic_resource.start = apic_phys;
2381	lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
2382	insert_resource(&iomem_resource, &lapic_resource);
2383
2384	return 0;
2385}
2386
2387/*
2388 * need call insert after e820_reserve_resources()
2389 * that is using request_resource
2390 */
2391late_initcall(lapic_insert_resource);