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1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_PKO_DEFS_H__
29#define __CVMX_PKO_DEFS_H__
30
31#define CVMX_PKO_MEM_COUNT0 \
32 CVMX_ADD_IO_SEG(0x0001180050001080ull)
33#define CVMX_PKO_MEM_COUNT1 \
34 CVMX_ADD_IO_SEG(0x0001180050001088ull)
35#define CVMX_PKO_MEM_DEBUG0 \
36 CVMX_ADD_IO_SEG(0x0001180050001100ull)
37#define CVMX_PKO_MEM_DEBUG1 \
38 CVMX_ADD_IO_SEG(0x0001180050001108ull)
39#define CVMX_PKO_MEM_DEBUG10 \
40 CVMX_ADD_IO_SEG(0x0001180050001150ull)
41#define CVMX_PKO_MEM_DEBUG11 \
42 CVMX_ADD_IO_SEG(0x0001180050001158ull)
43#define CVMX_PKO_MEM_DEBUG12 \
44 CVMX_ADD_IO_SEG(0x0001180050001160ull)
45#define CVMX_PKO_MEM_DEBUG13 \
46 CVMX_ADD_IO_SEG(0x0001180050001168ull)
47#define CVMX_PKO_MEM_DEBUG14 \
48 CVMX_ADD_IO_SEG(0x0001180050001170ull)
49#define CVMX_PKO_MEM_DEBUG2 \
50 CVMX_ADD_IO_SEG(0x0001180050001110ull)
51#define CVMX_PKO_MEM_DEBUG3 \
52 CVMX_ADD_IO_SEG(0x0001180050001118ull)
53#define CVMX_PKO_MEM_DEBUG4 \
54 CVMX_ADD_IO_SEG(0x0001180050001120ull)
55#define CVMX_PKO_MEM_DEBUG5 \
56 CVMX_ADD_IO_SEG(0x0001180050001128ull)
57#define CVMX_PKO_MEM_DEBUG6 \
58 CVMX_ADD_IO_SEG(0x0001180050001130ull)
59#define CVMX_PKO_MEM_DEBUG7 \
60 CVMX_ADD_IO_SEG(0x0001180050001138ull)
61#define CVMX_PKO_MEM_DEBUG8 \
62 CVMX_ADD_IO_SEG(0x0001180050001140ull)
63#define CVMX_PKO_MEM_DEBUG9 \
64 CVMX_ADD_IO_SEG(0x0001180050001148ull)
65#define CVMX_PKO_MEM_PORT_PTRS \
66 CVMX_ADD_IO_SEG(0x0001180050001010ull)
67#define CVMX_PKO_MEM_PORT_QOS \
68 CVMX_ADD_IO_SEG(0x0001180050001018ull)
69#define CVMX_PKO_MEM_PORT_RATE0 \
70 CVMX_ADD_IO_SEG(0x0001180050001020ull)
71#define CVMX_PKO_MEM_PORT_RATE1 \
72 CVMX_ADD_IO_SEG(0x0001180050001028ull)
73#define CVMX_PKO_MEM_QUEUE_PTRS \
74 CVMX_ADD_IO_SEG(0x0001180050001000ull)
75#define CVMX_PKO_MEM_QUEUE_QOS \
76 CVMX_ADD_IO_SEG(0x0001180050001008ull)
77#define CVMX_PKO_REG_BIST_RESULT \
78 CVMX_ADD_IO_SEG(0x0001180050000080ull)
79#define CVMX_PKO_REG_CMD_BUF \
80 CVMX_ADD_IO_SEG(0x0001180050000010ull)
81#define CVMX_PKO_REG_CRC_CTLX(offset) \
82 CVMX_ADD_IO_SEG(0x0001180050000028ull + (((offset) & 1) * 8))
83#define CVMX_PKO_REG_CRC_ENABLE \
84 CVMX_ADD_IO_SEG(0x0001180050000020ull)
85#define CVMX_PKO_REG_CRC_IVX(offset) \
86 CVMX_ADD_IO_SEG(0x0001180050000038ull + (((offset) & 1) * 8))
87#define CVMX_PKO_REG_DEBUG0 \
88 CVMX_ADD_IO_SEG(0x0001180050000098ull)
89#define CVMX_PKO_REG_DEBUG1 \
90 CVMX_ADD_IO_SEG(0x00011800500000A0ull)
91#define CVMX_PKO_REG_DEBUG2 \
92 CVMX_ADD_IO_SEG(0x00011800500000A8ull)
93#define CVMX_PKO_REG_DEBUG3 \
94 CVMX_ADD_IO_SEG(0x00011800500000B0ull)
95#define CVMX_PKO_REG_ENGINE_INFLIGHT \
96 CVMX_ADD_IO_SEG(0x0001180050000050ull)
97#define CVMX_PKO_REG_ENGINE_THRESH \
98 CVMX_ADD_IO_SEG(0x0001180050000058ull)
99#define CVMX_PKO_REG_ERROR \
100 CVMX_ADD_IO_SEG(0x0001180050000088ull)
101#define CVMX_PKO_REG_FLAGS \
102 CVMX_ADD_IO_SEG(0x0001180050000000ull)
103#define CVMX_PKO_REG_GMX_PORT_MODE \
104 CVMX_ADD_IO_SEG(0x0001180050000018ull)
105#define CVMX_PKO_REG_INT_MASK \
106 CVMX_ADD_IO_SEG(0x0001180050000090ull)
107#define CVMX_PKO_REG_QUEUE_MODE \
108 CVMX_ADD_IO_SEG(0x0001180050000048ull)
109#define CVMX_PKO_REG_QUEUE_PTRS1 \
110 CVMX_ADD_IO_SEG(0x0001180050000100ull)
111#define CVMX_PKO_REG_READ_IDX \
112 CVMX_ADD_IO_SEG(0x0001180050000008ull)
113
114union cvmx_pko_mem_count0 {
115 uint64_t u64;
116 struct cvmx_pko_mem_count0_s {
117 uint64_t reserved_32_63:32;
118 uint64_t count:32;
119 } s;
120 struct cvmx_pko_mem_count0_s cn30xx;
121 struct cvmx_pko_mem_count0_s cn31xx;
122 struct cvmx_pko_mem_count0_s cn38xx;
123 struct cvmx_pko_mem_count0_s cn38xxp2;
124 struct cvmx_pko_mem_count0_s cn50xx;
125 struct cvmx_pko_mem_count0_s cn52xx;
126 struct cvmx_pko_mem_count0_s cn52xxp1;
127 struct cvmx_pko_mem_count0_s cn56xx;
128 struct cvmx_pko_mem_count0_s cn56xxp1;
129 struct cvmx_pko_mem_count0_s cn58xx;
130 struct cvmx_pko_mem_count0_s cn58xxp1;
131};
132
133union cvmx_pko_mem_count1 {
134 uint64_t u64;
135 struct cvmx_pko_mem_count1_s {
136 uint64_t reserved_48_63:16;
137 uint64_t count:48;
138 } s;
139 struct cvmx_pko_mem_count1_s cn30xx;
140 struct cvmx_pko_mem_count1_s cn31xx;
141 struct cvmx_pko_mem_count1_s cn38xx;
142 struct cvmx_pko_mem_count1_s cn38xxp2;
143 struct cvmx_pko_mem_count1_s cn50xx;
144 struct cvmx_pko_mem_count1_s cn52xx;
145 struct cvmx_pko_mem_count1_s cn52xxp1;
146 struct cvmx_pko_mem_count1_s cn56xx;
147 struct cvmx_pko_mem_count1_s cn56xxp1;
148 struct cvmx_pko_mem_count1_s cn58xx;
149 struct cvmx_pko_mem_count1_s cn58xxp1;
150};
151
152union cvmx_pko_mem_debug0 {
153 uint64_t u64;
154 struct cvmx_pko_mem_debug0_s {
155 uint64_t fau:28;
156 uint64_t cmd:14;
157 uint64_t segs:6;
158 uint64_t size:16;
159 } s;
160 struct cvmx_pko_mem_debug0_s cn30xx;
161 struct cvmx_pko_mem_debug0_s cn31xx;
162 struct cvmx_pko_mem_debug0_s cn38xx;
163 struct cvmx_pko_mem_debug0_s cn38xxp2;
164 struct cvmx_pko_mem_debug0_s cn50xx;
165 struct cvmx_pko_mem_debug0_s cn52xx;
166 struct cvmx_pko_mem_debug0_s cn52xxp1;
167 struct cvmx_pko_mem_debug0_s cn56xx;
168 struct cvmx_pko_mem_debug0_s cn56xxp1;
169 struct cvmx_pko_mem_debug0_s cn58xx;
170 struct cvmx_pko_mem_debug0_s cn58xxp1;
171};
172
173union cvmx_pko_mem_debug1 {
174 uint64_t u64;
175 struct cvmx_pko_mem_debug1_s {
176 uint64_t i:1;
177 uint64_t back:4;
178 uint64_t pool:3;
179 uint64_t size:16;
180 uint64_t ptr:40;
181 } s;
182 struct cvmx_pko_mem_debug1_s cn30xx;
183 struct cvmx_pko_mem_debug1_s cn31xx;
184 struct cvmx_pko_mem_debug1_s cn38xx;
185 struct cvmx_pko_mem_debug1_s cn38xxp2;
186 struct cvmx_pko_mem_debug1_s cn50xx;
187 struct cvmx_pko_mem_debug1_s cn52xx;
188 struct cvmx_pko_mem_debug1_s cn52xxp1;
189 struct cvmx_pko_mem_debug1_s cn56xx;
190 struct cvmx_pko_mem_debug1_s cn56xxp1;
191 struct cvmx_pko_mem_debug1_s cn58xx;
192 struct cvmx_pko_mem_debug1_s cn58xxp1;
193};
194
195union cvmx_pko_mem_debug10 {
196 uint64_t u64;
197 struct cvmx_pko_mem_debug10_s {
198 uint64_t reserved_0_63:64;
199 } s;
200 struct cvmx_pko_mem_debug10_cn30xx {
201 uint64_t fau:28;
202 uint64_t cmd:14;
203 uint64_t segs:6;
204 uint64_t size:16;
205 } cn30xx;
206 struct cvmx_pko_mem_debug10_cn30xx cn31xx;
207 struct cvmx_pko_mem_debug10_cn30xx cn38xx;
208 struct cvmx_pko_mem_debug10_cn30xx cn38xxp2;
209 struct cvmx_pko_mem_debug10_cn50xx {
210 uint64_t reserved_49_63:15;
211 uint64_t ptrs1:17;
212 uint64_t reserved_17_31:15;
213 uint64_t ptrs2:17;
214 } cn50xx;
215 struct cvmx_pko_mem_debug10_cn50xx cn52xx;
216 struct cvmx_pko_mem_debug10_cn50xx cn52xxp1;
217 struct cvmx_pko_mem_debug10_cn50xx cn56xx;
218 struct cvmx_pko_mem_debug10_cn50xx cn56xxp1;
219 struct cvmx_pko_mem_debug10_cn50xx cn58xx;
220 struct cvmx_pko_mem_debug10_cn50xx cn58xxp1;
221};
222
223union cvmx_pko_mem_debug11 {
224 uint64_t u64;
225 struct cvmx_pko_mem_debug11_s {
226 uint64_t i:1;
227 uint64_t back:4;
228 uint64_t pool:3;
229 uint64_t size:16;
230 uint64_t reserved_0_39:40;
231 } s;
232 struct cvmx_pko_mem_debug11_cn30xx {
233 uint64_t i:1;
234 uint64_t back:4;
235 uint64_t pool:3;
236 uint64_t size:16;
237 uint64_t ptr:40;
238 } cn30xx;
239 struct cvmx_pko_mem_debug11_cn30xx cn31xx;
240 struct cvmx_pko_mem_debug11_cn30xx cn38xx;
241 struct cvmx_pko_mem_debug11_cn30xx cn38xxp2;
242 struct cvmx_pko_mem_debug11_cn50xx {
243 uint64_t reserved_23_63:41;
244 uint64_t maj:1;
245 uint64_t uid:3;
246 uint64_t sop:1;
247 uint64_t len:1;
248 uint64_t chk:1;
249 uint64_t cnt:13;
250 uint64_t mod:3;
251 } cn50xx;
252 struct cvmx_pko_mem_debug11_cn50xx cn52xx;
253 struct cvmx_pko_mem_debug11_cn50xx cn52xxp1;
254 struct cvmx_pko_mem_debug11_cn50xx cn56xx;
255 struct cvmx_pko_mem_debug11_cn50xx cn56xxp1;
256 struct cvmx_pko_mem_debug11_cn50xx cn58xx;
257 struct cvmx_pko_mem_debug11_cn50xx cn58xxp1;
258};
259
260union cvmx_pko_mem_debug12 {
261 uint64_t u64;
262 struct cvmx_pko_mem_debug12_s {
263 uint64_t reserved_0_63:64;
264 } s;
265 struct cvmx_pko_mem_debug12_cn30xx {
266 uint64_t data:64;
267 } cn30xx;
268 struct cvmx_pko_mem_debug12_cn30xx cn31xx;
269 struct cvmx_pko_mem_debug12_cn30xx cn38xx;
270 struct cvmx_pko_mem_debug12_cn30xx cn38xxp2;
271 struct cvmx_pko_mem_debug12_cn50xx {
272 uint64_t fau:28;
273 uint64_t cmd:14;
274 uint64_t segs:6;
275 uint64_t size:16;
276 } cn50xx;
277 struct cvmx_pko_mem_debug12_cn50xx cn52xx;
278 struct cvmx_pko_mem_debug12_cn50xx cn52xxp1;
279 struct cvmx_pko_mem_debug12_cn50xx cn56xx;
280 struct cvmx_pko_mem_debug12_cn50xx cn56xxp1;
281 struct cvmx_pko_mem_debug12_cn50xx cn58xx;
282 struct cvmx_pko_mem_debug12_cn50xx cn58xxp1;
283};
284
285union cvmx_pko_mem_debug13 {
286 uint64_t u64;
287 struct cvmx_pko_mem_debug13_s {
288 uint64_t i:1;
289 uint64_t back:4;
290 uint64_t pool:3;
291 uint64_t reserved_0_55:56;
292 } s;
293 struct cvmx_pko_mem_debug13_cn30xx {
294 uint64_t reserved_51_63:13;
295 uint64_t widx:17;
296 uint64_t ridx2:17;
297 uint64_t widx2:17;
298 } cn30xx;
299 struct cvmx_pko_mem_debug13_cn30xx cn31xx;
300 struct cvmx_pko_mem_debug13_cn30xx cn38xx;
301 struct cvmx_pko_mem_debug13_cn30xx cn38xxp2;
302 struct cvmx_pko_mem_debug13_cn50xx {
303 uint64_t i:1;
304 uint64_t back:4;
305 uint64_t pool:3;
306 uint64_t size:16;
307 uint64_t ptr:40;
308 } cn50xx;
309 struct cvmx_pko_mem_debug13_cn50xx cn52xx;
310 struct cvmx_pko_mem_debug13_cn50xx cn52xxp1;
311 struct cvmx_pko_mem_debug13_cn50xx cn56xx;
312 struct cvmx_pko_mem_debug13_cn50xx cn56xxp1;
313 struct cvmx_pko_mem_debug13_cn50xx cn58xx;
314 struct cvmx_pko_mem_debug13_cn50xx cn58xxp1;
315};
316
317union cvmx_pko_mem_debug14 {
318 uint64_t u64;
319 struct cvmx_pko_mem_debug14_s {
320 uint64_t reserved_0_63:64;
321 } s;
322 struct cvmx_pko_mem_debug14_cn30xx {
323 uint64_t reserved_17_63:47;
324 uint64_t ridx:17;
325 } cn30xx;
326 struct cvmx_pko_mem_debug14_cn30xx cn31xx;
327 struct cvmx_pko_mem_debug14_cn30xx cn38xx;
328 struct cvmx_pko_mem_debug14_cn30xx cn38xxp2;
329 struct cvmx_pko_mem_debug14_cn52xx {
330 uint64_t data:64;
331 } cn52xx;
332 struct cvmx_pko_mem_debug14_cn52xx cn52xxp1;
333 struct cvmx_pko_mem_debug14_cn52xx cn56xx;
334 struct cvmx_pko_mem_debug14_cn52xx cn56xxp1;
335};
336
337union cvmx_pko_mem_debug2 {
338 uint64_t u64;
339 struct cvmx_pko_mem_debug2_s {
340 uint64_t i:1;
341 uint64_t back:4;
342 uint64_t pool:3;
343 uint64_t size:16;
344 uint64_t ptr:40;
345 } s;
346 struct cvmx_pko_mem_debug2_s cn30xx;
347 struct cvmx_pko_mem_debug2_s cn31xx;
348 struct cvmx_pko_mem_debug2_s cn38xx;
349 struct cvmx_pko_mem_debug2_s cn38xxp2;
350 struct cvmx_pko_mem_debug2_s cn50xx;
351 struct cvmx_pko_mem_debug2_s cn52xx;
352 struct cvmx_pko_mem_debug2_s cn52xxp1;
353 struct cvmx_pko_mem_debug2_s cn56xx;
354 struct cvmx_pko_mem_debug2_s cn56xxp1;
355 struct cvmx_pko_mem_debug2_s cn58xx;
356 struct cvmx_pko_mem_debug2_s cn58xxp1;
357};
358
359union cvmx_pko_mem_debug3 {
360 uint64_t u64;
361 struct cvmx_pko_mem_debug3_s {
362 uint64_t reserved_0_63:64;
363 } s;
364 struct cvmx_pko_mem_debug3_cn30xx {
365 uint64_t i:1;
366 uint64_t back:4;
367 uint64_t pool:3;
368 uint64_t size:16;
369 uint64_t ptr:40;
370 } cn30xx;
371 struct cvmx_pko_mem_debug3_cn30xx cn31xx;
372 struct cvmx_pko_mem_debug3_cn30xx cn38xx;
373 struct cvmx_pko_mem_debug3_cn30xx cn38xxp2;
374 struct cvmx_pko_mem_debug3_cn50xx {
375 uint64_t data:64;
376 } cn50xx;
377 struct cvmx_pko_mem_debug3_cn50xx cn52xx;
378 struct cvmx_pko_mem_debug3_cn50xx cn52xxp1;
379 struct cvmx_pko_mem_debug3_cn50xx cn56xx;
380 struct cvmx_pko_mem_debug3_cn50xx cn56xxp1;
381 struct cvmx_pko_mem_debug3_cn50xx cn58xx;
382 struct cvmx_pko_mem_debug3_cn50xx cn58xxp1;
383};
384
385union cvmx_pko_mem_debug4 {
386 uint64_t u64;
387 struct cvmx_pko_mem_debug4_s {
388 uint64_t reserved_0_63:64;
389 } s;
390 struct cvmx_pko_mem_debug4_cn30xx {
391 uint64_t data:64;
392 } cn30xx;
393 struct cvmx_pko_mem_debug4_cn30xx cn31xx;
394 struct cvmx_pko_mem_debug4_cn30xx cn38xx;
395 struct cvmx_pko_mem_debug4_cn30xx cn38xxp2;
396 struct cvmx_pko_mem_debug4_cn50xx {
397 uint64_t cmnd_segs:3;
398 uint64_t cmnd_siz:16;
399 uint64_t cmnd_off:6;
400 uint64_t uid:3;
401 uint64_t dread_sop:1;
402 uint64_t init_dwrite:1;
403 uint64_t chk_once:1;
404 uint64_t chk_mode:1;
405 uint64_t active:1;
406 uint64_t static_p:1;
407 uint64_t qos:3;
408 uint64_t qcb_ridx:5;
409 uint64_t qid_off_max:4;
410 uint64_t qid_off:4;
411 uint64_t qid_base:8;
412 uint64_t wait:1;
413 uint64_t minor:2;
414 uint64_t major:3;
415 } cn50xx;
416 struct cvmx_pko_mem_debug4_cn52xx {
417 uint64_t curr_siz:8;
418 uint64_t curr_off:16;
419 uint64_t cmnd_segs:6;
420 uint64_t cmnd_siz:16;
421 uint64_t cmnd_off:6;
422 uint64_t uid:2;
423 uint64_t dread_sop:1;
424 uint64_t init_dwrite:1;
425 uint64_t chk_once:1;
426 uint64_t chk_mode:1;
427 uint64_t wait:1;
428 uint64_t minor:2;
429 uint64_t major:3;
430 } cn52xx;
431 struct cvmx_pko_mem_debug4_cn52xx cn52xxp1;
432 struct cvmx_pko_mem_debug4_cn52xx cn56xx;
433 struct cvmx_pko_mem_debug4_cn52xx cn56xxp1;
434 struct cvmx_pko_mem_debug4_cn50xx cn58xx;
435 struct cvmx_pko_mem_debug4_cn50xx cn58xxp1;
436};
437
438union cvmx_pko_mem_debug5 {
439 uint64_t u64;
440 struct cvmx_pko_mem_debug5_s {
441 uint64_t reserved_0_63:64;
442 } s;
443 struct cvmx_pko_mem_debug5_cn30xx {
444 uint64_t dwri_mod:1;
445 uint64_t dwri_sop:1;
446 uint64_t dwri_len:1;
447 uint64_t dwri_cnt:13;
448 uint64_t cmnd_siz:16;
449 uint64_t uid:1;
450 uint64_t xfer_wor:1;
451 uint64_t xfer_dwr:1;
452 uint64_t cbuf_fre:1;
453 uint64_t reserved_27_27:1;
454 uint64_t chk_mode:1;
455 uint64_t active:1;
456 uint64_t qos:3;
457 uint64_t qcb_ridx:5;
458 uint64_t qid_off:3;
459 uint64_t qid_base:7;
460 uint64_t wait:1;
461 uint64_t minor:2;
462 uint64_t major:4;
463 } cn30xx;
464 struct cvmx_pko_mem_debug5_cn30xx cn31xx;
465 struct cvmx_pko_mem_debug5_cn30xx cn38xx;
466 struct cvmx_pko_mem_debug5_cn30xx cn38xxp2;
467 struct cvmx_pko_mem_debug5_cn50xx {
468 uint64_t curr_ptr:29;
469 uint64_t curr_siz:16;
470 uint64_t curr_off:16;
471 uint64_t cmnd_segs:3;
472 } cn50xx;
473 struct cvmx_pko_mem_debug5_cn52xx {
474 uint64_t reserved_54_63:10;
475 uint64_t nxt_inflt:6;
476 uint64_t curr_ptr:40;
477 uint64_t curr_siz:8;
478 } cn52xx;
479 struct cvmx_pko_mem_debug5_cn52xx cn52xxp1;
480 struct cvmx_pko_mem_debug5_cn52xx cn56xx;
481 struct cvmx_pko_mem_debug5_cn52xx cn56xxp1;
482 struct cvmx_pko_mem_debug5_cn50xx cn58xx;
483 struct cvmx_pko_mem_debug5_cn50xx cn58xxp1;
484};
485
486union cvmx_pko_mem_debug6 {
487 uint64_t u64;
488 struct cvmx_pko_mem_debug6_s {
489 uint64_t reserved_37_63:27;
490 uint64_t qid_offres:4;
491 uint64_t qid_offths:4;
492 uint64_t preempter:1;
493 uint64_t preemptee:1;
494 uint64_t preempted:1;
495 uint64_t active:1;
496 uint64_t statc:1;
497 uint64_t qos:3;
498 uint64_t qcb_ridx:5;
499 uint64_t qid_offmax:4;
500 uint64_t reserved_0_11:12;
501 } s;
502 struct cvmx_pko_mem_debug6_cn30xx {
503 uint64_t reserved_11_63:53;
504 uint64_t qid_offm:3;
505 uint64_t static_p:1;
506 uint64_t work_min:3;
507 uint64_t dwri_chk:1;
508 uint64_t dwri_uid:1;
509 uint64_t dwri_mod:2;
510 } cn30xx;
511 struct cvmx_pko_mem_debug6_cn30xx cn31xx;
512 struct cvmx_pko_mem_debug6_cn30xx cn38xx;
513 struct cvmx_pko_mem_debug6_cn30xx cn38xxp2;
514 struct cvmx_pko_mem_debug6_cn50xx {
515 uint64_t reserved_11_63:53;
516 uint64_t curr_ptr:11;
517 } cn50xx;
518 struct cvmx_pko_mem_debug6_cn52xx {
519 uint64_t reserved_37_63:27;
520 uint64_t qid_offres:4;
521 uint64_t qid_offths:4;
522 uint64_t preempter:1;
523 uint64_t preemptee:1;
524 uint64_t preempted:1;
525 uint64_t active:1;
526 uint64_t statc:1;
527 uint64_t qos:3;
528 uint64_t qcb_ridx:5;
529 uint64_t qid_offmax:4;
530 uint64_t qid_off:4;
531 uint64_t qid_base:8;
532 } cn52xx;
533 struct cvmx_pko_mem_debug6_cn52xx cn52xxp1;
534 struct cvmx_pko_mem_debug6_cn52xx cn56xx;
535 struct cvmx_pko_mem_debug6_cn52xx cn56xxp1;
536 struct cvmx_pko_mem_debug6_cn50xx cn58xx;
537 struct cvmx_pko_mem_debug6_cn50xx cn58xxp1;
538};
539
540union cvmx_pko_mem_debug7 {
541 uint64_t u64;
542 struct cvmx_pko_mem_debug7_s {
543 uint64_t qos:5;
544 uint64_t tail:1;
545 uint64_t reserved_0_57:58;
546 } s;
547 struct cvmx_pko_mem_debug7_cn30xx {
548 uint64_t reserved_58_63:6;
549 uint64_t dwb:9;
550 uint64_t start:33;
551 uint64_t size:16;
552 } cn30xx;
553 struct cvmx_pko_mem_debug7_cn30xx cn31xx;
554 struct cvmx_pko_mem_debug7_cn30xx cn38xx;
555 struct cvmx_pko_mem_debug7_cn30xx cn38xxp2;
556 struct cvmx_pko_mem_debug7_cn50xx {
557 uint64_t qos:5;
558 uint64_t tail:1;
559 uint64_t buf_siz:13;
560 uint64_t buf_ptr:33;
561 uint64_t qcb_widx:6;
562 uint64_t qcb_ridx:6;
563 } cn50xx;
564 struct cvmx_pko_mem_debug7_cn50xx cn52xx;
565 struct cvmx_pko_mem_debug7_cn50xx cn52xxp1;
566 struct cvmx_pko_mem_debug7_cn50xx cn56xx;
567 struct cvmx_pko_mem_debug7_cn50xx cn56xxp1;
568 struct cvmx_pko_mem_debug7_cn50xx cn58xx;
569 struct cvmx_pko_mem_debug7_cn50xx cn58xxp1;
570};
571
572union cvmx_pko_mem_debug8 {
573 uint64_t u64;
574 struct cvmx_pko_mem_debug8_s {
575 uint64_t reserved_59_63:5;
576 uint64_t tail:1;
577 uint64_t buf_siz:13;
578 uint64_t reserved_0_44:45;
579 } s;
580 struct cvmx_pko_mem_debug8_cn30xx {
581 uint64_t qos:5;
582 uint64_t tail:1;
583 uint64_t buf_siz:13;
584 uint64_t buf_ptr:33;
585 uint64_t qcb_widx:6;
586 uint64_t qcb_ridx:6;
587 } cn30xx;
588 struct cvmx_pko_mem_debug8_cn30xx cn31xx;
589 struct cvmx_pko_mem_debug8_cn30xx cn38xx;
590 struct cvmx_pko_mem_debug8_cn30xx cn38xxp2;
591 struct cvmx_pko_mem_debug8_cn50xx {
592 uint64_t reserved_28_63:36;
593 uint64_t doorbell:20;
594 uint64_t reserved_6_7:2;
595 uint64_t static_p:1;
596 uint64_t s_tail:1;
597 uint64_t static_q:1;
598 uint64_t qos:3;
599 } cn50xx;
600 struct cvmx_pko_mem_debug8_cn52xx {
601 uint64_t reserved_29_63:35;
602 uint64_t preempter:1;
603 uint64_t doorbell:20;
604 uint64_t reserved_7_7:1;
605 uint64_t preemptee:1;
606 uint64_t static_p:1;
607 uint64_t s_tail:1;
608 uint64_t static_q:1;
609 uint64_t qos:3;
610 } cn52xx;
611 struct cvmx_pko_mem_debug8_cn52xx cn52xxp1;
612 struct cvmx_pko_mem_debug8_cn52xx cn56xx;
613 struct cvmx_pko_mem_debug8_cn52xx cn56xxp1;
614 struct cvmx_pko_mem_debug8_cn50xx cn58xx;
615 struct cvmx_pko_mem_debug8_cn50xx cn58xxp1;
616};
617
618union cvmx_pko_mem_debug9 {
619 uint64_t u64;
620 struct cvmx_pko_mem_debug9_s {
621 uint64_t reserved_49_63:15;
622 uint64_t ptrs0:17;
623 uint64_t reserved_0_31:32;
624 } s;
625 struct cvmx_pko_mem_debug9_cn30xx {
626 uint64_t reserved_28_63:36;
627 uint64_t doorbell:20;
628 uint64_t reserved_5_7:3;
629 uint64_t s_tail:1;
630 uint64_t static_q:1;
631 uint64_t qos:3;
632 } cn30xx;
633 struct cvmx_pko_mem_debug9_cn30xx cn31xx;
634 struct cvmx_pko_mem_debug9_cn38xx {
635 uint64_t reserved_28_63:36;
636 uint64_t doorbell:20;
637 uint64_t reserved_6_7:2;
638 uint64_t static_p:1;
639 uint64_t s_tail:1;
640 uint64_t static_q:1;
641 uint64_t qos:3;
642 } cn38xx;
643 struct cvmx_pko_mem_debug9_cn38xx cn38xxp2;
644 struct cvmx_pko_mem_debug9_cn50xx {
645 uint64_t reserved_49_63:15;
646 uint64_t ptrs0:17;
647 uint64_t reserved_17_31:15;
648 uint64_t ptrs3:17;
649 } cn50xx;
650 struct cvmx_pko_mem_debug9_cn50xx cn52xx;
651 struct cvmx_pko_mem_debug9_cn50xx cn52xxp1;
652 struct cvmx_pko_mem_debug9_cn50xx cn56xx;
653 struct cvmx_pko_mem_debug9_cn50xx cn56xxp1;
654 struct cvmx_pko_mem_debug9_cn50xx cn58xx;
655 struct cvmx_pko_mem_debug9_cn50xx cn58xxp1;
656};
657
658union cvmx_pko_mem_port_ptrs {
659 uint64_t u64;
660 struct cvmx_pko_mem_port_ptrs_s {
661 uint64_t reserved_62_63:2;
662 uint64_t static_p:1;
663 uint64_t qos_mask:8;
664 uint64_t reserved_16_52:37;
665 uint64_t bp_port:6;
666 uint64_t eid:4;
667 uint64_t pid:6;
668 } s;
669 struct cvmx_pko_mem_port_ptrs_s cn52xx;
670 struct cvmx_pko_mem_port_ptrs_s cn52xxp1;
671 struct cvmx_pko_mem_port_ptrs_s cn56xx;
672 struct cvmx_pko_mem_port_ptrs_s cn56xxp1;
673};
674
675union cvmx_pko_mem_port_qos {
676 uint64_t u64;
677 struct cvmx_pko_mem_port_qos_s {
678 uint64_t reserved_61_63:3;
679 uint64_t qos_mask:8;
680 uint64_t reserved_10_52:43;
681 uint64_t eid:4;
682 uint64_t pid:6;
683 } s;
684 struct cvmx_pko_mem_port_qos_s cn52xx;
685 struct cvmx_pko_mem_port_qos_s cn52xxp1;
686 struct cvmx_pko_mem_port_qos_s cn56xx;
687 struct cvmx_pko_mem_port_qos_s cn56xxp1;
688};
689
690union cvmx_pko_mem_port_rate0 {
691 uint64_t u64;
692 struct cvmx_pko_mem_port_rate0_s {
693 uint64_t reserved_51_63:13;
694 uint64_t rate_word:19;
695 uint64_t rate_pkt:24;
696 uint64_t reserved_6_7:2;
697 uint64_t pid:6;
698 } s;
699 struct cvmx_pko_mem_port_rate0_s cn52xx;
700 struct cvmx_pko_mem_port_rate0_s cn52xxp1;
701 struct cvmx_pko_mem_port_rate0_s cn56xx;
702 struct cvmx_pko_mem_port_rate0_s cn56xxp1;
703};
704
705union cvmx_pko_mem_port_rate1 {
706 uint64_t u64;
707 struct cvmx_pko_mem_port_rate1_s {
708 uint64_t reserved_32_63:32;
709 uint64_t rate_lim:24;
710 uint64_t reserved_6_7:2;
711 uint64_t pid:6;
712 } s;
713 struct cvmx_pko_mem_port_rate1_s cn52xx;
714 struct cvmx_pko_mem_port_rate1_s cn52xxp1;
715 struct cvmx_pko_mem_port_rate1_s cn56xx;
716 struct cvmx_pko_mem_port_rate1_s cn56xxp1;
717};
718
719union cvmx_pko_mem_queue_ptrs {
720 uint64_t u64;
721 struct cvmx_pko_mem_queue_ptrs_s {
722 uint64_t s_tail:1;
723 uint64_t static_p:1;
724 uint64_t static_q:1;
725 uint64_t qos_mask:8;
726 uint64_t buf_ptr:36;
727 uint64_t tail:1;
728 uint64_t index:3;
729 uint64_t port:6;
730 uint64_t queue:7;
731 } s;
732 struct cvmx_pko_mem_queue_ptrs_s cn30xx;
733 struct cvmx_pko_mem_queue_ptrs_s cn31xx;
734 struct cvmx_pko_mem_queue_ptrs_s cn38xx;
735 struct cvmx_pko_mem_queue_ptrs_s cn38xxp2;
736 struct cvmx_pko_mem_queue_ptrs_s cn50xx;
737 struct cvmx_pko_mem_queue_ptrs_s cn52xx;
738 struct cvmx_pko_mem_queue_ptrs_s cn52xxp1;
739 struct cvmx_pko_mem_queue_ptrs_s cn56xx;
740 struct cvmx_pko_mem_queue_ptrs_s cn56xxp1;
741 struct cvmx_pko_mem_queue_ptrs_s cn58xx;
742 struct cvmx_pko_mem_queue_ptrs_s cn58xxp1;
743};
744
745union cvmx_pko_mem_queue_qos {
746 uint64_t u64;
747 struct cvmx_pko_mem_queue_qos_s {
748 uint64_t reserved_61_63:3;
749 uint64_t qos_mask:8;
750 uint64_t reserved_13_52:40;
751 uint64_t pid:6;
752 uint64_t qid:7;
753 } s;
754 struct cvmx_pko_mem_queue_qos_s cn30xx;
755 struct cvmx_pko_mem_queue_qos_s cn31xx;
756 struct cvmx_pko_mem_queue_qos_s cn38xx;
757 struct cvmx_pko_mem_queue_qos_s cn38xxp2;
758 struct cvmx_pko_mem_queue_qos_s cn50xx;
759 struct cvmx_pko_mem_queue_qos_s cn52xx;
760 struct cvmx_pko_mem_queue_qos_s cn52xxp1;
761 struct cvmx_pko_mem_queue_qos_s cn56xx;
762 struct cvmx_pko_mem_queue_qos_s cn56xxp1;
763 struct cvmx_pko_mem_queue_qos_s cn58xx;
764 struct cvmx_pko_mem_queue_qos_s cn58xxp1;
765};
766
767union cvmx_pko_reg_bist_result {
768 uint64_t u64;
769 struct cvmx_pko_reg_bist_result_s {
770 uint64_t reserved_0_63:64;
771 } s;
772 struct cvmx_pko_reg_bist_result_cn30xx {
773 uint64_t reserved_27_63:37;
774 uint64_t psb2:5;
775 uint64_t count:1;
776 uint64_t rif:1;
777 uint64_t wif:1;
778 uint64_t ncb:1;
779 uint64_t out:1;
780 uint64_t crc:1;
781 uint64_t chk:1;
782 uint64_t qsb:2;
783 uint64_t qcb:2;
784 uint64_t pdb:4;
785 uint64_t psb:7;
786 } cn30xx;
787 struct cvmx_pko_reg_bist_result_cn30xx cn31xx;
788 struct cvmx_pko_reg_bist_result_cn30xx cn38xx;
789 struct cvmx_pko_reg_bist_result_cn30xx cn38xxp2;
790 struct cvmx_pko_reg_bist_result_cn50xx {
791 uint64_t reserved_33_63:31;
792 uint64_t csr:1;
793 uint64_t iob:1;
794 uint64_t out_crc:1;
795 uint64_t out_ctl:3;
796 uint64_t out_sta:1;
797 uint64_t out_wif:1;
798 uint64_t prt_chk:3;
799 uint64_t prt_nxt:1;
800 uint64_t prt_psb:6;
801 uint64_t ncb_inb:2;
802 uint64_t prt_qcb:2;
803 uint64_t prt_qsb:3;
804 uint64_t dat_dat:4;
805 uint64_t dat_ptr:4;
806 } cn50xx;
807 struct cvmx_pko_reg_bist_result_cn52xx {
808 uint64_t reserved_35_63:29;
809 uint64_t csr:1;
810 uint64_t iob:1;
811 uint64_t out_dat:1;
812 uint64_t out_ctl:3;
813 uint64_t out_sta:1;
814 uint64_t out_wif:1;
815 uint64_t prt_chk:3;
816 uint64_t prt_nxt:1;
817 uint64_t prt_psb:8;
818 uint64_t ncb_inb:2;
819 uint64_t prt_qcb:2;
820 uint64_t prt_qsb:3;
821 uint64_t prt_ctl:2;
822 uint64_t dat_dat:2;
823 uint64_t dat_ptr:4;
824 } cn52xx;
825 struct cvmx_pko_reg_bist_result_cn52xx cn52xxp1;
826 struct cvmx_pko_reg_bist_result_cn52xx cn56xx;
827 struct cvmx_pko_reg_bist_result_cn52xx cn56xxp1;
828 struct cvmx_pko_reg_bist_result_cn50xx cn58xx;
829 struct cvmx_pko_reg_bist_result_cn50xx cn58xxp1;
830};
831
832union cvmx_pko_reg_cmd_buf {
833 uint64_t u64;
834 struct cvmx_pko_reg_cmd_buf_s {
835 uint64_t reserved_23_63:41;
836 uint64_t pool:3;
837 uint64_t reserved_13_19:7;
838 uint64_t size:13;
839 } s;
840 struct cvmx_pko_reg_cmd_buf_s cn30xx;
841 struct cvmx_pko_reg_cmd_buf_s cn31xx;
842 struct cvmx_pko_reg_cmd_buf_s cn38xx;
843 struct cvmx_pko_reg_cmd_buf_s cn38xxp2;
844 struct cvmx_pko_reg_cmd_buf_s cn50xx;
845 struct cvmx_pko_reg_cmd_buf_s cn52xx;
846 struct cvmx_pko_reg_cmd_buf_s cn52xxp1;
847 struct cvmx_pko_reg_cmd_buf_s cn56xx;
848 struct cvmx_pko_reg_cmd_buf_s cn56xxp1;
849 struct cvmx_pko_reg_cmd_buf_s cn58xx;
850 struct cvmx_pko_reg_cmd_buf_s cn58xxp1;
851};
852
853union cvmx_pko_reg_crc_ctlx {
854 uint64_t u64;
855 struct cvmx_pko_reg_crc_ctlx_s {
856 uint64_t reserved_2_63:62;
857 uint64_t invres:1;
858 uint64_t refin:1;
859 } s;
860 struct cvmx_pko_reg_crc_ctlx_s cn38xx;
861 struct cvmx_pko_reg_crc_ctlx_s cn38xxp2;
862 struct cvmx_pko_reg_crc_ctlx_s cn58xx;
863 struct cvmx_pko_reg_crc_ctlx_s cn58xxp1;
864};
865
866union cvmx_pko_reg_crc_enable {
867 uint64_t u64;
868 struct cvmx_pko_reg_crc_enable_s {
869 uint64_t reserved_32_63:32;
870 uint64_t enable:32;
871 } s;
872 struct cvmx_pko_reg_crc_enable_s cn38xx;
873 struct cvmx_pko_reg_crc_enable_s cn38xxp2;
874 struct cvmx_pko_reg_crc_enable_s cn58xx;
875 struct cvmx_pko_reg_crc_enable_s cn58xxp1;
876};
877
878union cvmx_pko_reg_crc_ivx {
879 uint64_t u64;
880 struct cvmx_pko_reg_crc_ivx_s {
881 uint64_t reserved_32_63:32;
882 uint64_t iv:32;
883 } s;
884 struct cvmx_pko_reg_crc_ivx_s cn38xx;
885 struct cvmx_pko_reg_crc_ivx_s cn38xxp2;
886 struct cvmx_pko_reg_crc_ivx_s cn58xx;
887 struct cvmx_pko_reg_crc_ivx_s cn58xxp1;
888};
889
890union cvmx_pko_reg_debug0 {
891 uint64_t u64;
892 struct cvmx_pko_reg_debug0_s {
893 uint64_t asserts:64;
894 } s;
895 struct cvmx_pko_reg_debug0_cn30xx {
896 uint64_t reserved_17_63:47;
897 uint64_t asserts:17;
898 } cn30xx;
899 struct cvmx_pko_reg_debug0_cn30xx cn31xx;
900 struct cvmx_pko_reg_debug0_cn30xx cn38xx;
901 struct cvmx_pko_reg_debug0_cn30xx cn38xxp2;
902 struct cvmx_pko_reg_debug0_s cn50xx;
903 struct cvmx_pko_reg_debug0_s cn52xx;
904 struct cvmx_pko_reg_debug0_s cn52xxp1;
905 struct cvmx_pko_reg_debug0_s cn56xx;
906 struct cvmx_pko_reg_debug0_s cn56xxp1;
907 struct cvmx_pko_reg_debug0_s cn58xx;
908 struct cvmx_pko_reg_debug0_s cn58xxp1;
909};
910
911union cvmx_pko_reg_debug1 {
912 uint64_t u64;
913 struct cvmx_pko_reg_debug1_s {
914 uint64_t asserts:64;
915 } s;
916 struct cvmx_pko_reg_debug1_s cn50xx;
917 struct cvmx_pko_reg_debug1_s cn52xx;
918 struct cvmx_pko_reg_debug1_s cn52xxp1;
919 struct cvmx_pko_reg_debug1_s cn56xx;
920 struct cvmx_pko_reg_debug1_s cn56xxp1;
921 struct cvmx_pko_reg_debug1_s cn58xx;
922 struct cvmx_pko_reg_debug1_s cn58xxp1;
923};
924
925union cvmx_pko_reg_debug2 {
926 uint64_t u64;
927 struct cvmx_pko_reg_debug2_s {
928 uint64_t asserts:64;
929 } s;
930 struct cvmx_pko_reg_debug2_s cn50xx;
931 struct cvmx_pko_reg_debug2_s cn52xx;
932 struct cvmx_pko_reg_debug2_s cn52xxp1;
933 struct cvmx_pko_reg_debug2_s cn56xx;
934 struct cvmx_pko_reg_debug2_s cn56xxp1;
935 struct cvmx_pko_reg_debug2_s cn58xx;
936 struct cvmx_pko_reg_debug2_s cn58xxp1;
937};
938
939union cvmx_pko_reg_debug3 {
940 uint64_t u64;
941 struct cvmx_pko_reg_debug3_s {
942 uint64_t asserts:64;
943 } s;
944 struct cvmx_pko_reg_debug3_s cn50xx;
945 struct cvmx_pko_reg_debug3_s cn52xx;
946 struct cvmx_pko_reg_debug3_s cn52xxp1;
947 struct cvmx_pko_reg_debug3_s cn56xx;
948 struct cvmx_pko_reg_debug3_s cn56xxp1;
949 struct cvmx_pko_reg_debug3_s cn58xx;
950 struct cvmx_pko_reg_debug3_s cn58xxp1;
951};
952
953union cvmx_pko_reg_engine_inflight {
954 uint64_t u64;
955 struct cvmx_pko_reg_engine_inflight_s {
956 uint64_t reserved_40_63:24;
957 uint64_t engine9:4;
958 uint64_t engine8:4;
959 uint64_t engine7:4;
960 uint64_t engine6:4;
961 uint64_t engine5:4;
962 uint64_t engine4:4;
963 uint64_t engine3:4;
964 uint64_t engine2:4;
965 uint64_t engine1:4;
966 uint64_t engine0:4;
967 } s;
968 struct cvmx_pko_reg_engine_inflight_s cn52xx;
969 struct cvmx_pko_reg_engine_inflight_s cn52xxp1;
970 struct cvmx_pko_reg_engine_inflight_s cn56xx;
971 struct cvmx_pko_reg_engine_inflight_s cn56xxp1;
972};
973
974union cvmx_pko_reg_engine_thresh {
975 uint64_t u64;
976 struct cvmx_pko_reg_engine_thresh_s {
977 uint64_t reserved_10_63:54;
978 uint64_t mask:10;
979 } s;
980 struct cvmx_pko_reg_engine_thresh_s cn52xx;
981 struct cvmx_pko_reg_engine_thresh_s cn52xxp1;
982 struct cvmx_pko_reg_engine_thresh_s cn56xx;
983 struct cvmx_pko_reg_engine_thresh_s cn56xxp1;
984};
985
986union cvmx_pko_reg_error {
987 uint64_t u64;
988 struct cvmx_pko_reg_error_s {
989 uint64_t reserved_3_63:61;
990 uint64_t currzero:1;
991 uint64_t doorbell:1;
992 uint64_t parity:1;
993 } s;
994 struct cvmx_pko_reg_error_cn30xx {
995 uint64_t reserved_2_63:62;
996 uint64_t doorbell:1;
997 uint64_t parity:1;
998 } cn30xx;
999 struct cvmx_pko_reg_error_cn30xx cn31xx;
1000 struct cvmx_pko_reg_error_cn30xx cn38xx;
1001 struct cvmx_pko_reg_error_cn30xx cn38xxp2;
1002 struct cvmx_pko_reg_error_s cn50xx;
1003 struct cvmx_pko_reg_error_s cn52xx;
1004 struct cvmx_pko_reg_error_s cn52xxp1;
1005 struct cvmx_pko_reg_error_s cn56xx;
1006 struct cvmx_pko_reg_error_s cn56xxp1;
1007 struct cvmx_pko_reg_error_s cn58xx;
1008 struct cvmx_pko_reg_error_s cn58xxp1;
1009};
1010
1011union cvmx_pko_reg_flags {
1012 uint64_t u64;
1013 struct cvmx_pko_reg_flags_s {
1014 uint64_t reserved_4_63:60;
1015 uint64_t reset:1;
1016 uint64_t store_be:1;
1017 uint64_t ena_dwb:1;
1018 uint64_t ena_pko:1;
1019 } s;
1020 struct cvmx_pko_reg_flags_s cn30xx;
1021 struct cvmx_pko_reg_flags_s cn31xx;
1022 struct cvmx_pko_reg_flags_s cn38xx;
1023 struct cvmx_pko_reg_flags_s cn38xxp2;
1024 struct cvmx_pko_reg_flags_s cn50xx;
1025 struct cvmx_pko_reg_flags_s cn52xx;
1026 struct cvmx_pko_reg_flags_s cn52xxp1;
1027 struct cvmx_pko_reg_flags_s cn56xx;
1028 struct cvmx_pko_reg_flags_s cn56xxp1;
1029 struct cvmx_pko_reg_flags_s cn58xx;
1030 struct cvmx_pko_reg_flags_s cn58xxp1;
1031};
1032
1033union cvmx_pko_reg_gmx_port_mode {
1034 uint64_t u64;
1035 struct cvmx_pko_reg_gmx_port_mode_s {
1036 uint64_t reserved_6_63:58;
1037 uint64_t mode1:3;
1038 uint64_t mode0:3;
1039 } s;
1040 struct cvmx_pko_reg_gmx_port_mode_s cn30xx;
1041 struct cvmx_pko_reg_gmx_port_mode_s cn31xx;
1042 struct cvmx_pko_reg_gmx_port_mode_s cn38xx;
1043 struct cvmx_pko_reg_gmx_port_mode_s cn38xxp2;
1044 struct cvmx_pko_reg_gmx_port_mode_s cn50xx;
1045 struct cvmx_pko_reg_gmx_port_mode_s cn52xx;
1046 struct cvmx_pko_reg_gmx_port_mode_s cn52xxp1;
1047 struct cvmx_pko_reg_gmx_port_mode_s cn56xx;
1048 struct cvmx_pko_reg_gmx_port_mode_s cn56xxp1;
1049 struct cvmx_pko_reg_gmx_port_mode_s cn58xx;
1050 struct cvmx_pko_reg_gmx_port_mode_s cn58xxp1;
1051};
1052
1053union cvmx_pko_reg_int_mask {
1054 uint64_t u64;
1055 struct cvmx_pko_reg_int_mask_s {
1056 uint64_t reserved_3_63:61;
1057 uint64_t currzero:1;
1058 uint64_t doorbell:1;
1059 uint64_t parity:1;
1060 } s;
1061 struct cvmx_pko_reg_int_mask_cn30xx {
1062 uint64_t reserved_2_63:62;
1063 uint64_t doorbell:1;
1064 uint64_t parity:1;
1065 } cn30xx;
1066 struct cvmx_pko_reg_int_mask_cn30xx cn31xx;
1067 struct cvmx_pko_reg_int_mask_cn30xx cn38xx;
1068 struct cvmx_pko_reg_int_mask_cn30xx cn38xxp2;
1069 struct cvmx_pko_reg_int_mask_s cn50xx;
1070 struct cvmx_pko_reg_int_mask_s cn52xx;
1071 struct cvmx_pko_reg_int_mask_s cn52xxp1;
1072 struct cvmx_pko_reg_int_mask_s cn56xx;
1073 struct cvmx_pko_reg_int_mask_s cn56xxp1;
1074 struct cvmx_pko_reg_int_mask_s cn58xx;
1075 struct cvmx_pko_reg_int_mask_s cn58xxp1;
1076};
1077
1078union cvmx_pko_reg_queue_mode {
1079 uint64_t u64;
1080 struct cvmx_pko_reg_queue_mode_s {
1081 uint64_t reserved_2_63:62;
1082 uint64_t mode:2;
1083 } s;
1084 struct cvmx_pko_reg_queue_mode_s cn30xx;
1085 struct cvmx_pko_reg_queue_mode_s cn31xx;
1086 struct cvmx_pko_reg_queue_mode_s cn38xx;
1087 struct cvmx_pko_reg_queue_mode_s cn38xxp2;
1088 struct cvmx_pko_reg_queue_mode_s cn50xx;
1089 struct cvmx_pko_reg_queue_mode_s cn52xx;
1090 struct cvmx_pko_reg_queue_mode_s cn52xxp1;
1091 struct cvmx_pko_reg_queue_mode_s cn56xx;
1092 struct cvmx_pko_reg_queue_mode_s cn56xxp1;
1093 struct cvmx_pko_reg_queue_mode_s cn58xx;
1094 struct cvmx_pko_reg_queue_mode_s cn58xxp1;
1095};
1096
1097union cvmx_pko_reg_queue_ptrs1 {
1098 uint64_t u64;
1099 struct cvmx_pko_reg_queue_ptrs1_s {
1100 uint64_t reserved_2_63:62;
1101 uint64_t idx3:1;
1102 uint64_t qid7:1;
1103 } s;
1104 struct cvmx_pko_reg_queue_ptrs1_s cn50xx;
1105 struct cvmx_pko_reg_queue_ptrs1_s cn52xx;
1106 struct cvmx_pko_reg_queue_ptrs1_s cn52xxp1;
1107 struct cvmx_pko_reg_queue_ptrs1_s cn56xx;
1108 struct cvmx_pko_reg_queue_ptrs1_s cn56xxp1;
1109 struct cvmx_pko_reg_queue_ptrs1_s cn58xx;
1110 struct cvmx_pko_reg_queue_ptrs1_s cn58xxp1;
1111};
1112
1113union cvmx_pko_reg_read_idx {
1114 uint64_t u64;
1115 struct cvmx_pko_reg_read_idx_s {
1116 uint64_t reserved_16_63:48;
1117 uint64_t inc:8;
1118 uint64_t index:8;
1119 } s;
1120 struct cvmx_pko_reg_read_idx_s cn30xx;
1121 struct cvmx_pko_reg_read_idx_s cn31xx;
1122 struct cvmx_pko_reg_read_idx_s cn38xx;
1123 struct cvmx_pko_reg_read_idx_s cn38xxp2;
1124 struct cvmx_pko_reg_read_idx_s cn50xx;
1125 struct cvmx_pko_reg_read_idx_s cn52xx;
1126 struct cvmx_pko_reg_read_idx_s cn52xxp1;
1127 struct cvmx_pko_reg_read_idx_s cn56xx;
1128 struct cvmx_pko_reg_read_idx_s cn56xxp1;
1129 struct cvmx_pko_reg_read_idx_s cn58xx;
1130 struct cvmx_pko_reg_read_idx_s cn58xxp1;
1131};
1132
1133#endif