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1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2011 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_PEMX_DEFS_H__
29#define __CVMX_PEMX_DEFS_H__
30
31#define CVMX_PEMX_BAR1_INDEXX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C00000A8ull) + (((offset) & 15) + ((block_id) & 1) * 0x200000ull) * 8)
32#define CVMX_PEMX_BAR2_MASK(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000130ull) + ((block_id) & 1) * 0x1000000ull)
33#define CVMX_PEMX_BAR_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000128ull) + ((block_id) & 1) * 0x1000000ull)
34#define CVMX_PEMX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000018ull) + ((block_id) & 1) * 0x1000000ull)
35#define CVMX_PEMX_BIST_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000420ull) + ((block_id) & 1) * 0x1000000ull)
36#define CVMX_PEMX_CFG_RD(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000030ull) + ((block_id) & 1) * 0x1000000ull)
37#define CVMX_PEMX_CFG_WR(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000028ull) + ((block_id) & 1) * 0x1000000ull)
38#define CVMX_PEMX_CPL_LUT_VALID(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000098ull) + ((block_id) & 1) * 0x1000000ull)
39#define CVMX_PEMX_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000000ull) + ((block_id) & 1) * 0x1000000ull)
40#define CVMX_PEMX_DBG_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000008ull) + ((block_id) & 1) * 0x1000000ull)
41#define CVMX_PEMX_DBG_INFO_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800C00000A0ull) + ((block_id) & 1) * 0x1000000ull)
42#define CVMX_PEMX_DIAG_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000020ull) + ((block_id) & 1) * 0x1000000ull)
43#define CVMX_PEMX_INB_READ_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000138ull) + ((block_id) & 1) * 0x1000000ull)
44#define CVMX_PEMX_INT_ENB(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000410ull) + ((block_id) & 1) * 0x1000000ull)
45#define CVMX_PEMX_INT_ENB_INT(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000418ull) + ((block_id) & 1) * 0x1000000ull)
46#define CVMX_PEMX_INT_SUM(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000408ull) + ((block_id) & 1) * 0x1000000ull)
47#define CVMX_PEMX_P2N_BAR0_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000080ull) + ((block_id) & 1) * 0x1000000ull)
48#define CVMX_PEMX_P2N_BAR1_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000088ull) + ((block_id) & 1) * 0x1000000ull)
49#define CVMX_PEMX_P2N_BAR2_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000090ull) + ((block_id) & 1) * 0x1000000ull)
50#define CVMX_PEMX_P2P_BARX_END(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16)
51#define CVMX_PEMX_P2P_BARX_START(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C0000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16)
52#define CVMX_PEMX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000038ull) + ((block_id) & 1) * 0x1000000ull)
53
54union cvmx_pemx_bar1_indexx {
55 uint64_t u64;
56 struct cvmx_pemx_bar1_indexx_s {
57 uint64_t reserved_20_63:44;
58 uint64_t addr_idx:16;
59 uint64_t ca:1;
60 uint64_t end_swp:2;
61 uint64_t addr_v:1;
62 } s;
63 struct cvmx_pemx_bar1_indexx_s cn61xx;
64 struct cvmx_pemx_bar1_indexx_s cn63xx;
65 struct cvmx_pemx_bar1_indexx_s cn63xxp1;
66 struct cvmx_pemx_bar1_indexx_s cn66xx;
67 struct cvmx_pemx_bar1_indexx_s cn68xx;
68 struct cvmx_pemx_bar1_indexx_s cn68xxp1;
69};
70
71union cvmx_pemx_bar2_mask {
72 uint64_t u64;
73 struct cvmx_pemx_bar2_mask_s {
74 uint64_t reserved_38_63:26;
75 uint64_t mask:35;
76 uint64_t reserved_0_2:3;
77 } s;
78 struct cvmx_pemx_bar2_mask_s cn61xx;
79 struct cvmx_pemx_bar2_mask_s cn66xx;
80 struct cvmx_pemx_bar2_mask_s cn68xx;
81 struct cvmx_pemx_bar2_mask_s cn68xxp1;
82};
83
84union cvmx_pemx_bar_ctl {
85 uint64_t u64;
86 struct cvmx_pemx_bar_ctl_s {
87 uint64_t reserved_7_63:57;
88 uint64_t bar1_siz:3;
89 uint64_t bar2_enb:1;
90 uint64_t bar2_esx:2;
91 uint64_t bar2_cax:1;
92 } s;
93 struct cvmx_pemx_bar_ctl_s cn61xx;
94 struct cvmx_pemx_bar_ctl_s cn63xx;
95 struct cvmx_pemx_bar_ctl_s cn63xxp1;
96 struct cvmx_pemx_bar_ctl_s cn66xx;
97 struct cvmx_pemx_bar_ctl_s cn68xx;
98 struct cvmx_pemx_bar_ctl_s cn68xxp1;
99};
100
101union cvmx_pemx_bist_status {
102 uint64_t u64;
103 struct cvmx_pemx_bist_status_s {
104 uint64_t reserved_8_63:56;
105 uint64_t retry:1;
106 uint64_t rqdata0:1;
107 uint64_t rqdata1:1;
108 uint64_t rqdata2:1;
109 uint64_t rqdata3:1;
110 uint64_t rqhdr1:1;
111 uint64_t rqhdr0:1;
112 uint64_t sot:1;
113 } s;
114 struct cvmx_pemx_bist_status_s cn61xx;
115 struct cvmx_pemx_bist_status_s cn63xx;
116 struct cvmx_pemx_bist_status_s cn63xxp1;
117 struct cvmx_pemx_bist_status_s cn66xx;
118 struct cvmx_pemx_bist_status_s cn68xx;
119 struct cvmx_pemx_bist_status_s cn68xxp1;
120};
121
122union cvmx_pemx_bist_status2 {
123 uint64_t u64;
124 struct cvmx_pemx_bist_status2_s {
125 uint64_t reserved_10_63:54;
126 uint64_t e2p_cpl:1;
127 uint64_t e2p_n:1;
128 uint64_t e2p_p:1;
129 uint64_t peai_p2e:1;
130 uint64_t pef_tpf1:1;
131 uint64_t pef_tpf0:1;
132 uint64_t pef_tnf:1;
133 uint64_t pef_tcf1:1;
134 uint64_t pef_tc0:1;
135 uint64_t ppf:1;
136 } s;
137 struct cvmx_pemx_bist_status2_s cn61xx;
138 struct cvmx_pemx_bist_status2_s cn63xx;
139 struct cvmx_pemx_bist_status2_s cn63xxp1;
140 struct cvmx_pemx_bist_status2_s cn66xx;
141 struct cvmx_pemx_bist_status2_s cn68xx;
142 struct cvmx_pemx_bist_status2_s cn68xxp1;
143};
144
145union cvmx_pemx_cfg_rd {
146 uint64_t u64;
147 struct cvmx_pemx_cfg_rd_s {
148 uint64_t data:32;
149 uint64_t addr:32;
150 } s;
151 struct cvmx_pemx_cfg_rd_s cn61xx;
152 struct cvmx_pemx_cfg_rd_s cn63xx;
153 struct cvmx_pemx_cfg_rd_s cn63xxp1;
154 struct cvmx_pemx_cfg_rd_s cn66xx;
155 struct cvmx_pemx_cfg_rd_s cn68xx;
156 struct cvmx_pemx_cfg_rd_s cn68xxp1;
157};
158
159union cvmx_pemx_cfg_wr {
160 uint64_t u64;
161 struct cvmx_pemx_cfg_wr_s {
162 uint64_t data:32;
163 uint64_t addr:32;
164 } s;
165 struct cvmx_pemx_cfg_wr_s cn61xx;
166 struct cvmx_pemx_cfg_wr_s cn63xx;
167 struct cvmx_pemx_cfg_wr_s cn63xxp1;
168 struct cvmx_pemx_cfg_wr_s cn66xx;
169 struct cvmx_pemx_cfg_wr_s cn68xx;
170 struct cvmx_pemx_cfg_wr_s cn68xxp1;
171};
172
173union cvmx_pemx_cpl_lut_valid {
174 uint64_t u64;
175 struct cvmx_pemx_cpl_lut_valid_s {
176 uint64_t reserved_32_63:32;
177 uint64_t tag:32;
178 } s;
179 struct cvmx_pemx_cpl_lut_valid_s cn61xx;
180 struct cvmx_pemx_cpl_lut_valid_s cn63xx;
181 struct cvmx_pemx_cpl_lut_valid_s cn63xxp1;
182 struct cvmx_pemx_cpl_lut_valid_s cn66xx;
183 struct cvmx_pemx_cpl_lut_valid_s cn68xx;
184 struct cvmx_pemx_cpl_lut_valid_s cn68xxp1;
185};
186
187union cvmx_pemx_ctl_status {
188 uint64_t u64;
189 struct cvmx_pemx_ctl_status_s {
190 uint64_t reserved_48_63:16;
191 uint64_t auto_sd:1;
192 uint64_t dnum:5;
193 uint64_t pbus:8;
194 uint64_t reserved_32_33:2;
195 uint64_t cfg_rtry:16;
196 uint64_t reserved_12_15:4;
197 uint64_t pm_xtoff:1;
198 uint64_t pm_xpme:1;
199 uint64_t ob_p_cmd:1;
200 uint64_t reserved_7_8:2;
201 uint64_t nf_ecrc:1;
202 uint64_t dly_one:1;
203 uint64_t lnk_enb:1;
204 uint64_t ro_ctlp:1;
205 uint64_t fast_lm:1;
206 uint64_t inv_ecrc:1;
207 uint64_t inv_lcrc:1;
208 } s;
209 struct cvmx_pemx_ctl_status_s cn61xx;
210 struct cvmx_pemx_ctl_status_s cn63xx;
211 struct cvmx_pemx_ctl_status_s cn63xxp1;
212 struct cvmx_pemx_ctl_status_s cn66xx;
213 struct cvmx_pemx_ctl_status_s cn68xx;
214 struct cvmx_pemx_ctl_status_s cn68xxp1;
215};
216
217union cvmx_pemx_dbg_info {
218 uint64_t u64;
219 struct cvmx_pemx_dbg_info_s {
220 uint64_t reserved_31_63:33;
221 uint64_t ecrc_e:1;
222 uint64_t rawwpp:1;
223 uint64_t racpp:1;
224 uint64_t ramtlp:1;
225 uint64_t rarwdns:1;
226 uint64_t caar:1;
227 uint64_t racca:1;
228 uint64_t racur:1;
229 uint64_t rauc:1;
230 uint64_t rqo:1;
231 uint64_t fcuv:1;
232 uint64_t rpe:1;
233 uint64_t fcpvwt:1;
234 uint64_t dpeoosd:1;
235 uint64_t rtwdle:1;
236 uint64_t rdwdle:1;
237 uint64_t mre:1;
238 uint64_t rte:1;
239 uint64_t acto:1;
240 uint64_t rvdm:1;
241 uint64_t rumep:1;
242 uint64_t rptamrc:1;
243 uint64_t rpmerc:1;
244 uint64_t rfemrc:1;
245 uint64_t rnfemrc:1;
246 uint64_t rcemrc:1;
247 uint64_t rpoison:1;
248 uint64_t recrce:1;
249 uint64_t rtlplle:1;
250 uint64_t rtlpmal:1;
251 uint64_t spoison:1;
252 } s;
253 struct cvmx_pemx_dbg_info_s cn61xx;
254 struct cvmx_pemx_dbg_info_s cn63xx;
255 struct cvmx_pemx_dbg_info_s cn63xxp1;
256 struct cvmx_pemx_dbg_info_s cn66xx;
257 struct cvmx_pemx_dbg_info_s cn68xx;
258 struct cvmx_pemx_dbg_info_s cn68xxp1;
259};
260
261union cvmx_pemx_dbg_info_en {
262 uint64_t u64;
263 struct cvmx_pemx_dbg_info_en_s {
264 uint64_t reserved_31_63:33;
265 uint64_t ecrc_e:1;
266 uint64_t rawwpp:1;
267 uint64_t racpp:1;
268 uint64_t ramtlp:1;
269 uint64_t rarwdns:1;
270 uint64_t caar:1;
271 uint64_t racca:1;
272 uint64_t racur:1;
273 uint64_t rauc:1;
274 uint64_t rqo:1;
275 uint64_t fcuv:1;
276 uint64_t rpe:1;
277 uint64_t fcpvwt:1;
278 uint64_t dpeoosd:1;
279 uint64_t rtwdle:1;
280 uint64_t rdwdle:1;
281 uint64_t mre:1;
282 uint64_t rte:1;
283 uint64_t acto:1;
284 uint64_t rvdm:1;
285 uint64_t rumep:1;
286 uint64_t rptamrc:1;
287 uint64_t rpmerc:1;
288 uint64_t rfemrc:1;
289 uint64_t rnfemrc:1;
290 uint64_t rcemrc:1;
291 uint64_t rpoison:1;
292 uint64_t recrce:1;
293 uint64_t rtlplle:1;
294 uint64_t rtlpmal:1;
295 uint64_t spoison:1;
296 } s;
297 struct cvmx_pemx_dbg_info_en_s cn61xx;
298 struct cvmx_pemx_dbg_info_en_s cn63xx;
299 struct cvmx_pemx_dbg_info_en_s cn63xxp1;
300 struct cvmx_pemx_dbg_info_en_s cn66xx;
301 struct cvmx_pemx_dbg_info_en_s cn68xx;
302 struct cvmx_pemx_dbg_info_en_s cn68xxp1;
303};
304
305union cvmx_pemx_diag_status {
306 uint64_t u64;
307 struct cvmx_pemx_diag_status_s {
308 uint64_t reserved_4_63:60;
309 uint64_t pm_dst:1;
310 uint64_t pm_stat:1;
311 uint64_t pm_en:1;
312 uint64_t aux_en:1;
313 } s;
314 struct cvmx_pemx_diag_status_s cn61xx;
315 struct cvmx_pemx_diag_status_s cn63xx;
316 struct cvmx_pemx_diag_status_s cn63xxp1;
317 struct cvmx_pemx_diag_status_s cn66xx;
318 struct cvmx_pemx_diag_status_s cn68xx;
319 struct cvmx_pemx_diag_status_s cn68xxp1;
320};
321
322union cvmx_pemx_inb_read_credits {
323 uint64_t u64;
324 struct cvmx_pemx_inb_read_credits_s {
325 uint64_t reserved_6_63:58;
326 uint64_t num:6;
327 } s;
328 struct cvmx_pemx_inb_read_credits_s cn61xx;
329 struct cvmx_pemx_inb_read_credits_s cn66xx;
330 struct cvmx_pemx_inb_read_credits_s cn68xx;
331};
332
333union cvmx_pemx_int_enb {
334 uint64_t u64;
335 struct cvmx_pemx_int_enb_s {
336 uint64_t reserved_14_63:50;
337 uint64_t crs_dr:1;
338 uint64_t crs_er:1;
339 uint64_t rdlk:1;
340 uint64_t exc:1;
341 uint64_t un_bx:1;
342 uint64_t un_b2:1;
343 uint64_t un_b1:1;
344 uint64_t up_bx:1;
345 uint64_t up_b2:1;
346 uint64_t up_b1:1;
347 uint64_t pmem:1;
348 uint64_t pmei:1;
349 uint64_t se:1;
350 uint64_t aeri:1;
351 } s;
352 struct cvmx_pemx_int_enb_s cn61xx;
353 struct cvmx_pemx_int_enb_s cn63xx;
354 struct cvmx_pemx_int_enb_s cn63xxp1;
355 struct cvmx_pemx_int_enb_s cn66xx;
356 struct cvmx_pemx_int_enb_s cn68xx;
357 struct cvmx_pemx_int_enb_s cn68xxp1;
358};
359
360union cvmx_pemx_int_enb_int {
361 uint64_t u64;
362 struct cvmx_pemx_int_enb_int_s {
363 uint64_t reserved_14_63:50;
364 uint64_t crs_dr:1;
365 uint64_t crs_er:1;
366 uint64_t rdlk:1;
367 uint64_t exc:1;
368 uint64_t un_bx:1;
369 uint64_t un_b2:1;
370 uint64_t un_b1:1;
371 uint64_t up_bx:1;
372 uint64_t up_b2:1;
373 uint64_t up_b1:1;
374 uint64_t pmem:1;
375 uint64_t pmei:1;
376 uint64_t se:1;
377 uint64_t aeri:1;
378 } s;
379 struct cvmx_pemx_int_enb_int_s cn61xx;
380 struct cvmx_pemx_int_enb_int_s cn63xx;
381 struct cvmx_pemx_int_enb_int_s cn63xxp1;
382 struct cvmx_pemx_int_enb_int_s cn66xx;
383 struct cvmx_pemx_int_enb_int_s cn68xx;
384 struct cvmx_pemx_int_enb_int_s cn68xxp1;
385};
386
387union cvmx_pemx_int_sum {
388 uint64_t u64;
389 struct cvmx_pemx_int_sum_s {
390 uint64_t reserved_14_63:50;
391 uint64_t crs_dr:1;
392 uint64_t crs_er:1;
393 uint64_t rdlk:1;
394 uint64_t exc:1;
395 uint64_t un_bx:1;
396 uint64_t un_b2:1;
397 uint64_t un_b1:1;
398 uint64_t up_bx:1;
399 uint64_t up_b2:1;
400 uint64_t up_b1:1;
401 uint64_t pmem:1;
402 uint64_t pmei:1;
403 uint64_t se:1;
404 uint64_t aeri:1;
405 } s;
406 struct cvmx_pemx_int_sum_s cn61xx;
407 struct cvmx_pemx_int_sum_s cn63xx;
408 struct cvmx_pemx_int_sum_s cn63xxp1;
409 struct cvmx_pemx_int_sum_s cn66xx;
410 struct cvmx_pemx_int_sum_s cn68xx;
411 struct cvmx_pemx_int_sum_s cn68xxp1;
412};
413
414union cvmx_pemx_p2n_bar0_start {
415 uint64_t u64;
416 struct cvmx_pemx_p2n_bar0_start_s {
417 uint64_t addr:50;
418 uint64_t reserved_0_13:14;
419 } s;
420 struct cvmx_pemx_p2n_bar0_start_s cn61xx;
421 struct cvmx_pemx_p2n_bar0_start_s cn63xx;
422 struct cvmx_pemx_p2n_bar0_start_s cn63xxp1;
423 struct cvmx_pemx_p2n_bar0_start_s cn66xx;
424 struct cvmx_pemx_p2n_bar0_start_s cn68xx;
425 struct cvmx_pemx_p2n_bar0_start_s cn68xxp1;
426};
427
428union cvmx_pemx_p2n_bar1_start {
429 uint64_t u64;
430 struct cvmx_pemx_p2n_bar1_start_s {
431 uint64_t addr:38;
432 uint64_t reserved_0_25:26;
433 } s;
434 struct cvmx_pemx_p2n_bar1_start_s cn61xx;
435 struct cvmx_pemx_p2n_bar1_start_s cn63xx;
436 struct cvmx_pemx_p2n_bar1_start_s cn63xxp1;
437 struct cvmx_pemx_p2n_bar1_start_s cn66xx;
438 struct cvmx_pemx_p2n_bar1_start_s cn68xx;
439 struct cvmx_pemx_p2n_bar1_start_s cn68xxp1;
440};
441
442union cvmx_pemx_p2n_bar2_start {
443 uint64_t u64;
444 struct cvmx_pemx_p2n_bar2_start_s {
445 uint64_t addr:23;
446 uint64_t reserved_0_40:41;
447 } s;
448 struct cvmx_pemx_p2n_bar2_start_s cn61xx;
449 struct cvmx_pemx_p2n_bar2_start_s cn63xx;
450 struct cvmx_pemx_p2n_bar2_start_s cn63xxp1;
451 struct cvmx_pemx_p2n_bar2_start_s cn66xx;
452 struct cvmx_pemx_p2n_bar2_start_s cn68xx;
453 struct cvmx_pemx_p2n_bar2_start_s cn68xxp1;
454};
455
456union cvmx_pemx_p2p_barx_end {
457 uint64_t u64;
458 struct cvmx_pemx_p2p_barx_end_s {
459 uint64_t addr:52;
460 uint64_t reserved_0_11:12;
461 } s;
462 struct cvmx_pemx_p2p_barx_end_s cn63xx;
463 struct cvmx_pemx_p2p_barx_end_s cn63xxp1;
464 struct cvmx_pemx_p2p_barx_end_s cn66xx;
465 struct cvmx_pemx_p2p_barx_end_s cn68xx;
466 struct cvmx_pemx_p2p_barx_end_s cn68xxp1;
467};
468
469union cvmx_pemx_p2p_barx_start {
470 uint64_t u64;
471 struct cvmx_pemx_p2p_barx_start_s {
472 uint64_t addr:52;
473 uint64_t reserved_0_11:12;
474 } s;
475 struct cvmx_pemx_p2p_barx_start_s cn63xx;
476 struct cvmx_pemx_p2p_barx_start_s cn63xxp1;
477 struct cvmx_pemx_p2p_barx_start_s cn66xx;
478 struct cvmx_pemx_p2p_barx_start_s cn68xx;
479 struct cvmx_pemx_p2p_barx_start_s cn68xxp1;
480};
481
482union cvmx_pemx_tlp_credits {
483 uint64_t u64;
484 struct cvmx_pemx_tlp_credits_s {
485 uint64_t reserved_56_63:8;
486 uint64_t peai_ppf:8;
487 uint64_t pem_cpl:8;
488 uint64_t pem_np:8;
489 uint64_t pem_p:8;
490 uint64_t sli_cpl:8;
491 uint64_t sli_np:8;
492 uint64_t sli_p:8;
493 } s;
494 struct cvmx_pemx_tlp_credits_cn61xx {
495 uint64_t reserved_56_63:8;
496 uint64_t peai_ppf:8;
497 uint64_t reserved_24_47:24;
498 uint64_t sli_cpl:8;
499 uint64_t sli_np:8;
500 uint64_t sli_p:8;
501 } cn61xx;
502 struct cvmx_pemx_tlp_credits_s cn63xx;
503 struct cvmx_pemx_tlp_credits_s cn63xxp1;
504 struct cvmx_pemx_tlp_credits_s cn66xx;
505 struct cvmx_pemx_tlp_credits_s cn68xx;
506 struct cvmx_pemx_tlp_credits_s cn68xxp1;
507};
508
509#endif