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1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2009 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/**
29 * Typedefs and defines for working with Octeon physical addresses.
30 *
31 */
32#ifndef __CVMX_ADDRESS_H__
33#define __CVMX_ADDRESS_H__
34
35#if 0
36typedef enum {
37 CVMX_MIPS_SPACE_XKSEG = 3LL,
38 CVMX_MIPS_SPACE_XKPHYS = 2LL,
39 CVMX_MIPS_SPACE_XSSEG = 1LL,
40 CVMX_MIPS_SPACE_XUSEG = 0LL
41} cvmx_mips_space_t;
42#endif
43
44typedef enum {
45 CVMX_MIPS_XKSEG_SPACE_KSEG0 = 0LL,
46 CVMX_MIPS_XKSEG_SPACE_KSEG1 = 1LL,
47 CVMX_MIPS_XKSEG_SPACE_SSEG = 2LL,
48 CVMX_MIPS_XKSEG_SPACE_KSEG3 = 3LL
49} cvmx_mips_xkseg_space_t;
50
51/* decodes <14:13> of a kseg3 window address */
52typedef enum {
53 CVMX_ADD_WIN_SCR = 0L,
54 /* see cvmx_add_win_dma_dec_t for further decode */
55 CVMX_ADD_WIN_DMA = 1L,
56 CVMX_ADD_WIN_UNUSED = 2L,
57 CVMX_ADD_WIN_UNUSED2 = 3L
58} cvmx_add_win_dec_t;
59
60/* decode within DMA space */
61typedef enum {
62 /*
63 * Add store data to the write buffer entry, allocating it if
64 * necessary.
65 */
66 CVMX_ADD_WIN_DMA_ADD = 0L,
67 /* send out the write buffer entry to DRAM */
68 CVMX_ADD_WIN_DMA_SENDMEM = 1L,
69 /* store data must be normal DRAM memory space address in this case */
70 /* send out the write buffer entry as an IOBDMA command */
71 CVMX_ADD_WIN_DMA_SENDDMA = 2L,
72 /* see CVMX_ADD_WIN_DMA_SEND_DEC for data contents */
73 /* send out the write buffer entry as an IO write */
74 CVMX_ADD_WIN_DMA_SENDIO = 3L,
75 /* store data must be normal IO space address in this case */
76 /* send out a single-tick command on the NCB bus */
77 CVMX_ADD_WIN_DMA_SENDSINGLE = 4L,
78 /* no write buffer data needed/used */
79} cvmx_add_win_dma_dec_t;
80
81/*
82 * Physical Address Decode
83 *
84 * Octeon-I HW never interprets this X (<39:36> reserved
85 * for future expansion), software should set to 0.
86 *
87 * - 0x0 XXX0 0000 0000 to DRAM Cached
88 * - 0x0 XXX0 0FFF FFFF
89 *
90 * - 0x0 XXX0 1000 0000 to Boot Bus Uncached (Converted to 0x1 00X0 1000 0000
91 * - 0x0 XXX0 1FFF FFFF + EJTAG to 0x1 00X0 1FFF FFFF)
92 *
93 * - 0x0 XXX0 2000 0000 to DRAM Cached
94 * - 0x0 XXXF FFFF FFFF
95 *
96 * - 0x1 00X0 0000 0000 to Boot Bus Uncached
97 * - 0x1 00XF FFFF FFFF
98 *
99 * - 0x1 01X0 0000 0000 to Other NCB Uncached
100 * - 0x1 FFXF FFFF FFFF devices
101 *
102 * Decode of all Octeon addresses
103 */
104typedef union {
105
106 uint64_t u64;
107 /* mapped or unmapped virtual address */
108 struct {
109 uint64_t R:2;
110 uint64_t offset:62;
111 } sva;
112
113 /* mapped USEG virtual addresses (typically) */
114 struct {
115 uint64_t zeroes:33;
116 uint64_t offset:31;
117 } suseg;
118
119 /* mapped or unmapped virtual address */
120 struct {
121 uint64_t ones:33;
122 uint64_t sp:2;
123 uint64_t offset:29;
124 } sxkseg;
125
126 /*
127 * physical address accessed through xkphys unmapped virtual
128 * address.
129 */
130 struct {
131 uint64_t R:2; /* CVMX_MIPS_SPACE_XKPHYS in this case */
132 uint64_t cca:3; /* ignored by octeon */
133 uint64_t mbz:10;
134 uint64_t pa:49; /* physical address */
135 } sxkphys;
136
137 /* physical address */
138 struct {
139 uint64_t mbz:15;
140 /* if set, the address is uncached and resides on MCB bus */
141 uint64_t is_io:1;
142 /*
143 * the hardware ignores this field when is_io==0, else
144 * device ID.
145 */
146 uint64_t did:8;
147 /* the hardware ignores <39:36> in Octeon I */
148 uint64_t unaddr:4;
149 uint64_t offset:36;
150 } sphys;
151
152 /* physical mem address */
153 struct {
154 /* techically, <47:40> are dont-cares */
155 uint64_t zeroes:24;
156 /* the hardware ignores <39:36> in Octeon I */
157 uint64_t unaddr:4;
158 uint64_t offset:36;
159 } smem;
160
161 /* physical IO address */
162 struct {
163 uint64_t mem_region:2;
164 uint64_t mbz:13;
165 /* 1 in this case */
166 uint64_t is_io:1;
167 /*
168 * The hardware ignores this field when is_io==0, else
169 * device ID.
170 */
171 uint64_t did:8;
172 /* the hardware ignores <39:36> in Octeon I */
173 uint64_t unaddr:4;
174 uint64_t offset:36;
175 } sio;
176
177 /*
178 * Scratchpad virtual address - accessed through a window at
179 * the end of kseg3
180 */
181 struct {
182 uint64_t ones:49;
183 /* CVMX_ADD_WIN_SCR (0) in this case */
184 cvmx_add_win_dec_t csrdec:2;
185 uint64_t addr:13;
186 } sscr;
187
188 /* there should only be stores to IOBDMA space, no loads */
189 /*
190 * IOBDMA virtual address - accessed through a window at the
191 * end of kseg3
192 */
193 struct {
194 uint64_t ones:49;
195 uint64_t csrdec:2; /* CVMX_ADD_WIN_DMA (1) in this case */
196 uint64_t unused2:3;
197 uint64_t type:3;
198 uint64_t addr:7;
199 } sdma;
200
201 struct {
202 uint64_t didspace:24;
203 uint64_t unused:40;
204 } sfilldidspace;
205
206} cvmx_addr_t;
207
208/* These macros for used by 32 bit applications */
209
210#define CVMX_MIPS32_SPACE_KSEG0 1l
211#define CVMX_ADD_SEG32(segment, add) \
212 (((int32_t)segment << 31) | (int32_t)(add))
213
214/*
215 * Currently all IOs are performed using XKPHYS addressing. Linux uses
216 * the CvmMemCtl register to enable XKPHYS addressing to IO space from
217 * user mode. Future OSes may need to change the upper bits of IO
218 * addresses. The following define controls the upper two bits for all
219 * IO addresses generated by the simple executive library.
220 */
221#define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS
222
223/* These macros simplify the process of creating common IO addresses */
224#define CVMX_ADD_SEG(segment, add) ((((uint64_t)segment) << 62) | (add))
225#ifndef CVMX_ADD_IO_SEG
226#define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add))
227#endif
228#define CVMX_ADDR_DIDSPACE(did) (((CVMX_IO_SEG) << 22) | ((1ULL) << 8) | (did))
229#define CVMX_ADDR_DID(did) (CVMX_ADDR_DIDSPACE(did) << 40)
230#define CVMX_FULL_DID(did, subdid) (((did) << 3) | (subdid))
231
232 /* from include/ncb_rsl_id.v */
233#define CVMX_OCT_DID_MIS 0ULL /* misc stuff */
234#define CVMX_OCT_DID_GMX0 1ULL
235#define CVMX_OCT_DID_GMX1 2ULL
236#define CVMX_OCT_DID_PCI 3ULL
237#define CVMX_OCT_DID_KEY 4ULL
238#define CVMX_OCT_DID_FPA 5ULL
239#define CVMX_OCT_DID_DFA 6ULL
240#define CVMX_OCT_DID_ZIP 7ULL
241#define CVMX_OCT_DID_RNG 8ULL
242#define CVMX_OCT_DID_IPD 9ULL
243#define CVMX_OCT_DID_PKT 10ULL
244#define CVMX_OCT_DID_TIM 11ULL
245#define CVMX_OCT_DID_TAG 12ULL
246 /* the rest are not on the IO bus */
247#define CVMX_OCT_DID_L2C 16ULL
248#define CVMX_OCT_DID_LMC 17ULL
249#define CVMX_OCT_DID_SPX0 18ULL
250#define CVMX_OCT_DID_SPX1 19ULL
251#define CVMX_OCT_DID_PIP 20ULL
252#define CVMX_OCT_DID_ASX0 22ULL
253#define CVMX_OCT_DID_ASX1 23ULL
254#define CVMX_OCT_DID_IOB 30ULL
255
256#define CVMX_OCT_DID_PKT_SEND CVMX_FULL_DID(CVMX_OCT_DID_PKT, 2ULL)
257#define CVMX_OCT_DID_TAG_SWTAG CVMX_FULL_DID(CVMX_OCT_DID_TAG, 0ULL)
258#define CVMX_OCT_DID_TAG_TAG1 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 1ULL)
259#define CVMX_OCT_DID_TAG_TAG2 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 2ULL)
260#define CVMX_OCT_DID_TAG_TAG3 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 3ULL)
261#define CVMX_OCT_DID_TAG_NULL_RD CVMX_FULL_DID(CVMX_OCT_DID_TAG, 4ULL)
262#define CVMX_OCT_DID_TAG_CSR CVMX_FULL_DID(CVMX_OCT_DID_TAG, 7ULL)
263#define CVMX_OCT_DID_FAU_FAI CVMX_FULL_DID(CVMX_OCT_DID_IOB, 0ULL)
264#define CVMX_OCT_DID_TIM_CSR CVMX_FULL_DID(CVMX_OCT_DID_TIM, 0ULL)
265#define CVMX_OCT_DID_KEY_RW CVMX_FULL_DID(CVMX_OCT_DID_KEY, 0ULL)
266#define CVMX_OCT_DID_PCI_6 CVMX_FULL_DID(CVMX_OCT_DID_PCI, 6ULL)
267#define CVMX_OCT_DID_MIS_BOO CVMX_FULL_DID(CVMX_OCT_DID_MIS, 0ULL)
268#define CVMX_OCT_DID_PCI_RML CVMX_FULL_DID(CVMX_OCT_DID_PCI, 0ULL)
269#define CVMX_OCT_DID_IPD_CSR CVMX_FULL_DID(CVMX_OCT_DID_IPD, 7ULL)
270#define CVMX_OCT_DID_DFA_CSR CVMX_FULL_DID(CVMX_OCT_DID_DFA, 7ULL)
271#define CVMX_OCT_DID_MIS_CSR CVMX_FULL_DID(CVMX_OCT_DID_MIS, 7ULL)
272#define CVMX_OCT_DID_ZIP_CSR CVMX_FULL_DID(CVMX_OCT_DID_ZIP, 0ULL)
273
274#endif /* __CVMX_ADDRESS_H__ */