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1/*
2 * cpu.h: Values of the PRId register used to match up
3 * various MIPS cpu types.
4 *
5 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
6 * Copyright (C) 2004 Maciej W. Rozycki
7 */
8#ifndef _ASM_CPU_H
9#define _ASM_CPU_H
10
11/* Assigned Company values for bits 23:16 of the PRId Register
12 (CP0 register 15, select 0). As of the MIPS32 and MIPS64 specs from
13 MTI, the PRId register is defined in this (backwards compatible)
14 way:
15
16 +----------------+----------------+----------------+----------------+
17 | Company Options| Company ID | Processor ID | Revision |
18 +----------------+----------------+----------------+----------------+
19 31 24 23 16 15 8 7
20
21 I don't have docs for all the previous processors, but my impression is
22 that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
23 spec.
24*/
25
26#define PRID_COMP_LEGACY 0x000000
27#define PRID_COMP_MIPS 0x010000
28#define PRID_COMP_BROADCOM 0x020000
29#define PRID_COMP_ALCHEMY 0x030000
30#define PRID_COMP_SIBYTE 0x040000
31#define PRID_COMP_SANDCRAFT 0x050000
32#define PRID_COMP_NXP 0x060000
33#define PRID_COMP_TOSHIBA 0x070000
34#define PRID_COMP_LSI 0x080000
35#define PRID_COMP_LEXRA 0x0b0000
36#define PRID_COMP_NETLOGIC 0x0c0000
37#define PRID_COMP_CAVIUM 0x0d0000
38#define PRID_COMP_INGENIC 0xd00000
39
40/*
41 * Assigned values for the product ID register. In order to detect a
42 * certain CPU type exactly eventually additional registers may need to
43 * be examined. These are valid when 23:16 == PRID_COMP_LEGACY
44 */
45#define PRID_IMP_R2000 0x0100
46#define PRID_IMP_AU1_REV1 0x0100
47#define PRID_IMP_AU1_REV2 0x0200
48#define PRID_IMP_R3000 0x0200 /* Same as R2000A */
49#define PRID_IMP_R6000 0x0300 /* Same as R3000A */
50#define PRID_IMP_R4000 0x0400
51#define PRID_IMP_R6000A 0x0600
52#define PRID_IMP_R10000 0x0900
53#define PRID_IMP_R4300 0x0b00
54#define PRID_IMP_VR41XX 0x0c00
55#define PRID_IMP_R12000 0x0e00
56#define PRID_IMP_R14000 0x0f00
57#define PRID_IMP_R8000 0x1000
58#define PRID_IMP_PR4450 0x1200
59#define PRID_IMP_R4600 0x2000
60#define PRID_IMP_R4700 0x2100
61#define PRID_IMP_TX39 0x2200
62#define PRID_IMP_R4640 0x2200
63#define PRID_IMP_R4650 0x2200 /* Same as R4640 */
64#define PRID_IMP_R5000 0x2300
65#define PRID_IMP_TX49 0x2d00
66#define PRID_IMP_SONIC 0x2400
67#define PRID_IMP_MAGIC 0x2500
68#define PRID_IMP_RM7000 0x2700
69#define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */
70#define PRID_IMP_RM9000 0x3400
71#define PRID_IMP_LOONGSON1 0x4200
72#define PRID_IMP_R5432 0x5400
73#define PRID_IMP_R5500 0x5500
74#define PRID_IMP_LOONGSON2 0x6300
75
76#define PRID_IMP_UNKNOWN 0xff00
77
78/*
79 * These are the PRID's for when 23:16 == PRID_COMP_MIPS
80 */
81
82#define PRID_IMP_4KC 0x8000
83#define PRID_IMP_5KC 0x8100
84#define PRID_IMP_20KC 0x8200
85#define PRID_IMP_4KEC 0x8400
86#define PRID_IMP_4KSC 0x8600
87#define PRID_IMP_25KF 0x8800
88#define PRID_IMP_5KE 0x8900
89#define PRID_IMP_4KECR2 0x9000
90#define PRID_IMP_4KEMPR2 0x9100
91#define PRID_IMP_4KSD 0x9200
92#define PRID_IMP_24K 0x9300
93#define PRID_IMP_34K 0x9500
94#define PRID_IMP_24KE 0x9600
95#define PRID_IMP_74K 0x9700
96#define PRID_IMP_1004K 0x9900
97
98/*
99 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
100 */
101
102#define PRID_IMP_SB1 0x0100
103#define PRID_IMP_SB1A 0x1100
104
105/*
106 * These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT
107 */
108
109#define PRID_IMP_SR71000 0x0400
110
111/*
112 * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM
113 */
114
115#define PRID_IMP_BMIPS32_REV4 0x4000
116#define PRID_IMP_BMIPS32_REV8 0x8000
117#define PRID_IMP_BMIPS3300 0x9000
118#define PRID_IMP_BMIPS3300_ALT 0x9100
119#define PRID_IMP_BMIPS3300_BUG 0x0000
120#define PRID_IMP_BMIPS43XX 0xa000
121#define PRID_IMP_BMIPS5000 0x5a00
122
123#define PRID_REV_BMIPS4380_LO 0x0040
124#define PRID_REV_BMIPS4380_HI 0x006f
125
126/*
127 * These are the PRID's for when 23:16 == PRID_COMP_CAVIUM
128 */
129
130#define PRID_IMP_CAVIUM_CN38XX 0x0000
131#define PRID_IMP_CAVIUM_CN31XX 0x0100
132#define PRID_IMP_CAVIUM_CN30XX 0x0200
133#define PRID_IMP_CAVIUM_CN58XX 0x0300
134#define PRID_IMP_CAVIUM_CN56XX 0x0400
135#define PRID_IMP_CAVIUM_CN50XX 0x0600
136#define PRID_IMP_CAVIUM_CN52XX 0x0700
137#define PRID_IMP_CAVIUM_CN63XX 0x9000
138
139/*
140 * These are the PRID's for when 23:16 == PRID_COMP_INGENIC
141 */
142
143#define PRID_IMP_JZRISC 0x0200
144
145/*
146 * These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC
147 */
148#define PRID_IMP_NETLOGIC_XLR732 0x0000
149#define PRID_IMP_NETLOGIC_XLR716 0x0200
150#define PRID_IMP_NETLOGIC_XLR532 0x0900
151#define PRID_IMP_NETLOGIC_XLR308 0x0600
152#define PRID_IMP_NETLOGIC_XLR532C 0x0800
153#define PRID_IMP_NETLOGIC_XLR516C 0x0a00
154#define PRID_IMP_NETLOGIC_XLR508C 0x0b00
155#define PRID_IMP_NETLOGIC_XLR308C 0x0f00
156#define PRID_IMP_NETLOGIC_XLS608 0x8000
157#define PRID_IMP_NETLOGIC_XLS408 0x8800
158#define PRID_IMP_NETLOGIC_XLS404 0x8c00
159#define PRID_IMP_NETLOGIC_XLS208 0x8e00
160#define PRID_IMP_NETLOGIC_XLS204 0x8f00
161#define PRID_IMP_NETLOGIC_XLS108 0xce00
162#define PRID_IMP_NETLOGIC_XLS104 0xcf00
163#define PRID_IMP_NETLOGIC_XLS616B 0x4000
164#define PRID_IMP_NETLOGIC_XLS608B 0x4a00
165#define PRID_IMP_NETLOGIC_XLS416B 0x4400
166#define PRID_IMP_NETLOGIC_XLS412B 0x4c00
167#define PRID_IMP_NETLOGIC_XLS408B 0x4e00
168#define PRID_IMP_NETLOGIC_XLS404B 0x4f00
169
170/*
171 * Definitions for 7:0 on legacy processors
172 */
173
174#define PRID_REV_MASK 0x00ff
175
176#define PRID_REV_TX4927 0x0022
177#define PRID_REV_TX4937 0x0030
178#define PRID_REV_R4400 0x0040
179#define PRID_REV_R3000A 0x0030
180#define PRID_REV_R3000 0x0020
181#define PRID_REV_R2000A 0x0010
182#define PRID_REV_TX3912 0x0010
183#define PRID_REV_TX3922 0x0030
184#define PRID_REV_TX3927 0x0040
185#define PRID_REV_VR4111 0x0050
186#define PRID_REV_VR4181 0x0050 /* Same as VR4111 */
187#define PRID_REV_VR4121 0x0060
188#define PRID_REV_VR4122 0x0070
189#define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */
190#define PRID_REV_VR4130 0x0080
191#define PRID_REV_34K_V1_0_2 0x0022
192#define PRID_REV_LOONGSON2E 0x0002
193#define PRID_REV_LOONGSON2F 0x0003
194
195/*
196 * Older processors used to encode processor version and revision in two
197 * 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores
198 * have switched to use the 8-bits as 3:3:2 bitfield with the last field as
199 * the patch number. *ARGH*
200 */
201#define PRID_REV_ENCODE_44(ver, rev) \
202 ((ver) << 4 | (rev))
203#define PRID_REV_ENCODE_332(ver, rev, patch) \
204 ((ver) << 5 | (rev) << 2 | (patch))
205
206/*
207 * FPU implementation/revision register (CP1 control register 0).
208 *
209 * +---------------------------------+----------------+----------------+
210 * | 0 | Implementation | Revision |
211 * +---------------------------------+----------------+----------------+
212 * 31 16 15 8 7 0
213 */
214
215#define FPIR_IMP_NONE 0x0000
216
217enum cpu_type_enum {
218 CPU_UNKNOWN,
219
220 /*
221 * R2000 class processors
222 */
223 CPU_R2000, CPU_R3000, CPU_R3000A, CPU_R3041, CPU_R3051, CPU_R3052,
224 CPU_R3081, CPU_R3081E,
225
226 /*
227 * R6000 class processors
228 */
229 CPU_R6000, CPU_R6000A,
230
231 /*
232 * R4000 class processors
233 */
234 CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200, CPU_R4300, CPU_R4310,
235 CPU_R4400PC, CPU_R4400SC, CPU_R4400MC, CPU_R4600, CPU_R4640, CPU_R4650,
236 CPU_R4700, CPU_R5000, CPU_R5000A, CPU_R5500, CPU_NEVADA, CPU_R5432,
237 CPU_R10000, CPU_R12000, CPU_R14000, CPU_VR41XX, CPU_VR4111, CPU_VR4121,
238 CPU_VR4122, CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000,
239 CPU_SR71000, CPU_RM9000, CPU_TX49XX,
240
241 /*
242 * R8000 class processors
243 */
244 CPU_R8000,
245
246 /*
247 * TX3900 class processors
248 */
249 CPU_TX3912, CPU_TX3922, CPU_TX3927,
250
251 /*
252 * MIPS32 class processors
253 */
254 CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
255 CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
256 CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC,
257
258 /*
259 * MIPS64 class processors
260 */
261 CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
262 CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2,
263 CPU_XLR,
264
265 CPU_LAST
266};
267
268
269/*
270 * ISA Level encodings
271 *
272 */
273#define MIPS_CPU_ISA_I 0x00000001
274#define MIPS_CPU_ISA_II 0x00000002
275#define MIPS_CPU_ISA_III 0x00000004
276#define MIPS_CPU_ISA_IV 0x00000008
277#define MIPS_CPU_ISA_V 0x00000010
278#define MIPS_CPU_ISA_M32R1 0x00000020
279#define MIPS_CPU_ISA_M32R2 0x00000040
280#define MIPS_CPU_ISA_M64R1 0x00000080
281#define MIPS_CPU_ISA_M64R2 0x00000100
282
283#define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_I | MIPS_CPU_ISA_II | \
284 MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 )
285#define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \
286 MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)
287
288/*
289 * CPU Option encodings
290 */
291#define MIPS_CPU_TLB 0x00000001 /* CPU has TLB */
292#define MIPS_CPU_4KEX 0x00000002 /* "R4K" exception model */
293#define MIPS_CPU_3K_CACHE 0x00000004 /* R3000-style caches */
294#define MIPS_CPU_4K_CACHE 0x00000008 /* R4000-style caches */
295#define MIPS_CPU_TX39_CACHE 0x00000010 /* TX3900-style caches */
296#define MIPS_CPU_FPU 0x00000020 /* CPU has FPU */
297#define MIPS_CPU_32FPR 0x00000040 /* 32 dbl. prec. FP registers */
298#define MIPS_CPU_COUNTER 0x00000080 /* Cycle count/compare */
299#define MIPS_CPU_WATCH 0x00000100 /* watchpoint registers */
300#define MIPS_CPU_DIVEC 0x00000200 /* dedicated interrupt vector */
301#define MIPS_CPU_VCE 0x00000400 /* virt. coherence conflict possible */
302#define MIPS_CPU_CACHE_CDEX_P 0x00000800 /* Create_Dirty_Exclusive CACHE op */
303#define MIPS_CPU_CACHE_CDEX_S 0x00001000 /* ... same for seconary cache ... */
304#define MIPS_CPU_MCHECK 0x00002000 /* Machine check exception */
305#define MIPS_CPU_EJTAG 0x00004000 /* EJTAG exception */
306#define MIPS_CPU_NOFPUEX 0x00008000 /* no FPU exception */
307#define MIPS_CPU_LLSC 0x00010000 /* CPU has ll/sc instructions */
308#define MIPS_CPU_INCLUSIVE_CACHES 0x00020000 /* P-cache subset enforced */
309#define MIPS_CPU_PREFETCH 0x00040000 /* CPU has usable prefetch */
310#define MIPS_CPU_VINT 0x00080000 /* CPU supports MIPSR2 vectored interrupts */
311#define MIPS_CPU_VEIC 0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */
312#define MIPS_CPU_ULRI 0x00200000 /* CPU has ULRI feature */
313
314/*
315 * CPU ASE encodings
316 */
317#define MIPS_ASE_MIPS16 0x00000001 /* code compression */
318#define MIPS_ASE_MDMX 0x00000002 /* MIPS digital media extension */
319#define MIPS_ASE_MIPS3D 0x00000004 /* MIPS-3D */
320#define MIPS_ASE_SMARTMIPS 0x00000008 /* SmartMIPS */
321#define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */
322#define MIPS_ASE_MIPSMT 0x00000020 /* CPU supports MIPS MT */
323
324
325#endif /* _ASM_CPU_H */
1/*
2 * cpu.h: Values of the PRId register used to match up
3 * various MIPS cpu types.
4 *
5 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
6 * Copyright (C) 2004 Maciej W. Rozycki
7 */
8#ifndef _ASM_CPU_H
9#define _ASM_CPU_H
10
11/* Assigned Company values for bits 23:16 of the PRId Register
12 (CP0 register 15, select 0). As of the MIPS32 and MIPS64 specs from
13 MTI, the PRId register is defined in this (backwards compatible)
14 way:
15
16 +----------------+----------------+----------------+----------------+
17 | Company Options| Company ID | Processor ID | Revision |
18 +----------------+----------------+----------------+----------------+
19 31 24 23 16 15 8 7
20
21 I don't have docs for all the previous processors, but my impression is
22 that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
23 spec.
24*/
25
26#define PRID_COMP_LEGACY 0x000000
27#define PRID_COMP_MIPS 0x010000
28#define PRID_COMP_BROADCOM 0x020000
29#define PRID_COMP_ALCHEMY 0x030000
30#define PRID_COMP_SIBYTE 0x040000
31#define PRID_COMP_SANDCRAFT 0x050000
32#define PRID_COMP_NXP 0x060000
33#define PRID_COMP_TOSHIBA 0x070000
34#define PRID_COMP_LSI 0x080000
35#define PRID_COMP_LEXRA 0x0b0000
36#define PRID_COMP_NETLOGIC 0x0c0000
37#define PRID_COMP_CAVIUM 0x0d0000
38#define PRID_COMP_INGENIC 0xd00000
39
40/*
41 * Assigned values for the product ID register. In order to detect a
42 * certain CPU type exactly eventually additional registers may need to
43 * be examined. These are valid when 23:16 == PRID_COMP_LEGACY
44 */
45#define PRID_IMP_R2000 0x0100
46#define PRID_IMP_AU1_REV1 0x0100
47#define PRID_IMP_AU1_REV2 0x0200
48#define PRID_IMP_R3000 0x0200 /* Same as R2000A */
49#define PRID_IMP_R6000 0x0300 /* Same as R3000A */
50#define PRID_IMP_R4000 0x0400
51#define PRID_IMP_R6000A 0x0600
52#define PRID_IMP_R10000 0x0900
53#define PRID_IMP_R4300 0x0b00
54#define PRID_IMP_VR41XX 0x0c00
55#define PRID_IMP_R12000 0x0e00
56#define PRID_IMP_R14000 0x0f00
57#define PRID_IMP_R8000 0x1000
58#define PRID_IMP_PR4450 0x1200
59#define PRID_IMP_R4600 0x2000
60#define PRID_IMP_R4700 0x2100
61#define PRID_IMP_TX39 0x2200
62#define PRID_IMP_R4640 0x2200
63#define PRID_IMP_R4650 0x2200 /* Same as R4640 */
64#define PRID_IMP_R5000 0x2300
65#define PRID_IMP_TX49 0x2d00
66#define PRID_IMP_SONIC 0x2400
67#define PRID_IMP_MAGIC 0x2500
68#define PRID_IMP_RM7000 0x2700
69#define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */
70#define PRID_IMP_RM9000 0x3400
71#define PRID_IMP_LOONGSON1 0x4200
72#define PRID_IMP_R5432 0x5400
73#define PRID_IMP_R5500 0x5500
74#define PRID_IMP_LOONGSON2 0x6300
75
76#define PRID_IMP_UNKNOWN 0xff00
77
78/*
79 * These are the PRID's for when 23:16 == PRID_COMP_MIPS
80 */
81
82#define PRID_IMP_4KC 0x8000
83#define PRID_IMP_5KC 0x8100
84#define PRID_IMP_20KC 0x8200
85#define PRID_IMP_4KEC 0x8400
86#define PRID_IMP_4KSC 0x8600
87#define PRID_IMP_25KF 0x8800
88#define PRID_IMP_5KE 0x8900
89#define PRID_IMP_4KECR2 0x9000
90#define PRID_IMP_4KEMPR2 0x9100
91#define PRID_IMP_4KSD 0x9200
92#define PRID_IMP_24K 0x9300
93#define PRID_IMP_34K 0x9500
94#define PRID_IMP_24KE 0x9600
95#define PRID_IMP_74K 0x9700
96#define PRID_IMP_1004K 0x9900
97#define PRID_IMP_M14KC 0x9c00
98
99/*
100 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
101 */
102
103#define PRID_IMP_SB1 0x0100
104#define PRID_IMP_SB1A 0x1100
105
106/*
107 * These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT
108 */
109
110#define PRID_IMP_SR71000 0x0400
111
112/*
113 * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM
114 */
115
116#define PRID_IMP_BMIPS32_REV4 0x4000
117#define PRID_IMP_BMIPS32_REV8 0x8000
118#define PRID_IMP_BMIPS3300 0x9000
119#define PRID_IMP_BMIPS3300_ALT 0x9100
120#define PRID_IMP_BMIPS3300_BUG 0x0000
121#define PRID_IMP_BMIPS43XX 0xa000
122#define PRID_IMP_BMIPS5000 0x5a00
123
124#define PRID_REV_BMIPS4380_LO 0x0040
125#define PRID_REV_BMIPS4380_HI 0x006f
126
127/*
128 * These are the PRID's for when 23:16 == PRID_COMP_CAVIUM
129 */
130
131#define PRID_IMP_CAVIUM_CN38XX 0x0000
132#define PRID_IMP_CAVIUM_CN31XX 0x0100
133#define PRID_IMP_CAVIUM_CN30XX 0x0200
134#define PRID_IMP_CAVIUM_CN58XX 0x0300
135#define PRID_IMP_CAVIUM_CN56XX 0x0400
136#define PRID_IMP_CAVIUM_CN50XX 0x0600
137#define PRID_IMP_CAVIUM_CN52XX 0x0700
138#define PRID_IMP_CAVIUM_CN63XX 0x9000
139#define PRID_IMP_CAVIUM_CN68XX 0x9100
140#define PRID_IMP_CAVIUM_CN66XX 0x9200
141#define PRID_IMP_CAVIUM_CN61XX 0x9300
142
143/*
144 * These are the PRID's for when 23:16 == PRID_COMP_INGENIC
145 */
146
147#define PRID_IMP_JZRISC 0x0200
148
149/*
150 * These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC
151 */
152#define PRID_IMP_NETLOGIC_XLR732 0x0000
153#define PRID_IMP_NETLOGIC_XLR716 0x0200
154#define PRID_IMP_NETLOGIC_XLR532 0x0900
155#define PRID_IMP_NETLOGIC_XLR308 0x0600
156#define PRID_IMP_NETLOGIC_XLR532C 0x0800
157#define PRID_IMP_NETLOGIC_XLR516C 0x0a00
158#define PRID_IMP_NETLOGIC_XLR508C 0x0b00
159#define PRID_IMP_NETLOGIC_XLR308C 0x0f00
160#define PRID_IMP_NETLOGIC_XLS608 0x8000
161#define PRID_IMP_NETLOGIC_XLS408 0x8800
162#define PRID_IMP_NETLOGIC_XLS404 0x8c00
163#define PRID_IMP_NETLOGIC_XLS208 0x8e00
164#define PRID_IMP_NETLOGIC_XLS204 0x8f00
165#define PRID_IMP_NETLOGIC_XLS108 0xce00
166#define PRID_IMP_NETLOGIC_XLS104 0xcf00
167#define PRID_IMP_NETLOGIC_XLS616B 0x4000
168#define PRID_IMP_NETLOGIC_XLS608B 0x4a00
169#define PRID_IMP_NETLOGIC_XLS416B 0x4400
170#define PRID_IMP_NETLOGIC_XLS412B 0x4c00
171#define PRID_IMP_NETLOGIC_XLS408B 0x4e00
172#define PRID_IMP_NETLOGIC_XLS404B 0x4f00
173#define PRID_IMP_NETLOGIC_AU13XX 0x8000
174
175#define PRID_IMP_NETLOGIC_XLP8XX 0x1000
176#define PRID_IMP_NETLOGIC_XLP3XX 0x1100
177
178/*
179 * Definitions for 7:0 on legacy processors
180 */
181
182#define PRID_REV_MASK 0x00ff
183
184#define PRID_REV_TX4927 0x0022
185#define PRID_REV_TX4937 0x0030
186#define PRID_REV_R4400 0x0040
187#define PRID_REV_R3000A 0x0030
188#define PRID_REV_R3000 0x0020
189#define PRID_REV_R2000A 0x0010
190#define PRID_REV_TX3912 0x0010
191#define PRID_REV_TX3922 0x0030
192#define PRID_REV_TX3927 0x0040
193#define PRID_REV_VR4111 0x0050
194#define PRID_REV_VR4181 0x0050 /* Same as VR4111 */
195#define PRID_REV_VR4121 0x0060
196#define PRID_REV_VR4122 0x0070
197#define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */
198#define PRID_REV_VR4130 0x0080
199#define PRID_REV_34K_V1_0_2 0x0022
200#define PRID_REV_LOONGSON2E 0x0002
201#define PRID_REV_LOONGSON2F 0x0003
202
203/*
204 * Older processors used to encode processor version and revision in two
205 * 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores
206 * have switched to use the 8-bits as 3:3:2 bitfield with the last field as
207 * the patch number. *ARGH*
208 */
209#define PRID_REV_ENCODE_44(ver, rev) \
210 ((ver) << 4 | (rev))
211#define PRID_REV_ENCODE_332(ver, rev, patch) \
212 ((ver) << 5 | (rev) << 2 | (patch))
213
214/*
215 * FPU implementation/revision register (CP1 control register 0).
216 *
217 * +---------------------------------+----------------+----------------+
218 * | 0 | Implementation | Revision |
219 * +---------------------------------+----------------+----------------+
220 * 31 16 15 8 7 0
221 */
222
223#define FPIR_IMP_NONE 0x0000
224
225enum cpu_type_enum {
226 CPU_UNKNOWN,
227
228 /*
229 * R2000 class processors
230 */
231 CPU_R2000, CPU_R3000, CPU_R3000A, CPU_R3041, CPU_R3051, CPU_R3052,
232 CPU_R3081, CPU_R3081E,
233
234 /*
235 * R6000 class processors
236 */
237 CPU_R6000, CPU_R6000A,
238
239 /*
240 * R4000 class processors
241 */
242 CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200, CPU_R4300, CPU_R4310,
243 CPU_R4400PC, CPU_R4400SC, CPU_R4400MC, CPU_R4600, CPU_R4640, CPU_R4650,
244 CPU_R4700, CPU_R5000, CPU_R5000A, CPU_R5500, CPU_NEVADA, CPU_R5432,
245 CPU_R10000, CPU_R12000, CPU_R14000, CPU_VR41XX, CPU_VR4111, CPU_VR4121,
246 CPU_VR4122, CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000,
247 CPU_SR71000, CPU_RM9000, CPU_TX49XX,
248
249 /*
250 * R8000 class processors
251 */
252 CPU_R8000,
253
254 /*
255 * TX3900 class processors
256 */
257 CPU_TX3912, CPU_TX3922, CPU_TX3927,
258
259 /*
260 * MIPS32 class processors
261 */
262 CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
263 CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
264 CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_M14KC,
265
266 /*
267 * MIPS64 class processors
268 */
269 CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
270 CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2,
271 CPU_XLR, CPU_XLP,
272
273 CPU_LAST
274};
275
276
277/*
278 * ISA Level encodings
279 *
280 */
281#define MIPS_CPU_ISA_I 0x00000001
282#define MIPS_CPU_ISA_II 0x00000002
283#define MIPS_CPU_ISA_III 0x00000004
284#define MIPS_CPU_ISA_IV 0x00000008
285#define MIPS_CPU_ISA_V 0x00000010
286#define MIPS_CPU_ISA_M32R1 0x00000020
287#define MIPS_CPU_ISA_M32R2 0x00000040
288#define MIPS_CPU_ISA_M64R1 0x00000080
289#define MIPS_CPU_ISA_M64R2 0x00000100
290
291#define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_I | MIPS_CPU_ISA_II | \
292 MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2)
293#define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \
294 MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)
295
296/*
297 * CPU Option encodings
298 */
299#define MIPS_CPU_TLB 0x00000001 /* CPU has TLB */
300#define MIPS_CPU_4KEX 0x00000002 /* "R4K" exception model */
301#define MIPS_CPU_3K_CACHE 0x00000004 /* R3000-style caches */
302#define MIPS_CPU_4K_CACHE 0x00000008 /* R4000-style caches */
303#define MIPS_CPU_TX39_CACHE 0x00000010 /* TX3900-style caches */
304#define MIPS_CPU_FPU 0x00000020 /* CPU has FPU */
305#define MIPS_CPU_32FPR 0x00000040 /* 32 dbl. prec. FP registers */
306#define MIPS_CPU_COUNTER 0x00000080 /* Cycle count/compare */
307#define MIPS_CPU_WATCH 0x00000100 /* watchpoint registers */
308#define MIPS_CPU_DIVEC 0x00000200 /* dedicated interrupt vector */
309#define MIPS_CPU_VCE 0x00000400 /* virt. coherence conflict possible */
310#define MIPS_CPU_CACHE_CDEX_P 0x00000800 /* Create_Dirty_Exclusive CACHE op */
311#define MIPS_CPU_CACHE_CDEX_S 0x00001000 /* ... same for seconary cache ... */
312#define MIPS_CPU_MCHECK 0x00002000 /* Machine check exception */
313#define MIPS_CPU_EJTAG 0x00004000 /* EJTAG exception */
314#define MIPS_CPU_NOFPUEX 0x00008000 /* no FPU exception */
315#define MIPS_CPU_LLSC 0x00010000 /* CPU has ll/sc instructions */
316#define MIPS_CPU_INCLUSIVE_CACHES 0x00020000 /* P-cache subset enforced */
317#define MIPS_CPU_PREFETCH 0x00040000 /* CPU has usable prefetch */
318#define MIPS_CPU_VINT 0x00080000 /* CPU supports MIPSR2 vectored interrupts */
319#define MIPS_CPU_VEIC 0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */
320#define MIPS_CPU_ULRI 0x00200000 /* CPU has ULRI feature */
321
322/*
323 * CPU ASE encodings
324 */
325#define MIPS_ASE_MIPS16 0x00000001 /* code compression */
326#define MIPS_ASE_MDMX 0x00000002 /* MIPS digital media extension */
327#define MIPS_ASE_MIPS3D 0x00000004 /* MIPS-3D */
328#define MIPS_ASE_SMARTMIPS 0x00000008 /* SmartMIPS */
329#define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */
330#define MIPS_ASE_MIPSMT 0x00000020 /* CPU supports MIPS MT */
331
332
333#endif /* _ASM_CPU_H */