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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (c) 1994 - 1997, 99, 2000, 06, 07 Ralf Baechle (ralf@linux-mips.org)
7 * Copyright (c) 1999, 2000 Silicon Graphics, Inc.
8 */
9#ifndef _ASM_BITOPS_H
10#define _ASM_BITOPS_H
11
12#ifndef _LINUX_BITOPS_H
13#error only <linux/bitops.h> can be included directly
14#endif
15
16#include <linux/compiler.h>
17#include <linux/irqflags.h>
18#include <linux/types.h>
19#include <asm/barrier.h>
20#include <asm/bug.h>
21#include <asm/byteorder.h> /* sigh ... */
22#include <asm/cpu-features.h>
23#include <asm/sgidefs.h>
24#include <asm/war.h>
25
26#if _MIPS_SZLONG == 32
27#define SZLONG_LOG 5
28#define SZLONG_MASK 31UL
29#define __LL "ll "
30#define __SC "sc "
31#define __INS "ins "
32#define __EXT "ext "
33#elif _MIPS_SZLONG == 64
34#define SZLONG_LOG 6
35#define SZLONG_MASK 63UL
36#define __LL "lld "
37#define __SC "scd "
38#define __INS "dins "
39#define __EXT "dext "
40#endif
41
42/*
43 * clear_bit() doesn't provide any barrier for the compiler.
44 */
45#define smp_mb__before_clear_bit() smp_mb__before_llsc()
46#define smp_mb__after_clear_bit() smp_llsc_mb()
47
48/*
49 * set_bit - Atomically set a bit in memory
50 * @nr: the bit to set
51 * @addr: the address to start counting from
52 *
53 * This function is atomic and may not be reordered. See __set_bit()
54 * if you do not require the atomic guarantees.
55 * Note that @nr may be almost arbitrarily large; this function is not
56 * restricted to acting on a single-word quantity.
57 */
58static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
59{
60 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
61 unsigned short bit = nr & SZLONG_MASK;
62 unsigned long temp;
63
64 if (kernel_uses_llsc && R10000_LLSC_WAR) {
65 __asm__ __volatile__(
66 " .set mips3 \n"
67 "1: " __LL "%0, %1 # set_bit \n"
68 " or %0, %2 \n"
69 " " __SC "%0, %1 \n"
70 " beqzl %0, 1b \n"
71 " .set mips0 \n"
72 : "=&r" (temp), "=m" (*m)
73 : "ir" (1UL << bit), "m" (*m));
74#ifdef CONFIG_CPU_MIPSR2
75 } else if (kernel_uses_llsc && __builtin_constant_p(bit)) {
76 do {
77 __asm__ __volatile__(
78 " " __LL "%0, %1 # set_bit \n"
79 " " __INS "%0, %3, %2, 1 \n"
80 " " __SC "%0, %1 \n"
81 : "=&r" (temp), "+m" (*m)
82 : "ir" (bit), "r" (~0));
83 } while (unlikely(!temp));
84#endif /* CONFIG_CPU_MIPSR2 */
85 } else if (kernel_uses_llsc) {
86 do {
87 __asm__ __volatile__(
88 " .set mips3 \n"
89 " " __LL "%0, %1 # set_bit \n"
90 " or %0, %2 \n"
91 " " __SC "%0, %1 \n"
92 " .set mips0 \n"
93 : "=&r" (temp), "+m" (*m)
94 : "ir" (1UL << bit));
95 } while (unlikely(!temp));
96 } else {
97 volatile unsigned long *a = addr;
98 unsigned long mask;
99 unsigned long flags;
100
101 a += nr >> SZLONG_LOG;
102 mask = 1UL << bit;
103 raw_local_irq_save(flags);
104 *a |= mask;
105 raw_local_irq_restore(flags);
106 }
107}
108
109/*
110 * clear_bit - Clears a bit in memory
111 * @nr: Bit to clear
112 * @addr: Address to start counting from
113 *
114 * clear_bit() is atomic and may not be reordered. However, it does
115 * not contain a memory barrier, so if it is used for locking purposes,
116 * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
117 * in order to ensure changes are visible on other processors.
118 */
119static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
120{
121 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
122 unsigned short bit = nr & SZLONG_MASK;
123 unsigned long temp;
124
125 if (kernel_uses_llsc && R10000_LLSC_WAR) {
126 __asm__ __volatile__(
127 " .set mips3 \n"
128 "1: " __LL "%0, %1 # clear_bit \n"
129 " and %0, %2 \n"
130 " " __SC "%0, %1 \n"
131 " beqzl %0, 1b \n"
132 " .set mips0 \n"
133 : "=&r" (temp), "+m" (*m)
134 : "ir" (~(1UL << bit)));
135#ifdef CONFIG_CPU_MIPSR2
136 } else if (kernel_uses_llsc && __builtin_constant_p(bit)) {
137 do {
138 __asm__ __volatile__(
139 " " __LL "%0, %1 # clear_bit \n"
140 " " __INS "%0, $0, %2, 1 \n"
141 " " __SC "%0, %1 \n"
142 : "=&r" (temp), "+m" (*m)
143 : "ir" (bit));
144 } while (unlikely(!temp));
145#endif /* CONFIG_CPU_MIPSR2 */
146 } else if (kernel_uses_llsc) {
147 do {
148 __asm__ __volatile__(
149 " .set mips3 \n"
150 " " __LL "%0, %1 # clear_bit \n"
151 " and %0, %2 \n"
152 " " __SC "%0, %1 \n"
153 " .set mips0 \n"
154 : "=&r" (temp), "+m" (*m)
155 : "ir" (~(1UL << bit)));
156 } while (unlikely(!temp));
157 } else {
158 volatile unsigned long *a = addr;
159 unsigned long mask;
160 unsigned long flags;
161
162 a += nr >> SZLONG_LOG;
163 mask = 1UL << bit;
164 raw_local_irq_save(flags);
165 *a &= ~mask;
166 raw_local_irq_restore(flags);
167 }
168}
169
170/*
171 * clear_bit_unlock - Clears a bit in memory
172 * @nr: Bit to clear
173 * @addr: Address to start counting from
174 *
175 * clear_bit() is atomic and implies release semantics before the memory
176 * operation. It can be used for an unlock.
177 */
178static inline void clear_bit_unlock(unsigned long nr, volatile unsigned long *addr)
179{
180 smp_mb__before_clear_bit();
181 clear_bit(nr, addr);
182}
183
184/*
185 * change_bit - Toggle a bit in memory
186 * @nr: Bit to change
187 * @addr: Address to start counting from
188 *
189 * change_bit() is atomic and may not be reordered.
190 * Note that @nr may be almost arbitrarily large; this function is not
191 * restricted to acting on a single-word quantity.
192 */
193static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
194{
195 unsigned short bit = nr & SZLONG_MASK;
196
197 if (kernel_uses_llsc && R10000_LLSC_WAR) {
198 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
199 unsigned long temp;
200
201 __asm__ __volatile__(
202 " .set mips3 \n"
203 "1: " __LL "%0, %1 # change_bit \n"
204 " xor %0, %2 \n"
205 " " __SC "%0, %1 \n"
206 " beqzl %0, 1b \n"
207 " .set mips0 \n"
208 : "=&r" (temp), "+m" (*m)
209 : "ir" (1UL << bit));
210 } else if (kernel_uses_llsc) {
211 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
212 unsigned long temp;
213
214 do {
215 __asm__ __volatile__(
216 " .set mips3 \n"
217 " " __LL "%0, %1 # change_bit \n"
218 " xor %0, %2 \n"
219 " " __SC "%0, %1 \n"
220 " .set mips0 \n"
221 : "=&r" (temp), "+m" (*m)
222 : "ir" (1UL << bit));
223 } while (unlikely(!temp));
224 } else {
225 volatile unsigned long *a = addr;
226 unsigned long mask;
227 unsigned long flags;
228
229 a += nr >> SZLONG_LOG;
230 mask = 1UL << bit;
231 raw_local_irq_save(flags);
232 *a ^= mask;
233 raw_local_irq_restore(flags);
234 }
235}
236
237/*
238 * test_and_set_bit - Set a bit and return its old value
239 * @nr: Bit to set
240 * @addr: Address to count from
241 *
242 * This operation is atomic and cannot be reordered.
243 * It also implies a memory barrier.
244 */
245static inline int test_and_set_bit(unsigned long nr,
246 volatile unsigned long *addr)
247{
248 unsigned short bit = nr & SZLONG_MASK;
249 unsigned long res;
250
251 smp_mb__before_llsc();
252
253 if (kernel_uses_llsc && R10000_LLSC_WAR) {
254 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
255 unsigned long temp;
256
257 __asm__ __volatile__(
258 " .set mips3 \n"
259 "1: " __LL "%0, %1 # test_and_set_bit \n"
260 " or %2, %0, %3 \n"
261 " " __SC "%2, %1 \n"
262 " beqzl %2, 1b \n"
263 " and %2, %0, %3 \n"
264 " .set mips0 \n"
265 : "=&r" (temp), "+m" (*m), "=&r" (res)
266 : "r" (1UL << bit)
267 : "memory");
268 } else if (kernel_uses_llsc) {
269 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
270 unsigned long temp;
271
272 do {
273 __asm__ __volatile__(
274 " .set mips3 \n"
275 " " __LL "%0, %1 # test_and_set_bit \n"
276 " or %2, %0, %3 \n"
277 " " __SC "%2, %1 \n"
278 " .set mips0 \n"
279 : "=&r" (temp), "+m" (*m), "=&r" (res)
280 : "r" (1UL << bit)
281 : "memory");
282 } while (unlikely(!res));
283
284 res = temp & (1UL << bit);
285 } else {
286 volatile unsigned long *a = addr;
287 unsigned long mask;
288 unsigned long flags;
289
290 a += nr >> SZLONG_LOG;
291 mask = 1UL << bit;
292 raw_local_irq_save(flags);
293 res = (mask & *a);
294 *a |= mask;
295 raw_local_irq_restore(flags);
296 }
297
298 smp_llsc_mb();
299
300 return res != 0;
301}
302
303/*
304 * test_and_set_bit_lock - Set a bit and return its old value
305 * @nr: Bit to set
306 * @addr: Address to count from
307 *
308 * This operation is atomic and implies acquire ordering semantics
309 * after the memory operation.
310 */
311static inline int test_and_set_bit_lock(unsigned long nr,
312 volatile unsigned long *addr)
313{
314 unsigned short bit = nr & SZLONG_MASK;
315 unsigned long res;
316
317 if (kernel_uses_llsc && R10000_LLSC_WAR) {
318 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
319 unsigned long temp;
320
321 __asm__ __volatile__(
322 " .set mips3 \n"
323 "1: " __LL "%0, %1 # test_and_set_bit \n"
324 " or %2, %0, %3 \n"
325 " " __SC "%2, %1 \n"
326 " beqzl %2, 1b \n"
327 " and %2, %0, %3 \n"
328 " .set mips0 \n"
329 : "=&r" (temp), "+m" (*m), "=&r" (res)
330 : "r" (1UL << bit)
331 : "memory");
332 } else if (kernel_uses_llsc) {
333 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
334 unsigned long temp;
335
336 do {
337 __asm__ __volatile__(
338 " .set mips3 \n"
339 " " __LL "%0, %1 # test_and_set_bit \n"
340 " or %2, %0, %3 \n"
341 " " __SC "%2, %1 \n"
342 " .set mips0 \n"
343 : "=&r" (temp), "+m" (*m), "=&r" (res)
344 : "r" (1UL << bit)
345 : "memory");
346 } while (unlikely(!res));
347
348 res = temp & (1UL << bit);
349 } else {
350 volatile unsigned long *a = addr;
351 unsigned long mask;
352 unsigned long flags;
353
354 a += nr >> SZLONG_LOG;
355 mask = 1UL << bit;
356 raw_local_irq_save(flags);
357 res = (mask & *a);
358 *a |= mask;
359 raw_local_irq_restore(flags);
360 }
361
362 smp_llsc_mb();
363
364 return res != 0;
365}
366/*
367 * test_and_clear_bit - Clear a bit and return its old value
368 * @nr: Bit to clear
369 * @addr: Address to count from
370 *
371 * This operation is atomic and cannot be reordered.
372 * It also implies a memory barrier.
373 */
374static inline int test_and_clear_bit(unsigned long nr,
375 volatile unsigned long *addr)
376{
377 unsigned short bit = nr & SZLONG_MASK;
378 unsigned long res;
379
380 smp_mb__before_llsc();
381
382 if (kernel_uses_llsc && R10000_LLSC_WAR) {
383 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
384 unsigned long temp;
385
386 __asm__ __volatile__(
387 " .set mips3 \n"
388 "1: " __LL "%0, %1 # test_and_clear_bit \n"
389 " or %2, %0, %3 \n"
390 " xor %2, %3 \n"
391 " " __SC "%2, %1 \n"
392 " beqzl %2, 1b \n"
393 " and %2, %0, %3 \n"
394 " .set mips0 \n"
395 : "=&r" (temp), "+m" (*m), "=&r" (res)
396 : "r" (1UL << bit)
397 : "memory");
398#ifdef CONFIG_CPU_MIPSR2
399 } else if (kernel_uses_llsc && __builtin_constant_p(nr)) {
400 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
401 unsigned long temp;
402
403 do {
404 __asm__ __volatile__(
405 " " __LL "%0, %1 # test_and_clear_bit \n"
406 " " __EXT "%2, %0, %3, 1 \n"
407 " " __INS "%0, $0, %3, 1 \n"
408 " " __SC "%0, %1 \n"
409 : "=&r" (temp), "+m" (*m), "=&r" (res)
410 : "ir" (bit)
411 : "memory");
412 } while (unlikely(!temp));
413#endif
414 } else if (kernel_uses_llsc) {
415 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
416 unsigned long temp;
417
418 do {
419 __asm__ __volatile__(
420 " .set mips3 \n"
421 " " __LL "%0, %1 # test_and_clear_bit \n"
422 " or %2, %0, %3 \n"
423 " xor %2, %3 \n"
424 " " __SC "%2, %1 \n"
425 " .set mips0 \n"
426 : "=&r" (temp), "+m" (*m), "=&r" (res)
427 : "r" (1UL << bit)
428 : "memory");
429 } while (unlikely(!res));
430
431 res = temp & (1UL << bit);
432 } else {
433 volatile unsigned long *a = addr;
434 unsigned long mask;
435 unsigned long flags;
436
437 a += nr >> SZLONG_LOG;
438 mask = 1UL << bit;
439 raw_local_irq_save(flags);
440 res = (mask & *a);
441 *a &= ~mask;
442 raw_local_irq_restore(flags);
443 }
444
445 smp_llsc_mb();
446
447 return res != 0;
448}
449
450/*
451 * test_and_change_bit - Change a bit and return its old value
452 * @nr: Bit to change
453 * @addr: Address to count from
454 *
455 * This operation is atomic and cannot be reordered.
456 * It also implies a memory barrier.
457 */
458static inline int test_and_change_bit(unsigned long nr,
459 volatile unsigned long *addr)
460{
461 unsigned short bit = nr & SZLONG_MASK;
462 unsigned long res;
463
464 smp_mb__before_llsc();
465
466 if (kernel_uses_llsc && R10000_LLSC_WAR) {
467 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
468 unsigned long temp;
469
470 __asm__ __volatile__(
471 " .set mips3 \n"
472 "1: " __LL "%0, %1 # test_and_change_bit \n"
473 " xor %2, %0, %3 \n"
474 " " __SC "%2, %1 \n"
475 " beqzl %2, 1b \n"
476 " and %2, %0, %3 \n"
477 " .set mips0 \n"
478 : "=&r" (temp), "+m" (*m), "=&r" (res)
479 : "r" (1UL << bit)
480 : "memory");
481 } else if (kernel_uses_llsc) {
482 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
483 unsigned long temp;
484
485 do {
486 __asm__ __volatile__(
487 " .set mips3 \n"
488 " " __LL "%0, %1 # test_and_change_bit \n"
489 " xor %2, %0, %3 \n"
490 " " __SC "\t%2, %1 \n"
491 " .set mips0 \n"
492 : "=&r" (temp), "+m" (*m), "=&r" (res)
493 : "r" (1UL << bit)
494 : "memory");
495 } while (unlikely(!res));
496
497 res = temp & (1UL << bit);
498 } else {
499 volatile unsigned long *a = addr;
500 unsigned long mask;
501 unsigned long flags;
502
503 a += nr >> SZLONG_LOG;
504 mask = 1UL << bit;
505 raw_local_irq_save(flags);
506 res = (mask & *a);
507 *a ^= mask;
508 raw_local_irq_restore(flags);
509 }
510
511 smp_llsc_mb();
512
513 return res != 0;
514}
515
516#include <asm-generic/bitops/non-atomic.h>
517
518/*
519 * __clear_bit_unlock - Clears a bit in memory
520 * @nr: Bit to clear
521 * @addr: Address to start counting from
522 *
523 * __clear_bit() is non-atomic and implies release semantics before the memory
524 * operation. It can be used for an unlock if no other CPUs can concurrently
525 * modify other bits in the word.
526 */
527static inline void __clear_bit_unlock(unsigned long nr, volatile unsigned long *addr)
528{
529 smp_mb();
530 __clear_bit(nr, addr);
531}
532
533/*
534 * Return the bit position (0..63) of the most significant 1 bit in a word
535 * Returns -1 if no 1 bit exists
536 */
537static inline unsigned long __fls(unsigned long word)
538{
539 int num;
540
541 if (BITS_PER_LONG == 32 &&
542 __builtin_constant_p(cpu_has_clo_clz) && cpu_has_clo_clz) {
543 __asm__(
544 " .set push \n"
545 " .set mips32 \n"
546 " clz %0, %1 \n"
547 " .set pop \n"
548 : "=r" (num)
549 : "r" (word));
550
551 return 31 - num;
552 }
553
554 if (BITS_PER_LONG == 64 &&
555 __builtin_constant_p(cpu_has_mips64) && cpu_has_mips64) {
556 __asm__(
557 " .set push \n"
558 " .set mips64 \n"
559 " dclz %0, %1 \n"
560 " .set pop \n"
561 : "=r" (num)
562 : "r" (word));
563
564 return 63 - num;
565 }
566
567 num = BITS_PER_LONG - 1;
568
569#if BITS_PER_LONG == 64
570 if (!(word & (~0ul << 32))) {
571 num -= 32;
572 word <<= 32;
573 }
574#endif
575 if (!(word & (~0ul << (BITS_PER_LONG-16)))) {
576 num -= 16;
577 word <<= 16;
578 }
579 if (!(word & (~0ul << (BITS_PER_LONG-8)))) {
580 num -= 8;
581 word <<= 8;
582 }
583 if (!(word & (~0ul << (BITS_PER_LONG-4)))) {
584 num -= 4;
585 word <<= 4;
586 }
587 if (!(word & (~0ul << (BITS_PER_LONG-2)))) {
588 num -= 2;
589 word <<= 2;
590 }
591 if (!(word & (~0ul << (BITS_PER_LONG-1))))
592 num -= 1;
593 return num;
594}
595
596/*
597 * __ffs - find first bit in word.
598 * @word: The word to search
599 *
600 * Returns 0..SZLONG-1
601 * Undefined if no bit exists, so code should check against 0 first.
602 */
603static inline unsigned long __ffs(unsigned long word)
604{
605 return __fls(word & -word);
606}
607
608/*
609 * fls - find last bit set.
610 * @word: The word to search
611 *
612 * This is defined the same way as ffs.
613 * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
614 */
615static inline int fls(int x)
616{
617 int r;
618
619 if (__builtin_constant_p(cpu_has_clo_clz) && cpu_has_clo_clz) {
620 __asm__("clz %0, %1" : "=r" (x) : "r" (x));
621
622 return 32 - x;
623 }
624
625 r = 32;
626 if (!x)
627 return 0;
628 if (!(x & 0xffff0000u)) {
629 x <<= 16;
630 r -= 16;
631 }
632 if (!(x & 0xff000000u)) {
633 x <<= 8;
634 r -= 8;
635 }
636 if (!(x & 0xf0000000u)) {
637 x <<= 4;
638 r -= 4;
639 }
640 if (!(x & 0xc0000000u)) {
641 x <<= 2;
642 r -= 2;
643 }
644 if (!(x & 0x80000000u)) {
645 x <<= 1;
646 r -= 1;
647 }
648 return r;
649}
650
651#include <asm-generic/bitops/fls64.h>
652
653/*
654 * ffs - find first bit set.
655 * @word: The word to search
656 *
657 * This is defined the same way as
658 * the libc and compiler builtin ffs routines, therefore
659 * differs in spirit from the above ffz (man ffs).
660 */
661static inline int ffs(int word)
662{
663 if (!word)
664 return 0;
665
666 return fls(word & -word);
667}
668
669#include <asm-generic/bitops/ffz.h>
670#include <asm-generic/bitops/find.h>
671
672#ifdef __KERNEL__
673
674#include <asm-generic/bitops/sched.h>
675
676#include <asm/arch_hweight.h>
677#include <asm-generic/bitops/const_hweight.h>
678
679#include <asm-generic/bitops/le.h>
680#include <asm-generic/bitops/ext2-atomic.h>
681
682#endif /* __KERNEL__ */
683
684#endif /* _ASM_BITOPS_H */
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (c) 1994 - 1997, 99, 2000, 06, 07 Ralf Baechle (ralf@linux-mips.org)
7 * Copyright (c) 1999, 2000 Silicon Graphics, Inc.
8 */
9#ifndef _ASM_BITOPS_H
10#define _ASM_BITOPS_H
11
12#ifndef _LINUX_BITOPS_H
13#error only <linux/bitops.h> can be included directly
14#endif
15
16#include <linux/compiler.h>
17#include <linux/irqflags.h>
18#include <linux/types.h>
19#include <asm/barrier.h>
20#include <asm/byteorder.h> /* sigh ... */
21#include <asm/cpu-features.h>
22#include <asm/sgidefs.h>
23#include <asm/war.h>
24
25#if _MIPS_SZLONG == 32
26#define SZLONG_LOG 5
27#define SZLONG_MASK 31UL
28#define __LL "ll "
29#define __SC "sc "
30#define __INS "ins "
31#define __EXT "ext "
32#elif _MIPS_SZLONG == 64
33#define SZLONG_LOG 6
34#define SZLONG_MASK 63UL
35#define __LL "lld "
36#define __SC "scd "
37#define __INS "dins "
38#define __EXT "dext "
39#endif
40
41/*
42 * clear_bit() doesn't provide any barrier for the compiler.
43 */
44#define smp_mb__before_clear_bit() smp_mb__before_llsc()
45#define smp_mb__after_clear_bit() smp_llsc_mb()
46
47/*
48 * set_bit - Atomically set a bit in memory
49 * @nr: the bit to set
50 * @addr: the address to start counting from
51 *
52 * This function is atomic and may not be reordered. See __set_bit()
53 * if you do not require the atomic guarantees.
54 * Note that @nr may be almost arbitrarily large; this function is not
55 * restricted to acting on a single-word quantity.
56 */
57static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
58{
59 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
60 unsigned short bit = nr & SZLONG_MASK;
61 unsigned long temp;
62
63 if (kernel_uses_llsc && R10000_LLSC_WAR) {
64 __asm__ __volatile__(
65 " .set mips3 \n"
66 "1: " __LL "%0, %1 # set_bit \n"
67 " or %0, %2 \n"
68 " " __SC "%0, %1 \n"
69 " beqzl %0, 1b \n"
70 " .set mips0 \n"
71 : "=&r" (temp), "=m" (*m)
72 : "ir" (1UL << bit), "m" (*m));
73#ifdef CONFIG_CPU_MIPSR2
74 } else if (kernel_uses_llsc && __builtin_constant_p(bit)) {
75 do {
76 __asm__ __volatile__(
77 " " __LL "%0, %1 # set_bit \n"
78 " " __INS "%0, %3, %2, 1 \n"
79 " " __SC "%0, %1 \n"
80 : "=&r" (temp), "+m" (*m)
81 : "ir" (bit), "r" (~0));
82 } while (unlikely(!temp));
83#endif /* CONFIG_CPU_MIPSR2 */
84 } else if (kernel_uses_llsc) {
85 do {
86 __asm__ __volatile__(
87 " .set mips3 \n"
88 " " __LL "%0, %1 # set_bit \n"
89 " or %0, %2 \n"
90 " " __SC "%0, %1 \n"
91 " .set mips0 \n"
92 : "=&r" (temp), "+m" (*m)
93 : "ir" (1UL << bit));
94 } while (unlikely(!temp));
95 } else {
96 volatile unsigned long *a = addr;
97 unsigned long mask;
98 unsigned long flags;
99
100 a += nr >> SZLONG_LOG;
101 mask = 1UL << bit;
102 raw_local_irq_save(flags);
103 *a |= mask;
104 raw_local_irq_restore(flags);
105 }
106}
107
108/*
109 * clear_bit - Clears a bit in memory
110 * @nr: Bit to clear
111 * @addr: Address to start counting from
112 *
113 * clear_bit() is atomic and may not be reordered. However, it does
114 * not contain a memory barrier, so if it is used for locking purposes,
115 * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
116 * in order to ensure changes are visible on other processors.
117 */
118static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
119{
120 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
121 unsigned short bit = nr & SZLONG_MASK;
122 unsigned long temp;
123
124 if (kernel_uses_llsc && R10000_LLSC_WAR) {
125 __asm__ __volatile__(
126 " .set mips3 \n"
127 "1: " __LL "%0, %1 # clear_bit \n"
128 " and %0, %2 \n"
129 " " __SC "%0, %1 \n"
130 " beqzl %0, 1b \n"
131 " .set mips0 \n"
132 : "=&r" (temp), "+m" (*m)
133 : "ir" (~(1UL << bit)));
134#ifdef CONFIG_CPU_MIPSR2
135 } else if (kernel_uses_llsc && __builtin_constant_p(bit)) {
136 do {
137 __asm__ __volatile__(
138 " " __LL "%0, %1 # clear_bit \n"
139 " " __INS "%0, $0, %2, 1 \n"
140 " " __SC "%0, %1 \n"
141 : "=&r" (temp), "+m" (*m)
142 : "ir" (bit));
143 } while (unlikely(!temp));
144#endif /* CONFIG_CPU_MIPSR2 */
145 } else if (kernel_uses_llsc) {
146 do {
147 __asm__ __volatile__(
148 " .set mips3 \n"
149 " " __LL "%0, %1 # clear_bit \n"
150 " and %0, %2 \n"
151 " " __SC "%0, %1 \n"
152 " .set mips0 \n"
153 : "=&r" (temp), "+m" (*m)
154 : "ir" (~(1UL << bit)));
155 } while (unlikely(!temp));
156 } else {
157 volatile unsigned long *a = addr;
158 unsigned long mask;
159 unsigned long flags;
160
161 a += nr >> SZLONG_LOG;
162 mask = 1UL << bit;
163 raw_local_irq_save(flags);
164 *a &= ~mask;
165 raw_local_irq_restore(flags);
166 }
167}
168
169/*
170 * clear_bit_unlock - Clears a bit in memory
171 * @nr: Bit to clear
172 * @addr: Address to start counting from
173 *
174 * clear_bit() is atomic and implies release semantics before the memory
175 * operation. It can be used for an unlock.
176 */
177static inline void clear_bit_unlock(unsigned long nr, volatile unsigned long *addr)
178{
179 smp_mb__before_clear_bit();
180 clear_bit(nr, addr);
181}
182
183/*
184 * change_bit - Toggle a bit in memory
185 * @nr: Bit to change
186 * @addr: Address to start counting from
187 *
188 * change_bit() is atomic and may not be reordered.
189 * Note that @nr may be almost arbitrarily large; this function is not
190 * restricted to acting on a single-word quantity.
191 */
192static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
193{
194 unsigned short bit = nr & SZLONG_MASK;
195
196 if (kernel_uses_llsc && R10000_LLSC_WAR) {
197 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
198 unsigned long temp;
199
200 __asm__ __volatile__(
201 " .set mips3 \n"
202 "1: " __LL "%0, %1 # change_bit \n"
203 " xor %0, %2 \n"
204 " " __SC "%0, %1 \n"
205 " beqzl %0, 1b \n"
206 " .set mips0 \n"
207 : "=&r" (temp), "+m" (*m)
208 : "ir" (1UL << bit));
209 } else if (kernel_uses_llsc) {
210 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
211 unsigned long temp;
212
213 do {
214 __asm__ __volatile__(
215 " .set mips3 \n"
216 " " __LL "%0, %1 # change_bit \n"
217 " xor %0, %2 \n"
218 " " __SC "%0, %1 \n"
219 " .set mips0 \n"
220 : "=&r" (temp), "+m" (*m)
221 : "ir" (1UL << bit));
222 } while (unlikely(!temp));
223 } else {
224 volatile unsigned long *a = addr;
225 unsigned long mask;
226 unsigned long flags;
227
228 a += nr >> SZLONG_LOG;
229 mask = 1UL << bit;
230 raw_local_irq_save(flags);
231 *a ^= mask;
232 raw_local_irq_restore(flags);
233 }
234}
235
236/*
237 * test_and_set_bit - Set a bit and return its old value
238 * @nr: Bit to set
239 * @addr: Address to count from
240 *
241 * This operation is atomic and cannot be reordered.
242 * It also implies a memory barrier.
243 */
244static inline int test_and_set_bit(unsigned long nr,
245 volatile unsigned long *addr)
246{
247 unsigned short bit = nr & SZLONG_MASK;
248 unsigned long res;
249
250 smp_mb__before_llsc();
251
252 if (kernel_uses_llsc && R10000_LLSC_WAR) {
253 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
254 unsigned long temp;
255
256 __asm__ __volatile__(
257 " .set mips3 \n"
258 "1: " __LL "%0, %1 # test_and_set_bit \n"
259 " or %2, %0, %3 \n"
260 " " __SC "%2, %1 \n"
261 " beqzl %2, 1b \n"
262 " and %2, %0, %3 \n"
263 " .set mips0 \n"
264 : "=&r" (temp), "+m" (*m), "=&r" (res)
265 : "r" (1UL << bit)
266 : "memory");
267 } else if (kernel_uses_llsc) {
268 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
269 unsigned long temp;
270
271 do {
272 __asm__ __volatile__(
273 " .set mips3 \n"
274 " " __LL "%0, %1 # test_and_set_bit \n"
275 " or %2, %0, %3 \n"
276 " " __SC "%2, %1 \n"
277 " .set mips0 \n"
278 : "=&r" (temp), "+m" (*m), "=&r" (res)
279 : "r" (1UL << bit)
280 : "memory");
281 } while (unlikely(!res));
282
283 res = temp & (1UL << bit);
284 } else {
285 volatile unsigned long *a = addr;
286 unsigned long mask;
287 unsigned long flags;
288
289 a += nr >> SZLONG_LOG;
290 mask = 1UL << bit;
291 raw_local_irq_save(flags);
292 res = (mask & *a);
293 *a |= mask;
294 raw_local_irq_restore(flags);
295 }
296
297 smp_llsc_mb();
298
299 return res != 0;
300}
301
302/*
303 * test_and_set_bit_lock - Set a bit and return its old value
304 * @nr: Bit to set
305 * @addr: Address to count from
306 *
307 * This operation is atomic and implies acquire ordering semantics
308 * after the memory operation.
309 */
310static inline int test_and_set_bit_lock(unsigned long nr,
311 volatile unsigned long *addr)
312{
313 unsigned short bit = nr & SZLONG_MASK;
314 unsigned long res;
315
316 if (kernel_uses_llsc && R10000_LLSC_WAR) {
317 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
318 unsigned long temp;
319
320 __asm__ __volatile__(
321 " .set mips3 \n"
322 "1: " __LL "%0, %1 # test_and_set_bit \n"
323 " or %2, %0, %3 \n"
324 " " __SC "%2, %1 \n"
325 " beqzl %2, 1b \n"
326 " and %2, %0, %3 \n"
327 " .set mips0 \n"
328 : "=&r" (temp), "+m" (*m), "=&r" (res)
329 : "r" (1UL << bit)
330 : "memory");
331 } else if (kernel_uses_llsc) {
332 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
333 unsigned long temp;
334
335 do {
336 __asm__ __volatile__(
337 " .set mips3 \n"
338 " " __LL "%0, %1 # test_and_set_bit \n"
339 " or %2, %0, %3 \n"
340 " " __SC "%2, %1 \n"
341 " .set mips0 \n"
342 : "=&r" (temp), "+m" (*m), "=&r" (res)
343 : "r" (1UL << bit)
344 : "memory");
345 } while (unlikely(!res));
346
347 res = temp & (1UL << bit);
348 } else {
349 volatile unsigned long *a = addr;
350 unsigned long mask;
351 unsigned long flags;
352
353 a += nr >> SZLONG_LOG;
354 mask = 1UL << bit;
355 raw_local_irq_save(flags);
356 res = (mask & *a);
357 *a |= mask;
358 raw_local_irq_restore(flags);
359 }
360
361 smp_llsc_mb();
362
363 return res != 0;
364}
365/*
366 * test_and_clear_bit - Clear a bit and return its old value
367 * @nr: Bit to clear
368 * @addr: Address to count from
369 *
370 * This operation is atomic and cannot be reordered.
371 * It also implies a memory barrier.
372 */
373static inline int test_and_clear_bit(unsigned long nr,
374 volatile unsigned long *addr)
375{
376 unsigned short bit = nr & SZLONG_MASK;
377 unsigned long res;
378
379 smp_mb__before_llsc();
380
381 if (kernel_uses_llsc && R10000_LLSC_WAR) {
382 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
383 unsigned long temp;
384
385 __asm__ __volatile__(
386 " .set mips3 \n"
387 "1: " __LL "%0, %1 # test_and_clear_bit \n"
388 " or %2, %0, %3 \n"
389 " xor %2, %3 \n"
390 " " __SC "%2, %1 \n"
391 " beqzl %2, 1b \n"
392 " and %2, %0, %3 \n"
393 " .set mips0 \n"
394 : "=&r" (temp), "+m" (*m), "=&r" (res)
395 : "r" (1UL << bit)
396 : "memory");
397#ifdef CONFIG_CPU_MIPSR2
398 } else if (kernel_uses_llsc && __builtin_constant_p(nr)) {
399 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
400 unsigned long temp;
401
402 do {
403 __asm__ __volatile__(
404 " " __LL "%0, %1 # test_and_clear_bit \n"
405 " " __EXT "%2, %0, %3, 1 \n"
406 " " __INS "%0, $0, %3, 1 \n"
407 " " __SC "%0, %1 \n"
408 : "=&r" (temp), "+m" (*m), "=&r" (res)
409 : "ir" (bit)
410 : "memory");
411 } while (unlikely(!temp));
412#endif
413 } else if (kernel_uses_llsc) {
414 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
415 unsigned long temp;
416
417 do {
418 __asm__ __volatile__(
419 " .set mips3 \n"
420 " " __LL "%0, %1 # test_and_clear_bit \n"
421 " or %2, %0, %3 \n"
422 " xor %2, %3 \n"
423 " " __SC "%2, %1 \n"
424 " .set mips0 \n"
425 : "=&r" (temp), "+m" (*m), "=&r" (res)
426 : "r" (1UL << bit)
427 : "memory");
428 } while (unlikely(!res));
429
430 res = temp & (1UL << bit);
431 } else {
432 volatile unsigned long *a = addr;
433 unsigned long mask;
434 unsigned long flags;
435
436 a += nr >> SZLONG_LOG;
437 mask = 1UL << bit;
438 raw_local_irq_save(flags);
439 res = (mask & *a);
440 *a &= ~mask;
441 raw_local_irq_restore(flags);
442 }
443
444 smp_llsc_mb();
445
446 return res != 0;
447}
448
449/*
450 * test_and_change_bit - Change a bit and return its old value
451 * @nr: Bit to change
452 * @addr: Address to count from
453 *
454 * This operation is atomic and cannot be reordered.
455 * It also implies a memory barrier.
456 */
457static inline int test_and_change_bit(unsigned long nr,
458 volatile unsigned long *addr)
459{
460 unsigned short bit = nr & SZLONG_MASK;
461 unsigned long res;
462
463 smp_mb__before_llsc();
464
465 if (kernel_uses_llsc && R10000_LLSC_WAR) {
466 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
467 unsigned long temp;
468
469 __asm__ __volatile__(
470 " .set mips3 \n"
471 "1: " __LL "%0, %1 # test_and_change_bit \n"
472 " xor %2, %0, %3 \n"
473 " " __SC "%2, %1 \n"
474 " beqzl %2, 1b \n"
475 " and %2, %0, %3 \n"
476 " .set mips0 \n"
477 : "=&r" (temp), "+m" (*m), "=&r" (res)
478 : "r" (1UL << bit)
479 : "memory");
480 } else if (kernel_uses_llsc) {
481 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
482 unsigned long temp;
483
484 do {
485 __asm__ __volatile__(
486 " .set mips3 \n"
487 " " __LL "%0, %1 # test_and_change_bit \n"
488 " xor %2, %0, %3 \n"
489 " " __SC "\t%2, %1 \n"
490 " .set mips0 \n"
491 : "=&r" (temp), "+m" (*m), "=&r" (res)
492 : "r" (1UL << bit)
493 : "memory");
494 } while (unlikely(!res));
495
496 res = temp & (1UL << bit);
497 } else {
498 volatile unsigned long *a = addr;
499 unsigned long mask;
500 unsigned long flags;
501
502 a += nr >> SZLONG_LOG;
503 mask = 1UL << bit;
504 raw_local_irq_save(flags);
505 res = (mask & *a);
506 *a ^= mask;
507 raw_local_irq_restore(flags);
508 }
509
510 smp_llsc_mb();
511
512 return res != 0;
513}
514
515#include <asm-generic/bitops/non-atomic.h>
516
517/*
518 * __clear_bit_unlock - Clears a bit in memory
519 * @nr: Bit to clear
520 * @addr: Address to start counting from
521 *
522 * __clear_bit() is non-atomic and implies release semantics before the memory
523 * operation. It can be used for an unlock if no other CPUs can concurrently
524 * modify other bits in the word.
525 */
526static inline void __clear_bit_unlock(unsigned long nr, volatile unsigned long *addr)
527{
528 smp_mb();
529 __clear_bit(nr, addr);
530}
531
532/*
533 * Return the bit position (0..63) of the most significant 1 bit in a word
534 * Returns -1 if no 1 bit exists
535 */
536static inline unsigned long __fls(unsigned long word)
537{
538 int num;
539
540 if (BITS_PER_LONG == 32 &&
541 __builtin_constant_p(cpu_has_clo_clz) && cpu_has_clo_clz) {
542 __asm__(
543 " .set push \n"
544 " .set mips32 \n"
545 " clz %0, %1 \n"
546 " .set pop \n"
547 : "=r" (num)
548 : "r" (word));
549
550 return 31 - num;
551 }
552
553 if (BITS_PER_LONG == 64 &&
554 __builtin_constant_p(cpu_has_mips64) && cpu_has_mips64) {
555 __asm__(
556 " .set push \n"
557 " .set mips64 \n"
558 " dclz %0, %1 \n"
559 " .set pop \n"
560 : "=r" (num)
561 : "r" (word));
562
563 return 63 - num;
564 }
565
566 num = BITS_PER_LONG - 1;
567
568#if BITS_PER_LONG == 64
569 if (!(word & (~0ul << 32))) {
570 num -= 32;
571 word <<= 32;
572 }
573#endif
574 if (!(word & (~0ul << (BITS_PER_LONG-16)))) {
575 num -= 16;
576 word <<= 16;
577 }
578 if (!(word & (~0ul << (BITS_PER_LONG-8)))) {
579 num -= 8;
580 word <<= 8;
581 }
582 if (!(word & (~0ul << (BITS_PER_LONG-4)))) {
583 num -= 4;
584 word <<= 4;
585 }
586 if (!(word & (~0ul << (BITS_PER_LONG-2)))) {
587 num -= 2;
588 word <<= 2;
589 }
590 if (!(word & (~0ul << (BITS_PER_LONG-1))))
591 num -= 1;
592 return num;
593}
594
595/*
596 * __ffs - find first bit in word.
597 * @word: The word to search
598 *
599 * Returns 0..SZLONG-1
600 * Undefined if no bit exists, so code should check against 0 first.
601 */
602static inline unsigned long __ffs(unsigned long word)
603{
604 return __fls(word & -word);
605}
606
607/*
608 * fls - find last bit set.
609 * @word: The word to search
610 *
611 * This is defined the same way as ffs.
612 * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
613 */
614static inline int fls(int x)
615{
616 int r;
617
618 if (__builtin_constant_p(cpu_has_clo_clz) && cpu_has_clo_clz) {
619 __asm__("clz %0, %1" : "=r" (x) : "r" (x));
620
621 return 32 - x;
622 }
623
624 r = 32;
625 if (!x)
626 return 0;
627 if (!(x & 0xffff0000u)) {
628 x <<= 16;
629 r -= 16;
630 }
631 if (!(x & 0xff000000u)) {
632 x <<= 8;
633 r -= 8;
634 }
635 if (!(x & 0xf0000000u)) {
636 x <<= 4;
637 r -= 4;
638 }
639 if (!(x & 0xc0000000u)) {
640 x <<= 2;
641 r -= 2;
642 }
643 if (!(x & 0x80000000u)) {
644 x <<= 1;
645 r -= 1;
646 }
647 return r;
648}
649
650#include <asm-generic/bitops/fls64.h>
651
652/*
653 * ffs - find first bit set.
654 * @word: The word to search
655 *
656 * This is defined the same way as
657 * the libc and compiler builtin ffs routines, therefore
658 * differs in spirit from the above ffz (man ffs).
659 */
660static inline int ffs(int word)
661{
662 if (!word)
663 return 0;
664
665 return fls(word & -word);
666}
667
668#include <asm-generic/bitops/ffz.h>
669#include <asm-generic/bitops/find.h>
670
671#ifdef __KERNEL__
672
673#include <asm-generic/bitops/sched.h>
674
675#include <asm/arch_hweight.h>
676#include <asm-generic/bitops/const_hweight.h>
677
678#include <asm-generic/bitops/le.h>
679#include <asm-generic/bitops/ext2-atomic.h>
680
681#endif /* __KERNEL__ */
682
683#endif /* _ASM_BITOPS_H */