1/*
  2 * ci.h - common structures, functions, and macros of the ChipIdea driver
  3 *
  4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
  5 *
  6 * Author: David Lopo
  7 *
  8 * This program is free software; you can redistribute it and/or modify
  9 * it under the terms of the GNU General Public License version 2 as
 10 * published by the Free Software Foundation.
 11 */
 12
 13#ifndef __DRIVERS_USB_CHIPIDEA_CI_H
 14#define __DRIVERS_USB_CHIPIDEA_CI_H
 15
 16#include <linux/list.h>
 17#include <linux/irqreturn.h>
 18#include <linux/usb.h>
 19#include <linux/usb/gadget.h>
 20
 21/******************************************************************************
 22 * DEFINE
 23 *****************************************************************************/
 24#define CI13XXX_PAGE_SIZE  4096ul /* page size for TD's */
 25#define ENDPT_MAX          32
 26
 27/******************************************************************************
 28 * STRUCTURES
 29 *****************************************************************************/
 30/**
 31 * struct ci13xxx_ep - endpoint representation
 32 * @ep: endpoint structure for gadget drivers
 33 * @dir: endpoint direction (TX/RX)
 34 * @num: endpoint number
 35 * @type: endpoint type
 36 * @name: string description of the endpoint
 37 * @qh: queue head for this endpoint
 38 * @wedge: is the endpoint wedged
 39 * @udc: pointer to the controller
 40 * @lock: pointer to controller's spinlock
 41 * @td_pool: pointer to controller's TD pool
 42 */
 43struct ci13xxx_ep {
 44	struct usb_ep				ep;
 45	u8					dir;
 46	u8					num;
 47	u8					type;
 48	char					name[16];
 49	struct {
 50		struct list_head	queue;
 51		struct ci13xxx_qh	*ptr;
 52		dma_addr_t		dma;
 53	}					qh;
 54	int					wedge;
 55
 56	/* global resources */
 57	struct ci13xxx				*udc;
 58	spinlock_t				*lock;
 59	struct dma_pool				*td_pool;
 60};
 61
 62enum ci_role {
 63	CI_ROLE_HOST = 0,
 64	CI_ROLE_GADGET,
 65	CI_ROLE_END,
 66};
 67
 68/**
 69 * struct ci_role_driver - host/gadget role driver
 70 * start: start this role
 71 * stop: stop this role
 72 * irq: irq handler for this role
 73 * name: role name string (host/gadget)
 74 */
 75struct ci_role_driver {
 76	int		(*start)(struct ci13xxx *);
 77	void		(*stop)(struct ci13xxx *);
 78	irqreturn_t	(*irq)(struct ci13xxx *);
 79	const char	*name;
 80};
 81
 82/**
 83 * struct hw_bank - hardware register mapping representation
 84 * @lpm: set if the device is LPM capable
 85 * @phys: physical address of the controller's registers
 86 * @abs: absolute address of the beginning of register window
 87 * @cap: capability registers
 88 * @op: operational registers
 89 * @size: size of the register window
 90 * @regmap: register lookup table
 91 */
 92struct hw_bank {
 93	unsigned	lpm;
 94	resource_size_t	phys;
 95	void __iomem	*abs;
 96	void __iomem	*cap;
 97	void __iomem	*op;
 98	size_t		size;
 99	void __iomem	**regmap;
100};
101
102/**
103 * struct ci13xxx - chipidea device representation
104 * @dev: pointer to parent device
105 * @lock: access synchronization
106 * @hw_bank: hardware register mapping
107 * @irq: IRQ number
108 * @roles: array of supported roles for this controller
109 * @role: current role
110 * @is_otg: if the device is otg-capable
111 * @work: work for role changing
112 * @wq: workqueue thread
113 * @qh_pool: allocation pool for queue heads
114 * @td_pool: allocation pool for transfer descriptors
115 * @gadget: device side representation for peripheral controller
116 * @driver: gadget driver
117 * @hw_ep_max: total number of endpoints supported by hardware
118 * @ci13xxx_ep: array of endpoints
119 * @ep0_dir: ep0 direction
120 * @ep0out: pointer to ep0 OUT endpoint
121 * @ep0in: pointer to ep0 IN endpoint
122 * @status: ep0 status request
123 * @setaddr: if we should set the address on status completion
124 * @address: usb address received from the host
125 * @remote_wakeup: host-enabled remote wakeup
126 * @suspended: suspended by host
127 * @test_mode: the selected test mode
128 * @udc_driver: platform specific information supplied by parent device
129 * @vbus_active: is VBUS active
130 * @transceiver: pointer to USB PHY, if any
131 * @hcd: pointer to usb_hcd for ehci host driver
132 */
133struct ci13xxx {
134	struct device			*dev;
135	spinlock_t			lock;
136	struct hw_bank			hw_bank;
137	int				irq;
138	struct ci_role_driver		*roles[CI_ROLE_END];
139	enum ci_role			role;
140	bool				is_otg;
141	struct work_struct		work;
142	struct workqueue_struct		*wq;
143
144	struct dma_pool			*qh_pool;
145	struct dma_pool			*td_pool;
146
147	struct usb_gadget		gadget;
148	struct usb_gadget_driver	*driver;
149	unsigned			hw_ep_max;
150	struct ci13xxx_ep		ci13xxx_ep[ENDPT_MAX];
151	u32				ep0_dir;
152	struct ci13xxx_ep		*ep0out, *ep0in;
153
154	struct usb_request		*status;
155	bool				setaddr;
156	u8				address;
157	u8				remote_wakeup;
158	u8				suspended;
159	u8				test_mode;
160
161	struct ci13xxx_udc_driver	*udc_driver;
162	int				vbus_active;
163	struct usb_phy			*transceiver;
164	struct usb_hcd			*hcd;
165};
166
167static inline struct ci_role_driver *ci_role(struct ci13xxx *ci)
168{
169	BUG_ON(ci->role >= CI_ROLE_END || !ci->roles[ci->role]);
170	return ci->roles[ci->role];
171}
172
173static inline int ci_role_start(struct ci13xxx *ci, enum ci_role role)
174{
175	int ret;
176
177	if (role >= CI_ROLE_END)
178		return -EINVAL;
179
180	if (!ci->roles[role])
181		return -ENXIO;
182
183	ret = ci->roles[role]->start(ci);
184	if (!ret)
185		ci->role = role;
186	return ret;
187}
188
189static inline void ci_role_stop(struct ci13xxx *ci)
190{
191	enum ci_role role = ci->role;
192
193	if (role == CI_ROLE_END)
194		return;
195
196	ci->role = CI_ROLE_END;
197
198	ci->roles[role]->stop(ci);
199}
200
201/******************************************************************************
202 * REGISTERS
203 *****************************************************************************/
204/* register size */
205#define REG_BITS   (32)
206
207/* register indices */
208enum ci13xxx_regs {
209	CAP_CAPLENGTH,
210	CAP_HCCPARAMS,
211	CAP_DCCPARAMS,
212	CAP_TESTMODE,
213	CAP_LAST = CAP_TESTMODE,
214	OP_USBCMD,
215	OP_USBSTS,
216	OP_USBINTR,
217	OP_DEVICEADDR,
218	OP_ENDPTLISTADDR,
219	OP_PORTSC,
220	OP_DEVLC,
221	OP_OTGSC,
222	OP_USBMODE,
223	OP_ENDPTSETUPSTAT,
224	OP_ENDPTPRIME,
225	OP_ENDPTFLUSH,
226	OP_ENDPTSTAT,
227	OP_ENDPTCOMPLETE,
228	OP_ENDPTCTRL,
229	/* endptctrl1..15 follow */
230	OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2,
231};
232
233/**
234 * ffs_nr: find first (least significant) bit set
235 * @x: the word to search
236 *
237 * This function returns bit number (instead of position)
238 */
239static inline int ffs_nr(u32 x)
240{
241	int n = ffs(x);
242
243	return n ? n-1 : 32;
244}
245
246/**
247 * hw_read: reads from a hw register
248 * @reg:  register index
249 * @mask: bitfield mask
250 *
251 * This function returns register contents
252 */
253static inline u32 hw_read(struct ci13xxx *udc, enum ci13xxx_regs reg, u32 mask)
254{
255	return ioread32(udc->hw_bank.regmap[reg]) & mask;
256}
257
258/**
259 * hw_write: writes to a hw register
260 * @reg:  register index
261 * @mask: bitfield mask
262 * @data: new value
263 */
264static inline void hw_write(struct ci13xxx *udc, enum ci13xxx_regs reg,
265			    u32 mask, u32 data)
266{
267	if (~mask)
268		data = (ioread32(udc->hw_bank.regmap[reg]) & ~mask)
269			| (data & mask);
270
271	iowrite32(data, udc->hw_bank.regmap[reg]);
272}
273
274/**
275 * hw_test_and_clear: tests & clears a hw register
276 * @reg:  register index
277 * @mask: bitfield mask
278 *
279 * This function returns register contents
280 */
281static inline u32 hw_test_and_clear(struct ci13xxx *udc, enum ci13xxx_regs reg,
282				    u32 mask)
283{
284	u32 val = ioread32(udc->hw_bank.regmap[reg]) & mask;
285
286	iowrite32(val, udc->hw_bank.regmap[reg]);
287	return val;
288}
289
290/**
291 * hw_test_and_write: tests & writes a hw register
292 * @reg:  register index
293 * @mask: bitfield mask
294 * @data: new value
295 *
296 * This function returns register contents
297 */
298static inline u32 hw_test_and_write(struct ci13xxx *udc, enum ci13xxx_regs reg,
299				    u32 mask, u32 data)
300{
301	u32 val = hw_read(udc, reg, ~0);
302
303	hw_write(udc, reg, mask, data);
304	return (val & mask) >> ffs_nr(mask);
305}
306
307int hw_device_reset(struct ci13xxx *ci, u32 mode);
308
309int hw_port_test_set(struct ci13xxx *ci, u8 mode);
310
311u8 hw_port_test_get(struct ci13xxx *ci);
312
313#endif	/* __DRIVERS_USB_CHIPIDEA_CI_H */