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1/*
2 * Copyright (c) 2010-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef AR9003_EEPROM_H
18#define AR9003_EEPROM_H
19
20#include <linux/types.h>
21
22#define AR9300_EEP_VER 0xD000
23#define AR9300_EEP_VER_MINOR_MASK 0xFFF
24#define AR9300_EEP_MINOR_VER_1 0x1
25#define AR9300_EEP_MINOR_VER AR9300_EEP_MINOR_VER_1
26
27/* 16-bit offset location start of calibration struct */
28#define AR9300_EEP_START_LOC 256
29#define AR9300_NUM_5G_CAL_PIERS 8
30#define AR9300_NUM_2G_CAL_PIERS 3
31#define AR9300_NUM_5G_20_TARGET_POWERS 8
32#define AR9300_NUM_5G_40_TARGET_POWERS 8
33#define AR9300_NUM_2G_CCK_TARGET_POWERS 2
34#define AR9300_NUM_2G_20_TARGET_POWERS 3
35#define AR9300_NUM_2G_40_TARGET_POWERS 3
36/* #define AR9300_NUM_CTLS 21 */
37#define AR9300_NUM_CTLS_5G 9
38#define AR9300_NUM_CTLS_2G 12
39#define AR9300_NUM_BAND_EDGES_5G 8
40#define AR9300_NUM_BAND_EDGES_2G 4
41#define AR9300_EEPMISC_BIG_ENDIAN 0x01
42#define AR9300_EEPMISC_WOW 0x02
43#define AR9300_CUSTOMER_DATA_SIZE 20
44
45#define FBIN2FREQ(x, y) ((y) ? (2300 + x) : (4800 + 5 * x))
46#define AR9300_MAX_CHAINS 3
47#define AR9300_ANT_16S 25
48#define AR9300_FUTURE_MODAL_SZ 6
49
50#define AR9300_PAPRD_RATE_MASK 0x01ffffff
51#define AR9300_PAPRD_SCALE_1 0x0e000000
52#define AR9300_PAPRD_SCALE_1_S 25
53#define AR9300_PAPRD_SCALE_2 0x70000000
54#define AR9300_PAPRD_SCALE_2_S 28
55
56/* Delta from which to start power to pdadc table */
57/* This offset is used in both open loop and closed loop power control
58 * schemes. In open loop power control, it is not really needed, but for
59 * the "sake of consistency" it was kept. For certain AP designs, this
60 * value is overwritten by the value in the flag "pwrTableOffset" just
61 * before writing the pdadc vs pwr into the chip registers.
62 */
63#define AR9300_PWR_TABLE_OFFSET 0
64
65/* byte addressable */
66#define AR9300_EEPROM_SIZE (16*1024)
67
68#define AR9300_BASE_ADDR_4K 0xfff
69#define AR9300_BASE_ADDR 0x3ff
70#define AR9300_BASE_ADDR_512 0x1ff
71
72#define AR9300_OTP_BASE 0x14000
73#define AR9300_OTP_STATUS 0x15f18
74#define AR9300_OTP_STATUS_TYPE 0x7
75#define AR9300_OTP_STATUS_VALID 0x4
76#define AR9300_OTP_STATUS_ACCESS_BUSY 0x2
77#define AR9300_OTP_STATUS_SM_BUSY 0x1
78#define AR9300_OTP_READ_DATA 0x15f1c
79
80enum targetPowerHTRates {
81 HT_TARGET_RATE_0_8_16,
82 HT_TARGET_RATE_1_3_9_11_17_19,
83 HT_TARGET_RATE_4,
84 HT_TARGET_RATE_5,
85 HT_TARGET_RATE_6,
86 HT_TARGET_RATE_7,
87 HT_TARGET_RATE_12,
88 HT_TARGET_RATE_13,
89 HT_TARGET_RATE_14,
90 HT_TARGET_RATE_15,
91 HT_TARGET_RATE_20,
92 HT_TARGET_RATE_21,
93 HT_TARGET_RATE_22,
94 HT_TARGET_RATE_23
95};
96
97enum targetPowerLegacyRates {
98 LEGACY_TARGET_RATE_6_24,
99 LEGACY_TARGET_RATE_36,
100 LEGACY_TARGET_RATE_48,
101 LEGACY_TARGET_RATE_54
102};
103
104enum targetPowerCckRates {
105 LEGACY_TARGET_RATE_1L_5L,
106 LEGACY_TARGET_RATE_5S,
107 LEGACY_TARGET_RATE_11L,
108 LEGACY_TARGET_RATE_11S
109};
110
111enum ar9300_Rates {
112 ALL_TARGET_LEGACY_6_24,
113 ALL_TARGET_LEGACY_36,
114 ALL_TARGET_LEGACY_48,
115 ALL_TARGET_LEGACY_54,
116 ALL_TARGET_LEGACY_1L_5L,
117 ALL_TARGET_LEGACY_5S,
118 ALL_TARGET_LEGACY_11L,
119 ALL_TARGET_LEGACY_11S,
120 ALL_TARGET_HT20_0_8_16,
121 ALL_TARGET_HT20_1_3_9_11_17_19,
122 ALL_TARGET_HT20_4,
123 ALL_TARGET_HT20_5,
124 ALL_TARGET_HT20_6,
125 ALL_TARGET_HT20_7,
126 ALL_TARGET_HT20_12,
127 ALL_TARGET_HT20_13,
128 ALL_TARGET_HT20_14,
129 ALL_TARGET_HT20_15,
130 ALL_TARGET_HT20_20,
131 ALL_TARGET_HT20_21,
132 ALL_TARGET_HT20_22,
133 ALL_TARGET_HT20_23,
134 ALL_TARGET_HT40_0_8_16,
135 ALL_TARGET_HT40_1_3_9_11_17_19,
136 ALL_TARGET_HT40_4,
137 ALL_TARGET_HT40_5,
138 ALL_TARGET_HT40_6,
139 ALL_TARGET_HT40_7,
140 ALL_TARGET_HT40_12,
141 ALL_TARGET_HT40_13,
142 ALL_TARGET_HT40_14,
143 ALL_TARGET_HT40_15,
144 ALL_TARGET_HT40_20,
145 ALL_TARGET_HT40_21,
146 ALL_TARGET_HT40_22,
147 ALL_TARGET_HT40_23,
148 ar9300RateSize,
149};
150
151
152struct eepFlags {
153 u8 opFlags;
154 u8 eepMisc;
155} __packed;
156
157enum CompressAlgorithm {
158 _CompressNone = 0,
159 _CompressLzma,
160 _CompressPairs,
161 _CompressBlock,
162 _Compress4,
163 _Compress5,
164 _Compress6,
165 _Compress7,
166};
167
168struct ar9300_base_eep_hdr {
169 __le16 regDmn[2];
170 /* 4 bits tx and 4 bits rx */
171 u8 txrxMask;
172 struct eepFlags opCapFlags;
173 u8 rfSilent;
174 u8 blueToothOptions;
175 u8 deviceCap;
176 /* takes lower byte in eeprom location */
177 u8 deviceType;
178 /* offset in dB to be added to beginning
179 * of pdadc table in calibration
180 */
181 int8_t pwrTableOffset;
182 u8 params_for_tuning_caps[2];
183 /*
184 * bit0 - enable tx temp comp
185 * bit1 - enable tx volt comp
186 * bit2 - enable fastClock - default to 1
187 * bit3 - enable doubling - default to 1
188 * bit4 - enable internal regulator - default to 1
189 */
190 u8 featureEnable;
191 /* misc flags: bit0 - turn down drivestrength */
192 u8 miscConfiguration;
193 u8 eepromWriteEnableGpio;
194 u8 wlanDisableGpio;
195 u8 wlanLedGpio;
196 u8 rxBandSelectGpio;
197 u8 txrxgain;
198 /* SW controlled internal regulator fields */
199 __le32 swreg;
200} __packed;
201
202struct ar9300_modal_eep_header {
203 /* 4 idle, t1, t2, b (4 bits per setting) */
204 __le32 antCtrlCommon;
205 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
206 __le32 antCtrlCommon2;
207 /* 6 idle, t, r, rx1, rx12, b (2 bits each) */
208 __le16 antCtrlChain[AR9300_MAX_CHAINS];
209 /* 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
210 u8 xatten1DB[AR9300_MAX_CHAINS];
211 /* 3 xatten1_margin for merlin (0xa20c/b20c 16:12 */
212 u8 xatten1Margin[AR9300_MAX_CHAINS];
213 int8_t tempSlope;
214 int8_t voltSlope;
215 /* spur channels in usual fbin coding format */
216 u8 spurChans[AR_EEPROM_MODAL_SPURS];
217 /* 3 Check if the register is per chain */
218 int8_t noiseFloorThreshCh[AR9300_MAX_CHAINS];
219 u8 ob[AR9300_MAX_CHAINS];
220 u8 db_stage2[AR9300_MAX_CHAINS];
221 u8 db_stage3[AR9300_MAX_CHAINS];
222 u8 db_stage4[AR9300_MAX_CHAINS];
223 u8 xpaBiasLvl;
224 u8 txFrameToDataStart;
225 u8 txFrameToPaOn;
226 u8 txClip;
227 int8_t antennaGain;
228 u8 switchSettling;
229 int8_t adcDesiredSize;
230 u8 txEndToXpaOff;
231 u8 txEndToRxOn;
232 u8 txFrameToXpaOn;
233 u8 thresh62;
234 __le32 papdRateMaskHt20;
235 __le32 papdRateMaskHt40;
236 u8 futureModal[10];
237} __packed;
238
239struct ar9300_cal_data_per_freq_op_loop {
240 int8_t refPower;
241 /* pdadc voltage at power measurement */
242 u8 voltMeas;
243 /* pcdac used for power measurement */
244 u8 tempMeas;
245 /* range is -60 to -127 create a mapping equation 1db resolution */
246 int8_t rxNoisefloorCal;
247 /*range is same as noisefloor */
248 int8_t rxNoisefloorPower;
249 /* temp measured when noisefloor cal was performed */
250 u8 rxTempMeas;
251} __packed;
252
253struct cal_tgt_pow_legacy {
254 u8 tPow2x[4];
255} __packed;
256
257struct cal_tgt_pow_ht {
258 u8 tPow2x[14];
259} __packed;
260
261struct cal_ctl_data_2g {
262 u8 ctlEdges[AR9300_NUM_BAND_EDGES_2G];
263} __packed;
264
265struct cal_ctl_data_5g {
266 u8 ctlEdges[AR9300_NUM_BAND_EDGES_5G];
267} __packed;
268
269struct ar9300_BaseExtension_1 {
270 u8 ant_div_control;
271 u8 future[13];
272} __packed;
273
274struct ar9300_BaseExtension_2 {
275 int8_t tempSlopeLow;
276 int8_t tempSlopeHigh;
277 u8 xatten1DBLow[AR9300_MAX_CHAINS];
278 u8 xatten1MarginLow[AR9300_MAX_CHAINS];
279 u8 xatten1DBHigh[AR9300_MAX_CHAINS];
280 u8 xatten1MarginHigh[AR9300_MAX_CHAINS];
281} __packed;
282
283struct ar9300_eeprom {
284 u8 eepromVersion;
285 u8 templateVersion;
286 u8 macAddr[6];
287 u8 custData[AR9300_CUSTOMER_DATA_SIZE];
288
289 struct ar9300_base_eep_hdr baseEepHeader;
290
291 struct ar9300_modal_eep_header modalHeader2G;
292 struct ar9300_BaseExtension_1 base_ext1;
293 u8 calFreqPier2G[AR9300_NUM_2G_CAL_PIERS];
294 struct ar9300_cal_data_per_freq_op_loop
295 calPierData2G[AR9300_MAX_CHAINS][AR9300_NUM_2G_CAL_PIERS];
296 u8 calTarget_freqbin_Cck[AR9300_NUM_2G_CCK_TARGET_POWERS];
297 u8 calTarget_freqbin_2G[AR9300_NUM_2G_20_TARGET_POWERS];
298 u8 calTarget_freqbin_2GHT20[AR9300_NUM_2G_20_TARGET_POWERS];
299 u8 calTarget_freqbin_2GHT40[AR9300_NUM_2G_40_TARGET_POWERS];
300 struct cal_tgt_pow_legacy
301 calTargetPowerCck[AR9300_NUM_2G_CCK_TARGET_POWERS];
302 struct cal_tgt_pow_legacy
303 calTargetPower2G[AR9300_NUM_2G_20_TARGET_POWERS];
304 struct cal_tgt_pow_ht
305 calTargetPower2GHT20[AR9300_NUM_2G_20_TARGET_POWERS];
306 struct cal_tgt_pow_ht
307 calTargetPower2GHT40[AR9300_NUM_2G_40_TARGET_POWERS];
308 u8 ctlIndex_2G[AR9300_NUM_CTLS_2G];
309 u8 ctl_freqbin_2G[AR9300_NUM_CTLS_2G][AR9300_NUM_BAND_EDGES_2G];
310 struct cal_ctl_data_2g ctlPowerData_2G[AR9300_NUM_CTLS_2G];
311 struct ar9300_modal_eep_header modalHeader5G;
312 struct ar9300_BaseExtension_2 base_ext2;
313 u8 calFreqPier5G[AR9300_NUM_5G_CAL_PIERS];
314 struct ar9300_cal_data_per_freq_op_loop
315 calPierData5G[AR9300_MAX_CHAINS][AR9300_NUM_5G_CAL_PIERS];
316 u8 calTarget_freqbin_5G[AR9300_NUM_5G_20_TARGET_POWERS];
317 u8 calTarget_freqbin_5GHT20[AR9300_NUM_5G_20_TARGET_POWERS];
318 u8 calTarget_freqbin_5GHT40[AR9300_NUM_5G_40_TARGET_POWERS];
319 struct cal_tgt_pow_legacy
320 calTargetPower5G[AR9300_NUM_5G_20_TARGET_POWERS];
321 struct cal_tgt_pow_ht
322 calTargetPower5GHT20[AR9300_NUM_5G_20_TARGET_POWERS];
323 struct cal_tgt_pow_ht
324 calTargetPower5GHT40[AR9300_NUM_5G_40_TARGET_POWERS];
325 u8 ctlIndex_5G[AR9300_NUM_CTLS_5G];
326 u8 ctl_freqbin_5G[AR9300_NUM_CTLS_5G][AR9300_NUM_BAND_EDGES_5G];
327 struct cal_ctl_data_5g ctlPowerData_5G[AR9300_NUM_CTLS_5G];
328} __packed;
329
330s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah);
331s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah);
332
333u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is_2ghz);
334
335unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah,
336 struct ath9k_channel *chan);
337#endif
1/*
2 * Copyright (c) 2010-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef AR9003_EEPROM_H
18#define AR9003_EEPROM_H
19
20#include <linux/types.h>
21
22#define AR9300_EEP_VER 0xD000
23#define AR9300_EEP_VER_MINOR_MASK 0xFFF
24#define AR9300_EEP_MINOR_VER_1 0x1
25#define AR9300_EEP_MINOR_VER AR9300_EEP_MINOR_VER_1
26
27/* 16-bit offset location start of calibration struct */
28#define AR9300_EEP_START_LOC 256
29#define AR9300_NUM_5G_CAL_PIERS 8
30#define AR9300_NUM_2G_CAL_PIERS 3
31#define AR9300_NUM_5G_20_TARGET_POWERS 8
32#define AR9300_NUM_5G_40_TARGET_POWERS 8
33#define AR9300_NUM_2G_CCK_TARGET_POWERS 2
34#define AR9300_NUM_2G_20_TARGET_POWERS 3
35#define AR9300_NUM_2G_40_TARGET_POWERS 3
36/* #define AR9300_NUM_CTLS 21 */
37#define AR9300_NUM_CTLS_5G 9
38#define AR9300_NUM_CTLS_2G 12
39#define AR9300_NUM_BAND_EDGES_5G 8
40#define AR9300_NUM_BAND_EDGES_2G 4
41#define AR9300_EEPMISC_BIG_ENDIAN 0x01
42#define AR9300_EEPMISC_WOW 0x02
43#define AR9300_CUSTOMER_DATA_SIZE 20
44
45#define AR9300_MAX_CHAINS 3
46#define AR9300_ANT_16S 25
47#define AR9300_FUTURE_MODAL_SZ 6
48
49#define AR9300_PAPRD_RATE_MASK 0x01ffffff
50#define AR9300_PAPRD_SCALE_1 0x0e000000
51#define AR9300_PAPRD_SCALE_1_S 25
52#define AR9300_PAPRD_SCALE_2 0x70000000
53#define AR9300_PAPRD_SCALE_2_S 28
54
55/* Delta from which to start power to pdadc table */
56/* This offset is used in both open loop and closed loop power control
57 * schemes. In open loop power control, it is not really needed, but for
58 * the "sake of consistency" it was kept. For certain AP designs, this
59 * value is overwritten by the value in the flag "pwrTableOffset" just
60 * before writing the pdadc vs pwr into the chip registers.
61 */
62#define AR9300_PWR_TABLE_OFFSET 0
63
64/* byte addressable */
65#define AR9300_EEPROM_SIZE (16*1024)
66
67#define AR9300_BASE_ADDR_4K 0xfff
68#define AR9300_BASE_ADDR 0x3ff
69#define AR9300_BASE_ADDR_512 0x1ff
70
71#define AR9300_OTP_BASE 0x14000
72#define AR9300_OTP_STATUS 0x15f18
73#define AR9300_OTP_STATUS_TYPE 0x7
74#define AR9300_OTP_STATUS_VALID 0x4
75#define AR9300_OTP_STATUS_ACCESS_BUSY 0x2
76#define AR9300_OTP_STATUS_SM_BUSY 0x1
77#define AR9300_OTP_READ_DATA 0x15f1c
78
79enum targetPowerHTRates {
80 HT_TARGET_RATE_0_8_16,
81 HT_TARGET_RATE_1_3_9_11_17_19,
82 HT_TARGET_RATE_4,
83 HT_TARGET_RATE_5,
84 HT_TARGET_RATE_6,
85 HT_TARGET_RATE_7,
86 HT_TARGET_RATE_12,
87 HT_TARGET_RATE_13,
88 HT_TARGET_RATE_14,
89 HT_TARGET_RATE_15,
90 HT_TARGET_RATE_20,
91 HT_TARGET_RATE_21,
92 HT_TARGET_RATE_22,
93 HT_TARGET_RATE_23
94};
95
96enum targetPowerLegacyRates {
97 LEGACY_TARGET_RATE_6_24,
98 LEGACY_TARGET_RATE_36,
99 LEGACY_TARGET_RATE_48,
100 LEGACY_TARGET_RATE_54
101};
102
103enum targetPowerCckRates {
104 LEGACY_TARGET_RATE_1L_5L,
105 LEGACY_TARGET_RATE_5S,
106 LEGACY_TARGET_RATE_11L,
107 LEGACY_TARGET_RATE_11S
108};
109
110enum ar9300_Rates {
111 ALL_TARGET_LEGACY_6_24,
112 ALL_TARGET_LEGACY_36,
113 ALL_TARGET_LEGACY_48,
114 ALL_TARGET_LEGACY_54,
115 ALL_TARGET_LEGACY_1L_5L,
116 ALL_TARGET_LEGACY_5S,
117 ALL_TARGET_LEGACY_11L,
118 ALL_TARGET_LEGACY_11S,
119 ALL_TARGET_HT20_0_8_16,
120 ALL_TARGET_HT20_1_3_9_11_17_19,
121 ALL_TARGET_HT20_4,
122 ALL_TARGET_HT20_5,
123 ALL_TARGET_HT20_6,
124 ALL_TARGET_HT20_7,
125 ALL_TARGET_HT20_12,
126 ALL_TARGET_HT20_13,
127 ALL_TARGET_HT20_14,
128 ALL_TARGET_HT20_15,
129 ALL_TARGET_HT20_20,
130 ALL_TARGET_HT20_21,
131 ALL_TARGET_HT20_22,
132 ALL_TARGET_HT20_23,
133 ALL_TARGET_HT40_0_8_16,
134 ALL_TARGET_HT40_1_3_9_11_17_19,
135 ALL_TARGET_HT40_4,
136 ALL_TARGET_HT40_5,
137 ALL_TARGET_HT40_6,
138 ALL_TARGET_HT40_7,
139 ALL_TARGET_HT40_12,
140 ALL_TARGET_HT40_13,
141 ALL_TARGET_HT40_14,
142 ALL_TARGET_HT40_15,
143 ALL_TARGET_HT40_20,
144 ALL_TARGET_HT40_21,
145 ALL_TARGET_HT40_22,
146 ALL_TARGET_HT40_23,
147 ar9300RateSize,
148};
149
150
151struct eepFlags {
152 u8 opFlags;
153 u8 eepMisc;
154} __packed;
155
156enum CompressAlgorithm {
157 _CompressNone = 0,
158 _CompressLzma,
159 _CompressPairs,
160 _CompressBlock,
161 _Compress4,
162 _Compress5,
163 _Compress6,
164 _Compress7,
165};
166
167struct ar9300_base_eep_hdr {
168 __le16 regDmn[2];
169 /* 4 bits tx and 4 bits rx */
170 u8 txrxMask;
171 struct eepFlags opCapFlags;
172 u8 rfSilent;
173 u8 blueToothOptions;
174 u8 deviceCap;
175 /* takes lower byte in eeprom location */
176 u8 deviceType;
177 /* offset in dB to be added to beginning
178 * of pdadc table in calibration
179 */
180 int8_t pwrTableOffset;
181 u8 params_for_tuning_caps[2];
182 /*
183 * bit0 - enable tx temp comp
184 * bit1 - enable tx volt comp
185 * bit2 - enable fastClock - default to 1
186 * bit3 - enable doubling - default to 1
187 * bit4 - enable internal regulator - default to 1
188 */
189 u8 featureEnable;
190 /* misc flags: bit0 - turn down drivestrength */
191 u8 miscConfiguration;
192 u8 eepromWriteEnableGpio;
193 u8 wlanDisableGpio;
194 u8 wlanLedGpio;
195 u8 rxBandSelectGpio;
196 u8 txrxgain;
197 /* SW controlled internal regulator fields */
198 __le32 swreg;
199} __packed;
200
201struct ar9300_modal_eep_header {
202 /* 4 idle, t1, t2, b (4 bits per setting) */
203 __le32 antCtrlCommon;
204 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
205 __le32 antCtrlCommon2;
206 /* 6 idle, t, r, rx1, rx12, b (2 bits each) */
207 __le16 antCtrlChain[AR9300_MAX_CHAINS];
208 /* 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
209 u8 xatten1DB[AR9300_MAX_CHAINS];
210 /* 3 xatten1_margin for merlin (0xa20c/b20c 16:12 */
211 u8 xatten1Margin[AR9300_MAX_CHAINS];
212 int8_t tempSlope;
213 int8_t voltSlope;
214 /* spur channels in usual fbin coding format */
215 u8 spurChans[AR_EEPROM_MODAL_SPURS];
216 /* 3 Check if the register is per chain */
217 int8_t noiseFloorThreshCh[AR9300_MAX_CHAINS];
218 u8 reserved[11];
219 int8_t quick_drop;
220 u8 xpaBiasLvl;
221 u8 txFrameToDataStart;
222 u8 txFrameToPaOn;
223 u8 txClip;
224 int8_t antennaGain;
225 u8 switchSettling;
226 int8_t adcDesiredSize;
227 u8 txEndToXpaOff;
228 u8 txEndToRxOn;
229 u8 txFrameToXpaOn;
230 u8 thresh62;
231 __le32 papdRateMaskHt20;
232 __le32 papdRateMaskHt40;
233 __le16 switchcomspdt;
234 u8 futureModal[8];
235} __packed;
236
237struct ar9300_cal_data_per_freq_op_loop {
238 int8_t refPower;
239 /* pdadc voltage at power measurement */
240 u8 voltMeas;
241 /* pcdac used for power measurement */
242 u8 tempMeas;
243 /* range is -60 to -127 create a mapping equation 1db resolution */
244 int8_t rxNoisefloorCal;
245 /*range is same as noisefloor */
246 int8_t rxNoisefloorPower;
247 /* temp measured when noisefloor cal was performed */
248 u8 rxTempMeas;
249} __packed;
250
251struct cal_tgt_pow_legacy {
252 u8 tPow2x[4];
253} __packed;
254
255struct cal_tgt_pow_ht {
256 u8 tPow2x[14];
257} __packed;
258
259struct cal_ctl_data_2g {
260 u8 ctlEdges[AR9300_NUM_BAND_EDGES_2G];
261} __packed;
262
263struct cal_ctl_data_5g {
264 u8 ctlEdges[AR9300_NUM_BAND_EDGES_5G];
265} __packed;
266
267struct ar9300_BaseExtension_1 {
268 u8 ant_div_control;
269 u8 future[11];
270 int8_t quick_drop_low;
271 int8_t quick_drop_high;
272} __packed;
273
274struct ar9300_BaseExtension_2 {
275 int8_t tempSlopeLow;
276 int8_t tempSlopeHigh;
277 u8 xatten1DBLow[AR9300_MAX_CHAINS];
278 u8 xatten1MarginLow[AR9300_MAX_CHAINS];
279 u8 xatten1DBHigh[AR9300_MAX_CHAINS];
280 u8 xatten1MarginHigh[AR9300_MAX_CHAINS];
281} __packed;
282
283struct ar9300_eeprom {
284 u8 eepromVersion;
285 u8 templateVersion;
286 u8 macAddr[6];
287 u8 custData[AR9300_CUSTOMER_DATA_SIZE];
288
289 struct ar9300_base_eep_hdr baseEepHeader;
290
291 struct ar9300_modal_eep_header modalHeader2G;
292 struct ar9300_BaseExtension_1 base_ext1;
293 u8 calFreqPier2G[AR9300_NUM_2G_CAL_PIERS];
294 struct ar9300_cal_data_per_freq_op_loop
295 calPierData2G[AR9300_MAX_CHAINS][AR9300_NUM_2G_CAL_PIERS];
296 u8 calTarget_freqbin_Cck[AR9300_NUM_2G_CCK_TARGET_POWERS];
297 u8 calTarget_freqbin_2G[AR9300_NUM_2G_20_TARGET_POWERS];
298 u8 calTarget_freqbin_2GHT20[AR9300_NUM_2G_20_TARGET_POWERS];
299 u8 calTarget_freqbin_2GHT40[AR9300_NUM_2G_40_TARGET_POWERS];
300 struct cal_tgt_pow_legacy
301 calTargetPowerCck[AR9300_NUM_2G_CCK_TARGET_POWERS];
302 struct cal_tgt_pow_legacy
303 calTargetPower2G[AR9300_NUM_2G_20_TARGET_POWERS];
304 struct cal_tgt_pow_ht
305 calTargetPower2GHT20[AR9300_NUM_2G_20_TARGET_POWERS];
306 struct cal_tgt_pow_ht
307 calTargetPower2GHT40[AR9300_NUM_2G_40_TARGET_POWERS];
308 u8 ctlIndex_2G[AR9300_NUM_CTLS_2G];
309 u8 ctl_freqbin_2G[AR9300_NUM_CTLS_2G][AR9300_NUM_BAND_EDGES_2G];
310 struct cal_ctl_data_2g ctlPowerData_2G[AR9300_NUM_CTLS_2G];
311 struct ar9300_modal_eep_header modalHeader5G;
312 struct ar9300_BaseExtension_2 base_ext2;
313 u8 calFreqPier5G[AR9300_NUM_5G_CAL_PIERS];
314 struct ar9300_cal_data_per_freq_op_loop
315 calPierData5G[AR9300_MAX_CHAINS][AR9300_NUM_5G_CAL_PIERS];
316 u8 calTarget_freqbin_5G[AR9300_NUM_5G_20_TARGET_POWERS];
317 u8 calTarget_freqbin_5GHT20[AR9300_NUM_5G_20_TARGET_POWERS];
318 u8 calTarget_freqbin_5GHT40[AR9300_NUM_5G_40_TARGET_POWERS];
319 struct cal_tgt_pow_legacy
320 calTargetPower5G[AR9300_NUM_5G_20_TARGET_POWERS];
321 struct cal_tgt_pow_ht
322 calTargetPower5GHT20[AR9300_NUM_5G_20_TARGET_POWERS];
323 struct cal_tgt_pow_ht
324 calTargetPower5GHT40[AR9300_NUM_5G_40_TARGET_POWERS];
325 u8 ctlIndex_5G[AR9300_NUM_CTLS_5G];
326 u8 ctl_freqbin_5G[AR9300_NUM_CTLS_5G][AR9300_NUM_BAND_EDGES_5G];
327 struct cal_ctl_data_5g ctlPowerData_5G[AR9300_NUM_CTLS_5G];
328} __packed;
329
330s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah);
331s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah);
332
333u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is_2ghz);
334
335unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah,
336 struct ath9k_channel *chan);
337
338void ar9003_hw_internal_regulator_apply(struct ath_hw *ah);
339
340#endif