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1/*
2 * Copyright (c) 2004-2010 Atheros Communications Inc.
3 * Copyright (c) 2011 Qualcomm Atheros, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18#ifndef TARGET_H
19#define TARGET_H
20
21#define AR6003_BOARD_DATA_SZ 1024
22#define AR6003_BOARD_EXT_DATA_SZ 768
23#define AR6003_BOARD_EXT_DATA_SZ_V2 1024
24
25#define AR6004_BOARD_DATA_SZ 6144
26#define AR6004_BOARD_EXT_DATA_SZ 0
27
28#define RESET_CONTROL_ADDRESS 0x00000000
29#define RESET_CONTROL_COLD_RST 0x00000100
30#define RESET_CONTROL_MBOX_RST 0x00000004
31
32#define CPU_CLOCK_STANDARD_S 0
33#define CPU_CLOCK_STANDARD 0x00000003
34#define CPU_CLOCK_ADDRESS 0x00000020
35
36#define CLOCK_CONTROL_ADDRESS 0x00000028
37#define CLOCK_CONTROL_LF_CLK32_S 2
38#define CLOCK_CONTROL_LF_CLK32 0x00000004
39
40#define SYSTEM_SLEEP_ADDRESS 0x000000c4
41#define SYSTEM_SLEEP_DISABLE_S 0
42#define SYSTEM_SLEEP_DISABLE 0x00000001
43
44#define LPO_CAL_ADDRESS 0x000000e0
45#define LPO_CAL_ENABLE_S 20
46#define LPO_CAL_ENABLE 0x00100000
47
48#define GPIO_PIN10_ADDRESS 0x00000050
49#define GPIO_PIN11_ADDRESS 0x00000054
50#define GPIO_PIN12_ADDRESS 0x00000058
51#define GPIO_PIN13_ADDRESS 0x0000005c
52
53#define HOST_INT_STATUS_ADDRESS 0x00000400
54#define HOST_INT_STATUS_ERROR_S 7
55#define HOST_INT_STATUS_ERROR 0x00000080
56
57#define HOST_INT_STATUS_CPU_S 6
58#define HOST_INT_STATUS_CPU 0x00000040
59
60#define HOST_INT_STATUS_COUNTER_S 4
61#define HOST_INT_STATUS_COUNTER 0x00000010
62
63#define CPU_INT_STATUS_ADDRESS 0x00000401
64
65#define ERROR_INT_STATUS_ADDRESS 0x00000402
66#define ERROR_INT_STATUS_WAKEUP_S 2
67#define ERROR_INT_STATUS_WAKEUP 0x00000004
68
69#define ERROR_INT_STATUS_RX_UNDERFLOW_S 1
70#define ERROR_INT_STATUS_RX_UNDERFLOW 0x00000002
71
72#define ERROR_INT_STATUS_TX_OVERFLOW_S 0
73#define ERROR_INT_STATUS_TX_OVERFLOW 0x00000001
74
75#define COUNTER_INT_STATUS_ADDRESS 0x00000403
76#define COUNTER_INT_STATUS_COUNTER_S 0
77#define COUNTER_INT_STATUS_COUNTER 0x000000ff
78
79#define RX_LOOKAHEAD_VALID_ADDRESS 0x00000405
80
81#define INT_STATUS_ENABLE_ADDRESS 0x00000418
82#define INT_STATUS_ENABLE_ERROR_S 7
83#define INT_STATUS_ENABLE_ERROR 0x00000080
84
85#define INT_STATUS_ENABLE_CPU_S 6
86#define INT_STATUS_ENABLE_CPU 0x00000040
87
88#define INT_STATUS_ENABLE_INT_S 5
89#define INT_STATUS_ENABLE_INT 0x00000020
90#define INT_STATUS_ENABLE_COUNTER_S 4
91#define INT_STATUS_ENABLE_COUNTER 0x00000010
92
93#define INT_STATUS_ENABLE_MBOX_DATA_S 0
94#define INT_STATUS_ENABLE_MBOX_DATA 0x0000000f
95
96#define CPU_INT_STATUS_ENABLE_ADDRESS 0x00000419
97#define CPU_INT_STATUS_ENABLE_BIT_S 0
98#define CPU_INT_STATUS_ENABLE_BIT 0x000000ff
99
100#define ERROR_STATUS_ENABLE_ADDRESS 0x0000041a
101#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_S 1
102#define ERROR_STATUS_ENABLE_RX_UNDERFLOW 0x00000002
103
104#define ERROR_STATUS_ENABLE_TX_OVERFLOW_S 0
105#define ERROR_STATUS_ENABLE_TX_OVERFLOW 0x00000001
106
107#define COUNTER_INT_STATUS_ENABLE_ADDRESS 0x0000041b
108#define COUNTER_INT_STATUS_ENABLE_BIT_S 0
109#define COUNTER_INT_STATUS_ENABLE_BIT 0x000000ff
110
111#define COUNT_ADDRESS 0x00000420
112
113#define COUNT_DEC_ADDRESS 0x00000440
114
115#define WINDOW_DATA_ADDRESS 0x00000474
116#define WINDOW_WRITE_ADDR_ADDRESS 0x00000478
117#define WINDOW_READ_ADDR_ADDRESS 0x0000047c
118#define CPU_DBG_SEL_ADDRESS 0x00000483
119#define CPU_DBG_ADDRESS 0x00000484
120
121#define LOCAL_SCRATCH_ADDRESS 0x000000c0
122#define ATH6KL_OPTION_SLEEP_DISABLE 0x08
123
124#define RTC_BASE_ADDRESS 0x00004000
125#define GPIO_BASE_ADDRESS 0x00014000
126#define MBOX_BASE_ADDRESS 0x00018000
127#define ANALOG_INTF_BASE_ADDRESS 0x0001c000
128
129/* real name of the register is unknown */
130#define ATH6KL_ANALOG_PLL_REGISTER (ANALOG_INTF_BASE_ADDRESS + 0x284)
131
132#define SM(f, v) (((v) << f##_S) & f)
133#define MS(f, v) (((v) & f) >> f##_S)
134
135/*
136 * xxx_HOST_INTEREST_ADDRESS is the address in Target RAM of the
137 * host_interest structure.
138 *
139 * Host Interest is shared between Host and Target in order to coordinate
140 * between the two, and is intended to remain constant (with additions only
141 * at the end).
142 */
143#define ATH6KL_AR6003_HI_START_ADDR 0x00540600
144#define ATH6KL_AR6004_HI_START_ADDR 0x00400800
145
146/*
147 * These are items that the Host may need to access
148 * via BMI or via the Diagnostic Window. The position
149 * of items in this structure must remain constant.
150 * across firmware revisions!
151 *
152 * Types for each item must be fixed size across target and host platforms.
153 * The structure is used only to calculate offset for each register with
154 * HI_ITEM() macro, no values are stored to it.
155 *
156 * More items may be added at the end.
157 */
158struct host_interest {
159 /*
160 * Pointer to application-defined area, if any.
161 * Set by Target application during startup.
162 */
163 u32 hi_app_host_interest; /* 0x00 */
164
165 /* Pointer to register dump area, valid after Target crash. */
166 u32 hi_failure_state; /* 0x04 */
167
168 /* Pointer to debug logging header */
169 u32 hi_dbglog_hdr; /* 0x08 */
170
171 u32 hi_unused1; /* 0x0c */
172
173 /*
174 * General-purpose flag bits, similar to ATH6KL_OPTION_* flags.
175 * Can be used by application rather than by OS.
176 */
177 u32 hi_option_flag; /* 0x10 */
178
179 /*
180 * Boolean that determines whether or not to
181 * display messages on the serial port.
182 */
183 u32 hi_serial_enable; /* 0x14 */
184
185 /* Start address of DataSet index, if any */
186 u32 hi_dset_list_head; /* 0x18 */
187
188 /* Override Target application start address */
189 u32 hi_app_start; /* 0x1c */
190
191 /* Clock and voltage tuning */
192 u32 hi_skip_clock_init; /* 0x20 */
193 u32 hi_core_clock_setting; /* 0x24 */
194 u32 hi_cpu_clock_setting; /* 0x28 */
195 u32 hi_system_sleep_setting; /* 0x2c */
196 u32 hi_xtal_control_setting; /* 0x30 */
197 u32 hi_pll_ctrl_setting_24ghz; /* 0x34 */
198 u32 hi_pll_ctrl_setting_5ghz; /* 0x38 */
199 u32 hi_ref_voltage_trim_setting; /* 0x3c */
200 u32 hi_clock_info; /* 0x40 */
201
202 /*
203 * Flash configuration overrides, used only
204 * when firmware is not executing from flash.
205 * (When using flash, modify the global variables
206 * with equivalent names.)
207 */
208 u32 hi_bank0_addr_value; /* 0x44 */
209 u32 hi_bank0_read_value; /* 0x48 */
210 u32 hi_bank0_write_value; /* 0x4c */
211 u32 hi_bank0_config_value; /* 0x50 */
212
213 /* Pointer to Board Data */
214 u32 hi_board_data; /* 0x54 */
215 u32 hi_board_data_initialized; /* 0x58 */
216
217 u32 hi_dset_ram_index_tbl; /* 0x5c */
218
219 u32 hi_desired_baud_rate; /* 0x60 */
220 u32 hi_dbglog_config; /* 0x64 */
221 u32 hi_end_ram_reserve_sz; /* 0x68 */
222 u32 hi_mbox_io_block_sz; /* 0x6c */
223
224 u32 hi_num_bpatch_streams; /* 0x70 -- unused */
225 u32 hi_mbox_isr_yield_limit; /* 0x74 */
226
227 u32 hi_refclk_hz; /* 0x78 */
228 u32 hi_ext_clk_detected; /* 0x7c */
229 u32 hi_dbg_uart_txpin; /* 0x80 */
230 u32 hi_dbg_uart_rxpin; /* 0x84 */
231 u32 hi_hci_uart_baud; /* 0x88 */
232 u32 hi_hci_uart_pin_assignments; /* 0x8C */
233 /*
234 * NOTE: byte [0] = tx pin, [1] = rx pin, [2] = rts pin, [3] = cts
235 * pin
236 */
237 u32 hi_hci_uart_baud_scale_val; /* 0x90 */
238 u32 hi_hci_uart_baud_step_val; /* 0x94 */
239
240 u32 hi_allocram_start; /* 0x98 */
241 u32 hi_allocram_sz; /* 0x9c */
242 u32 hi_hci_bridge_flags; /* 0xa0 */
243 u32 hi_hci_uart_support_pins; /* 0xa4 */
244 /*
245 * NOTE: byte [0] = RESET pin (bit 7 is polarity),
246 * bytes[1]..bytes[3] are for future use
247 */
248 u32 hi_hci_uart_pwr_mgmt_params; /* 0xa8 */
249 /*
250 * 0xa8 - [1]: 0 = UART FC active low, 1 = UART FC active high
251 * [31:16]: wakeup timeout in ms
252 */
253
254 /* Pointer to extended board data */
255 u32 hi_board_ext_data; /* 0xac */
256 u32 hi_board_ext_data_config; /* 0xb0 */
257
258 /*
259 * Bit [0] : valid
260 * Bit[31:16: size
261 */
262 /*
263 * hi_reset_flag is used to do some stuff when target reset.
264 * such as restore app_start after warm reset or
265 * preserve host Interest area, or preserve ROM data, literals etc.
266 */
267 u32 hi_reset_flag; /* 0xb4 */
268 /* indicate hi_reset_flag is valid */
269 u32 hi_reset_flag_valid; /* 0xb8 */
270 u32 hi_hci_uart_pwr_mgmt_params_ext; /* 0xbc */
271 /*
272 * 0xbc - [31:0]: idle timeout in ms
273 */
274 /* ACS flags */
275 u32 hi_acs_flags; /* 0xc0 */
276 u32 hi_console_flags; /* 0xc4 */
277 u32 hi_nvram_state; /* 0xc8 */
278 u32 hi_option_flag2; /* 0xcc */
279
280 /* If non-zero, override values sent to Host in WMI_READY event. */
281 u32 hi_sw_version_override; /* 0xd0 */
282 u32 hi_abi_version_override; /* 0xd4 */
283
284 /*
285 * Percentage of high priority RX traffic to total expected RX traffic -
286 * applicable only to ar6004
287 */
288 u32 hi_hp_rx_traffic_ratio; /* 0xd8 */
289
290 /* test applications flags */
291 u32 hi_test_apps_related ; /* 0xdc */
292 /* location of test script */
293 u32 hi_ota_testscript; /* 0xe0 */
294 /* location of CAL data */
295 u32 hi_cal_data; /* 0xe4 */
296 /* Number of packet log buffers */
297 u32 hi_pktlog_num_buffers; /* 0xe8 */
298
299} __packed;
300
301#define HI_ITEM(item) offsetof(struct host_interest, item)
302
303#define HI_OPTION_MAC_ADDR_METHOD_SHIFT 3
304
305#define HI_OPTION_FW_MODE_IBSS 0x0
306#define HI_OPTION_FW_MODE_BSS_STA 0x1
307#define HI_OPTION_FW_MODE_AP 0x2
308
309#define HI_OPTION_FW_SUBMODE_NONE 0x0
310#define HI_OPTION_FW_SUBMODE_P2PDEV 0x1
311#define HI_OPTION_FW_SUBMODE_P2PCLIENT 0x2
312#define HI_OPTION_FW_SUBMODE_P2PGO 0x3
313
314#define HI_OPTION_NUM_DEV_SHIFT 0x9
315
316#define HI_OPTION_FW_BRIDGE_SHIFT 0x04
317
318/* Fw Mode/SubMode Mask
319|------------------------------------------------------------------------------|
320| SUB | SUB | SUB | SUB | | | |
321| MODE[3] | MODE[2] | MODE[1] | MODE[0] | MODE[3] | MODE[2] | MODE[1] | MODE[0|
322| (2) | (2) | (2) | (2) | (2) | (2) | (2) | (2)
323|------------------------------------------------------------------------------|
324*/
325#define HI_OPTION_FW_MODE_BITS 0x2
326#define HI_OPTION_FW_MODE_SHIFT 0xC
327
328#define HI_OPTION_FW_SUBMODE_BITS 0x2
329#define HI_OPTION_FW_SUBMODE_SHIFT 0x14
330
331/* Convert a Target virtual address into a Target physical address */
332#define AR6003_VTOP(vaddr) ((vaddr) & 0x001fffff)
333#define AR6004_VTOP(vaddr) (vaddr)
334
335#define TARG_VTOP(target_type, vaddr) \
336 (((target_type) == TARGET_TYPE_AR6003) ? AR6003_VTOP(vaddr) : \
337 (((target_type) == TARGET_TYPE_AR6004) ? AR6004_VTOP(vaddr) : 0))
338
339#define ATH6KL_FWLOG_PAYLOAD_SIZE 1500
340
341struct ath6kl_dbglog_buf {
342 __le32 next;
343 __le32 buffer_addr;
344 __le32 bufsize;
345 __le32 length;
346 __le32 count;
347 __le32 free;
348} __packed;
349
350struct ath6kl_dbglog_hdr {
351 __le32 dbuf_addr;
352 __le32 dropped;
353} __packed;
354
355#endif