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1/*
2 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
3 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
4 <mdsxyz123@yahoo.com>
5 Copyright (C) 2007, 2008 Jean Delvare <khali@linux-fr.org>
6 Copyright (C) 2010 Intel Corporation,
7 David Woodhouse <dwmw2@infradead.org>
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22*/
23
24/*
25 Supports the following Intel I/O Controller Hubs (ICH):
26
27 I/O Block I2C
28 region SMBus Block proc. block
29 Chip name PCI ID size PEC buffer call read
30 ----------------------------------------------------------------------
31 82801AA (ICH) 0x2413 16 no no no no
32 82801AB (ICH0) 0x2423 16 no no no no
33 82801BA (ICH2) 0x2443 16 no no no no
34 82801CA (ICH3) 0x2483 32 soft no no no
35 82801DB (ICH4) 0x24c3 32 hard yes no no
36 82801E (ICH5) 0x24d3 32 hard yes yes yes
37 6300ESB 0x25a4 32 hard yes yes yes
38 82801F (ICH6) 0x266a 32 hard yes yes yes
39 6310ESB/6320ESB 0x269b 32 hard yes yes yes
40 82801G (ICH7) 0x27da 32 hard yes yes yes
41 82801H (ICH8) 0x283e 32 hard yes yes yes
42 82801I (ICH9) 0x2930 32 hard yes yes yes
43 EP80579 (Tolapai) 0x5032 32 hard yes yes yes
44 ICH10 0x3a30 32 hard yes yes yes
45 ICH10 0x3a60 32 hard yes yes yes
46 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes
47 6 Series (PCH) 0x1c22 32 hard yes yes yes
48 Patsburg (PCH) 0x1d22 32 hard yes yes yes
49 Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes
50 Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes
51 Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes
52 DH89xxCC (PCH) 0x2330 32 hard yes yes yes
53 Panther Point (PCH) 0x1e22 32 hard yes yes yes
54
55 Features supported by this driver:
56 Software PEC no
57 Hardware PEC yes
58 Block buffer yes
59 Block process call transaction no
60 I2C block read transaction yes (doesn't use the block buffer)
61 Slave mode no
62
63 See the file Documentation/i2c/busses/i2c-i801 for details.
64*/
65
66#include <linux/module.h>
67#include <linux/pci.h>
68#include <linux/kernel.h>
69#include <linux/stddef.h>
70#include <linux/delay.h>
71#include <linux/ioport.h>
72#include <linux/init.h>
73#include <linux/i2c.h>
74#include <linux/acpi.h>
75#include <linux/io.h>
76#include <linux/dmi.h>
77#include <linux/slab.h>
78
79/* I801 SMBus address offsets */
80#define SMBHSTSTS(p) (0 + (p)->smba)
81#define SMBHSTCNT(p) (2 + (p)->smba)
82#define SMBHSTCMD(p) (3 + (p)->smba)
83#define SMBHSTADD(p) (4 + (p)->smba)
84#define SMBHSTDAT0(p) (5 + (p)->smba)
85#define SMBHSTDAT1(p) (6 + (p)->smba)
86#define SMBBLKDAT(p) (7 + (p)->smba)
87#define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */
88#define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */
89#define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */
90
91/* PCI Address Constants */
92#define SMBBAR 4
93#define SMBHSTCFG 0x040
94
95/* Host configuration bits for SMBHSTCFG */
96#define SMBHSTCFG_HST_EN 1
97#define SMBHSTCFG_SMB_SMI_EN 2
98#define SMBHSTCFG_I2C_EN 4
99
100/* Auxiliary control register bits, ICH4+ only */
101#define SMBAUXCTL_CRC 1
102#define SMBAUXCTL_E32B 2
103
104/* kill bit for SMBHSTCNT */
105#define SMBHSTCNT_KILL 2
106
107/* Other settings */
108#define MAX_TIMEOUT 100
109#define ENABLE_INT9 0 /* set to 0x01 to enable - untested */
110
111/* I801 command constants */
112#define I801_QUICK 0x00
113#define I801_BYTE 0x04
114#define I801_BYTE_DATA 0x08
115#define I801_WORD_DATA 0x0C
116#define I801_PROC_CALL 0x10 /* unimplemented */
117#define I801_BLOCK_DATA 0x14
118#define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
119#define I801_BLOCK_LAST 0x34
120#define I801_I2C_BLOCK_LAST 0x38 /* ICH5 and later */
121#define I801_START 0x40
122#define I801_PEC_EN 0x80 /* ICH3 and later */
123
124/* I801 Hosts Status register bits */
125#define SMBHSTSTS_BYTE_DONE 0x80
126#define SMBHSTSTS_INUSE_STS 0x40
127#define SMBHSTSTS_SMBALERT_STS 0x20
128#define SMBHSTSTS_FAILED 0x10
129#define SMBHSTSTS_BUS_ERR 0x08
130#define SMBHSTSTS_DEV_ERR 0x04
131#define SMBHSTSTS_INTR 0x02
132#define SMBHSTSTS_HOST_BUSY 0x01
133
134#define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_FAILED | \
135 SMBHSTSTS_BUS_ERR | SMBHSTSTS_DEV_ERR | \
136 SMBHSTSTS_INTR)
137
138/* Older devices have their ID defined in <linux/pci_ids.h> */
139#define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
140#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
141/* Patsburg also has three 'Integrated Device Function' SMBus controllers */
142#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
143#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
144#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
145#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22
146#define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330
147#define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
148
149struct i801_priv {
150 struct i2c_adapter adapter;
151 unsigned long smba;
152 unsigned char original_hstcfg;
153 struct pci_dev *pci_dev;
154 unsigned int features;
155};
156
157static struct pci_driver i801_driver;
158
159#define FEATURE_SMBUS_PEC (1 << 0)
160#define FEATURE_BLOCK_BUFFER (1 << 1)
161#define FEATURE_BLOCK_PROC (1 << 2)
162#define FEATURE_I2C_BLOCK_READ (1 << 3)
163/* Not really a feature, but it's convenient to handle it as such */
164#define FEATURE_IDF (1 << 15)
165
166static const char *i801_feature_names[] = {
167 "SMBus PEC",
168 "Block buffer",
169 "Block process call",
170 "I2C block read",
171};
172
173static unsigned int disable_features;
174module_param(disable_features, uint, S_IRUGO | S_IWUSR);
175MODULE_PARM_DESC(disable_features, "Disable selected driver features");
176
177/* Make sure the SMBus host is ready to start transmitting.
178 Return 0 if it is, -EBUSY if it is not. */
179static int i801_check_pre(struct i801_priv *priv)
180{
181 int status;
182
183 status = inb_p(SMBHSTSTS(priv));
184 if (status & SMBHSTSTS_HOST_BUSY) {
185 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
186 return -EBUSY;
187 }
188
189 status &= STATUS_FLAGS;
190 if (status) {
191 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
192 status);
193 outb_p(status, SMBHSTSTS(priv));
194 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
195 if (status) {
196 dev_err(&priv->pci_dev->dev,
197 "Failed clearing status flags (%02x)\n",
198 status);
199 return -EBUSY;
200 }
201 }
202
203 return 0;
204}
205
206/* Convert the status register to an error code, and clear it. */
207static int i801_check_post(struct i801_priv *priv, int status, int timeout)
208{
209 int result = 0;
210
211 /* If the SMBus is still busy, we give up */
212 if (timeout) {
213 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
214 /* try to stop the current command */
215 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
216 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
217 SMBHSTCNT(priv));
218 msleep(1);
219 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
220 SMBHSTCNT(priv));
221
222 /* Check if it worked */
223 status = inb_p(SMBHSTSTS(priv));
224 if ((status & SMBHSTSTS_HOST_BUSY) ||
225 !(status & SMBHSTSTS_FAILED))
226 dev_err(&priv->pci_dev->dev,
227 "Failed terminating the transaction\n");
228 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
229 return -ETIMEDOUT;
230 }
231
232 if (status & SMBHSTSTS_FAILED) {
233 result = -EIO;
234 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
235 }
236 if (status & SMBHSTSTS_DEV_ERR) {
237 result = -ENXIO;
238 dev_dbg(&priv->pci_dev->dev, "No response\n");
239 }
240 if (status & SMBHSTSTS_BUS_ERR) {
241 result = -EAGAIN;
242 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
243 }
244
245 if (result) {
246 /* Clear error flags */
247 outb_p(status & STATUS_FLAGS, SMBHSTSTS(priv));
248 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
249 if (status) {
250 dev_warn(&priv->pci_dev->dev, "Failed clearing status "
251 "flags at end of transaction (%02x)\n",
252 status);
253 }
254 }
255
256 return result;
257}
258
259static int i801_transaction(struct i801_priv *priv, int xact)
260{
261 int status;
262 int result;
263 int timeout = 0;
264
265 result = i801_check_pre(priv);
266 if (result < 0)
267 return result;
268
269 /* the current contents of SMBHSTCNT can be overwritten, since PEC,
270 * INTREN, SMBSCMD are passed in xact */
271 outb_p(xact | I801_START, SMBHSTCNT(priv));
272
273 /* We will always wait for a fraction of a second! */
274 do {
275 msleep(1);
276 status = inb_p(SMBHSTSTS(priv));
277 } while ((status & SMBHSTSTS_HOST_BUSY) && (timeout++ < MAX_TIMEOUT));
278
279 result = i801_check_post(priv, status, timeout > MAX_TIMEOUT);
280 if (result < 0)
281 return result;
282
283 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
284 return 0;
285}
286
287/* wait for INTR bit as advised by Intel */
288static void i801_wait_hwpec(struct i801_priv *priv)
289{
290 int timeout = 0;
291 int status;
292
293 do {
294 msleep(1);
295 status = inb_p(SMBHSTSTS(priv));
296 } while ((!(status & SMBHSTSTS_INTR))
297 && (timeout++ < MAX_TIMEOUT));
298
299 if (timeout > MAX_TIMEOUT)
300 dev_dbg(&priv->pci_dev->dev, "PEC Timeout!\n");
301
302 outb_p(status, SMBHSTSTS(priv));
303}
304
305static int i801_block_transaction_by_block(struct i801_priv *priv,
306 union i2c_smbus_data *data,
307 char read_write, int hwpec)
308{
309 int i, len;
310 int status;
311
312 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
313
314 /* Use 32-byte buffer to process this transaction */
315 if (read_write == I2C_SMBUS_WRITE) {
316 len = data->block[0];
317 outb_p(len, SMBHSTDAT0(priv));
318 for (i = 0; i < len; i++)
319 outb_p(data->block[i+1], SMBBLKDAT(priv));
320 }
321
322 status = i801_transaction(priv, I801_BLOCK_DATA | ENABLE_INT9 |
323 I801_PEC_EN * hwpec);
324 if (status)
325 return status;
326
327 if (read_write == I2C_SMBUS_READ) {
328 len = inb_p(SMBHSTDAT0(priv));
329 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
330 return -EPROTO;
331
332 data->block[0] = len;
333 for (i = 0; i < len; i++)
334 data->block[i + 1] = inb_p(SMBBLKDAT(priv));
335 }
336 return 0;
337}
338
339static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
340 union i2c_smbus_data *data,
341 char read_write, int command,
342 int hwpec)
343{
344 int i, len;
345 int smbcmd;
346 int status;
347 int result;
348 int timeout;
349
350 result = i801_check_pre(priv);
351 if (result < 0)
352 return result;
353
354 len = data->block[0];
355
356 if (read_write == I2C_SMBUS_WRITE) {
357 outb_p(len, SMBHSTDAT0(priv));
358 outb_p(data->block[1], SMBBLKDAT(priv));
359 }
360
361 for (i = 1; i <= len; i++) {
362 if (i == len && read_write == I2C_SMBUS_READ) {
363 if (command == I2C_SMBUS_I2C_BLOCK_DATA)
364 smbcmd = I801_I2C_BLOCK_LAST;
365 else
366 smbcmd = I801_BLOCK_LAST;
367 } else {
368 if (command == I2C_SMBUS_I2C_BLOCK_DATA
369 && read_write == I2C_SMBUS_READ)
370 smbcmd = I801_I2C_BLOCK_DATA;
371 else
372 smbcmd = I801_BLOCK_DATA;
373 }
374 outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT(priv));
375
376 if (i == 1)
377 outb_p(inb(SMBHSTCNT(priv)) | I801_START,
378 SMBHSTCNT(priv));
379
380 /* We will always wait for a fraction of a second! */
381 timeout = 0;
382 do {
383 msleep(1);
384 status = inb_p(SMBHSTSTS(priv));
385 } while ((!(status & SMBHSTSTS_BYTE_DONE))
386 && (timeout++ < MAX_TIMEOUT));
387
388 result = i801_check_post(priv, status, timeout > MAX_TIMEOUT);
389 if (result < 0)
390 return result;
391
392 if (i == 1 && read_write == I2C_SMBUS_READ
393 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
394 len = inb_p(SMBHSTDAT0(priv));
395 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
396 dev_err(&priv->pci_dev->dev,
397 "Illegal SMBus block read size %d\n",
398 len);
399 /* Recover */
400 while (inb_p(SMBHSTSTS(priv)) &
401 SMBHSTSTS_HOST_BUSY)
402 outb_p(SMBHSTSTS_BYTE_DONE,
403 SMBHSTSTS(priv));
404 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
405 return -EPROTO;
406 }
407 data->block[0] = len;
408 }
409
410 /* Retrieve/store value in SMBBLKDAT */
411 if (read_write == I2C_SMBUS_READ)
412 data->block[i] = inb_p(SMBBLKDAT(priv));
413 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
414 outb_p(data->block[i+1], SMBBLKDAT(priv));
415
416 /* signals SMBBLKDAT ready */
417 outb_p(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR, SMBHSTSTS(priv));
418 }
419
420 return 0;
421}
422
423static int i801_set_block_buffer_mode(struct i801_priv *priv)
424{
425 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
426 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
427 return -EIO;
428 return 0;
429}
430
431/* Block transaction function */
432static int i801_block_transaction(struct i801_priv *priv,
433 union i2c_smbus_data *data, char read_write,
434 int command, int hwpec)
435{
436 int result = 0;
437 unsigned char hostc;
438
439 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
440 if (read_write == I2C_SMBUS_WRITE) {
441 /* set I2C_EN bit in configuration register */
442 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
443 pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
444 hostc | SMBHSTCFG_I2C_EN);
445 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
446 dev_err(&priv->pci_dev->dev,
447 "I2C block read is unsupported!\n");
448 return -EOPNOTSUPP;
449 }
450 }
451
452 if (read_write == I2C_SMBUS_WRITE
453 || command == I2C_SMBUS_I2C_BLOCK_DATA) {
454 if (data->block[0] < 1)
455 data->block[0] = 1;
456 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
457 data->block[0] = I2C_SMBUS_BLOCK_MAX;
458 } else {
459 data->block[0] = 32; /* max for SMBus block reads */
460 }
461
462 /* Experience has shown that the block buffer can only be used for
463 SMBus (not I2C) block transactions, even though the datasheet
464 doesn't mention this limitation. */
465 if ((priv->features & FEATURE_BLOCK_BUFFER)
466 && command != I2C_SMBUS_I2C_BLOCK_DATA
467 && i801_set_block_buffer_mode(priv) == 0)
468 result = i801_block_transaction_by_block(priv, data,
469 read_write, hwpec);
470 else
471 result = i801_block_transaction_byte_by_byte(priv, data,
472 read_write,
473 command, hwpec);
474
475 if (result == 0 && hwpec)
476 i801_wait_hwpec(priv);
477
478 if (command == I2C_SMBUS_I2C_BLOCK_DATA
479 && read_write == I2C_SMBUS_WRITE) {
480 /* restore saved configuration register value */
481 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
482 }
483 return result;
484}
485
486/* Return negative errno on error. */
487static s32 i801_access(struct i2c_adapter *adap, u16 addr,
488 unsigned short flags, char read_write, u8 command,
489 int size, union i2c_smbus_data *data)
490{
491 int hwpec;
492 int block = 0;
493 int ret, xact = 0;
494 struct i801_priv *priv = i2c_get_adapdata(adap);
495
496 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
497 && size != I2C_SMBUS_QUICK
498 && size != I2C_SMBUS_I2C_BLOCK_DATA;
499
500 switch (size) {
501 case I2C_SMBUS_QUICK:
502 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
503 SMBHSTADD(priv));
504 xact = I801_QUICK;
505 break;
506 case I2C_SMBUS_BYTE:
507 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
508 SMBHSTADD(priv));
509 if (read_write == I2C_SMBUS_WRITE)
510 outb_p(command, SMBHSTCMD(priv));
511 xact = I801_BYTE;
512 break;
513 case I2C_SMBUS_BYTE_DATA:
514 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
515 SMBHSTADD(priv));
516 outb_p(command, SMBHSTCMD(priv));
517 if (read_write == I2C_SMBUS_WRITE)
518 outb_p(data->byte, SMBHSTDAT0(priv));
519 xact = I801_BYTE_DATA;
520 break;
521 case I2C_SMBUS_WORD_DATA:
522 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
523 SMBHSTADD(priv));
524 outb_p(command, SMBHSTCMD(priv));
525 if (read_write == I2C_SMBUS_WRITE) {
526 outb_p(data->word & 0xff, SMBHSTDAT0(priv));
527 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
528 }
529 xact = I801_WORD_DATA;
530 break;
531 case I2C_SMBUS_BLOCK_DATA:
532 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
533 SMBHSTADD(priv));
534 outb_p(command, SMBHSTCMD(priv));
535 block = 1;
536 break;
537 case I2C_SMBUS_I2C_BLOCK_DATA:
538 /* NB: page 240 of ICH5 datasheet shows that the R/#W
539 * bit should be cleared here, even when reading */
540 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
541 if (read_write == I2C_SMBUS_READ) {
542 /* NB: page 240 of ICH5 datasheet also shows
543 * that DATA1 is the cmd field when reading */
544 outb_p(command, SMBHSTDAT1(priv));
545 } else
546 outb_p(command, SMBHSTCMD(priv));
547 block = 1;
548 break;
549 default:
550 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
551 size);
552 return -EOPNOTSUPP;
553 }
554
555 if (hwpec) /* enable/disable hardware PEC */
556 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
557 else
558 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
559 SMBAUXCTL(priv));
560
561 if (block)
562 ret = i801_block_transaction(priv, data, read_write, size,
563 hwpec);
564 else
565 ret = i801_transaction(priv, xact | ENABLE_INT9);
566
567 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
568 time, so we forcibly disable it after every transaction. Turn off
569 E32B for the same reason. */
570 if (hwpec || block)
571 outb_p(inb_p(SMBAUXCTL(priv)) &
572 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
573
574 if (block)
575 return ret;
576 if (ret)
577 return ret;
578 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
579 return 0;
580
581 switch (xact & 0x7f) {
582 case I801_BYTE: /* Result put in SMBHSTDAT0 */
583 case I801_BYTE_DATA:
584 data->byte = inb_p(SMBHSTDAT0(priv));
585 break;
586 case I801_WORD_DATA:
587 data->word = inb_p(SMBHSTDAT0(priv)) +
588 (inb_p(SMBHSTDAT1(priv)) << 8);
589 break;
590 }
591 return 0;
592}
593
594
595static u32 i801_func(struct i2c_adapter *adapter)
596{
597 struct i801_priv *priv = i2c_get_adapdata(adapter);
598
599 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
600 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
601 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
602 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
603 ((priv->features & FEATURE_I2C_BLOCK_READ) ?
604 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
605}
606
607static const struct i2c_algorithm smbus_algorithm = {
608 .smbus_xfer = i801_access,
609 .functionality = i801_func,
610};
611
612static const struct pci_device_id i801_ids[] = {
613 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
614 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
615 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
616 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
617 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
618 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
619 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
620 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
621 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
622 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
623 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
624 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
625 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
626 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
627 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
628 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
629 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
630 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
631 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
632 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
633 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
634 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
635 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
636 { 0, }
637};
638
639MODULE_DEVICE_TABLE(pci, i801_ids);
640
641#if defined CONFIG_X86 && defined CONFIG_DMI
642static unsigned char apanel_addr;
643
644/* Scan the system ROM for the signature "FJKEYINF" */
645static __init const void __iomem *bios_signature(const void __iomem *bios)
646{
647 ssize_t offset;
648 const unsigned char signature[] = "FJKEYINF";
649
650 for (offset = 0; offset < 0x10000; offset += 0x10) {
651 if (check_signature(bios + offset, signature,
652 sizeof(signature)-1))
653 return bios + offset;
654 }
655 return NULL;
656}
657
658static void __init input_apanel_init(void)
659{
660 void __iomem *bios;
661 const void __iomem *p;
662
663 bios = ioremap(0xF0000, 0x10000); /* Can't fail */
664 p = bios_signature(bios);
665 if (p) {
666 /* just use the first address */
667 apanel_addr = readb(p + 8 + 3) >> 1;
668 }
669 iounmap(bios);
670}
671
672struct dmi_onboard_device_info {
673 const char *name;
674 u8 type;
675 unsigned short i2c_addr;
676 const char *i2c_type;
677};
678
679static struct dmi_onboard_device_info __devinitdata dmi_devices[] = {
680 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
681 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
682 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
683};
684
685static void __devinit dmi_check_onboard_device(u8 type, const char *name,
686 struct i2c_adapter *adap)
687{
688 int i;
689 struct i2c_board_info info;
690
691 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
692 /* & ~0x80, ignore enabled/disabled bit */
693 if ((type & ~0x80) != dmi_devices[i].type)
694 continue;
695 if (strcasecmp(name, dmi_devices[i].name))
696 continue;
697
698 memset(&info, 0, sizeof(struct i2c_board_info));
699 info.addr = dmi_devices[i].i2c_addr;
700 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
701 i2c_new_device(adap, &info);
702 break;
703 }
704}
705
706/* We use our own function to check for onboard devices instead of
707 dmi_find_device() as some buggy BIOS's have the devices we are interested
708 in marked as disabled */
709static void __devinit dmi_check_onboard_devices(const struct dmi_header *dm,
710 void *adap)
711{
712 int i, count;
713
714 if (dm->type != 10)
715 return;
716
717 count = (dm->length - sizeof(struct dmi_header)) / 2;
718 for (i = 0; i < count; i++) {
719 const u8 *d = (char *)(dm + 1) + (i * 2);
720 const char *name = ((char *) dm) + dm->length;
721 u8 type = d[0];
722 u8 s = d[1];
723
724 if (!s)
725 continue;
726 s--;
727 while (s > 0 && name[0]) {
728 name += strlen(name) + 1;
729 s--;
730 }
731 if (name[0] == 0) /* Bogus string reference */
732 continue;
733
734 dmi_check_onboard_device(type, name, adap);
735 }
736}
737
738/* Register optional slaves */
739static void __devinit i801_probe_optional_slaves(struct i801_priv *priv)
740{
741 /* Only register slaves on main SMBus channel */
742 if (priv->features & FEATURE_IDF)
743 return;
744
745 if (apanel_addr) {
746 struct i2c_board_info info;
747
748 memset(&info, 0, sizeof(struct i2c_board_info));
749 info.addr = apanel_addr;
750 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
751 i2c_new_device(&priv->adapter, &info);
752 }
753
754 if (dmi_name_in_vendors("FUJITSU"))
755 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
756}
757#else
758static void __init input_apanel_init(void) {}
759static void __devinit i801_probe_optional_slaves(struct i801_priv *priv) {}
760#endif /* CONFIG_X86 && CONFIG_DMI */
761
762static int __devinit i801_probe(struct pci_dev *dev,
763 const struct pci_device_id *id)
764{
765 unsigned char temp;
766 int err, i;
767 struct i801_priv *priv;
768
769 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
770 if (!priv)
771 return -ENOMEM;
772
773 i2c_set_adapdata(&priv->adapter, priv);
774 priv->adapter.owner = THIS_MODULE;
775 priv->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
776 priv->adapter.algo = &smbus_algorithm;
777
778 priv->pci_dev = dev;
779 switch (dev->device) {
780 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
781 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
782 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
783 priv->features |= FEATURE_IDF;
784 /* fall through */
785 default:
786 priv->features |= FEATURE_I2C_BLOCK_READ;
787 /* fall through */
788 case PCI_DEVICE_ID_INTEL_82801DB_3:
789 priv->features |= FEATURE_SMBUS_PEC;
790 priv->features |= FEATURE_BLOCK_BUFFER;
791 /* fall through */
792 case PCI_DEVICE_ID_INTEL_82801CA_3:
793 case PCI_DEVICE_ID_INTEL_82801BA_2:
794 case PCI_DEVICE_ID_INTEL_82801AB_3:
795 case PCI_DEVICE_ID_INTEL_82801AA_3:
796 break;
797 }
798
799 /* Disable features on user request */
800 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
801 if (priv->features & disable_features & (1 << i))
802 dev_notice(&dev->dev, "%s disabled by user\n",
803 i801_feature_names[i]);
804 }
805 priv->features &= ~disable_features;
806
807 err = pci_enable_device(dev);
808 if (err) {
809 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
810 err);
811 goto exit;
812 }
813
814 /* Determine the address of the SMBus area */
815 priv->smba = pci_resource_start(dev, SMBBAR);
816 if (!priv->smba) {
817 dev_err(&dev->dev, "SMBus base address uninitialized, "
818 "upgrade BIOS\n");
819 err = -ENODEV;
820 goto exit;
821 }
822
823 err = acpi_check_resource_conflict(&dev->resource[SMBBAR]);
824 if (err) {
825 err = -ENODEV;
826 goto exit;
827 }
828
829 err = pci_request_region(dev, SMBBAR, i801_driver.name);
830 if (err) {
831 dev_err(&dev->dev, "Failed to request SMBus region "
832 "0x%lx-0x%Lx\n", priv->smba,
833 (unsigned long long)pci_resource_end(dev, SMBBAR));
834 goto exit;
835 }
836
837 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
838 priv->original_hstcfg = temp;
839 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
840 if (!(temp & SMBHSTCFG_HST_EN)) {
841 dev_info(&dev->dev, "Enabling SMBus device\n");
842 temp |= SMBHSTCFG_HST_EN;
843 }
844 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
845
846 if (temp & SMBHSTCFG_SMB_SMI_EN)
847 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
848 else
849 dev_dbg(&dev->dev, "SMBus using PCI Interrupt\n");
850
851 /* Clear special mode bits */
852 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
853 outb_p(inb_p(SMBAUXCTL(priv)) &
854 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
855
856 /* set up the sysfs linkage to our parent device */
857 priv->adapter.dev.parent = &dev->dev;
858
859 /* Retry up to 3 times on lost arbitration */
860 priv->adapter.retries = 3;
861
862 snprintf(priv->adapter.name, sizeof(priv->adapter.name),
863 "SMBus I801 adapter at %04lx", priv->smba);
864 err = i2c_add_adapter(&priv->adapter);
865 if (err) {
866 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
867 goto exit_release;
868 }
869
870 i801_probe_optional_slaves(priv);
871
872 pci_set_drvdata(dev, priv);
873 return 0;
874
875exit_release:
876 pci_release_region(dev, SMBBAR);
877exit:
878 kfree(priv);
879 return err;
880}
881
882static void __devexit i801_remove(struct pci_dev *dev)
883{
884 struct i801_priv *priv = pci_get_drvdata(dev);
885
886 i2c_del_adapter(&priv->adapter);
887 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
888 pci_release_region(dev, SMBBAR);
889 pci_set_drvdata(dev, NULL);
890 kfree(priv);
891 /*
892 * do not call pci_disable_device(dev) since it can cause hard hangs on
893 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
894 */
895}
896
897#ifdef CONFIG_PM
898static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
899{
900 struct i801_priv *priv = pci_get_drvdata(dev);
901
902 pci_save_state(dev);
903 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
904 pci_set_power_state(dev, pci_choose_state(dev, mesg));
905 return 0;
906}
907
908static int i801_resume(struct pci_dev *dev)
909{
910 pci_set_power_state(dev, PCI_D0);
911 pci_restore_state(dev);
912 return pci_enable_device(dev);
913}
914#else
915#define i801_suspend NULL
916#define i801_resume NULL
917#endif
918
919static struct pci_driver i801_driver = {
920 .name = "i801_smbus",
921 .id_table = i801_ids,
922 .probe = i801_probe,
923 .remove = __devexit_p(i801_remove),
924 .suspend = i801_suspend,
925 .resume = i801_resume,
926};
927
928static int __init i2c_i801_init(void)
929{
930 if (dmi_name_in_vendors("FUJITSU"))
931 input_apanel_init();
932 return pci_register_driver(&i801_driver);
933}
934
935static void __exit i2c_i801_exit(void)
936{
937 pci_unregister_driver(&i801_driver);
938}
939
940MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, "
941 "Jean Delvare <khali@linux-fr.org>");
942MODULE_DESCRIPTION("I801 SMBus driver");
943MODULE_LICENSE("GPL");
944
945module_init(i2c_i801_init);
946module_exit(i2c_i801_exit);
1/*
2 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
3 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
4 <mdsxyz123@yahoo.com>
5 Copyright (C) 2007 - 2012 Jean Delvare <khali@linux-fr.org>
6 Copyright (C) 2010 Intel Corporation,
7 David Woodhouse <dwmw2@infradead.org>
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22*/
23
24/*
25 Supports the following Intel I/O Controller Hubs (ICH):
26
27 I/O Block I2C
28 region SMBus Block proc. block
29 Chip name PCI ID size PEC buffer call read
30 ----------------------------------------------------------------------
31 82801AA (ICH) 0x2413 16 no no no no
32 82801AB (ICH0) 0x2423 16 no no no no
33 82801BA (ICH2) 0x2443 16 no no no no
34 82801CA (ICH3) 0x2483 32 soft no no no
35 82801DB (ICH4) 0x24c3 32 hard yes no no
36 82801E (ICH5) 0x24d3 32 hard yes yes yes
37 6300ESB 0x25a4 32 hard yes yes yes
38 82801F (ICH6) 0x266a 32 hard yes yes yes
39 6310ESB/6320ESB 0x269b 32 hard yes yes yes
40 82801G (ICH7) 0x27da 32 hard yes yes yes
41 82801H (ICH8) 0x283e 32 hard yes yes yes
42 82801I (ICH9) 0x2930 32 hard yes yes yes
43 EP80579 (Tolapai) 0x5032 32 hard yes yes yes
44 ICH10 0x3a30 32 hard yes yes yes
45 ICH10 0x3a60 32 hard yes yes yes
46 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes
47 6 Series (PCH) 0x1c22 32 hard yes yes yes
48 Patsburg (PCH) 0x1d22 32 hard yes yes yes
49 Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes
50 Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes
51 Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes
52 DH89xxCC (PCH) 0x2330 32 hard yes yes yes
53 Panther Point (PCH) 0x1e22 32 hard yes yes yes
54 Lynx Point (PCH) 0x8c22 32 hard yes yes yes
55 Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes
56
57 Features supported by this driver:
58 Software PEC no
59 Hardware PEC yes
60 Block buffer yes
61 Block process call transaction no
62 I2C block read transaction yes (doesn't use the block buffer)
63 Slave mode no
64
65 See the file Documentation/i2c/busses/i2c-i801 for details.
66*/
67
68#include <linux/module.h>
69#include <linux/pci.h>
70#include <linux/kernel.h>
71#include <linux/stddef.h>
72#include <linux/delay.h>
73#include <linux/ioport.h>
74#include <linux/init.h>
75#include <linux/i2c.h>
76#include <linux/acpi.h>
77#include <linux/io.h>
78#include <linux/dmi.h>
79#include <linux/slab.h>
80
81/* I801 SMBus address offsets */
82#define SMBHSTSTS(p) (0 + (p)->smba)
83#define SMBHSTCNT(p) (2 + (p)->smba)
84#define SMBHSTCMD(p) (3 + (p)->smba)
85#define SMBHSTADD(p) (4 + (p)->smba)
86#define SMBHSTDAT0(p) (5 + (p)->smba)
87#define SMBHSTDAT1(p) (6 + (p)->smba)
88#define SMBBLKDAT(p) (7 + (p)->smba)
89#define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */
90#define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */
91#define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */
92
93/* PCI Address Constants */
94#define SMBBAR 4
95#define SMBHSTCFG 0x040
96
97/* Host configuration bits for SMBHSTCFG */
98#define SMBHSTCFG_HST_EN 1
99#define SMBHSTCFG_SMB_SMI_EN 2
100#define SMBHSTCFG_I2C_EN 4
101
102/* Auxiliary control register bits, ICH4+ only */
103#define SMBAUXCTL_CRC 1
104#define SMBAUXCTL_E32B 2
105
106/* kill bit for SMBHSTCNT */
107#define SMBHSTCNT_KILL 2
108
109/* Other settings */
110#define MAX_RETRIES 400
111#define ENABLE_INT9 0 /* set to 0x01 to enable - untested */
112
113/* I801 command constants */
114#define I801_QUICK 0x00
115#define I801_BYTE 0x04
116#define I801_BYTE_DATA 0x08
117#define I801_WORD_DATA 0x0C
118#define I801_PROC_CALL 0x10 /* unimplemented */
119#define I801_BLOCK_DATA 0x14
120#define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
121#define I801_BLOCK_LAST 0x34
122#define I801_I2C_BLOCK_LAST 0x38 /* ICH5 and later */
123#define I801_START 0x40
124#define I801_PEC_EN 0x80 /* ICH3 and later */
125
126/* I801 Hosts Status register bits */
127#define SMBHSTSTS_BYTE_DONE 0x80
128#define SMBHSTSTS_INUSE_STS 0x40
129#define SMBHSTSTS_SMBALERT_STS 0x20
130#define SMBHSTSTS_FAILED 0x10
131#define SMBHSTSTS_BUS_ERR 0x08
132#define SMBHSTSTS_DEV_ERR 0x04
133#define SMBHSTSTS_INTR 0x02
134#define SMBHSTSTS_HOST_BUSY 0x01
135
136#define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_FAILED | \
137 SMBHSTSTS_BUS_ERR | SMBHSTSTS_DEV_ERR | \
138 SMBHSTSTS_INTR)
139
140/* Older devices have their ID defined in <linux/pci_ids.h> */
141#define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
142#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
143/* Patsburg also has three 'Integrated Device Function' SMBus controllers */
144#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
145#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
146#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
147#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22
148#define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330
149#define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
150#define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22
151#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22
152
153struct i801_priv {
154 struct i2c_adapter adapter;
155 unsigned long smba;
156 unsigned char original_hstcfg;
157 struct pci_dev *pci_dev;
158 unsigned int features;
159};
160
161static struct pci_driver i801_driver;
162
163#define FEATURE_SMBUS_PEC (1 << 0)
164#define FEATURE_BLOCK_BUFFER (1 << 1)
165#define FEATURE_BLOCK_PROC (1 << 2)
166#define FEATURE_I2C_BLOCK_READ (1 << 3)
167/* Not really a feature, but it's convenient to handle it as such */
168#define FEATURE_IDF (1 << 15)
169
170static const char *i801_feature_names[] = {
171 "SMBus PEC",
172 "Block buffer",
173 "Block process call",
174 "I2C block read",
175};
176
177static unsigned int disable_features;
178module_param(disable_features, uint, S_IRUGO | S_IWUSR);
179MODULE_PARM_DESC(disable_features, "Disable selected driver features");
180
181/* Make sure the SMBus host is ready to start transmitting.
182 Return 0 if it is, -EBUSY if it is not. */
183static int i801_check_pre(struct i801_priv *priv)
184{
185 int status;
186
187 status = inb_p(SMBHSTSTS(priv));
188 if (status & SMBHSTSTS_HOST_BUSY) {
189 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
190 return -EBUSY;
191 }
192
193 status &= STATUS_FLAGS;
194 if (status) {
195 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
196 status);
197 outb_p(status, SMBHSTSTS(priv));
198 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
199 if (status) {
200 dev_err(&priv->pci_dev->dev,
201 "Failed clearing status flags (%02x)\n",
202 status);
203 return -EBUSY;
204 }
205 }
206
207 return 0;
208}
209
210/* Convert the status register to an error code, and clear it. */
211static int i801_check_post(struct i801_priv *priv, int status, int timeout)
212{
213 int result = 0;
214
215 /* If the SMBus is still busy, we give up */
216 if (timeout) {
217 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
218 /* try to stop the current command */
219 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
220 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
221 SMBHSTCNT(priv));
222 usleep_range(1000, 2000);
223 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
224 SMBHSTCNT(priv));
225
226 /* Check if it worked */
227 status = inb_p(SMBHSTSTS(priv));
228 if ((status & SMBHSTSTS_HOST_BUSY) ||
229 !(status & SMBHSTSTS_FAILED))
230 dev_err(&priv->pci_dev->dev,
231 "Failed terminating the transaction\n");
232 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
233 return -ETIMEDOUT;
234 }
235
236 if (status & SMBHSTSTS_FAILED) {
237 result = -EIO;
238 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
239 }
240 if (status & SMBHSTSTS_DEV_ERR) {
241 result = -ENXIO;
242 dev_dbg(&priv->pci_dev->dev, "No response\n");
243 }
244 if (status & SMBHSTSTS_BUS_ERR) {
245 result = -EAGAIN;
246 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
247 }
248
249 if (result) {
250 /* Clear error flags */
251 outb_p(status & STATUS_FLAGS, SMBHSTSTS(priv));
252 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
253 if (status) {
254 dev_warn(&priv->pci_dev->dev, "Failed clearing status "
255 "flags at end of transaction (%02x)\n",
256 status);
257 }
258 }
259
260 return result;
261}
262
263static int i801_transaction(struct i801_priv *priv, int xact)
264{
265 int status;
266 int result;
267 int timeout = 0;
268
269 result = i801_check_pre(priv);
270 if (result < 0)
271 return result;
272
273 /* the current contents of SMBHSTCNT can be overwritten, since PEC,
274 * INTREN, SMBSCMD are passed in xact */
275 outb_p(xact | I801_START, SMBHSTCNT(priv));
276
277 /* We will always wait for a fraction of a second! */
278 do {
279 usleep_range(250, 500);
280 status = inb_p(SMBHSTSTS(priv));
281 } while ((status & SMBHSTSTS_HOST_BUSY) && (timeout++ < MAX_RETRIES));
282
283 result = i801_check_post(priv, status, timeout > MAX_RETRIES);
284 if (result < 0)
285 return result;
286
287 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
288 return 0;
289}
290
291/* wait for INTR bit as advised by Intel */
292static void i801_wait_hwpec(struct i801_priv *priv)
293{
294 int timeout = 0;
295 int status;
296
297 do {
298 usleep_range(250, 500);
299 status = inb_p(SMBHSTSTS(priv));
300 } while ((!(status & SMBHSTSTS_INTR))
301 && (timeout++ < MAX_RETRIES));
302
303 if (timeout > MAX_RETRIES)
304 dev_dbg(&priv->pci_dev->dev, "PEC Timeout!\n");
305
306 outb_p(status, SMBHSTSTS(priv));
307}
308
309static int i801_block_transaction_by_block(struct i801_priv *priv,
310 union i2c_smbus_data *data,
311 char read_write, int hwpec)
312{
313 int i, len;
314 int status;
315
316 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
317
318 /* Use 32-byte buffer to process this transaction */
319 if (read_write == I2C_SMBUS_WRITE) {
320 len = data->block[0];
321 outb_p(len, SMBHSTDAT0(priv));
322 for (i = 0; i < len; i++)
323 outb_p(data->block[i+1], SMBBLKDAT(priv));
324 }
325
326 status = i801_transaction(priv, I801_BLOCK_DATA | ENABLE_INT9 |
327 I801_PEC_EN * hwpec);
328 if (status)
329 return status;
330
331 if (read_write == I2C_SMBUS_READ) {
332 len = inb_p(SMBHSTDAT0(priv));
333 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
334 return -EPROTO;
335
336 data->block[0] = len;
337 for (i = 0; i < len; i++)
338 data->block[i + 1] = inb_p(SMBBLKDAT(priv));
339 }
340 return 0;
341}
342
343static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
344 union i2c_smbus_data *data,
345 char read_write, int command,
346 int hwpec)
347{
348 int i, len;
349 int smbcmd;
350 int status;
351 int result;
352 int timeout;
353
354 result = i801_check_pre(priv);
355 if (result < 0)
356 return result;
357
358 len = data->block[0];
359
360 if (read_write == I2C_SMBUS_WRITE) {
361 outb_p(len, SMBHSTDAT0(priv));
362 outb_p(data->block[1], SMBBLKDAT(priv));
363 }
364
365 for (i = 1; i <= len; i++) {
366 if (i == len && read_write == I2C_SMBUS_READ) {
367 if (command == I2C_SMBUS_I2C_BLOCK_DATA)
368 smbcmd = I801_I2C_BLOCK_LAST;
369 else
370 smbcmd = I801_BLOCK_LAST;
371 } else {
372 if (command == I2C_SMBUS_I2C_BLOCK_DATA
373 && read_write == I2C_SMBUS_READ)
374 smbcmd = I801_I2C_BLOCK_DATA;
375 else
376 smbcmd = I801_BLOCK_DATA;
377 }
378 outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT(priv));
379
380 if (i == 1)
381 outb_p(inb(SMBHSTCNT(priv)) | I801_START,
382 SMBHSTCNT(priv));
383
384 /* We will always wait for a fraction of a second! */
385 timeout = 0;
386 do {
387 usleep_range(250, 500);
388 status = inb_p(SMBHSTSTS(priv));
389 } while ((!(status & SMBHSTSTS_BYTE_DONE))
390 && (timeout++ < MAX_RETRIES));
391
392 result = i801_check_post(priv, status, timeout > MAX_RETRIES);
393 if (result < 0)
394 return result;
395
396 if (i == 1 && read_write == I2C_SMBUS_READ
397 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
398 len = inb_p(SMBHSTDAT0(priv));
399 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
400 dev_err(&priv->pci_dev->dev,
401 "Illegal SMBus block read size %d\n",
402 len);
403 /* Recover */
404 while (inb_p(SMBHSTSTS(priv)) &
405 SMBHSTSTS_HOST_BUSY)
406 outb_p(SMBHSTSTS_BYTE_DONE,
407 SMBHSTSTS(priv));
408 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
409 return -EPROTO;
410 }
411 data->block[0] = len;
412 }
413
414 /* Retrieve/store value in SMBBLKDAT */
415 if (read_write == I2C_SMBUS_READ)
416 data->block[i] = inb_p(SMBBLKDAT(priv));
417 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
418 outb_p(data->block[i+1], SMBBLKDAT(priv));
419
420 /* signals SMBBLKDAT ready */
421 outb_p(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR, SMBHSTSTS(priv));
422 }
423
424 return 0;
425}
426
427static int i801_set_block_buffer_mode(struct i801_priv *priv)
428{
429 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
430 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
431 return -EIO;
432 return 0;
433}
434
435/* Block transaction function */
436static int i801_block_transaction(struct i801_priv *priv,
437 union i2c_smbus_data *data, char read_write,
438 int command, int hwpec)
439{
440 int result = 0;
441 unsigned char hostc;
442
443 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
444 if (read_write == I2C_SMBUS_WRITE) {
445 /* set I2C_EN bit in configuration register */
446 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
447 pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
448 hostc | SMBHSTCFG_I2C_EN);
449 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
450 dev_err(&priv->pci_dev->dev,
451 "I2C block read is unsupported!\n");
452 return -EOPNOTSUPP;
453 }
454 }
455
456 if (read_write == I2C_SMBUS_WRITE
457 || command == I2C_SMBUS_I2C_BLOCK_DATA) {
458 if (data->block[0] < 1)
459 data->block[0] = 1;
460 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
461 data->block[0] = I2C_SMBUS_BLOCK_MAX;
462 } else {
463 data->block[0] = 32; /* max for SMBus block reads */
464 }
465
466 /* Experience has shown that the block buffer can only be used for
467 SMBus (not I2C) block transactions, even though the datasheet
468 doesn't mention this limitation. */
469 if ((priv->features & FEATURE_BLOCK_BUFFER)
470 && command != I2C_SMBUS_I2C_BLOCK_DATA
471 && i801_set_block_buffer_mode(priv) == 0)
472 result = i801_block_transaction_by_block(priv, data,
473 read_write, hwpec);
474 else
475 result = i801_block_transaction_byte_by_byte(priv, data,
476 read_write,
477 command, hwpec);
478
479 if (result == 0 && hwpec)
480 i801_wait_hwpec(priv);
481
482 if (command == I2C_SMBUS_I2C_BLOCK_DATA
483 && read_write == I2C_SMBUS_WRITE) {
484 /* restore saved configuration register value */
485 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
486 }
487 return result;
488}
489
490/* Return negative errno on error. */
491static s32 i801_access(struct i2c_adapter *adap, u16 addr,
492 unsigned short flags, char read_write, u8 command,
493 int size, union i2c_smbus_data *data)
494{
495 int hwpec;
496 int block = 0;
497 int ret, xact = 0;
498 struct i801_priv *priv = i2c_get_adapdata(adap);
499
500 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
501 && size != I2C_SMBUS_QUICK
502 && size != I2C_SMBUS_I2C_BLOCK_DATA;
503
504 switch (size) {
505 case I2C_SMBUS_QUICK:
506 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
507 SMBHSTADD(priv));
508 xact = I801_QUICK;
509 break;
510 case I2C_SMBUS_BYTE:
511 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
512 SMBHSTADD(priv));
513 if (read_write == I2C_SMBUS_WRITE)
514 outb_p(command, SMBHSTCMD(priv));
515 xact = I801_BYTE;
516 break;
517 case I2C_SMBUS_BYTE_DATA:
518 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
519 SMBHSTADD(priv));
520 outb_p(command, SMBHSTCMD(priv));
521 if (read_write == I2C_SMBUS_WRITE)
522 outb_p(data->byte, SMBHSTDAT0(priv));
523 xact = I801_BYTE_DATA;
524 break;
525 case I2C_SMBUS_WORD_DATA:
526 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
527 SMBHSTADD(priv));
528 outb_p(command, SMBHSTCMD(priv));
529 if (read_write == I2C_SMBUS_WRITE) {
530 outb_p(data->word & 0xff, SMBHSTDAT0(priv));
531 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
532 }
533 xact = I801_WORD_DATA;
534 break;
535 case I2C_SMBUS_BLOCK_DATA:
536 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
537 SMBHSTADD(priv));
538 outb_p(command, SMBHSTCMD(priv));
539 block = 1;
540 break;
541 case I2C_SMBUS_I2C_BLOCK_DATA:
542 /* NB: page 240 of ICH5 datasheet shows that the R/#W
543 * bit should be cleared here, even when reading */
544 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
545 if (read_write == I2C_SMBUS_READ) {
546 /* NB: page 240 of ICH5 datasheet also shows
547 * that DATA1 is the cmd field when reading */
548 outb_p(command, SMBHSTDAT1(priv));
549 } else
550 outb_p(command, SMBHSTCMD(priv));
551 block = 1;
552 break;
553 default:
554 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
555 size);
556 return -EOPNOTSUPP;
557 }
558
559 if (hwpec) /* enable/disable hardware PEC */
560 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
561 else
562 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
563 SMBAUXCTL(priv));
564
565 if (block)
566 ret = i801_block_transaction(priv, data, read_write, size,
567 hwpec);
568 else
569 ret = i801_transaction(priv, xact | ENABLE_INT9);
570
571 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
572 time, so we forcibly disable it after every transaction. Turn off
573 E32B for the same reason. */
574 if (hwpec || block)
575 outb_p(inb_p(SMBAUXCTL(priv)) &
576 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
577
578 if (block)
579 return ret;
580 if (ret)
581 return ret;
582 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
583 return 0;
584
585 switch (xact & 0x7f) {
586 case I801_BYTE: /* Result put in SMBHSTDAT0 */
587 case I801_BYTE_DATA:
588 data->byte = inb_p(SMBHSTDAT0(priv));
589 break;
590 case I801_WORD_DATA:
591 data->word = inb_p(SMBHSTDAT0(priv)) +
592 (inb_p(SMBHSTDAT1(priv)) << 8);
593 break;
594 }
595 return 0;
596}
597
598
599static u32 i801_func(struct i2c_adapter *adapter)
600{
601 struct i801_priv *priv = i2c_get_adapdata(adapter);
602
603 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
604 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
605 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
606 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
607 ((priv->features & FEATURE_I2C_BLOCK_READ) ?
608 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
609}
610
611static const struct i2c_algorithm smbus_algorithm = {
612 .smbus_xfer = i801_access,
613 .functionality = i801_func,
614};
615
616static DEFINE_PCI_DEVICE_TABLE(i801_ids) = {
617 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
618 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
619 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
620 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
621 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
622 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
623 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
624 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
625 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
626 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
627 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
628 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
629 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
630 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
631 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
632 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
633 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
634 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
635 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
636 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
637 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
638 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
639 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
640 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
641 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
642 { 0, }
643};
644
645MODULE_DEVICE_TABLE(pci, i801_ids);
646
647#if defined CONFIG_X86 && defined CONFIG_DMI
648static unsigned char apanel_addr;
649
650/* Scan the system ROM for the signature "FJKEYINF" */
651static __init const void __iomem *bios_signature(const void __iomem *bios)
652{
653 ssize_t offset;
654 const unsigned char signature[] = "FJKEYINF";
655
656 for (offset = 0; offset < 0x10000; offset += 0x10) {
657 if (check_signature(bios + offset, signature,
658 sizeof(signature)-1))
659 return bios + offset;
660 }
661 return NULL;
662}
663
664static void __init input_apanel_init(void)
665{
666 void __iomem *bios;
667 const void __iomem *p;
668
669 bios = ioremap(0xF0000, 0x10000); /* Can't fail */
670 p = bios_signature(bios);
671 if (p) {
672 /* just use the first address */
673 apanel_addr = readb(p + 8 + 3) >> 1;
674 }
675 iounmap(bios);
676}
677
678struct dmi_onboard_device_info {
679 const char *name;
680 u8 type;
681 unsigned short i2c_addr;
682 const char *i2c_type;
683};
684
685static struct dmi_onboard_device_info __devinitdata dmi_devices[] = {
686 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
687 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
688 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
689};
690
691static void __devinit dmi_check_onboard_device(u8 type, const char *name,
692 struct i2c_adapter *adap)
693{
694 int i;
695 struct i2c_board_info info;
696
697 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
698 /* & ~0x80, ignore enabled/disabled bit */
699 if ((type & ~0x80) != dmi_devices[i].type)
700 continue;
701 if (strcasecmp(name, dmi_devices[i].name))
702 continue;
703
704 memset(&info, 0, sizeof(struct i2c_board_info));
705 info.addr = dmi_devices[i].i2c_addr;
706 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
707 i2c_new_device(adap, &info);
708 break;
709 }
710}
711
712/* We use our own function to check for onboard devices instead of
713 dmi_find_device() as some buggy BIOS's have the devices we are interested
714 in marked as disabled */
715static void __devinit dmi_check_onboard_devices(const struct dmi_header *dm,
716 void *adap)
717{
718 int i, count;
719
720 if (dm->type != 10)
721 return;
722
723 count = (dm->length - sizeof(struct dmi_header)) / 2;
724 for (i = 0; i < count; i++) {
725 const u8 *d = (char *)(dm + 1) + (i * 2);
726 const char *name = ((char *) dm) + dm->length;
727 u8 type = d[0];
728 u8 s = d[1];
729
730 if (!s)
731 continue;
732 s--;
733 while (s > 0 && name[0]) {
734 name += strlen(name) + 1;
735 s--;
736 }
737 if (name[0] == 0) /* Bogus string reference */
738 continue;
739
740 dmi_check_onboard_device(type, name, adap);
741 }
742}
743
744/* Register optional slaves */
745static void __devinit i801_probe_optional_slaves(struct i801_priv *priv)
746{
747 /* Only register slaves on main SMBus channel */
748 if (priv->features & FEATURE_IDF)
749 return;
750
751 if (apanel_addr) {
752 struct i2c_board_info info;
753
754 memset(&info, 0, sizeof(struct i2c_board_info));
755 info.addr = apanel_addr;
756 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
757 i2c_new_device(&priv->adapter, &info);
758 }
759
760 if (dmi_name_in_vendors("FUJITSU"))
761 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
762}
763#else
764static void __init input_apanel_init(void) {}
765static void __devinit i801_probe_optional_slaves(struct i801_priv *priv) {}
766#endif /* CONFIG_X86 && CONFIG_DMI */
767
768static int __devinit i801_probe(struct pci_dev *dev,
769 const struct pci_device_id *id)
770{
771 unsigned char temp;
772 int err, i;
773 struct i801_priv *priv;
774
775 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
776 if (!priv)
777 return -ENOMEM;
778
779 i2c_set_adapdata(&priv->adapter, priv);
780 priv->adapter.owner = THIS_MODULE;
781 priv->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
782 priv->adapter.algo = &smbus_algorithm;
783
784 priv->pci_dev = dev;
785 switch (dev->device) {
786 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
787 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
788 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
789 priv->features |= FEATURE_IDF;
790 /* fall through */
791 default:
792 priv->features |= FEATURE_I2C_BLOCK_READ;
793 /* fall through */
794 case PCI_DEVICE_ID_INTEL_82801DB_3:
795 priv->features |= FEATURE_SMBUS_PEC;
796 priv->features |= FEATURE_BLOCK_BUFFER;
797 /* fall through */
798 case PCI_DEVICE_ID_INTEL_82801CA_3:
799 case PCI_DEVICE_ID_INTEL_82801BA_2:
800 case PCI_DEVICE_ID_INTEL_82801AB_3:
801 case PCI_DEVICE_ID_INTEL_82801AA_3:
802 break;
803 }
804
805 /* Disable features on user request */
806 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
807 if (priv->features & disable_features & (1 << i))
808 dev_notice(&dev->dev, "%s disabled by user\n",
809 i801_feature_names[i]);
810 }
811 priv->features &= ~disable_features;
812
813 err = pci_enable_device(dev);
814 if (err) {
815 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
816 err);
817 goto exit;
818 }
819
820 /* Determine the address of the SMBus area */
821 priv->smba = pci_resource_start(dev, SMBBAR);
822 if (!priv->smba) {
823 dev_err(&dev->dev, "SMBus base address uninitialized, "
824 "upgrade BIOS\n");
825 err = -ENODEV;
826 goto exit;
827 }
828
829 err = acpi_check_resource_conflict(&dev->resource[SMBBAR]);
830 if (err) {
831 err = -ENODEV;
832 goto exit;
833 }
834
835 err = pci_request_region(dev, SMBBAR, i801_driver.name);
836 if (err) {
837 dev_err(&dev->dev, "Failed to request SMBus region "
838 "0x%lx-0x%Lx\n", priv->smba,
839 (unsigned long long)pci_resource_end(dev, SMBBAR));
840 goto exit;
841 }
842
843 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
844 priv->original_hstcfg = temp;
845 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
846 if (!(temp & SMBHSTCFG_HST_EN)) {
847 dev_info(&dev->dev, "Enabling SMBus device\n");
848 temp |= SMBHSTCFG_HST_EN;
849 }
850 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
851
852 if (temp & SMBHSTCFG_SMB_SMI_EN)
853 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
854 else
855 dev_dbg(&dev->dev, "SMBus using PCI Interrupt\n");
856
857 /* Clear special mode bits */
858 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
859 outb_p(inb_p(SMBAUXCTL(priv)) &
860 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
861
862 /* set up the sysfs linkage to our parent device */
863 priv->adapter.dev.parent = &dev->dev;
864
865 /* Retry up to 3 times on lost arbitration */
866 priv->adapter.retries = 3;
867
868 snprintf(priv->adapter.name, sizeof(priv->adapter.name),
869 "SMBus I801 adapter at %04lx", priv->smba);
870 err = i2c_add_adapter(&priv->adapter);
871 if (err) {
872 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
873 goto exit_release;
874 }
875
876 i801_probe_optional_slaves(priv);
877
878 pci_set_drvdata(dev, priv);
879 return 0;
880
881exit_release:
882 pci_release_region(dev, SMBBAR);
883exit:
884 kfree(priv);
885 return err;
886}
887
888static void __devexit i801_remove(struct pci_dev *dev)
889{
890 struct i801_priv *priv = pci_get_drvdata(dev);
891
892 i2c_del_adapter(&priv->adapter);
893 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
894 pci_release_region(dev, SMBBAR);
895 pci_set_drvdata(dev, NULL);
896 kfree(priv);
897 /*
898 * do not call pci_disable_device(dev) since it can cause hard hangs on
899 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
900 */
901}
902
903#ifdef CONFIG_PM
904static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
905{
906 struct i801_priv *priv = pci_get_drvdata(dev);
907
908 pci_save_state(dev);
909 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
910 pci_set_power_state(dev, pci_choose_state(dev, mesg));
911 return 0;
912}
913
914static int i801_resume(struct pci_dev *dev)
915{
916 pci_set_power_state(dev, PCI_D0);
917 pci_restore_state(dev);
918 return pci_enable_device(dev);
919}
920#else
921#define i801_suspend NULL
922#define i801_resume NULL
923#endif
924
925static struct pci_driver i801_driver = {
926 .name = "i801_smbus",
927 .id_table = i801_ids,
928 .probe = i801_probe,
929 .remove = __devexit_p(i801_remove),
930 .suspend = i801_suspend,
931 .resume = i801_resume,
932};
933
934static int __init i2c_i801_init(void)
935{
936 if (dmi_name_in_vendors("FUJITSU"))
937 input_apanel_init();
938 return pci_register_driver(&i801_driver);
939}
940
941static void __exit i2c_i801_exit(void)
942{
943 pci_unregister_driver(&i801_driver);
944}
945
946MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, "
947 "Jean Delvare <khali@linux-fr.org>");
948MODULE_DESCRIPTION("I801 SMBus driver");
949MODULE_LICENSE("GPL");
950
951module_init(i2c_i801_init);
952module_exit(i2c_i801_exit);