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1/**************************************************************************
2 * Copyright (c) 2007, Intel Corporation.
3 * All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
19 * develop this driver.
20 *
21 **************************************************************************/
22/*
23 */
24
25#include <drm/drmP.h>
26#include "psb_drv.h"
27#include "psb_reg.h"
28#include "psb_intel_reg.h"
29#include "power.h"
30#include "psb_irq.h"
31#include "mdfld_output.h"
32
33/*
34 * inline functions
35 */
36
37static inline u32
38psb_pipestat(int pipe)
39{
40 if (pipe == 0)
41 return PIPEASTAT;
42 if (pipe == 1)
43 return PIPEBSTAT;
44 if (pipe == 2)
45 return PIPECSTAT;
46 BUG();
47}
48
49static inline u32
50mid_pipe_event(int pipe)
51{
52 if (pipe == 0)
53 return _PSB_PIPEA_EVENT_FLAG;
54 if (pipe == 1)
55 return _MDFLD_PIPEB_EVENT_FLAG;
56 if (pipe == 2)
57 return _MDFLD_PIPEC_EVENT_FLAG;
58 BUG();
59}
60
61static inline u32
62mid_pipe_vsync(int pipe)
63{
64 if (pipe == 0)
65 return _PSB_VSYNC_PIPEA_FLAG;
66 if (pipe == 1)
67 return _PSB_VSYNC_PIPEB_FLAG;
68 if (pipe == 2)
69 return _MDFLD_PIPEC_VBLANK_FLAG;
70 BUG();
71}
72
73static inline u32
74mid_pipeconf(int pipe)
75{
76 if (pipe == 0)
77 return PIPEACONF;
78 if (pipe == 1)
79 return PIPEBCONF;
80 if (pipe == 2)
81 return PIPECCONF;
82 BUG();
83}
84
85void
86psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask)
87{
88 if ((dev_priv->pipestat[pipe] & mask) != mask) {
89 u32 reg = psb_pipestat(pipe);
90 dev_priv->pipestat[pipe] |= mask;
91 /* Enable the interrupt, clear any pending status */
92 if (gma_power_begin(dev_priv->dev, false)) {
93 u32 writeVal = PSB_RVDC32(reg);
94 writeVal |= (mask | (mask >> 16));
95 PSB_WVDC32(writeVal, reg);
96 (void) PSB_RVDC32(reg);
97 gma_power_end(dev_priv->dev);
98 }
99 }
100}
101
102void
103psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask)
104{
105 if ((dev_priv->pipestat[pipe] & mask) != 0) {
106 u32 reg = psb_pipestat(pipe);
107 dev_priv->pipestat[pipe] &= ~mask;
108 if (gma_power_begin(dev_priv->dev, false)) {
109 u32 writeVal = PSB_RVDC32(reg);
110 writeVal &= ~mask;
111 PSB_WVDC32(writeVal, reg);
112 (void) PSB_RVDC32(reg);
113 gma_power_end(dev_priv->dev);
114 }
115 }
116}
117
118static void mid_enable_pipe_event(struct drm_psb_private *dev_priv, int pipe)
119{
120 if (gma_power_begin(dev_priv->dev, false)) {
121 u32 pipe_event = mid_pipe_event(pipe);
122 dev_priv->vdc_irq_mask |= pipe_event;
123 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
124 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
125 gma_power_end(dev_priv->dev);
126 }
127}
128
129static void mid_disable_pipe_event(struct drm_psb_private *dev_priv, int pipe)
130{
131 if (dev_priv->pipestat[pipe] == 0) {
132 if (gma_power_begin(dev_priv->dev, false)) {
133 u32 pipe_event = mid_pipe_event(pipe);
134 dev_priv->vdc_irq_mask &= ~pipe_event;
135 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
136 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
137 gma_power_end(dev_priv->dev);
138 }
139 }
140}
141
142/**
143 * Display controller interrupt handler for pipe event.
144 *
145 */
146static void mid_pipe_event_handler(struct drm_device *dev, int pipe)
147{
148 struct drm_psb_private *dev_priv =
149 (struct drm_psb_private *) dev->dev_private;
150
151 uint32_t pipe_stat_val = 0;
152 uint32_t pipe_stat_reg = psb_pipestat(pipe);
153 uint32_t pipe_enable = dev_priv->pipestat[pipe];
154 uint32_t pipe_status = dev_priv->pipestat[pipe] >> 16;
155 uint32_t pipe_clear;
156 uint32_t i = 0;
157
158 spin_lock(&dev_priv->irqmask_lock);
159
160 pipe_stat_val = PSB_RVDC32(pipe_stat_reg);
161 pipe_stat_val &= pipe_enable | pipe_status;
162 pipe_stat_val &= pipe_stat_val >> 16;
163
164 spin_unlock(&dev_priv->irqmask_lock);
165
166 /* Clear the 2nd level interrupt status bits
167 * Sometimes the bits are very sticky so we repeat until they unstick */
168 for (i = 0; i < 0xffff; i++) {
169 PSB_WVDC32(PSB_RVDC32(pipe_stat_reg), pipe_stat_reg);
170 pipe_clear = PSB_RVDC32(pipe_stat_reg) & pipe_status;
171
172 if (pipe_clear == 0)
173 break;
174 }
175
176 if (pipe_clear)
177 dev_err(dev->dev,
178 "%s, can't clear status bits for pipe %d, its value = 0x%x.\n",
179 __func__, pipe, PSB_RVDC32(pipe_stat_reg));
180
181 if (pipe_stat_val & PIPE_VBLANK_STATUS)
182 drm_handle_vblank(dev, pipe);
183
184 if (pipe_stat_val & PIPE_TE_STATUS)
185 drm_handle_vblank(dev, pipe);
186}
187
188/*
189 * Display controller interrupt handler.
190 */
191static void psb_vdc_interrupt(struct drm_device *dev, uint32_t vdc_stat)
192{
193 if (vdc_stat & _PSB_IRQ_ASLE)
194 psb_intel_opregion_asle_intr(dev);
195
196 if (vdc_stat & _PSB_VSYNC_PIPEA_FLAG)
197 mid_pipe_event_handler(dev, 0);
198
199 if (vdc_stat & _PSB_VSYNC_PIPEB_FLAG)
200 mid_pipe_event_handler(dev, 1);
201}
202
203irqreturn_t psb_irq_handler(DRM_IRQ_ARGS)
204{
205 struct drm_device *dev = arg;
206 struct drm_psb_private *dev_priv = dev->dev_private;
207 uint32_t vdc_stat, dsp_int = 0, sgx_int = 0, hotplug_int = 0;
208 int handled = 0;
209
210 spin_lock(&dev_priv->irqmask_lock);
211
212 vdc_stat = PSB_RVDC32(PSB_INT_IDENTITY_R);
213
214 if (vdc_stat & _PSB_PIPE_EVENT_FLAG)
215 dsp_int = 1;
216
217 /* FIXME: Handle Medfield
218 if (vdc_stat & _MDFLD_DISP_ALL_IRQ_FLAG)
219 dsp_int = 1;
220 */
221
222 if (vdc_stat & _PSB_IRQ_SGX_FLAG)
223 sgx_int = 1;
224 if (vdc_stat & _PSB_IRQ_DISP_HOTSYNC)
225 hotplug_int = 1;
226
227 vdc_stat &= dev_priv->vdc_irq_mask;
228 spin_unlock(&dev_priv->irqmask_lock);
229
230 if (dsp_int && gma_power_is_on(dev)) {
231 psb_vdc_interrupt(dev, vdc_stat);
232 handled = 1;
233 }
234
235 if (sgx_int) {
236 /* Not expected - we have it masked, shut it up */
237 u32 s, s2;
238 s = PSB_RSGX32(PSB_CR_EVENT_STATUS);
239 s2 = PSB_RSGX32(PSB_CR_EVENT_STATUS2);
240 PSB_WSGX32(s, PSB_CR_EVENT_HOST_CLEAR);
241 PSB_WSGX32(s2, PSB_CR_EVENT_HOST_CLEAR2);
242 /* if s & _PSB_CE_TWOD_COMPLETE we have 2D done but
243 we may as well poll even if we add that ! */
244 handled = 1;
245 }
246
247 /* Note: this bit has other meanings on some devices, so we will
248 need to address that later if it ever matters */
249 if (hotplug_int && dev_priv->ops->hotplug) {
250 handled = dev_priv->ops->hotplug(dev);
251 REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT));
252 }
253
254 PSB_WVDC32(vdc_stat, PSB_INT_IDENTITY_R);
255 (void) PSB_RVDC32(PSB_INT_IDENTITY_R);
256 DRM_READMEMORYBARRIER();
257
258 if (!handled)
259 return IRQ_NONE;
260
261 return IRQ_HANDLED;
262}
263
264void psb_irq_preinstall(struct drm_device *dev)
265{
266 struct drm_psb_private *dev_priv =
267 (struct drm_psb_private *) dev->dev_private;
268 unsigned long irqflags;
269
270 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
271
272 if (gma_power_is_on(dev))
273 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
274 if (dev->vblank_enabled[0])
275 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEA_FLAG;
276 if (dev->vblank_enabled[1])
277 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEB_FLAG;
278
279 /* FIXME: Handle Medfield irq mask
280 if (dev->vblank_enabled[1])
281 dev_priv->vdc_irq_mask |= _MDFLD_PIPEB_EVENT_FLAG;
282 if (dev->vblank_enabled[2])
283 dev_priv->vdc_irq_mask |= _MDFLD_PIPEC_EVENT_FLAG;
284 */
285
286 /* Revisit this area - want per device masks ? */
287 if (dev_priv->ops->hotplug)
288 dev_priv->vdc_irq_mask |= _PSB_IRQ_DISP_HOTSYNC;
289 dev_priv->vdc_irq_mask |= _PSB_IRQ_ASLE;
290
291 /* This register is safe even if display island is off */
292 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
293 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
294}
295
296int psb_irq_postinstall(struct drm_device *dev)
297{
298 struct drm_psb_private *dev_priv =
299 (struct drm_psb_private *) dev->dev_private;
300 unsigned long irqflags;
301
302 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
303
304 /* This register is safe even if display island is off */
305 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
306 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
307
308 if (dev->vblank_enabled[0])
309 psb_enable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE);
310 else
311 psb_disable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE);
312
313 if (dev->vblank_enabled[1])
314 psb_enable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE);
315 else
316 psb_disable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE);
317
318 if (dev->vblank_enabled[2])
319 psb_enable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE);
320 else
321 psb_disable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE);
322
323 if (dev_priv->ops->hotplug_enable)
324 dev_priv->ops->hotplug_enable(dev, true);
325
326 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
327 return 0;
328}
329
330void psb_irq_uninstall(struct drm_device *dev)
331{
332 struct drm_psb_private *dev_priv = dev->dev_private;
333 unsigned long irqflags;
334
335 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
336
337 if (dev_priv->ops->hotplug_enable)
338 dev_priv->ops->hotplug_enable(dev, false);
339
340 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
341
342 if (dev->vblank_enabled[0])
343 psb_disable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE);
344
345 if (dev->vblank_enabled[1])
346 psb_disable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE);
347
348 if (dev->vblank_enabled[2])
349 psb_disable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE);
350
351 dev_priv->vdc_irq_mask &= _PSB_IRQ_SGX_FLAG |
352 _PSB_IRQ_MSVDX_FLAG |
353 _LNC_IRQ_TOPAZ_FLAG;
354
355 /* These two registers are safe even if display island is off */
356 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
357 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
358
359 wmb();
360
361 /* This register is safe even if display island is off */
362 PSB_WVDC32(PSB_RVDC32(PSB_INT_IDENTITY_R), PSB_INT_IDENTITY_R);
363 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
364}
365
366void psb_irq_turn_on_dpst(struct drm_device *dev)
367{
368 struct drm_psb_private *dev_priv =
369 (struct drm_psb_private *) dev->dev_private;
370 u32 hist_reg;
371 u32 pwm_reg;
372
373 if (gma_power_begin(dev, false)) {
374 PSB_WVDC32(1 << 31, HISTOGRAM_LOGIC_CONTROL);
375 hist_reg = PSB_RVDC32(HISTOGRAM_LOGIC_CONTROL);
376 PSB_WVDC32(1 << 31, HISTOGRAM_INT_CONTROL);
377 hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL);
378
379 PSB_WVDC32(0x80010100, PWM_CONTROL_LOGIC);
380 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
381 PSB_WVDC32(pwm_reg | PWM_PHASEIN_ENABLE
382 | PWM_PHASEIN_INT_ENABLE,
383 PWM_CONTROL_LOGIC);
384 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
385
386 psb_enable_pipestat(dev_priv, 0, PIPE_DPST_EVENT_ENABLE);
387
388 hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL);
389 PSB_WVDC32(hist_reg | HISTOGRAM_INT_CTRL_CLEAR,
390 HISTOGRAM_INT_CONTROL);
391 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
392 PSB_WVDC32(pwm_reg | 0x80010100 | PWM_PHASEIN_ENABLE,
393 PWM_CONTROL_LOGIC);
394
395 gma_power_end(dev);
396 }
397}
398
399int psb_irq_enable_dpst(struct drm_device *dev)
400{
401 struct drm_psb_private *dev_priv =
402 (struct drm_psb_private *) dev->dev_private;
403 unsigned long irqflags;
404
405 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
406
407 /* enable DPST */
408 mid_enable_pipe_event(dev_priv, 0);
409 psb_irq_turn_on_dpst(dev);
410
411 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
412 return 0;
413}
414
415void psb_irq_turn_off_dpst(struct drm_device *dev)
416{
417 struct drm_psb_private *dev_priv =
418 (struct drm_psb_private *) dev->dev_private;
419 u32 hist_reg;
420 u32 pwm_reg;
421
422 if (gma_power_begin(dev, false)) {
423 PSB_WVDC32(0x00000000, HISTOGRAM_INT_CONTROL);
424 hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL);
425
426 psb_disable_pipestat(dev_priv, 0, PIPE_DPST_EVENT_ENABLE);
427
428 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
429 PSB_WVDC32(pwm_reg & ~PWM_PHASEIN_INT_ENABLE,
430 PWM_CONTROL_LOGIC);
431 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
432
433 gma_power_end(dev);
434 }
435}
436
437int psb_irq_disable_dpst(struct drm_device *dev)
438{
439 struct drm_psb_private *dev_priv =
440 (struct drm_psb_private *) dev->dev_private;
441 unsigned long irqflags;
442
443 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
444
445 mid_disable_pipe_event(dev_priv, 0);
446 psb_irq_turn_off_dpst(dev);
447
448 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
449
450 return 0;
451}
452
453#ifdef PSB_FIXME
454static int psb_vblank_do_wait(struct drm_device *dev,
455 unsigned int *sequence, atomic_t *counter)
456{
457 unsigned int cur_vblank;
458 int ret = 0;
459 DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
460 (((cur_vblank = atomic_read(counter))
461 - *sequence) <= (1 << 23)));
462 *sequence = cur_vblank;
463
464 return ret;
465}
466#endif
467
468/*
469 * It is used to enable VBLANK interrupt
470 */
471int psb_enable_vblank(struct drm_device *dev, int pipe)
472{
473 struct drm_psb_private *dev_priv = dev->dev_private;
474 unsigned long irqflags;
475 uint32_t reg_val = 0;
476 uint32_t pipeconf_reg = mid_pipeconf(pipe);
477
478 /* Medfield is different - we should perhaps extract out vblank
479 and blacklight etc ops */
480 if (IS_MFLD(dev))
481 return mdfld_enable_te(dev, pipe);
482
483 if (gma_power_begin(dev, false)) {
484 reg_val = REG_READ(pipeconf_reg);
485 gma_power_end(dev);
486 }
487
488 if (!(reg_val & PIPEACONF_ENABLE))
489 return -EINVAL;
490
491 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
492
493 if (pipe == 0)
494 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEA_FLAG;
495 else if (pipe == 1)
496 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEB_FLAG;
497
498 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
499 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
500 psb_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE);
501
502 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
503
504 return 0;
505}
506
507/*
508 * It is used to disable VBLANK interrupt
509 */
510void psb_disable_vblank(struct drm_device *dev, int pipe)
511{
512 struct drm_psb_private *dev_priv = dev->dev_private;
513 unsigned long irqflags;
514
515 if (IS_MFLD(dev))
516 mdfld_disable_te(dev, pipe);
517 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
518
519 if (pipe == 0)
520 dev_priv->vdc_irq_mask &= ~_PSB_VSYNC_PIPEA_FLAG;
521 else if (pipe == 1)
522 dev_priv->vdc_irq_mask &= ~_PSB_VSYNC_PIPEB_FLAG;
523
524 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
525 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
526 psb_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE);
527
528 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
529}
530
531/*
532 * It is used to enable TE interrupt
533 */
534int mdfld_enable_te(struct drm_device *dev, int pipe)
535{
536 struct drm_psb_private *dev_priv =
537 (struct drm_psb_private *) dev->dev_private;
538 unsigned long irqflags;
539 uint32_t reg_val = 0;
540 uint32_t pipeconf_reg = mid_pipeconf(pipe);
541
542 if (gma_power_begin(dev, false)) {
543 reg_val = REG_READ(pipeconf_reg);
544 gma_power_end(dev);
545 }
546
547 if (!(reg_val & PIPEACONF_ENABLE))
548 return -EINVAL;
549
550 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
551
552 mid_enable_pipe_event(dev_priv, pipe);
553 psb_enable_pipestat(dev_priv, pipe, PIPE_TE_ENABLE);
554
555 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
556
557 return 0;
558}
559
560/*
561 * It is used to disable TE interrupt
562 */
563void mdfld_disable_te(struct drm_device *dev, int pipe)
564{
565 struct drm_psb_private *dev_priv =
566 (struct drm_psb_private *) dev->dev_private;
567 unsigned long irqflags;
568
569 if (!dev_priv->dsr_enable)
570 return;
571
572 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
573
574 mid_disable_pipe_event(dev_priv, pipe);
575 psb_disable_pipestat(dev_priv, pipe, PIPE_TE_ENABLE);
576
577 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
578}
579
580/* Called from drm generic code, passed a 'crtc', which
581 * we use as a pipe index
582 */
583u32 psb_get_vblank_counter(struct drm_device *dev, int pipe)
584{
585 uint32_t high_frame = PIPEAFRAMEHIGH;
586 uint32_t low_frame = PIPEAFRAMEPIXEL;
587 uint32_t pipeconf_reg = PIPEACONF;
588 uint32_t reg_val = 0;
589 uint32_t high1 = 0, high2 = 0, low = 0, count = 0;
590
591 switch (pipe) {
592 case 0:
593 break;
594 case 1:
595 high_frame = PIPEBFRAMEHIGH;
596 low_frame = PIPEBFRAMEPIXEL;
597 pipeconf_reg = PIPEBCONF;
598 break;
599 case 2:
600 high_frame = PIPECFRAMEHIGH;
601 low_frame = PIPECFRAMEPIXEL;
602 pipeconf_reg = PIPECCONF;
603 break;
604 default:
605 dev_err(dev->dev, "%s, invalid pipe.\n", __func__);
606 return 0;
607 }
608
609 if (!gma_power_begin(dev, false))
610 return 0;
611
612 reg_val = REG_READ(pipeconf_reg);
613
614 if (!(reg_val & PIPEACONF_ENABLE)) {
615 dev_err(dev->dev, "trying to get vblank count for disabled pipe %d\n",
616 pipe);
617 goto psb_get_vblank_counter_exit;
618 }
619
620 /*
621 * High & low register fields aren't synchronized, so make sure
622 * we get a low value that's stable across two reads of the high
623 * register.
624 */
625 do {
626 high1 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
627 PIPE_FRAME_HIGH_SHIFT);
628 low = ((REG_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
629 PIPE_FRAME_LOW_SHIFT);
630 high2 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
631 PIPE_FRAME_HIGH_SHIFT);
632 } while (high1 != high2);
633
634 count = (high1 << 8) | low;
635
636psb_get_vblank_counter_exit:
637
638 gma_power_end(dev);
639
640 return count;
641}
642