Loading...
1/*
2 * Broadcom specific AMBA
3 * PCI Core
4 *
5 * Copyright 2005, Broadcom Corporation
6 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
7 *
8 * Licensed under the GNU/GPL. See COPYING for details.
9 */
10
11#include "bcma_private.h"
12#include <linux/bcma/bcma.h>
13
14/**************************************************
15 * R/W ops.
16 **************************************************/
17
18static u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address)
19{
20 pcicore_write32(pc, 0x130, address);
21 pcicore_read32(pc, 0x130);
22 return pcicore_read32(pc, 0x134);
23}
24
25#if 0
26static void bcma_pcie_write(struct bcma_drv_pci *pc, u32 address, u32 data)
27{
28 pcicore_write32(pc, 0x130, address);
29 pcicore_read32(pc, 0x130);
30 pcicore_write32(pc, 0x134, data);
31}
32#endif
33
34static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u8 phy)
35{
36 const u16 mdio_control = 0x128;
37 const u16 mdio_data = 0x12C;
38 u32 v;
39 int i;
40
41 v = (1 << 30); /* Start of Transaction */
42 v |= (1 << 28); /* Write Transaction */
43 v |= (1 << 17); /* Turnaround */
44 v |= (0x1F << 18);
45 v |= (phy << 4);
46 pcicore_write32(pc, mdio_data, v);
47
48 udelay(10);
49 for (i = 0; i < 200; i++) {
50 v = pcicore_read32(pc, mdio_control);
51 if (v & 0x100 /* Trans complete */)
52 break;
53 msleep(1);
54 }
55}
56
57static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u8 device, u8 address)
58{
59 const u16 mdio_control = 0x128;
60 const u16 mdio_data = 0x12C;
61 int max_retries = 10;
62 u16 ret = 0;
63 u32 v;
64 int i;
65
66 v = 0x80; /* Enable Preamble Sequence */
67 v |= 0x2; /* MDIO Clock Divisor */
68 pcicore_write32(pc, mdio_control, v);
69
70 if (pc->core->id.rev >= 10) {
71 max_retries = 200;
72 bcma_pcie_mdio_set_phy(pc, device);
73 }
74
75 v = (1 << 30); /* Start of Transaction */
76 v |= (1 << 29); /* Read Transaction */
77 v |= (1 << 17); /* Turnaround */
78 if (pc->core->id.rev < 10)
79 v |= (u32)device << 22;
80 v |= (u32)address << 18;
81 pcicore_write32(pc, mdio_data, v);
82 /* Wait for the device to complete the transaction */
83 udelay(10);
84 for (i = 0; i < max_retries; i++) {
85 v = pcicore_read32(pc, mdio_control);
86 if (v & 0x100 /* Trans complete */) {
87 udelay(10);
88 ret = pcicore_read32(pc, mdio_data);
89 break;
90 }
91 msleep(1);
92 }
93 pcicore_write32(pc, mdio_control, 0);
94 return ret;
95}
96
97static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u8 device,
98 u8 address, u16 data)
99{
100 const u16 mdio_control = 0x128;
101 const u16 mdio_data = 0x12C;
102 int max_retries = 10;
103 u32 v;
104 int i;
105
106 v = 0x80; /* Enable Preamble Sequence */
107 v |= 0x2; /* MDIO Clock Divisor */
108 pcicore_write32(pc, mdio_control, v);
109
110 if (pc->core->id.rev >= 10) {
111 max_retries = 200;
112 bcma_pcie_mdio_set_phy(pc, device);
113 }
114
115 v = (1 << 30); /* Start of Transaction */
116 v |= (1 << 28); /* Write Transaction */
117 v |= (1 << 17); /* Turnaround */
118 if (pc->core->id.rev < 10)
119 v |= (u32)device << 22;
120 v |= (u32)address << 18;
121 v |= data;
122 pcicore_write32(pc, mdio_data, v);
123 /* Wait for the device to complete the transaction */
124 udelay(10);
125 for (i = 0; i < max_retries; i++) {
126 v = pcicore_read32(pc, mdio_control);
127 if (v & 0x100 /* Trans complete */)
128 break;
129 msleep(1);
130 }
131 pcicore_write32(pc, mdio_control, 0);
132}
133
134/**************************************************
135 * Workarounds.
136 **************************************************/
137
138static u8 bcma_pcicore_polarity_workaround(struct bcma_drv_pci *pc)
139{
140 return (bcma_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80;
141}
142
143static void bcma_pcicore_serdes_workaround(struct bcma_drv_pci *pc)
144{
145 const u8 serdes_pll_device = 0x1D;
146 const u8 serdes_rx_device = 0x1F;
147 u16 tmp;
148
149 bcma_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */,
150 bcma_pcicore_polarity_workaround(pc));
151 tmp = bcma_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */);
152 if (tmp & 0x4000)
153 bcma_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000);
154}
155
156/**************************************************
157 * Init.
158 **************************************************/
159
160static void bcma_core_pci_clientmode_init(struct bcma_drv_pci *pc)
161{
162 bcma_pcicore_serdes_workaround(pc);
163}
164
165static bool bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc)
166{
167 struct bcma_bus *bus = pc->core->bus;
168 u16 chipid_top;
169
170 chipid_top = (bus->chipinfo.id & 0xFF00);
171 if (chipid_top != 0x4700 &&
172 chipid_top != 0x5300)
173 return false;
174
175#ifdef CONFIG_SSB_DRIVER_PCICORE
176 if (bus->sprom.boardflags_lo & SSB_PCICORE_BFL_NOPCI)
177 return false;
178#endif /* CONFIG_SSB_DRIVER_PCICORE */
179
180#if 0
181 /* TODO: on BCMA we use address from EROM instead of magic formula */
182 u32 tmp;
183 return !mips_busprobe32(tmp, (bus->mmio +
184 (pc->core->core_index * BCMA_CORE_SIZE)));
185#endif
186
187 return true;
188}
189
190void bcma_core_pci_init(struct bcma_drv_pci *pc)
191{
192 if (bcma_core_pci_is_in_hostmode(pc)) {
193#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
194 bcma_core_pci_hostmode_init(pc);
195#else
196 pr_err("Driver compiled without support for hostmode PCI\n");
197#endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */
198 } else {
199 bcma_core_pci_clientmode_init(pc);
200 }
201}
202
203int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, struct bcma_device *core,
204 bool enable)
205{
206 struct pci_dev *pdev = pc->core->bus->host_pci;
207 u32 coremask, tmp;
208 int err;
209
210 err = pci_read_config_dword(pdev, BCMA_PCI_IRQMASK, &tmp);
211 if (err)
212 goto out;
213
214 coremask = BIT(core->core_index) << 8;
215 if (enable)
216 tmp |= coremask;
217 else
218 tmp &= ~coremask;
219
220 err = pci_write_config_dword(pdev, BCMA_PCI_IRQMASK, tmp);
221
222out:
223 return err;
224}
225EXPORT_SYMBOL_GPL(bcma_core_pci_irq_ctl);
1/*
2 * Broadcom specific AMBA
3 * PCI Core
4 *
5 * Copyright 2005, 2011, Broadcom Corporation
6 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
7 * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
8 *
9 * Licensed under the GNU/GPL. See COPYING for details.
10 */
11
12#include "bcma_private.h"
13#include <linux/export.h>
14#include <linux/bcma/bcma.h>
15
16/**************************************************
17 * R/W ops.
18 **************************************************/
19
20u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address)
21{
22 pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address);
23 pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR);
24 return pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_DATA);
25}
26
27static void bcma_pcie_write(struct bcma_drv_pci *pc, u32 address, u32 data)
28{
29 pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address);
30 pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR);
31 pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_DATA, data);
32}
33
34static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u8 phy)
35{
36 u32 v;
37 int i;
38
39 v = BCMA_CORE_PCI_MDIODATA_START;
40 v |= BCMA_CORE_PCI_MDIODATA_WRITE;
41 v |= (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
42 BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
43 v |= (BCMA_CORE_PCI_MDIODATA_BLK_ADDR <<
44 BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
45 v |= BCMA_CORE_PCI_MDIODATA_TA;
46 v |= (phy << 4);
47 pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
48
49 udelay(10);
50 for (i = 0; i < 200; i++) {
51 v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
52 if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
53 break;
54 msleep(1);
55 }
56}
57
58static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u8 device, u8 address)
59{
60 int max_retries = 10;
61 u16 ret = 0;
62 u32 v;
63 int i;
64
65 /* enable mdio access to SERDES */
66 v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN;
67 v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL;
68 pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v);
69
70 if (pc->core->id.rev >= 10) {
71 max_retries = 200;
72 bcma_pcie_mdio_set_phy(pc, device);
73 v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
74 BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
75 v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
76 } else {
77 v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD);
78 v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD);
79 }
80
81 v = BCMA_CORE_PCI_MDIODATA_START;
82 v |= BCMA_CORE_PCI_MDIODATA_READ;
83 v |= BCMA_CORE_PCI_MDIODATA_TA;
84
85 pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
86 /* Wait for the device to complete the transaction */
87 udelay(10);
88 for (i = 0; i < max_retries; i++) {
89 v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
90 if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE) {
91 udelay(10);
92 ret = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_DATA);
93 break;
94 }
95 msleep(1);
96 }
97 pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
98 return ret;
99}
100
101static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u8 device,
102 u8 address, u16 data)
103{
104 int max_retries = 10;
105 u32 v;
106 int i;
107
108 /* enable mdio access to SERDES */
109 v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN;
110 v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL;
111 pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v);
112
113 if (pc->core->id.rev >= 10) {
114 max_retries = 200;
115 bcma_pcie_mdio_set_phy(pc, device);
116 v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
117 BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
118 v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
119 } else {
120 v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD);
121 v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD);
122 }
123
124 v = BCMA_CORE_PCI_MDIODATA_START;
125 v |= BCMA_CORE_PCI_MDIODATA_WRITE;
126 v |= BCMA_CORE_PCI_MDIODATA_TA;
127 v |= data;
128 pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
129 /* Wait for the device to complete the transaction */
130 udelay(10);
131 for (i = 0; i < max_retries; i++) {
132 v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
133 if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
134 break;
135 msleep(1);
136 }
137 pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
138}
139
140/**************************************************
141 * Workarounds.
142 **************************************************/
143
144static u8 bcma_pcicore_polarity_workaround(struct bcma_drv_pci *pc)
145{
146 u32 tmp;
147
148 tmp = bcma_pcie_read(pc, BCMA_CORE_PCI_PLP_STATUSREG);
149 if (tmp & BCMA_CORE_PCI_PLP_POLARITYINV_STAT)
150 return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE |
151 BCMA_CORE_PCI_SERDES_RX_CTRL_POLARITY;
152 else
153 return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE;
154}
155
156static void bcma_pcicore_serdes_workaround(struct bcma_drv_pci *pc)
157{
158 u16 tmp;
159
160 bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_RX,
161 BCMA_CORE_PCI_SERDES_RX_CTRL,
162 bcma_pcicore_polarity_workaround(pc));
163 tmp = bcma_pcie_mdio_read(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL,
164 BCMA_CORE_PCI_SERDES_PLL_CTRL);
165 if (tmp & BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN)
166 bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL,
167 BCMA_CORE_PCI_SERDES_PLL_CTRL,
168 tmp & ~BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN);
169}
170
171static void bcma_core_pci_fixcfg(struct bcma_drv_pci *pc)
172{
173 struct bcma_device *core = pc->core;
174 u16 val16, core_index;
175 uint regoff;
176
177 regoff = BCMA_CORE_PCI_SPROM(BCMA_CORE_PCI_SPROM_PI_OFFSET);
178 core_index = (u16)core->core_index;
179
180 val16 = pcicore_read16(pc, regoff);
181 if (((val16 & BCMA_CORE_PCI_SPROM_PI_MASK) >> BCMA_CORE_PCI_SPROM_PI_SHIFT)
182 != core_index) {
183 val16 = (core_index << BCMA_CORE_PCI_SPROM_PI_SHIFT) |
184 (val16 & ~BCMA_CORE_PCI_SPROM_PI_MASK);
185 pcicore_write16(pc, regoff, val16);
186 }
187}
188
189/* Fix MISC config to allow coming out of L2/L3-Ready state w/o PRST */
190/* Needs to happen when coming out of 'standby'/'hibernate' */
191static void bcma_core_pci_config_fixup(struct bcma_drv_pci *pc)
192{
193 u16 val16;
194 uint regoff;
195
196 regoff = BCMA_CORE_PCI_SPROM(BCMA_CORE_PCI_SPROM_MISC_CONFIG);
197
198 val16 = pcicore_read16(pc, regoff);
199
200 if (!(val16 & BCMA_CORE_PCI_SPROM_L23READY_EXIT_NOPERST)) {
201 val16 |= BCMA_CORE_PCI_SPROM_L23READY_EXIT_NOPERST;
202 pcicore_write16(pc, regoff, val16);
203 }
204}
205
206/**************************************************
207 * Init.
208 **************************************************/
209
210static void __devinit bcma_core_pci_clientmode_init(struct bcma_drv_pci *pc)
211{
212 bcma_core_pci_fixcfg(pc);
213 bcma_pcicore_serdes_workaround(pc);
214 bcma_core_pci_config_fixup(pc);
215}
216
217void __devinit bcma_core_pci_init(struct bcma_drv_pci *pc)
218{
219 if (pc->setup_done)
220 return;
221
222#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
223 pc->hostmode = bcma_core_pci_is_in_hostmode(pc);
224 if (pc->hostmode)
225 bcma_core_pci_hostmode_init(pc);
226#endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */
227
228 if (!pc->hostmode)
229 bcma_core_pci_clientmode_init(pc);
230}
231
232int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, struct bcma_device *core,
233 bool enable)
234{
235 struct pci_dev *pdev;
236 u32 coremask, tmp;
237 int err = 0;
238
239 if (!pc || core->bus->hosttype != BCMA_HOSTTYPE_PCI) {
240 /* This bcma device is not on a PCI host-bus. So the IRQs are
241 * not routed through the PCI core.
242 * So we must not enable routing through the PCI core. */
243 goto out;
244 }
245
246 pdev = pc->core->bus->host_pci;
247
248 err = pci_read_config_dword(pdev, BCMA_PCI_IRQMASK, &tmp);
249 if (err)
250 goto out;
251
252 coremask = BIT(core->core_index) << 8;
253 if (enable)
254 tmp |= coremask;
255 else
256 tmp &= ~coremask;
257
258 err = pci_write_config_dword(pdev, BCMA_PCI_IRQMASK, tmp);
259
260out:
261 return err;
262}
263EXPORT_SYMBOL_GPL(bcma_core_pci_irq_ctl);
264
265void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend)
266{
267 u32 w;
268
269 w = bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG);
270 if (extend)
271 w |= BCMA_CORE_PCI_ASPMTIMER_EXTEND;
272 else
273 w &= ~BCMA_CORE_PCI_ASPMTIMER_EXTEND;
274 bcma_pcie_write(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG, w);
275 bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG);
276}
277EXPORT_SYMBOL_GPL(bcma_core_pci_extend_L1timer);