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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2000, 2001 Keith M Wesolowski
7 */
8#include <linux/kernel.h>
9#include <linux/init.h>
10#include <linux/pci.h>
11#include <linux/types.h>
12#include <asm/pci.h>
13#include <asm/ip32/mace.h>
14
15#if 0
16# define DPRINTK(args...) printk(args);
17#else
18# define DPRINTK(args...)
19#endif
20
21/*
22 * O2 has up to 5 PCI devices connected into the MACE bridge. The device
23 * map looks like this:
24 *
25 * 0 aic7xxx 0
26 * 1 aic7xxx 1
27 * 2 expansion slot
28 * 3 N/C
29 * 4 N/C
30 */
31
32static inline int mkaddr(struct pci_bus *bus, unsigned int devfn,
33 unsigned int reg)
34{
35 return ((bus->number & 0xff) << 16) |
36 ((devfn & 0xff) << 8) |
37 (reg & 0xfc);
38}
39
40
41static int
42mace_pci_read_config(struct pci_bus *bus, unsigned int devfn,
43 int reg, int size, u32 *val)
44{
45 u32 control = mace->pci.control;
46
47 /* disable master aborts interrupts during config read */
48 mace->pci.control = control & ~MACEPCI_CONTROL_MAR_INT;
49 mace->pci.config_addr = mkaddr(bus, devfn, reg);
50 switch (size) {
51 case 1:
52 *val = mace->pci.config_data.b[(reg & 3) ^ 3];
53 break;
54 case 2:
55 *val = mace->pci.config_data.w[((reg >> 1) & 1) ^ 1];
56 break;
57 case 4:
58 *val = mace->pci.config_data.l;
59 break;
60 }
61 /* ack possible master abort */
62 mace->pci.error &= ~MACEPCI_ERROR_MASTER_ABORT;
63 mace->pci.control = control;
64 /*
65 * someone forgot to set the ultra bit for the onboard
66 * scsi chips; we fake it here
67 */
68 if (bus->number == 0 && reg == 0x40 && size == 4 &&
69 (devfn == (1 << 3) || devfn == (2 << 3)))
70 *val |= 0x1000;
71
72 DPRINTK("read%d: reg=%08x,val=%02x\n", size * 8, reg, *val);
73
74 return PCIBIOS_SUCCESSFUL;
75}
76
77static int
78mace_pci_write_config(struct pci_bus *bus, unsigned int devfn,
79 int reg, int size, u32 val)
80{
81 mace->pci.config_addr = mkaddr(bus, devfn, reg);
82 switch (size) {
83 case 1:
84 mace->pci.config_data.b[(reg & 3) ^ 3] = val;
85 break;
86 case 2:
87 mace->pci.config_data.w[((reg >> 1) & 1) ^ 1] = val;
88 break;
89 case 4:
90 mace->pci.config_data.l = val;
91 break;
92 }
93
94 DPRINTK("write%d: reg=%08x,val=%02x\n", size * 8, reg, val);
95
96 return PCIBIOS_SUCCESSFUL;
97}
98
99struct pci_ops mace_pci_ops = {
100 .read = mace_pci_read_config,
101 .write = mace_pci_write_config,
102};
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2000, 2001 Keith M Wesolowski
7 */
8#include <linux/kernel.h>
9#include <linux/init.h>
10#include <linux/pci.h>
11#include <linux/types.h>
12#include <asm/pci.h>
13#include <asm/ip32/mace.h>
14
15#if 0
16# define DPRINTK(args...) printk(args);
17#else
18# define DPRINTK(args...)
19#endif
20
21/*
22 * O2 has up to 5 PCI devices connected into the MACE bridge. The device
23 * map looks like this:
24 *
25 * 0 aic7xxx 0
26 * 1 aic7xxx 1
27 * 2 expansion slot
28 * 3 N/C
29 * 4 N/C
30 */
31
32static inline int mkaddr(struct pci_bus *bus, unsigned int devfn,
33 unsigned int reg)
34{
35 return ((bus->number & 0xff) << 16) |
36 ((devfn & 0xff) << 8) |
37 (reg & 0xfc);
38}
39
40
41static int
42mace_pci_read_config(struct pci_bus *bus, unsigned int devfn,
43 int reg, int size, u32 *val)
44{
45 u32 control = mace->pci.control;
46
47 /* disable master aborts interrupts during config read */
48 mace->pci.control = control & ~MACEPCI_CONTROL_MAR_INT;
49 mace->pci.config_addr = mkaddr(bus, devfn, reg);
50 switch (size) {
51 case 1:
52 *val = mace->pci.config_data.b[(reg & 3) ^ 3];
53 break;
54 case 2:
55 *val = mace->pci.config_data.w[((reg >> 1) & 1) ^ 1];
56 break;
57 case 4:
58 *val = mace->pci.config_data.l;
59 break;
60 }
61 /* ack possible master abort */
62 mace->pci.error &= ~MACEPCI_ERROR_MASTER_ABORT;
63 mace->pci.control = control;
64 /*
65 * someone forgot to set the ultra bit for the onboard
66 * scsi chips; we fake it here
67 */
68 if (bus->number == 0 && reg == 0x40 && size == 4 &&
69 (devfn == (1 << 3) || devfn == (2 << 3)))
70 *val |= 0x1000;
71
72 DPRINTK("read%d: reg=%08x,val=%02x\n", size * 8, reg, *val);
73
74 return PCIBIOS_SUCCESSFUL;
75}
76
77static int
78mace_pci_write_config(struct pci_bus *bus, unsigned int devfn,
79 int reg, int size, u32 val)
80{
81 mace->pci.config_addr = mkaddr(bus, devfn, reg);
82 switch (size) {
83 case 1:
84 mace->pci.config_data.b[(reg & 3) ^ 3] = val;
85 break;
86 case 2:
87 mace->pci.config_data.w[((reg >> 1) & 1) ^ 1] = val;
88 break;
89 case 4:
90 mace->pci.config_data.l = val;
91 break;
92 }
93
94 DPRINTK("write%d: reg=%08x,val=%02x\n", size * 8, reg, val);
95
96 return PCIBIOS_SUCCESSFUL;
97}
98
99struct pci_ops mace_pci_ops = {
100 .read = mace_pci_read_config,
101 .write = mace_pci_write_config,
102};