Loading...
1/* linux/arch/arm/plat-s3c24xx/irq.c
2 *
3 * Copyright (c) 2003-2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19*/
20
21#include <linux/init.h>
22#include <linux/module.h>
23#include <linux/interrupt.h>
24#include <linux/ioport.h>
25#include <linux/sysdev.h>
26#include <linux/syscore_ops.h>
27
28#include <asm/irq.h>
29#include <asm/mach/irq.h>
30
31#include <plat/regs-irqtype.h>
32
33#include <plat/cpu.h>
34#include <plat/pm.h>
35#include <plat/irq.h>
36
37static void
38s3c_irq_mask(struct irq_data *data)
39{
40 unsigned int irqno = data->irq - IRQ_EINT0;
41 unsigned long mask;
42
43 mask = __raw_readl(S3C2410_INTMSK);
44 mask |= 1UL << irqno;
45 __raw_writel(mask, S3C2410_INTMSK);
46}
47
48static inline void
49s3c_irq_ack(struct irq_data *data)
50{
51 unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
52
53 __raw_writel(bitval, S3C2410_SRCPND);
54 __raw_writel(bitval, S3C2410_INTPND);
55}
56
57static inline void
58s3c_irq_maskack(struct irq_data *data)
59{
60 unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
61 unsigned long mask;
62
63 mask = __raw_readl(S3C2410_INTMSK);
64 __raw_writel(mask|bitval, S3C2410_INTMSK);
65
66 __raw_writel(bitval, S3C2410_SRCPND);
67 __raw_writel(bitval, S3C2410_INTPND);
68}
69
70
71static void
72s3c_irq_unmask(struct irq_data *data)
73{
74 unsigned int irqno = data->irq;
75 unsigned long mask;
76
77 if (irqno != IRQ_TIMER4 && irqno != IRQ_EINT8t23)
78 irqdbf2("s3c_irq_unmask %d\n", irqno);
79
80 irqno -= IRQ_EINT0;
81
82 mask = __raw_readl(S3C2410_INTMSK);
83 mask &= ~(1UL << irqno);
84 __raw_writel(mask, S3C2410_INTMSK);
85}
86
87struct irq_chip s3c_irq_level_chip = {
88 .name = "s3c-level",
89 .irq_ack = s3c_irq_maskack,
90 .irq_mask = s3c_irq_mask,
91 .irq_unmask = s3c_irq_unmask,
92 .irq_set_wake = s3c_irq_wake
93};
94
95struct irq_chip s3c_irq_chip = {
96 .name = "s3c",
97 .irq_ack = s3c_irq_ack,
98 .irq_mask = s3c_irq_mask,
99 .irq_unmask = s3c_irq_unmask,
100 .irq_set_wake = s3c_irq_wake
101};
102
103static void
104s3c_irqext_mask(struct irq_data *data)
105{
106 unsigned int irqno = data->irq - EXTINT_OFF;
107 unsigned long mask;
108
109 mask = __raw_readl(S3C24XX_EINTMASK);
110 mask |= ( 1UL << irqno);
111 __raw_writel(mask, S3C24XX_EINTMASK);
112}
113
114static void
115s3c_irqext_ack(struct irq_data *data)
116{
117 unsigned long req;
118 unsigned long bit;
119 unsigned long mask;
120
121 bit = 1UL << (data->irq - EXTINT_OFF);
122
123 mask = __raw_readl(S3C24XX_EINTMASK);
124
125 __raw_writel(bit, S3C24XX_EINTPEND);
126
127 req = __raw_readl(S3C24XX_EINTPEND);
128 req &= ~mask;
129
130 /* not sure if we should be acking the parent irq... */
131
132 if (data->irq <= IRQ_EINT7) {
133 if ((req & 0xf0) == 0)
134 s3c_irq_ack(irq_get_irq_data(IRQ_EINT4t7));
135 } else {
136 if ((req >> 8) == 0)
137 s3c_irq_ack(irq_get_irq_data(IRQ_EINT8t23));
138 }
139}
140
141static void
142s3c_irqext_unmask(struct irq_data *data)
143{
144 unsigned int irqno = data->irq - EXTINT_OFF;
145 unsigned long mask;
146
147 mask = __raw_readl(S3C24XX_EINTMASK);
148 mask &= ~(1UL << irqno);
149 __raw_writel(mask, S3C24XX_EINTMASK);
150}
151
152int
153s3c_irqext_type(struct irq_data *data, unsigned int type)
154{
155 void __iomem *extint_reg;
156 void __iomem *gpcon_reg;
157 unsigned long gpcon_offset, extint_offset;
158 unsigned long newvalue = 0, value;
159
160 if ((data->irq >= IRQ_EINT0) && (data->irq <= IRQ_EINT3)) {
161 gpcon_reg = S3C2410_GPFCON;
162 extint_reg = S3C24XX_EXTINT0;
163 gpcon_offset = (data->irq - IRQ_EINT0) * 2;
164 extint_offset = (data->irq - IRQ_EINT0) * 4;
165 } else if ((data->irq >= IRQ_EINT4) && (data->irq <= IRQ_EINT7)) {
166 gpcon_reg = S3C2410_GPFCON;
167 extint_reg = S3C24XX_EXTINT0;
168 gpcon_offset = (data->irq - (EXTINT_OFF)) * 2;
169 extint_offset = (data->irq - (EXTINT_OFF)) * 4;
170 } else if ((data->irq >= IRQ_EINT8) && (data->irq <= IRQ_EINT15)) {
171 gpcon_reg = S3C2410_GPGCON;
172 extint_reg = S3C24XX_EXTINT1;
173 gpcon_offset = (data->irq - IRQ_EINT8) * 2;
174 extint_offset = (data->irq - IRQ_EINT8) * 4;
175 } else if ((data->irq >= IRQ_EINT16) && (data->irq <= IRQ_EINT23)) {
176 gpcon_reg = S3C2410_GPGCON;
177 extint_reg = S3C24XX_EXTINT2;
178 gpcon_offset = (data->irq - IRQ_EINT8) * 2;
179 extint_offset = (data->irq - IRQ_EINT16) * 4;
180 } else {
181 return -1;
182 }
183
184 /* Set the GPIO to external interrupt mode */
185 value = __raw_readl(gpcon_reg);
186 value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset);
187 __raw_writel(value, gpcon_reg);
188
189 /* Set the external interrupt to pointed trigger type */
190 switch (type)
191 {
192 case IRQ_TYPE_NONE:
193 printk(KERN_WARNING "No edge setting!\n");
194 break;
195
196 case IRQ_TYPE_EDGE_RISING:
197 newvalue = S3C2410_EXTINT_RISEEDGE;
198 break;
199
200 case IRQ_TYPE_EDGE_FALLING:
201 newvalue = S3C2410_EXTINT_FALLEDGE;
202 break;
203
204 case IRQ_TYPE_EDGE_BOTH:
205 newvalue = S3C2410_EXTINT_BOTHEDGE;
206 break;
207
208 case IRQ_TYPE_LEVEL_LOW:
209 newvalue = S3C2410_EXTINT_LOWLEV;
210 break;
211
212 case IRQ_TYPE_LEVEL_HIGH:
213 newvalue = S3C2410_EXTINT_HILEV;
214 break;
215
216 default:
217 printk(KERN_ERR "No such irq type %d", type);
218 return -1;
219 }
220
221 value = __raw_readl(extint_reg);
222 value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset);
223 __raw_writel(value, extint_reg);
224
225 return 0;
226}
227
228static struct irq_chip s3c_irqext_chip = {
229 .name = "s3c-ext",
230 .irq_mask = s3c_irqext_mask,
231 .irq_unmask = s3c_irqext_unmask,
232 .irq_ack = s3c_irqext_ack,
233 .irq_set_type = s3c_irqext_type,
234 .irq_set_wake = s3c_irqext_wake
235};
236
237static struct irq_chip s3c_irq_eint0t4 = {
238 .name = "s3c-ext0",
239 .irq_ack = s3c_irq_ack,
240 .irq_mask = s3c_irq_mask,
241 .irq_unmask = s3c_irq_unmask,
242 .irq_set_wake = s3c_irq_wake,
243 .irq_set_type = s3c_irqext_type,
244};
245
246/* mask values for the parent registers for each of the interrupt types */
247
248#define INTMSK_UART0 (1UL << (IRQ_UART0 - IRQ_EINT0))
249#define INTMSK_UART1 (1UL << (IRQ_UART1 - IRQ_EINT0))
250#define INTMSK_UART2 (1UL << (IRQ_UART2 - IRQ_EINT0))
251#define INTMSK_ADCPARENT (1UL << (IRQ_ADCPARENT - IRQ_EINT0))
252
253
254/* UART0 */
255
256static void
257s3c_irq_uart0_mask(struct irq_data *data)
258{
259 s3c_irqsub_mask(data->irq, INTMSK_UART0, 7);
260}
261
262static void
263s3c_irq_uart0_unmask(struct irq_data *data)
264{
265 s3c_irqsub_unmask(data->irq, INTMSK_UART0);
266}
267
268static void
269s3c_irq_uart0_ack(struct irq_data *data)
270{
271 s3c_irqsub_maskack(data->irq, INTMSK_UART0, 7);
272}
273
274static struct irq_chip s3c_irq_uart0 = {
275 .name = "s3c-uart0",
276 .irq_mask = s3c_irq_uart0_mask,
277 .irq_unmask = s3c_irq_uart0_unmask,
278 .irq_ack = s3c_irq_uart0_ack,
279};
280
281/* UART1 */
282
283static void
284s3c_irq_uart1_mask(struct irq_data *data)
285{
286 s3c_irqsub_mask(data->irq, INTMSK_UART1, 7 << 3);
287}
288
289static void
290s3c_irq_uart1_unmask(struct irq_data *data)
291{
292 s3c_irqsub_unmask(data->irq, INTMSK_UART1);
293}
294
295static void
296s3c_irq_uart1_ack(struct irq_data *data)
297{
298 s3c_irqsub_maskack(data->irq, INTMSK_UART1, 7 << 3);
299}
300
301static struct irq_chip s3c_irq_uart1 = {
302 .name = "s3c-uart1",
303 .irq_mask = s3c_irq_uart1_mask,
304 .irq_unmask = s3c_irq_uart1_unmask,
305 .irq_ack = s3c_irq_uart1_ack,
306};
307
308/* UART2 */
309
310static void
311s3c_irq_uart2_mask(struct irq_data *data)
312{
313 s3c_irqsub_mask(data->irq, INTMSK_UART2, 7 << 6);
314}
315
316static void
317s3c_irq_uart2_unmask(struct irq_data *data)
318{
319 s3c_irqsub_unmask(data->irq, INTMSK_UART2);
320}
321
322static void
323s3c_irq_uart2_ack(struct irq_data *data)
324{
325 s3c_irqsub_maskack(data->irq, INTMSK_UART2, 7 << 6);
326}
327
328static struct irq_chip s3c_irq_uart2 = {
329 .name = "s3c-uart2",
330 .irq_mask = s3c_irq_uart2_mask,
331 .irq_unmask = s3c_irq_uart2_unmask,
332 .irq_ack = s3c_irq_uart2_ack,
333};
334
335/* ADC and Touchscreen */
336
337static void
338s3c_irq_adc_mask(struct irq_data *d)
339{
340 s3c_irqsub_mask(d->irq, INTMSK_ADCPARENT, 3 << 9);
341}
342
343static void
344s3c_irq_adc_unmask(struct irq_data *d)
345{
346 s3c_irqsub_unmask(d->irq, INTMSK_ADCPARENT);
347}
348
349static void
350s3c_irq_adc_ack(struct irq_data *d)
351{
352 s3c_irqsub_ack(d->irq, INTMSK_ADCPARENT, 3 << 9);
353}
354
355static struct irq_chip s3c_irq_adc = {
356 .name = "s3c-adc",
357 .irq_mask = s3c_irq_adc_mask,
358 .irq_unmask = s3c_irq_adc_unmask,
359 .irq_ack = s3c_irq_adc_ack,
360};
361
362/* irq demux for adc */
363static void s3c_irq_demux_adc(unsigned int irq,
364 struct irq_desc *desc)
365{
366 unsigned int subsrc, submsk;
367 unsigned int offset = 9;
368
369 /* read the current pending interrupts, and the mask
370 * for what it is available */
371
372 subsrc = __raw_readl(S3C2410_SUBSRCPND);
373 submsk = __raw_readl(S3C2410_INTSUBMSK);
374
375 subsrc &= ~submsk;
376 subsrc >>= offset;
377 subsrc &= 3;
378
379 if (subsrc != 0) {
380 if (subsrc & 1) {
381 generic_handle_irq(IRQ_TC);
382 }
383 if (subsrc & 2) {
384 generic_handle_irq(IRQ_ADC);
385 }
386 }
387}
388
389static void s3c_irq_demux_uart(unsigned int start)
390{
391 unsigned int subsrc, submsk;
392 unsigned int offset = start - IRQ_S3CUART_RX0;
393
394 /* read the current pending interrupts, and the mask
395 * for what it is available */
396
397 subsrc = __raw_readl(S3C2410_SUBSRCPND);
398 submsk = __raw_readl(S3C2410_INTSUBMSK);
399
400 irqdbf2("s3c_irq_demux_uart: start=%d (%d), subsrc=0x%08x,0x%08x\n",
401 start, offset, subsrc, submsk);
402
403 subsrc &= ~submsk;
404 subsrc >>= offset;
405 subsrc &= 7;
406
407 if (subsrc != 0) {
408 if (subsrc & 1)
409 generic_handle_irq(start);
410
411 if (subsrc & 2)
412 generic_handle_irq(start+1);
413
414 if (subsrc & 4)
415 generic_handle_irq(start+2);
416 }
417}
418
419/* uart demux entry points */
420
421static void
422s3c_irq_demux_uart0(unsigned int irq,
423 struct irq_desc *desc)
424{
425 irq = irq;
426 s3c_irq_demux_uart(IRQ_S3CUART_RX0);
427}
428
429static void
430s3c_irq_demux_uart1(unsigned int irq,
431 struct irq_desc *desc)
432{
433 irq = irq;
434 s3c_irq_demux_uart(IRQ_S3CUART_RX1);
435}
436
437static void
438s3c_irq_demux_uart2(unsigned int irq,
439 struct irq_desc *desc)
440{
441 irq = irq;
442 s3c_irq_demux_uart(IRQ_S3CUART_RX2);
443}
444
445static void
446s3c_irq_demux_extint8(unsigned int irq,
447 struct irq_desc *desc)
448{
449 unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND);
450 unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK);
451
452 eintpnd &= ~eintmsk;
453 eintpnd &= ~0xff; /* ignore lower irqs */
454
455 /* we may as well handle all the pending IRQs here */
456
457 while (eintpnd) {
458 irq = __ffs(eintpnd);
459 eintpnd &= ~(1<<irq);
460
461 irq += (IRQ_EINT4 - 4);
462 generic_handle_irq(irq);
463 }
464
465}
466
467static void
468s3c_irq_demux_extint4t7(unsigned int irq,
469 struct irq_desc *desc)
470{
471 unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND);
472 unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK);
473
474 eintpnd &= ~eintmsk;
475 eintpnd &= 0xff; /* only lower irqs */
476
477 /* we may as well handle all the pending IRQs here */
478
479 while (eintpnd) {
480 irq = __ffs(eintpnd);
481 eintpnd &= ~(1<<irq);
482
483 irq += (IRQ_EINT4 - 4);
484
485 generic_handle_irq(irq);
486 }
487}
488
489#ifdef CONFIG_FIQ
490/**
491 * s3c24xx_set_fiq - set the FIQ routing
492 * @irq: IRQ number to route to FIQ on processor.
493 * @on: Whether to route @irq to the FIQ, or to remove the FIQ routing.
494 *
495 * Change the state of the IRQ to FIQ routing depending on @irq and @on. If
496 * @on is true, the @irq is checked to see if it can be routed and the
497 * interrupt controller updated to route the IRQ. If @on is false, the FIQ
498 * routing is cleared, regardless of which @irq is specified.
499 */
500int s3c24xx_set_fiq(unsigned int irq, bool on)
501{
502 u32 intmod;
503 unsigned offs;
504
505 if (on) {
506 offs = irq - FIQ_START;
507 if (offs > 31)
508 return -EINVAL;
509
510 intmod = 1 << offs;
511 } else {
512 intmod = 0;
513 }
514
515 __raw_writel(intmod, S3C2410_INTMOD);
516 return 0;
517}
518
519EXPORT_SYMBOL_GPL(s3c24xx_set_fiq);
520#endif
521
522
523/* s3c24xx_init_irq
524 *
525 * Initialise S3C2410 IRQ system
526*/
527
528void __init s3c24xx_init_irq(void)
529{
530 unsigned long pend;
531 unsigned long last;
532 int irqno;
533 int i;
534
535#ifdef CONFIG_FIQ
536 init_FIQ();
537#endif
538
539 irqdbf("s3c2410_init_irq: clearing interrupt status flags\n");
540
541 /* first, clear all interrupts pending... */
542
543 last = 0;
544 for (i = 0; i < 4; i++) {
545 pend = __raw_readl(S3C24XX_EINTPEND);
546
547 if (pend == 0 || pend == last)
548 break;
549
550 __raw_writel(pend, S3C24XX_EINTPEND);
551 printk("irq: clearing pending ext status %08x\n", (int)pend);
552 last = pend;
553 }
554
555 last = 0;
556 for (i = 0; i < 4; i++) {
557 pend = __raw_readl(S3C2410_INTPND);
558
559 if (pend == 0 || pend == last)
560 break;
561
562 __raw_writel(pend, S3C2410_SRCPND);
563 __raw_writel(pend, S3C2410_INTPND);
564 printk("irq: clearing pending status %08x\n", (int)pend);
565 last = pend;
566 }
567
568 last = 0;
569 for (i = 0; i < 4; i++) {
570 pend = __raw_readl(S3C2410_SUBSRCPND);
571
572 if (pend == 0 || pend == last)
573 break;
574
575 printk("irq: clearing subpending status %08x\n", (int)pend);
576 __raw_writel(pend, S3C2410_SUBSRCPND);
577 last = pend;
578 }
579
580 /* register the main interrupts */
581
582 irqdbf("s3c2410_init_irq: registering s3c2410 interrupt handlers\n");
583
584 for (irqno = IRQ_EINT4t7; irqno <= IRQ_ADCPARENT; irqno++) {
585 /* set all the s3c2410 internal irqs */
586
587 switch (irqno) {
588 /* deal with the special IRQs (cascaded) */
589
590 case IRQ_EINT4t7:
591 case IRQ_EINT8t23:
592 case IRQ_UART0:
593 case IRQ_UART1:
594 case IRQ_UART2:
595 case IRQ_ADCPARENT:
596 irq_set_chip_and_handler(irqno, &s3c_irq_level_chip,
597 handle_level_irq);
598 break;
599
600 case IRQ_RESERVED6:
601 case IRQ_RESERVED24:
602 /* no IRQ here */
603 break;
604
605 default:
606 //irqdbf("registering irq %d (s3c irq)\n", irqno);
607 irq_set_chip_and_handler(irqno, &s3c_irq_chip,
608 handle_edge_irq);
609 set_irq_flags(irqno, IRQF_VALID);
610 }
611 }
612
613 /* setup the cascade irq handlers */
614
615 irq_set_chained_handler(IRQ_EINT4t7, s3c_irq_demux_extint4t7);
616 irq_set_chained_handler(IRQ_EINT8t23, s3c_irq_demux_extint8);
617
618 irq_set_chained_handler(IRQ_UART0, s3c_irq_demux_uart0);
619 irq_set_chained_handler(IRQ_UART1, s3c_irq_demux_uart1);
620 irq_set_chained_handler(IRQ_UART2, s3c_irq_demux_uart2);
621 irq_set_chained_handler(IRQ_ADCPARENT, s3c_irq_demux_adc);
622
623 /* external interrupts */
624
625 for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
626 irqdbf("registering irq %d (ext int)\n", irqno);
627 irq_set_chip_and_handler(irqno, &s3c_irq_eint0t4,
628 handle_edge_irq);
629 set_irq_flags(irqno, IRQF_VALID);
630 }
631
632 for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) {
633 irqdbf("registering irq %d (extended s3c irq)\n", irqno);
634 irq_set_chip_and_handler(irqno, &s3c_irqext_chip,
635 handle_edge_irq);
636 set_irq_flags(irqno, IRQF_VALID);
637 }
638
639 /* register the uart interrupts */
640
641 irqdbf("s3c2410: registering external interrupts\n");
642
643 for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) {
644 irqdbf("registering irq %d (s3c uart0 irq)\n", irqno);
645 irq_set_chip_and_handler(irqno, &s3c_irq_uart0,
646 handle_level_irq);
647 set_irq_flags(irqno, IRQF_VALID);
648 }
649
650 for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) {
651 irqdbf("registering irq %d (s3c uart1 irq)\n", irqno);
652 irq_set_chip_and_handler(irqno, &s3c_irq_uart1,
653 handle_level_irq);
654 set_irq_flags(irqno, IRQF_VALID);
655 }
656
657 for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) {
658 irqdbf("registering irq %d (s3c uart2 irq)\n", irqno);
659 irq_set_chip_and_handler(irqno, &s3c_irq_uart2,
660 handle_level_irq);
661 set_irq_flags(irqno, IRQF_VALID);
662 }
663
664 for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) {
665 irqdbf("registering irq %d (s3c adc irq)\n", irqno);
666 irq_set_chip_and_handler(irqno, &s3c_irq_adc, handle_edge_irq);
667 set_irq_flags(irqno, IRQF_VALID);
668 }
669
670 irqdbf("s3c2410: registered interrupt handlers\n");
671}
672
673struct syscore_ops s3c24xx_irq_syscore_ops = {
674 .suspend = s3c24xx_irq_suspend,
675 .resume = s3c24xx_irq_resume,
676};
1/* linux/arch/arm/plat-s3c24xx/irq.c
2 *
3 * Copyright (c) 2003-2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19*/
20
21#include <linux/init.h>
22#include <linux/module.h>
23#include <linux/interrupt.h>
24#include <linux/ioport.h>
25#include <linux/device.h>
26#include <linux/syscore_ops.h>
27
28#include <asm/irq.h>
29#include <asm/mach/irq.h>
30
31#include <plat/regs-irqtype.h>
32
33#include <plat/cpu.h>
34#include <plat/pm.h>
35#include <plat/irq.h>
36
37static void
38s3c_irq_mask(struct irq_data *data)
39{
40 unsigned int irqno = data->irq - IRQ_EINT0;
41 unsigned long mask;
42
43 mask = __raw_readl(S3C2410_INTMSK);
44 mask |= 1UL << irqno;
45 __raw_writel(mask, S3C2410_INTMSK);
46}
47
48static inline void
49s3c_irq_ack(struct irq_data *data)
50{
51 unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
52
53 __raw_writel(bitval, S3C2410_SRCPND);
54 __raw_writel(bitval, S3C2410_INTPND);
55}
56
57static inline void
58s3c_irq_maskack(struct irq_data *data)
59{
60 unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
61 unsigned long mask;
62
63 mask = __raw_readl(S3C2410_INTMSK);
64 __raw_writel(mask|bitval, S3C2410_INTMSK);
65
66 __raw_writel(bitval, S3C2410_SRCPND);
67 __raw_writel(bitval, S3C2410_INTPND);
68}
69
70
71static void
72s3c_irq_unmask(struct irq_data *data)
73{
74 unsigned int irqno = data->irq;
75 unsigned long mask;
76
77 if (irqno != IRQ_TIMER4 && irqno != IRQ_EINT8t23)
78 irqdbf2("s3c_irq_unmask %d\n", irqno);
79
80 irqno -= IRQ_EINT0;
81
82 mask = __raw_readl(S3C2410_INTMSK);
83 mask &= ~(1UL << irqno);
84 __raw_writel(mask, S3C2410_INTMSK);
85}
86
87struct irq_chip s3c_irq_level_chip = {
88 .name = "s3c-level",
89 .irq_ack = s3c_irq_maskack,
90 .irq_mask = s3c_irq_mask,
91 .irq_unmask = s3c_irq_unmask,
92 .irq_set_wake = s3c_irq_wake
93};
94
95struct irq_chip s3c_irq_chip = {
96 .name = "s3c",
97 .irq_ack = s3c_irq_ack,
98 .irq_mask = s3c_irq_mask,
99 .irq_unmask = s3c_irq_unmask,
100 .irq_set_wake = s3c_irq_wake
101};
102
103static void
104s3c_irqext_mask(struct irq_data *data)
105{
106 unsigned int irqno = data->irq - EXTINT_OFF;
107 unsigned long mask;
108
109 mask = __raw_readl(S3C24XX_EINTMASK);
110 mask |= ( 1UL << irqno);
111 __raw_writel(mask, S3C24XX_EINTMASK);
112}
113
114static void
115s3c_irqext_ack(struct irq_data *data)
116{
117 unsigned long req;
118 unsigned long bit;
119 unsigned long mask;
120
121 bit = 1UL << (data->irq - EXTINT_OFF);
122
123 mask = __raw_readl(S3C24XX_EINTMASK);
124
125 __raw_writel(bit, S3C24XX_EINTPEND);
126
127 req = __raw_readl(S3C24XX_EINTPEND);
128 req &= ~mask;
129
130 /* not sure if we should be acking the parent irq... */
131
132 if (data->irq <= IRQ_EINT7) {
133 if ((req & 0xf0) == 0)
134 s3c_irq_ack(irq_get_irq_data(IRQ_EINT4t7));
135 } else {
136 if ((req >> 8) == 0)
137 s3c_irq_ack(irq_get_irq_data(IRQ_EINT8t23));
138 }
139}
140
141static void
142s3c_irqext_unmask(struct irq_data *data)
143{
144 unsigned int irqno = data->irq - EXTINT_OFF;
145 unsigned long mask;
146
147 mask = __raw_readl(S3C24XX_EINTMASK);
148 mask &= ~(1UL << irqno);
149 __raw_writel(mask, S3C24XX_EINTMASK);
150}
151
152int
153s3c_irqext_type(struct irq_data *data, unsigned int type)
154{
155 void __iomem *extint_reg;
156 void __iomem *gpcon_reg;
157 unsigned long gpcon_offset, extint_offset;
158 unsigned long newvalue = 0, value;
159
160 if ((data->irq >= IRQ_EINT0) && (data->irq <= IRQ_EINT3)) {
161 gpcon_reg = S3C2410_GPFCON;
162 extint_reg = S3C24XX_EXTINT0;
163 gpcon_offset = (data->irq - IRQ_EINT0) * 2;
164 extint_offset = (data->irq - IRQ_EINT0) * 4;
165 } else if ((data->irq >= IRQ_EINT4) && (data->irq <= IRQ_EINT7)) {
166 gpcon_reg = S3C2410_GPFCON;
167 extint_reg = S3C24XX_EXTINT0;
168 gpcon_offset = (data->irq - (EXTINT_OFF)) * 2;
169 extint_offset = (data->irq - (EXTINT_OFF)) * 4;
170 } else if ((data->irq >= IRQ_EINT8) && (data->irq <= IRQ_EINT15)) {
171 gpcon_reg = S3C2410_GPGCON;
172 extint_reg = S3C24XX_EXTINT1;
173 gpcon_offset = (data->irq - IRQ_EINT8) * 2;
174 extint_offset = (data->irq - IRQ_EINT8) * 4;
175 } else if ((data->irq >= IRQ_EINT16) && (data->irq <= IRQ_EINT23)) {
176 gpcon_reg = S3C2410_GPGCON;
177 extint_reg = S3C24XX_EXTINT2;
178 gpcon_offset = (data->irq - IRQ_EINT8) * 2;
179 extint_offset = (data->irq - IRQ_EINT16) * 4;
180 } else {
181 return -1;
182 }
183
184 /* Set the GPIO to external interrupt mode */
185 value = __raw_readl(gpcon_reg);
186 value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset);
187 __raw_writel(value, gpcon_reg);
188
189 /* Set the external interrupt to pointed trigger type */
190 switch (type)
191 {
192 case IRQ_TYPE_NONE:
193 printk(KERN_WARNING "No edge setting!\n");
194 break;
195
196 case IRQ_TYPE_EDGE_RISING:
197 newvalue = S3C2410_EXTINT_RISEEDGE;
198 break;
199
200 case IRQ_TYPE_EDGE_FALLING:
201 newvalue = S3C2410_EXTINT_FALLEDGE;
202 break;
203
204 case IRQ_TYPE_EDGE_BOTH:
205 newvalue = S3C2410_EXTINT_BOTHEDGE;
206 break;
207
208 case IRQ_TYPE_LEVEL_LOW:
209 newvalue = S3C2410_EXTINT_LOWLEV;
210 break;
211
212 case IRQ_TYPE_LEVEL_HIGH:
213 newvalue = S3C2410_EXTINT_HILEV;
214 break;
215
216 default:
217 printk(KERN_ERR "No such irq type %d", type);
218 return -1;
219 }
220
221 value = __raw_readl(extint_reg);
222 value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset);
223 __raw_writel(value, extint_reg);
224
225 return 0;
226}
227
228static struct irq_chip s3c_irqext_chip = {
229 .name = "s3c-ext",
230 .irq_mask = s3c_irqext_mask,
231 .irq_unmask = s3c_irqext_unmask,
232 .irq_ack = s3c_irqext_ack,
233 .irq_set_type = s3c_irqext_type,
234 .irq_set_wake = s3c_irqext_wake
235};
236
237static struct irq_chip s3c_irq_eint0t4 = {
238 .name = "s3c-ext0",
239 .irq_ack = s3c_irq_ack,
240 .irq_mask = s3c_irq_mask,
241 .irq_unmask = s3c_irq_unmask,
242 .irq_set_wake = s3c_irq_wake,
243 .irq_set_type = s3c_irqext_type,
244};
245
246/* mask values for the parent registers for each of the interrupt types */
247
248#define INTMSK_UART0 (1UL << (IRQ_UART0 - IRQ_EINT0))
249#define INTMSK_UART1 (1UL << (IRQ_UART1 - IRQ_EINT0))
250#define INTMSK_UART2 (1UL << (IRQ_UART2 - IRQ_EINT0))
251#define INTMSK_ADCPARENT (1UL << (IRQ_ADCPARENT - IRQ_EINT0))
252
253
254/* UART0 */
255
256static void
257s3c_irq_uart0_mask(struct irq_data *data)
258{
259 s3c_irqsub_mask(data->irq, INTMSK_UART0, 7);
260}
261
262static void
263s3c_irq_uart0_unmask(struct irq_data *data)
264{
265 s3c_irqsub_unmask(data->irq, INTMSK_UART0);
266}
267
268static void
269s3c_irq_uart0_ack(struct irq_data *data)
270{
271 s3c_irqsub_maskack(data->irq, INTMSK_UART0, 7);
272}
273
274static struct irq_chip s3c_irq_uart0 = {
275 .name = "s3c-uart0",
276 .irq_mask = s3c_irq_uart0_mask,
277 .irq_unmask = s3c_irq_uart0_unmask,
278 .irq_ack = s3c_irq_uart0_ack,
279};
280
281/* UART1 */
282
283static void
284s3c_irq_uart1_mask(struct irq_data *data)
285{
286 s3c_irqsub_mask(data->irq, INTMSK_UART1, 7 << 3);
287}
288
289static void
290s3c_irq_uart1_unmask(struct irq_data *data)
291{
292 s3c_irqsub_unmask(data->irq, INTMSK_UART1);
293}
294
295static void
296s3c_irq_uart1_ack(struct irq_data *data)
297{
298 s3c_irqsub_maskack(data->irq, INTMSK_UART1, 7 << 3);
299}
300
301static struct irq_chip s3c_irq_uart1 = {
302 .name = "s3c-uart1",
303 .irq_mask = s3c_irq_uart1_mask,
304 .irq_unmask = s3c_irq_uart1_unmask,
305 .irq_ack = s3c_irq_uart1_ack,
306};
307
308/* UART2 */
309
310static void
311s3c_irq_uart2_mask(struct irq_data *data)
312{
313 s3c_irqsub_mask(data->irq, INTMSK_UART2, 7 << 6);
314}
315
316static void
317s3c_irq_uart2_unmask(struct irq_data *data)
318{
319 s3c_irqsub_unmask(data->irq, INTMSK_UART2);
320}
321
322static void
323s3c_irq_uart2_ack(struct irq_data *data)
324{
325 s3c_irqsub_maskack(data->irq, INTMSK_UART2, 7 << 6);
326}
327
328static struct irq_chip s3c_irq_uart2 = {
329 .name = "s3c-uart2",
330 .irq_mask = s3c_irq_uart2_mask,
331 .irq_unmask = s3c_irq_uart2_unmask,
332 .irq_ack = s3c_irq_uart2_ack,
333};
334
335/* ADC and Touchscreen */
336
337static void
338s3c_irq_adc_mask(struct irq_data *d)
339{
340 s3c_irqsub_mask(d->irq, INTMSK_ADCPARENT, 3 << 9);
341}
342
343static void
344s3c_irq_adc_unmask(struct irq_data *d)
345{
346 s3c_irqsub_unmask(d->irq, INTMSK_ADCPARENT);
347}
348
349static void
350s3c_irq_adc_ack(struct irq_data *d)
351{
352 s3c_irqsub_ack(d->irq, INTMSK_ADCPARENT, 3 << 9);
353}
354
355static struct irq_chip s3c_irq_adc = {
356 .name = "s3c-adc",
357 .irq_mask = s3c_irq_adc_mask,
358 .irq_unmask = s3c_irq_adc_unmask,
359 .irq_ack = s3c_irq_adc_ack,
360};
361
362/* irq demux for adc */
363static void s3c_irq_demux_adc(unsigned int irq,
364 struct irq_desc *desc)
365{
366 unsigned int subsrc, submsk;
367 unsigned int offset = 9;
368
369 /* read the current pending interrupts, and the mask
370 * for what it is available */
371
372 subsrc = __raw_readl(S3C2410_SUBSRCPND);
373 submsk = __raw_readl(S3C2410_INTSUBMSK);
374
375 subsrc &= ~submsk;
376 subsrc >>= offset;
377 subsrc &= 3;
378
379 if (subsrc != 0) {
380 if (subsrc & 1) {
381 generic_handle_irq(IRQ_TC);
382 }
383 if (subsrc & 2) {
384 generic_handle_irq(IRQ_ADC);
385 }
386 }
387}
388
389static void s3c_irq_demux_uart(unsigned int start)
390{
391 unsigned int subsrc, submsk;
392 unsigned int offset = start - IRQ_S3CUART_RX0;
393
394 /* read the current pending interrupts, and the mask
395 * for what it is available */
396
397 subsrc = __raw_readl(S3C2410_SUBSRCPND);
398 submsk = __raw_readl(S3C2410_INTSUBMSK);
399
400 irqdbf2("s3c_irq_demux_uart: start=%d (%d), subsrc=0x%08x,0x%08x\n",
401 start, offset, subsrc, submsk);
402
403 subsrc &= ~submsk;
404 subsrc >>= offset;
405 subsrc &= 7;
406
407 if (subsrc != 0) {
408 if (subsrc & 1)
409 generic_handle_irq(start);
410
411 if (subsrc & 2)
412 generic_handle_irq(start+1);
413
414 if (subsrc & 4)
415 generic_handle_irq(start+2);
416 }
417}
418
419/* uart demux entry points */
420
421static void
422s3c_irq_demux_uart0(unsigned int irq,
423 struct irq_desc *desc)
424{
425 irq = irq;
426 s3c_irq_demux_uart(IRQ_S3CUART_RX0);
427}
428
429static void
430s3c_irq_demux_uart1(unsigned int irq,
431 struct irq_desc *desc)
432{
433 irq = irq;
434 s3c_irq_demux_uart(IRQ_S3CUART_RX1);
435}
436
437static void
438s3c_irq_demux_uart2(unsigned int irq,
439 struct irq_desc *desc)
440{
441 irq = irq;
442 s3c_irq_demux_uart(IRQ_S3CUART_RX2);
443}
444
445static void
446s3c_irq_demux_extint8(unsigned int irq,
447 struct irq_desc *desc)
448{
449 unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND);
450 unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK);
451
452 eintpnd &= ~eintmsk;
453 eintpnd &= ~0xff; /* ignore lower irqs */
454
455 /* we may as well handle all the pending IRQs here */
456
457 while (eintpnd) {
458 irq = __ffs(eintpnd);
459 eintpnd &= ~(1<<irq);
460
461 irq += (IRQ_EINT4 - 4);
462 generic_handle_irq(irq);
463 }
464
465}
466
467static void
468s3c_irq_demux_extint4t7(unsigned int irq,
469 struct irq_desc *desc)
470{
471 unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND);
472 unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK);
473
474 eintpnd &= ~eintmsk;
475 eintpnd &= 0xff; /* only lower irqs */
476
477 /* we may as well handle all the pending IRQs here */
478
479 while (eintpnd) {
480 irq = __ffs(eintpnd);
481 eintpnd &= ~(1<<irq);
482
483 irq += (IRQ_EINT4 - 4);
484
485 generic_handle_irq(irq);
486 }
487}
488
489#ifdef CONFIG_FIQ
490/**
491 * s3c24xx_set_fiq - set the FIQ routing
492 * @irq: IRQ number to route to FIQ on processor.
493 * @on: Whether to route @irq to the FIQ, or to remove the FIQ routing.
494 *
495 * Change the state of the IRQ to FIQ routing depending on @irq and @on. If
496 * @on is true, the @irq is checked to see if it can be routed and the
497 * interrupt controller updated to route the IRQ. If @on is false, the FIQ
498 * routing is cleared, regardless of which @irq is specified.
499 */
500int s3c24xx_set_fiq(unsigned int irq, bool on)
501{
502 u32 intmod;
503 unsigned offs;
504
505 if (on) {
506 offs = irq - FIQ_START;
507 if (offs > 31)
508 return -EINVAL;
509
510 intmod = 1 << offs;
511 } else {
512 intmod = 0;
513 }
514
515 __raw_writel(intmod, S3C2410_INTMOD);
516 return 0;
517}
518
519EXPORT_SYMBOL_GPL(s3c24xx_set_fiq);
520#endif
521
522
523/* s3c24xx_init_irq
524 *
525 * Initialise S3C2410 IRQ system
526*/
527
528void __init s3c24xx_init_irq(void)
529{
530 unsigned long pend;
531 unsigned long last;
532 int irqno;
533 int i;
534
535#ifdef CONFIG_FIQ
536 init_FIQ();
537#endif
538
539 irqdbf("s3c2410_init_irq: clearing interrupt status flags\n");
540
541 /* first, clear all interrupts pending... */
542
543 last = 0;
544 for (i = 0; i < 4; i++) {
545 pend = __raw_readl(S3C24XX_EINTPEND);
546
547 if (pend == 0 || pend == last)
548 break;
549
550 __raw_writel(pend, S3C24XX_EINTPEND);
551 printk("irq: clearing pending ext status %08x\n", (int)pend);
552 last = pend;
553 }
554
555 last = 0;
556 for (i = 0; i < 4; i++) {
557 pend = __raw_readl(S3C2410_INTPND);
558
559 if (pend == 0 || pend == last)
560 break;
561
562 __raw_writel(pend, S3C2410_SRCPND);
563 __raw_writel(pend, S3C2410_INTPND);
564 printk("irq: clearing pending status %08x\n", (int)pend);
565 last = pend;
566 }
567
568 last = 0;
569 for (i = 0; i < 4; i++) {
570 pend = __raw_readl(S3C2410_SUBSRCPND);
571
572 if (pend == 0 || pend == last)
573 break;
574
575 printk("irq: clearing subpending status %08x\n", (int)pend);
576 __raw_writel(pend, S3C2410_SUBSRCPND);
577 last = pend;
578 }
579
580 /* register the main interrupts */
581
582 irqdbf("s3c2410_init_irq: registering s3c2410 interrupt handlers\n");
583
584 for (irqno = IRQ_EINT4t7; irqno <= IRQ_ADCPARENT; irqno++) {
585 /* set all the s3c2410 internal irqs */
586
587 switch (irqno) {
588 /* deal with the special IRQs (cascaded) */
589
590 case IRQ_EINT4t7:
591 case IRQ_EINT8t23:
592 case IRQ_UART0:
593 case IRQ_UART1:
594 case IRQ_UART2:
595 case IRQ_ADCPARENT:
596 irq_set_chip_and_handler(irqno, &s3c_irq_level_chip,
597 handle_level_irq);
598 break;
599
600 case IRQ_RESERVED6:
601 case IRQ_RESERVED24:
602 /* no IRQ here */
603 break;
604
605 default:
606 //irqdbf("registering irq %d (s3c irq)\n", irqno);
607 irq_set_chip_and_handler(irqno, &s3c_irq_chip,
608 handle_edge_irq);
609 set_irq_flags(irqno, IRQF_VALID);
610 }
611 }
612
613 /* setup the cascade irq handlers */
614
615 irq_set_chained_handler(IRQ_EINT4t7, s3c_irq_demux_extint4t7);
616 irq_set_chained_handler(IRQ_EINT8t23, s3c_irq_demux_extint8);
617
618 irq_set_chained_handler(IRQ_UART0, s3c_irq_demux_uart0);
619 irq_set_chained_handler(IRQ_UART1, s3c_irq_demux_uart1);
620 irq_set_chained_handler(IRQ_UART2, s3c_irq_demux_uart2);
621 irq_set_chained_handler(IRQ_ADCPARENT, s3c_irq_demux_adc);
622
623 /* external interrupts */
624
625 for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
626 irqdbf("registering irq %d (ext int)\n", irqno);
627 irq_set_chip_and_handler(irqno, &s3c_irq_eint0t4,
628 handle_edge_irq);
629 set_irq_flags(irqno, IRQF_VALID);
630 }
631
632 for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) {
633 irqdbf("registering irq %d (extended s3c irq)\n", irqno);
634 irq_set_chip_and_handler(irqno, &s3c_irqext_chip,
635 handle_edge_irq);
636 set_irq_flags(irqno, IRQF_VALID);
637 }
638
639 /* register the uart interrupts */
640
641 irqdbf("s3c2410: registering external interrupts\n");
642
643 for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) {
644 irqdbf("registering irq %d (s3c uart0 irq)\n", irqno);
645 irq_set_chip_and_handler(irqno, &s3c_irq_uart0,
646 handle_level_irq);
647 set_irq_flags(irqno, IRQF_VALID);
648 }
649
650 for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) {
651 irqdbf("registering irq %d (s3c uart1 irq)\n", irqno);
652 irq_set_chip_and_handler(irqno, &s3c_irq_uart1,
653 handle_level_irq);
654 set_irq_flags(irqno, IRQF_VALID);
655 }
656
657 for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) {
658 irqdbf("registering irq %d (s3c uart2 irq)\n", irqno);
659 irq_set_chip_and_handler(irqno, &s3c_irq_uart2,
660 handle_level_irq);
661 set_irq_flags(irqno, IRQF_VALID);
662 }
663
664 for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) {
665 irqdbf("registering irq %d (s3c adc irq)\n", irqno);
666 irq_set_chip_and_handler(irqno, &s3c_irq_adc, handle_edge_irq);
667 set_irq_flags(irqno, IRQF_VALID);
668 }
669
670 irqdbf("s3c2410: registered interrupt handlers\n");
671}
672
673struct syscore_ops s3c24xx_irq_syscore_ops = {
674 .suspend = s3c24xx_irq_suspend,
675 .resume = s3c24xx_irq_resume,
676};