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1/*
2 * Copyright (C) 2008 Nokia Corporation
3 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#ifndef __OMAP_OMAPDSS_H
19#define __OMAP_OMAPDSS_H
20
21#include <linux/list.h>
22#include <linux/kobject.h>
23#include <linux/device.h>
24
25#define DISPC_IRQ_FRAMEDONE (1 << 0)
26#define DISPC_IRQ_VSYNC (1 << 1)
27#define DISPC_IRQ_EVSYNC_EVEN (1 << 2)
28#define DISPC_IRQ_EVSYNC_ODD (1 << 3)
29#define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4)
30#define DISPC_IRQ_PROG_LINE_NUM (1 << 5)
31#define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6)
32#define DISPC_IRQ_GFX_END_WIN (1 << 7)
33#define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8)
34#define DISPC_IRQ_OCP_ERR (1 << 9)
35#define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10)
36#define DISPC_IRQ_VID1_END_WIN (1 << 11)
37#define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12)
38#define DISPC_IRQ_VID2_END_WIN (1 << 13)
39#define DISPC_IRQ_SYNC_LOST (1 << 14)
40#define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15)
41#define DISPC_IRQ_WAKEUP (1 << 16)
42#define DISPC_IRQ_SYNC_LOST2 (1 << 17)
43#define DISPC_IRQ_VSYNC2 (1 << 18)
44#define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21)
45#define DISPC_IRQ_FRAMEDONE2 (1 << 22)
46
47struct omap_dss_device;
48struct omap_overlay_manager;
49
50enum omap_display_type {
51 OMAP_DISPLAY_TYPE_NONE = 0,
52 OMAP_DISPLAY_TYPE_DPI = 1 << 0,
53 OMAP_DISPLAY_TYPE_DBI = 1 << 1,
54 OMAP_DISPLAY_TYPE_SDI = 1 << 2,
55 OMAP_DISPLAY_TYPE_DSI = 1 << 3,
56 OMAP_DISPLAY_TYPE_VENC = 1 << 4,
57 OMAP_DISPLAY_TYPE_HDMI = 1 << 5,
58};
59
60enum omap_plane {
61 OMAP_DSS_GFX = 0,
62 OMAP_DSS_VIDEO1 = 1,
63 OMAP_DSS_VIDEO2 = 2
64};
65
66enum omap_channel {
67 OMAP_DSS_CHANNEL_LCD = 0,
68 OMAP_DSS_CHANNEL_DIGIT = 1,
69 OMAP_DSS_CHANNEL_LCD2 = 2,
70};
71
72enum omap_color_mode {
73 OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */
74 OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */
75 OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */
76 OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */
77 OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */
78 OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */
79 OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */
80 OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */
81 OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */
82 OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */
83 OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */
84 OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */
85 OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */
86 OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */
87 OMAP_DSS_COLOR_NV12 = 1 << 14, /* NV12 format: YUV 4:2:0 */
88 OMAP_DSS_COLOR_RGBA16 = 1 << 15, /* RGBA16 - 4444 */
89 OMAP_DSS_COLOR_RGBX16 = 1 << 16, /* RGBx16 - 4444 */
90 OMAP_DSS_COLOR_ARGB16_1555 = 1 << 17, /* ARGB16 - 1555 */
91 OMAP_DSS_COLOR_XRGB16_1555 = 1 << 18, /* xRGB16 - 1555 */
92};
93
94enum omap_lcd_display_type {
95 OMAP_DSS_LCD_DISPLAY_STN,
96 OMAP_DSS_LCD_DISPLAY_TFT,
97};
98
99enum omap_dss_load_mode {
100 OMAP_DSS_LOAD_CLUT_AND_FRAME = 0,
101 OMAP_DSS_LOAD_CLUT_ONLY = 1,
102 OMAP_DSS_LOAD_FRAME_ONLY = 2,
103 OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3,
104};
105
106enum omap_dss_trans_key_type {
107 OMAP_DSS_COLOR_KEY_GFX_DST = 0,
108 OMAP_DSS_COLOR_KEY_VID_SRC = 1,
109};
110
111enum omap_rfbi_te_mode {
112 OMAP_DSS_RFBI_TE_MODE_1 = 1,
113 OMAP_DSS_RFBI_TE_MODE_2 = 2,
114};
115
116enum omap_panel_config {
117 OMAP_DSS_LCD_IVS = 1<<0,
118 OMAP_DSS_LCD_IHS = 1<<1,
119 OMAP_DSS_LCD_IPC = 1<<2,
120 OMAP_DSS_LCD_IEO = 1<<3,
121 OMAP_DSS_LCD_RF = 1<<4,
122 OMAP_DSS_LCD_ONOFF = 1<<5,
123
124 OMAP_DSS_LCD_TFT = 1<<20,
125};
126
127enum omap_dss_venc_type {
128 OMAP_DSS_VENC_TYPE_COMPOSITE,
129 OMAP_DSS_VENC_TYPE_SVIDEO,
130};
131
132enum omap_display_caps {
133 OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0,
134 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1,
135};
136
137enum omap_dss_display_state {
138 OMAP_DSS_DISPLAY_DISABLED = 0,
139 OMAP_DSS_DISPLAY_ACTIVE,
140 OMAP_DSS_DISPLAY_SUSPENDED,
141};
142
143/* XXX perhaps this should be removed */
144enum omap_dss_overlay_managers {
145 OMAP_DSS_OVL_MGR_LCD,
146 OMAP_DSS_OVL_MGR_TV,
147 OMAP_DSS_OVL_MGR_LCD2,
148};
149
150enum omap_dss_rotation_type {
151 OMAP_DSS_ROT_DMA = 0,
152 OMAP_DSS_ROT_VRFB = 1,
153};
154
155/* clockwise rotation angle */
156enum omap_dss_rotation_angle {
157 OMAP_DSS_ROT_0 = 0,
158 OMAP_DSS_ROT_90 = 1,
159 OMAP_DSS_ROT_180 = 2,
160 OMAP_DSS_ROT_270 = 3,
161};
162
163enum omap_overlay_caps {
164 OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
165 OMAP_DSS_OVL_CAP_DISPC = 1 << 1,
166};
167
168enum omap_overlay_manager_caps {
169 OMAP_DSS_OVL_MGR_CAP_DISPC = 1 << 0,
170};
171
172enum omap_dss_clk_source {
173 OMAP_DSS_CLK_SRC_FCK = 0, /* OMAP2/3: DSS1_ALWON_FCLK
174 * OMAP4: DSS_FCLK */
175 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, /* OMAP3: DSI1_PLL_FCLK
176 * OMAP4: PLL1_CLK1 */
177 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, /* OMAP3: DSI2_PLL_FCLK
178 * OMAP4: PLL1_CLK2 */
179 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC, /* OMAP4: PLL2_CLK1 */
180 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI, /* OMAP4: PLL2_CLK2 */
181};
182
183/* RFBI */
184
185struct rfbi_timings {
186 int cs_on_time;
187 int cs_off_time;
188 int we_on_time;
189 int we_off_time;
190 int re_on_time;
191 int re_off_time;
192 int we_cycle_time;
193 int re_cycle_time;
194 int cs_pulse_width;
195 int access_time;
196
197 int clk_div;
198
199 u32 tim[5]; /* set by rfbi_convert_timings() */
200
201 int converted;
202};
203
204void omap_rfbi_write_command(const void *buf, u32 len);
205void omap_rfbi_read_data(void *buf, u32 len);
206void omap_rfbi_write_data(const void *buf, u32 len);
207void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
208 u16 x, u16 y,
209 u16 w, u16 h);
210int omap_rfbi_enable_te(bool enable, unsigned line);
211int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
212 unsigned hs_pulse_time, unsigned vs_pulse_time,
213 int hs_pol_inv, int vs_pol_inv, int extif_div);
214void rfbi_bus_lock(void);
215void rfbi_bus_unlock(void);
216
217/* DSI */
218void dsi_bus_lock(struct omap_dss_device *dssdev);
219void dsi_bus_unlock(struct omap_dss_device *dssdev);
220int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
221 int len);
222int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel,
223 u8 dcs_cmd);
224int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
225 u8 param);
226int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
227 u8 *data, int len);
228int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
229 u8 *buf, int buflen);
230int dsi_vc_dcs_read_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
231 u8 *data);
232int dsi_vc_dcs_read_2(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
233 u8 *data1, u8 *data2);
234int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
235 u16 len);
236int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel);
237int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel);
238
239/* Board specific data */
240struct omap_dss_board_info {
241 int (*get_context_loss_count)(struct device *dev);
242 int num_devices;
243 struct omap_dss_device **devices;
244 struct omap_dss_device *default_device;
245 void (*dsi_mux_pads)(bool enable);
246};
247
248#if defined(CONFIG_OMAP2_DSS_MODULE) || defined(CONFIG_OMAP2_DSS)
249/* Init with the board info */
250extern int omap_display_init(struct omap_dss_board_info *board_data);
251#else
252static inline int omap_display_init(struct omap_dss_board_info *board_data)
253{
254 return 0;
255}
256#endif
257
258struct omap_display_platform_data {
259 struct omap_dss_board_info *board_data;
260 /* TODO: Additional members to be added when PM is considered */
261};
262
263struct omap_video_timings {
264 /* Unit: pixels */
265 u16 x_res;
266 /* Unit: pixels */
267 u16 y_res;
268 /* Unit: KHz */
269 u32 pixel_clock;
270 /* Unit: pixel clocks */
271 u16 hsw; /* Horizontal synchronization pulse width */
272 /* Unit: pixel clocks */
273 u16 hfp; /* Horizontal front porch */
274 /* Unit: pixel clocks */
275 u16 hbp; /* Horizontal back porch */
276 /* Unit: line clocks */
277 u16 vsw; /* Vertical synchronization pulse width */
278 /* Unit: line clocks */
279 u16 vfp; /* Vertical front porch */
280 /* Unit: line clocks */
281 u16 vbp; /* Vertical back porch */
282};
283
284#ifdef CONFIG_OMAP2_DSS_VENC
285/* Hardcoded timings for tv modes. Venc only uses these to
286 * identify the mode, and does not actually use the configs
287 * itself. However, the configs should be something that
288 * a normal monitor can also show */
289extern const struct omap_video_timings omap_dss_pal_timings;
290extern const struct omap_video_timings omap_dss_ntsc_timings;
291#endif
292
293struct omap_dss_cpr_coefs {
294 s16 rr, rg, rb;
295 s16 gr, gg, gb;
296 s16 br, bg, bb;
297};
298
299struct omap_overlay_info {
300 bool enabled;
301
302 u32 paddr;
303 void __iomem *vaddr;
304 u32 p_uv_addr; /* for NV12 format */
305 u16 screen_width;
306 u16 width;
307 u16 height;
308 enum omap_color_mode color_mode;
309 u8 rotation;
310 enum omap_dss_rotation_type rotation_type;
311 bool mirror;
312
313 u16 pos_x;
314 u16 pos_y;
315 u16 out_width; /* if 0, out_width == width */
316 u16 out_height; /* if 0, out_height == height */
317 u8 global_alpha;
318 u8 pre_mult_alpha;
319};
320
321struct omap_overlay {
322 struct kobject kobj;
323 struct list_head list;
324
325 /* static fields */
326 const char *name;
327 int id;
328 enum omap_color_mode supported_modes;
329 enum omap_overlay_caps caps;
330
331 /* dynamic fields */
332 struct omap_overlay_manager *manager;
333 struct omap_overlay_info info;
334
335 /* if true, info has been changed, but not applied() yet */
336 bool info_dirty;
337
338 int (*set_manager)(struct omap_overlay *ovl,
339 struct omap_overlay_manager *mgr);
340 int (*unset_manager)(struct omap_overlay *ovl);
341
342 int (*set_overlay_info)(struct omap_overlay *ovl,
343 struct omap_overlay_info *info);
344 void (*get_overlay_info)(struct omap_overlay *ovl,
345 struct omap_overlay_info *info);
346
347 int (*wait_for_go)(struct omap_overlay *ovl);
348};
349
350struct omap_overlay_manager_info {
351 u32 default_color;
352
353 enum omap_dss_trans_key_type trans_key_type;
354 u32 trans_key;
355 bool trans_enabled;
356
357 bool alpha_enabled;
358
359 bool cpr_enable;
360 struct omap_dss_cpr_coefs cpr_coefs;
361};
362
363struct omap_overlay_manager {
364 struct kobject kobj;
365 struct list_head list;
366
367 /* static fields */
368 const char *name;
369 int id;
370 enum omap_overlay_manager_caps caps;
371 int num_overlays;
372 struct omap_overlay **overlays;
373 enum omap_display_type supported_displays;
374
375 /* dynamic fields */
376 struct omap_dss_device *device;
377 struct omap_overlay_manager_info info;
378
379 bool device_changed;
380 /* if true, info has been changed but not applied() yet */
381 bool info_dirty;
382
383 int (*set_device)(struct omap_overlay_manager *mgr,
384 struct omap_dss_device *dssdev);
385 int (*unset_device)(struct omap_overlay_manager *mgr);
386
387 int (*set_manager_info)(struct omap_overlay_manager *mgr,
388 struct omap_overlay_manager_info *info);
389 void (*get_manager_info)(struct omap_overlay_manager *mgr,
390 struct omap_overlay_manager_info *info);
391
392 int (*apply)(struct omap_overlay_manager *mgr);
393 int (*wait_for_go)(struct omap_overlay_manager *mgr);
394 int (*wait_for_vsync)(struct omap_overlay_manager *mgr);
395
396 int (*enable)(struct omap_overlay_manager *mgr);
397 int (*disable)(struct omap_overlay_manager *mgr);
398};
399
400struct omap_dss_device {
401 struct device dev;
402
403 enum omap_display_type type;
404
405 enum omap_channel channel;
406
407 union {
408 struct {
409 u8 data_lines;
410 } dpi;
411
412 struct {
413 u8 channel;
414 u8 data_lines;
415 } rfbi;
416
417 struct {
418 u8 datapairs;
419 } sdi;
420
421 struct {
422 u8 clk_lane;
423 u8 clk_pol;
424 u8 data1_lane;
425 u8 data1_pol;
426 u8 data2_lane;
427 u8 data2_pol;
428 u8 data3_lane;
429 u8 data3_pol;
430 u8 data4_lane;
431 u8 data4_pol;
432
433 int module;
434
435 bool ext_te;
436 u8 ext_te_gpio;
437 } dsi;
438
439 struct {
440 enum omap_dss_venc_type type;
441 bool invert_polarity;
442 } venc;
443 } phy;
444
445 struct {
446 struct {
447 struct {
448 u16 lck_div;
449 u16 pck_div;
450 enum omap_dss_clk_source lcd_clk_src;
451 } channel;
452
453 enum omap_dss_clk_source dispc_fclk_src;
454 } dispc;
455
456 struct {
457 u16 regn;
458 u16 regm;
459 u16 regm_dispc;
460 u16 regm_dsi;
461
462 u16 lp_clk_div;
463 enum omap_dss_clk_source dsi_fclk_src;
464 } dsi;
465
466 struct {
467 u16 regn;
468 u16 regm2;
469 } hdmi;
470 } clocks;
471
472 struct {
473 struct omap_video_timings timings;
474
475 int acbi; /* ac-bias pin transitions per interrupt */
476 /* Unit: line clocks */
477 int acb; /* ac-bias pin frequency */
478
479 enum omap_panel_config config;
480 } panel;
481
482 struct {
483 u8 pixel_size;
484 struct rfbi_timings rfbi_timings;
485 } ctrl;
486
487 int reset_gpio;
488
489 int max_backlight_level;
490
491 const char *name;
492
493 /* used to match device to driver */
494 const char *driver_name;
495
496 void *data;
497
498 struct omap_dss_driver *driver;
499
500 /* helper variable for driver suspend/resume */
501 bool activate_after_resume;
502
503 enum omap_display_caps caps;
504
505 struct omap_overlay_manager *manager;
506
507 enum omap_dss_display_state state;
508
509 /* platform specific */
510 int (*platform_enable)(struct omap_dss_device *dssdev);
511 void (*platform_disable)(struct omap_dss_device *dssdev);
512 int (*set_backlight)(struct omap_dss_device *dssdev, int level);
513 int (*get_backlight)(struct omap_dss_device *dssdev);
514};
515
516struct omap_dss_driver {
517 struct device_driver driver;
518
519 int (*probe)(struct omap_dss_device *);
520 void (*remove)(struct omap_dss_device *);
521
522 int (*enable)(struct omap_dss_device *display);
523 void (*disable)(struct omap_dss_device *display);
524 int (*suspend)(struct omap_dss_device *display);
525 int (*resume)(struct omap_dss_device *display);
526 int (*run_test)(struct omap_dss_device *display, int test);
527
528 int (*update)(struct omap_dss_device *dssdev,
529 u16 x, u16 y, u16 w, u16 h);
530 int (*sync)(struct omap_dss_device *dssdev);
531
532 int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
533 int (*get_te)(struct omap_dss_device *dssdev);
534
535 u8 (*get_rotate)(struct omap_dss_device *dssdev);
536 int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
537
538 bool (*get_mirror)(struct omap_dss_device *dssdev);
539 int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
540
541 int (*memory_read)(struct omap_dss_device *dssdev,
542 void *buf, size_t size,
543 u16 x, u16 y, u16 w, u16 h);
544
545 void (*get_resolution)(struct omap_dss_device *dssdev,
546 u16 *xres, u16 *yres);
547 void (*get_dimensions)(struct omap_dss_device *dssdev,
548 u32 *width, u32 *height);
549 int (*get_recommended_bpp)(struct omap_dss_device *dssdev);
550
551 int (*check_timings)(struct omap_dss_device *dssdev,
552 struct omap_video_timings *timings);
553 void (*set_timings)(struct omap_dss_device *dssdev,
554 struct omap_video_timings *timings);
555 void (*get_timings)(struct omap_dss_device *dssdev,
556 struct omap_video_timings *timings);
557
558 int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
559 u32 (*get_wss)(struct omap_dss_device *dssdev);
560};
561
562int omap_dss_register_driver(struct omap_dss_driver *);
563void omap_dss_unregister_driver(struct omap_dss_driver *);
564
565void omap_dss_get_device(struct omap_dss_device *dssdev);
566void omap_dss_put_device(struct omap_dss_device *dssdev);
567#define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
568struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
569struct omap_dss_device *omap_dss_find_device(void *data,
570 int (*match)(struct omap_dss_device *dssdev, void *data));
571
572int omap_dss_start_device(struct omap_dss_device *dssdev);
573void omap_dss_stop_device(struct omap_dss_device *dssdev);
574
575int omap_dss_get_num_overlay_managers(void);
576struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
577
578int omap_dss_get_num_overlays(void);
579struct omap_overlay *omap_dss_get_overlay(int num);
580
581void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
582 u16 *xres, u16 *yres);
583int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev);
584
585typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
586int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
587int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
588
589int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout);
590int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
591 unsigned long timeout);
592
593#define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver)
594#define to_dss_device(x) container_of((x), struct omap_dss_device, dev)
595
596void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
597 bool enable);
598int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable);
599
600int omap_dsi_prepare_update(struct omap_dss_device *dssdev,
601 u16 *x, u16 *y, u16 *w, u16 *h,
602 bool enlarge_update_area);
603int omap_dsi_update(struct omap_dss_device *dssdev,
604 int channel,
605 u16 x, u16 y, u16 w, u16 h,
606 void (*callback)(int, void *), void *data);
607int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel);
608int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id);
609void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel);
610
611int omapdss_dsi_display_enable(struct omap_dss_device *dssdev);
612void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
613 bool disconnect_lanes, bool enter_ulps);
614
615int omapdss_dpi_display_enable(struct omap_dss_device *dssdev);
616void omapdss_dpi_display_disable(struct omap_dss_device *dssdev);
617void dpi_set_timings(struct omap_dss_device *dssdev,
618 struct omap_video_timings *timings);
619int dpi_check_timings(struct omap_dss_device *dssdev,
620 struct omap_video_timings *timings);
621
622int omapdss_sdi_display_enable(struct omap_dss_device *dssdev);
623void omapdss_sdi_display_disable(struct omap_dss_device *dssdev);
624
625int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev);
626void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev);
627int omap_rfbi_prepare_update(struct omap_dss_device *dssdev,
628 u16 *x, u16 *y, u16 *w, u16 *h);
629int omap_rfbi_update(struct omap_dss_device *dssdev,
630 u16 x, u16 y, u16 w, u16 h,
631 void (*callback)(void *), void *data);
632int omap_rfbi_configure(struct omap_dss_device *dssdev, int pixel_size,
633 int data_lines);
634
635#endif
1/*
2 * Copyright (C) 2008 Nokia Corporation
3 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#ifndef __OMAP_OMAPDSS_H
19#define __OMAP_OMAPDSS_H
20
21#include <linux/list.h>
22#include <linux/kobject.h>
23#include <linux/device.h>
24#include <linux/interrupt.h>
25
26#include <video/videomode.h>
27
28#define DISPC_IRQ_FRAMEDONE (1 << 0)
29#define DISPC_IRQ_VSYNC (1 << 1)
30#define DISPC_IRQ_EVSYNC_EVEN (1 << 2)
31#define DISPC_IRQ_EVSYNC_ODD (1 << 3)
32#define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4)
33#define DISPC_IRQ_PROG_LINE_NUM (1 << 5)
34#define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6)
35#define DISPC_IRQ_GFX_END_WIN (1 << 7)
36#define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8)
37#define DISPC_IRQ_OCP_ERR (1 << 9)
38#define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10)
39#define DISPC_IRQ_VID1_END_WIN (1 << 11)
40#define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12)
41#define DISPC_IRQ_VID2_END_WIN (1 << 13)
42#define DISPC_IRQ_SYNC_LOST (1 << 14)
43#define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15)
44#define DISPC_IRQ_WAKEUP (1 << 16)
45#define DISPC_IRQ_SYNC_LOST2 (1 << 17)
46#define DISPC_IRQ_VSYNC2 (1 << 18)
47#define DISPC_IRQ_VID3_END_WIN (1 << 19)
48#define DISPC_IRQ_VID3_FIFO_UNDERFLOW (1 << 20)
49#define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21)
50#define DISPC_IRQ_FRAMEDONE2 (1 << 22)
51#define DISPC_IRQ_FRAMEDONEWB (1 << 23)
52#define DISPC_IRQ_FRAMEDONETV (1 << 24)
53#define DISPC_IRQ_WBBUFFEROVERFLOW (1 << 25)
54#define DISPC_IRQ_SYNC_LOST3 (1 << 27)
55#define DISPC_IRQ_VSYNC3 (1 << 28)
56#define DISPC_IRQ_ACBIAS_COUNT_STAT3 (1 << 29)
57#define DISPC_IRQ_FRAMEDONE3 (1 << 30)
58
59struct omap_dss_device;
60struct omap_overlay_manager;
61struct dss_lcd_mgr_config;
62struct snd_aes_iec958;
63struct snd_cea_861_aud_if;
64
65enum omap_display_type {
66 OMAP_DISPLAY_TYPE_NONE = 0,
67 OMAP_DISPLAY_TYPE_DPI = 1 << 0,
68 OMAP_DISPLAY_TYPE_DBI = 1 << 1,
69 OMAP_DISPLAY_TYPE_SDI = 1 << 2,
70 OMAP_DISPLAY_TYPE_DSI = 1 << 3,
71 OMAP_DISPLAY_TYPE_VENC = 1 << 4,
72 OMAP_DISPLAY_TYPE_HDMI = 1 << 5,
73 OMAP_DISPLAY_TYPE_DVI = 1 << 6,
74};
75
76enum omap_plane {
77 OMAP_DSS_GFX = 0,
78 OMAP_DSS_VIDEO1 = 1,
79 OMAP_DSS_VIDEO2 = 2,
80 OMAP_DSS_VIDEO3 = 3,
81 OMAP_DSS_WB = 4,
82};
83
84enum omap_channel {
85 OMAP_DSS_CHANNEL_LCD = 0,
86 OMAP_DSS_CHANNEL_DIGIT = 1,
87 OMAP_DSS_CHANNEL_LCD2 = 2,
88 OMAP_DSS_CHANNEL_LCD3 = 3,
89};
90
91enum omap_color_mode {
92 OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */
93 OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */
94 OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */
95 OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */
96 OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */
97 OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */
98 OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */
99 OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */
100 OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */
101 OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */
102 OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */
103 OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */
104 OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */
105 OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */
106 OMAP_DSS_COLOR_NV12 = 1 << 14, /* NV12 format: YUV 4:2:0 */
107 OMAP_DSS_COLOR_RGBA16 = 1 << 15, /* RGBA16 - 4444 */
108 OMAP_DSS_COLOR_RGBX16 = 1 << 16, /* RGBx16 - 4444 */
109 OMAP_DSS_COLOR_ARGB16_1555 = 1 << 17, /* ARGB16 - 1555 */
110 OMAP_DSS_COLOR_XRGB16_1555 = 1 << 18, /* xRGB16 - 1555 */
111};
112
113enum omap_dss_load_mode {
114 OMAP_DSS_LOAD_CLUT_AND_FRAME = 0,
115 OMAP_DSS_LOAD_CLUT_ONLY = 1,
116 OMAP_DSS_LOAD_FRAME_ONLY = 2,
117 OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3,
118};
119
120enum omap_dss_trans_key_type {
121 OMAP_DSS_COLOR_KEY_GFX_DST = 0,
122 OMAP_DSS_COLOR_KEY_VID_SRC = 1,
123};
124
125enum omap_rfbi_te_mode {
126 OMAP_DSS_RFBI_TE_MODE_1 = 1,
127 OMAP_DSS_RFBI_TE_MODE_2 = 2,
128};
129
130enum omap_dss_signal_level {
131 OMAPDSS_SIG_ACTIVE_HIGH = 0,
132 OMAPDSS_SIG_ACTIVE_LOW = 1,
133};
134
135enum omap_dss_signal_edge {
136 OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
137 OMAPDSS_DRIVE_SIG_RISING_EDGE,
138 OMAPDSS_DRIVE_SIG_FALLING_EDGE,
139};
140
141enum omap_dss_venc_type {
142 OMAP_DSS_VENC_TYPE_COMPOSITE,
143 OMAP_DSS_VENC_TYPE_SVIDEO,
144};
145
146enum omap_dss_dsi_pixel_format {
147 OMAP_DSS_DSI_FMT_RGB888,
148 OMAP_DSS_DSI_FMT_RGB666,
149 OMAP_DSS_DSI_FMT_RGB666_PACKED,
150 OMAP_DSS_DSI_FMT_RGB565,
151};
152
153enum omap_dss_dsi_mode {
154 OMAP_DSS_DSI_CMD_MODE = 0,
155 OMAP_DSS_DSI_VIDEO_MODE,
156};
157
158enum omap_display_caps {
159 OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0,
160 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1,
161};
162
163enum omap_dss_display_state {
164 OMAP_DSS_DISPLAY_DISABLED = 0,
165 OMAP_DSS_DISPLAY_ACTIVE,
166};
167
168enum omap_dss_audio_state {
169 OMAP_DSS_AUDIO_DISABLED = 0,
170 OMAP_DSS_AUDIO_ENABLED,
171 OMAP_DSS_AUDIO_CONFIGURED,
172 OMAP_DSS_AUDIO_PLAYING,
173};
174
175struct omap_dss_audio {
176 struct snd_aes_iec958 *iec;
177 struct snd_cea_861_aud_if *cea;
178};
179
180enum omap_dss_rotation_type {
181 OMAP_DSS_ROT_DMA = 1 << 0,
182 OMAP_DSS_ROT_VRFB = 1 << 1,
183 OMAP_DSS_ROT_TILER = 1 << 2,
184};
185
186/* clockwise rotation angle */
187enum omap_dss_rotation_angle {
188 OMAP_DSS_ROT_0 = 0,
189 OMAP_DSS_ROT_90 = 1,
190 OMAP_DSS_ROT_180 = 2,
191 OMAP_DSS_ROT_270 = 3,
192};
193
194enum omap_overlay_caps {
195 OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
196 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA = 1 << 1,
197 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA = 1 << 2,
198 OMAP_DSS_OVL_CAP_ZORDER = 1 << 3,
199 OMAP_DSS_OVL_CAP_POS = 1 << 4,
200 OMAP_DSS_OVL_CAP_REPLICATION = 1 << 5,
201};
202
203enum omap_overlay_manager_caps {
204 OMAP_DSS_DUMMY_VALUE, /* add a dummy value to prevent compiler error */
205};
206
207enum omap_dss_clk_source {
208 OMAP_DSS_CLK_SRC_FCK = 0, /* OMAP2/3: DSS1_ALWON_FCLK
209 * OMAP4: DSS_FCLK */
210 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, /* OMAP3: DSI1_PLL_FCLK
211 * OMAP4: PLL1_CLK1 */
212 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, /* OMAP3: DSI2_PLL_FCLK
213 * OMAP4: PLL1_CLK2 */
214 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC, /* OMAP4: PLL2_CLK1 */
215 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI, /* OMAP4: PLL2_CLK2 */
216};
217
218enum omap_hdmi_flags {
219 OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP = 1 << 0,
220};
221
222enum omap_dss_output_id {
223 OMAP_DSS_OUTPUT_DPI = 1 << 0,
224 OMAP_DSS_OUTPUT_DBI = 1 << 1,
225 OMAP_DSS_OUTPUT_SDI = 1 << 2,
226 OMAP_DSS_OUTPUT_DSI1 = 1 << 3,
227 OMAP_DSS_OUTPUT_DSI2 = 1 << 4,
228 OMAP_DSS_OUTPUT_VENC = 1 << 5,
229 OMAP_DSS_OUTPUT_HDMI = 1 << 6,
230};
231
232/* RFBI */
233
234struct rfbi_timings {
235 int cs_on_time;
236 int cs_off_time;
237 int we_on_time;
238 int we_off_time;
239 int re_on_time;
240 int re_off_time;
241 int we_cycle_time;
242 int re_cycle_time;
243 int cs_pulse_width;
244 int access_time;
245
246 int clk_div;
247
248 u32 tim[5]; /* set by rfbi_convert_timings() */
249
250 int converted;
251};
252
253/* DSI */
254
255enum omap_dss_dsi_trans_mode {
256 /* Sync Pulses: both sync start and end packets sent */
257 OMAP_DSS_DSI_PULSE_MODE,
258 /* Sync Events: only sync start packets sent */
259 OMAP_DSS_DSI_EVENT_MODE,
260 /* Burst: only sync start packets sent, pixels are time compressed */
261 OMAP_DSS_DSI_BURST_MODE,
262};
263
264struct omap_dss_dsi_videomode_timings {
265 unsigned long hsclk;
266
267 unsigned ndl;
268 unsigned bitspp;
269
270 /* pixels */
271 u16 hact;
272 /* lines */
273 u16 vact;
274
275 /* DSI video mode blanking data */
276 /* Unit: byte clock cycles */
277 u16 hss;
278 u16 hsa;
279 u16 hse;
280 u16 hfp;
281 u16 hbp;
282 /* Unit: line clocks */
283 u16 vsa;
284 u16 vfp;
285 u16 vbp;
286
287 /* DSI blanking modes */
288 int blanking_mode;
289 int hsa_blanking_mode;
290 int hbp_blanking_mode;
291 int hfp_blanking_mode;
292
293 enum omap_dss_dsi_trans_mode trans_mode;
294
295 bool ddr_clk_always_on;
296 int window_sync;
297};
298
299struct omap_dss_dsi_config {
300 enum omap_dss_dsi_mode mode;
301 enum omap_dss_dsi_pixel_format pixel_format;
302 const struct omap_video_timings *timings;
303
304 unsigned long hs_clk_min, hs_clk_max;
305 unsigned long lp_clk_min, lp_clk_max;
306
307 bool ddr_clk_always_on;
308 enum omap_dss_dsi_trans_mode trans_mode;
309};
310
311enum omapdss_version {
312 OMAPDSS_VER_UNKNOWN = 0,
313 OMAPDSS_VER_OMAP24xx,
314 OMAPDSS_VER_OMAP34xx_ES1, /* OMAP3430 ES1.0, 2.0 */
315 OMAPDSS_VER_OMAP34xx_ES3, /* OMAP3430 ES3.0+ */
316 OMAPDSS_VER_OMAP3630,
317 OMAPDSS_VER_AM35xx,
318 OMAPDSS_VER_OMAP4430_ES1, /* OMAP4430 ES1.0 */
319 OMAPDSS_VER_OMAP4430_ES2, /* OMAP4430 ES2.0, 2.1, 2.2 */
320 OMAPDSS_VER_OMAP4, /* All other OMAP4s */
321 OMAPDSS_VER_OMAP5,
322};
323
324/* Board specific data */
325struct omap_dss_board_info {
326 int num_devices;
327 struct omap_dss_device **devices;
328 struct omap_dss_device *default_device;
329 const char *default_display_name;
330 int (*dsi_enable_pads)(int dsi_id, unsigned lane_mask);
331 void (*dsi_disable_pads)(int dsi_id, unsigned lane_mask);
332 int (*set_min_bus_tput)(struct device *dev, unsigned long r);
333 enum omapdss_version version;
334};
335
336/* Init with the board info */
337extern int omap_display_init(struct omap_dss_board_info *board_data);
338/* HDMI mux init*/
339extern int omap_hdmi_init(enum omap_hdmi_flags flags);
340
341struct omap_video_timings {
342 /* Unit: pixels */
343 u16 x_res;
344 /* Unit: pixels */
345 u16 y_res;
346 /* Unit: Hz */
347 u32 pixelclock;
348 /* Unit: pixel clocks */
349 u16 hsw; /* Horizontal synchronization pulse width */
350 /* Unit: pixel clocks */
351 u16 hfp; /* Horizontal front porch */
352 /* Unit: pixel clocks */
353 u16 hbp; /* Horizontal back porch */
354 /* Unit: line clocks */
355 u16 vsw; /* Vertical synchronization pulse width */
356 /* Unit: line clocks */
357 u16 vfp; /* Vertical front porch */
358 /* Unit: line clocks */
359 u16 vbp; /* Vertical back porch */
360
361 /* Vsync logic level */
362 enum omap_dss_signal_level vsync_level;
363 /* Hsync logic level */
364 enum omap_dss_signal_level hsync_level;
365 /* Interlaced or Progressive timings */
366 bool interlace;
367 /* Pixel clock edge to drive LCD data */
368 enum omap_dss_signal_edge data_pclk_edge;
369 /* Data enable logic level */
370 enum omap_dss_signal_level de_level;
371 /* Pixel clock edges to drive HSYNC and VSYNC signals */
372 enum omap_dss_signal_edge sync_pclk_edge;
373};
374
375#ifdef CONFIG_OMAP2_DSS_VENC
376/* Hardcoded timings for tv modes. Venc only uses these to
377 * identify the mode, and does not actually use the configs
378 * itself. However, the configs should be something that
379 * a normal monitor can also show */
380extern const struct omap_video_timings omap_dss_pal_timings;
381extern const struct omap_video_timings omap_dss_ntsc_timings;
382#endif
383
384struct omap_dss_cpr_coefs {
385 s16 rr, rg, rb;
386 s16 gr, gg, gb;
387 s16 br, bg, bb;
388};
389
390struct omap_overlay_info {
391 u32 paddr;
392 u32 p_uv_addr; /* for NV12 format */
393 u16 screen_width;
394 u16 width;
395 u16 height;
396 enum omap_color_mode color_mode;
397 u8 rotation;
398 enum omap_dss_rotation_type rotation_type;
399 bool mirror;
400
401 u16 pos_x;
402 u16 pos_y;
403 u16 out_width; /* if 0, out_width == width */
404 u16 out_height; /* if 0, out_height == height */
405 u8 global_alpha;
406 u8 pre_mult_alpha;
407 u8 zorder;
408};
409
410struct omap_overlay {
411 struct kobject kobj;
412 struct list_head list;
413
414 /* static fields */
415 const char *name;
416 enum omap_plane id;
417 enum omap_color_mode supported_modes;
418 enum omap_overlay_caps caps;
419
420 /* dynamic fields */
421 struct omap_overlay_manager *manager;
422
423 /*
424 * The following functions do not block:
425 *
426 * is_enabled
427 * set_overlay_info
428 * get_overlay_info
429 *
430 * The rest of the functions may block and cannot be called from
431 * interrupt context
432 */
433
434 int (*enable)(struct omap_overlay *ovl);
435 int (*disable)(struct omap_overlay *ovl);
436 bool (*is_enabled)(struct omap_overlay *ovl);
437
438 int (*set_manager)(struct omap_overlay *ovl,
439 struct omap_overlay_manager *mgr);
440 int (*unset_manager)(struct omap_overlay *ovl);
441
442 int (*set_overlay_info)(struct omap_overlay *ovl,
443 struct omap_overlay_info *info);
444 void (*get_overlay_info)(struct omap_overlay *ovl,
445 struct omap_overlay_info *info);
446
447 int (*wait_for_go)(struct omap_overlay *ovl);
448
449 struct omap_dss_device *(*get_device)(struct omap_overlay *ovl);
450};
451
452struct omap_overlay_manager_info {
453 u32 default_color;
454
455 enum omap_dss_trans_key_type trans_key_type;
456 u32 trans_key;
457 bool trans_enabled;
458
459 bool partial_alpha_enabled;
460
461 bool cpr_enable;
462 struct omap_dss_cpr_coefs cpr_coefs;
463};
464
465struct omap_overlay_manager {
466 struct kobject kobj;
467
468 /* static fields */
469 const char *name;
470 enum omap_channel id;
471 enum omap_overlay_manager_caps caps;
472 struct list_head overlays;
473 enum omap_display_type supported_displays;
474 enum omap_dss_output_id supported_outputs;
475
476 /* dynamic fields */
477 struct omap_dss_device *output;
478
479 /*
480 * The following functions do not block:
481 *
482 * set_manager_info
483 * get_manager_info
484 * apply
485 *
486 * The rest of the functions may block and cannot be called from
487 * interrupt context
488 */
489
490 int (*set_output)(struct omap_overlay_manager *mgr,
491 struct omap_dss_device *output);
492 int (*unset_output)(struct omap_overlay_manager *mgr);
493
494 int (*set_manager_info)(struct omap_overlay_manager *mgr,
495 struct omap_overlay_manager_info *info);
496 void (*get_manager_info)(struct omap_overlay_manager *mgr,
497 struct omap_overlay_manager_info *info);
498
499 int (*apply)(struct omap_overlay_manager *mgr);
500 int (*wait_for_go)(struct omap_overlay_manager *mgr);
501 int (*wait_for_vsync)(struct omap_overlay_manager *mgr);
502
503 struct omap_dss_device *(*get_device)(struct omap_overlay_manager *mgr);
504};
505
506/* 22 pins means 1 clk lane and 10 data lanes */
507#define OMAP_DSS_MAX_DSI_PINS 22
508
509struct omap_dsi_pin_config {
510 int num_pins;
511 /*
512 * pin numbers in the following order:
513 * clk+, clk-
514 * data1+, data1-
515 * data2+, data2-
516 * ...
517 */
518 int pins[OMAP_DSS_MAX_DSI_PINS];
519};
520
521struct omap_dss_writeback_info {
522 u32 paddr;
523 u32 p_uv_addr;
524 u16 buf_width;
525 u16 width;
526 u16 height;
527 enum omap_color_mode color_mode;
528 u8 rotation;
529 enum omap_dss_rotation_type rotation_type;
530 bool mirror;
531 u8 pre_mult_alpha;
532};
533
534struct omapdss_dpi_ops {
535 int (*connect)(struct omap_dss_device *dssdev,
536 struct omap_dss_device *dst);
537 void (*disconnect)(struct omap_dss_device *dssdev,
538 struct omap_dss_device *dst);
539
540 int (*enable)(struct omap_dss_device *dssdev);
541 void (*disable)(struct omap_dss_device *dssdev);
542
543 int (*check_timings)(struct omap_dss_device *dssdev,
544 struct omap_video_timings *timings);
545 void (*set_timings)(struct omap_dss_device *dssdev,
546 struct omap_video_timings *timings);
547 void (*get_timings)(struct omap_dss_device *dssdev,
548 struct omap_video_timings *timings);
549
550 void (*set_data_lines)(struct omap_dss_device *dssdev, int data_lines);
551};
552
553struct omapdss_sdi_ops {
554 int (*connect)(struct omap_dss_device *dssdev,
555 struct omap_dss_device *dst);
556 void (*disconnect)(struct omap_dss_device *dssdev,
557 struct omap_dss_device *dst);
558
559 int (*enable)(struct omap_dss_device *dssdev);
560 void (*disable)(struct omap_dss_device *dssdev);
561
562 int (*check_timings)(struct omap_dss_device *dssdev,
563 struct omap_video_timings *timings);
564 void (*set_timings)(struct omap_dss_device *dssdev,
565 struct omap_video_timings *timings);
566 void (*get_timings)(struct omap_dss_device *dssdev,
567 struct omap_video_timings *timings);
568
569 void (*set_datapairs)(struct omap_dss_device *dssdev, int datapairs);
570};
571
572struct omapdss_dvi_ops {
573 int (*connect)(struct omap_dss_device *dssdev,
574 struct omap_dss_device *dst);
575 void (*disconnect)(struct omap_dss_device *dssdev,
576 struct omap_dss_device *dst);
577
578 int (*enable)(struct omap_dss_device *dssdev);
579 void (*disable)(struct omap_dss_device *dssdev);
580
581 int (*check_timings)(struct omap_dss_device *dssdev,
582 struct omap_video_timings *timings);
583 void (*set_timings)(struct omap_dss_device *dssdev,
584 struct omap_video_timings *timings);
585 void (*get_timings)(struct omap_dss_device *dssdev,
586 struct omap_video_timings *timings);
587};
588
589struct omapdss_atv_ops {
590 int (*connect)(struct omap_dss_device *dssdev,
591 struct omap_dss_device *dst);
592 void (*disconnect)(struct omap_dss_device *dssdev,
593 struct omap_dss_device *dst);
594
595 int (*enable)(struct omap_dss_device *dssdev);
596 void (*disable)(struct omap_dss_device *dssdev);
597
598 int (*check_timings)(struct omap_dss_device *dssdev,
599 struct omap_video_timings *timings);
600 void (*set_timings)(struct omap_dss_device *dssdev,
601 struct omap_video_timings *timings);
602 void (*get_timings)(struct omap_dss_device *dssdev,
603 struct omap_video_timings *timings);
604
605 void (*set_type)(struct omap_dss_device *dssdev,
606 enum omap_dss_venc_type type);
607 void (*invert_vid_out_polarity)(struct omap_dss_device *dssdev,
608 bool invert_polarity);
609
610 int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
611 u32 (*get_wss)(struct omap_dss_device *dssdev);
612};
613
614struct omapdss_hdmi_ops {
615 int (*connect)(struct omap_dss_device *dssdev,
616 struct omap_dss_device *dst);
617 void (*disconnect)(struct omap_dss_device *dssdev,
618 struct omap_dss_device *dst);
619
620 int (*enable)(struct omap_dss_device *dssdev);
621 void (*disable)(struct omap_dss_device *dssdev);
622
623 int (*check_timings)(struct omap_dss_device *dssdev,
624 struct omap_video_timings *timings);
625 void (*set_timings)(struct omap_dss_device *dssdev,
626 struct omap_video_timings *timings);
627 void (*get_timings)(struct omap_dss_device *dssdev,
628 struct omap_video_timings *timings);
629
630 int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len);
631 bool (*detect)(struct omap_dss_device *dssdev);
632
633 /*
634 * Note: These functions might sleep. Do not call while
635 * holding a spinlock/readlock.
636 */
637 int (*audio_enable)(struct omap_dss_device *dssdev);
638 void (*audio_disable)(struct omap_dss_device *dssdev);
639 bool (*audio_supported)(struct omap_dss_device *dssdev);
640 int (*audio_config)(struct omap_dss_device *dssdev,
641 struct omap_dss_audio *audio);
642 /* Note: These functions may not sleep */
643 int (*audio_start)(struct omap_dss_device *dssdev);
644 void (*audio_stop)(struct omap_dss_device *dssdev);
645};
646
647struct omapdss_dsi_ops {
648 int (*connect)(struct omap_dss_device *dssdev,
649 struct omap_dss_device *dst);
650 void (*disconnect)(struct omap_dss_device *dssdev,
651 struct omap_dss_device *dst);
652
653 int (*enable)(struct omap_dss_device *dssdev);
654 void (*disable)(struct omap_dss_device *dssdev, bool disconnect_lanes,
655 bool enter_ulps);
656
657 /* bus configuration */
658 int (*set_config)(struct omap_dss_device *dssdev,
659 const struct omap_dss_dsi_config *cfg);
660 int (*configure_pins)(struct omap_dss_device *dssdev,
661 const struct omap_dsi_pin_config *pin_cfg);
662
663 void (*enable_hs)(struct omap_dss_device *dssdev, int channel,
664 bool enable);
665 int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
666
667 int (*update)(struct omap_dss_device *dssdev, int channel,
668 void (*callback)(int, void *), void *data);
669
670 void (*bus_lock)(struct omap_dss_device *dssdev);
671 void (*bus_unlock)(struct omap_dss_device *dssdev);
672
673 int (*enable_video_output)(struct omap_dss_device *dssdev, int channel);
674 void (*disable_video_output)(struct omap_dss_device *dssdev,
675 int channel);
676
677 int (*request_vc)(struct omap_dss_device *dssdev, int *channel);
678 int (*set_vc_id)(struct omap_dss_device *dssdev, int channel,
679 int vc_id);
680 void (*release_vc)(struct omap_dss_device *dssdev, int channel);
681
682 /* data transfer */
683 int (*dcs_write)(struct omap_dss_device *dssdev, int channel,
684 u8 *data, int len);
685 int (*dcs_write_nosync)(struct omap_dss_device *dssdev, int channel,
686 u8 *data, int len);
687 int (*dcs_read)(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
688 u8 *data, int len);
689
690 int (*gen_write)(struct omap_dss_device *dssdev, int channel,
691 u8 *data, int len);
692 int (*gen_write_nosync)(struct omap_dss_device *dssdev, int channel,
693 u8 *data, int len);
694 int (*gen_read)(struct omap_dss_device *dssdev, int channel,
695 u8 *reqdata, int reqlen,
696 u8 *data, int len);
697
698 int (*bta_sync)(struct omap_dss_device *dssdev, int channel);
699
700 int (*set_max_rx_packet_size)(struct omap_dss_device *dssdev,
701 int channel, u16 plen);
702};
703
704struct omap_dss_device {
705 struct device *dev;
706
707 struct module *owner;
708
709 struct list_head panel_list;
710
711 /* alias in the form of "display%d" */
712 char alias[16];
713
714 enum omap_display_type type;
715 enum omap_display_type output_type;
716
717 union {
718 struct {
719 u8 data_lines;
720 } dpi;
721
722 struct {
723 u8 channel;
724 u8 data_lines;
725 } rfbi;
726
727 struct {
728 u8 datapairs;
729 } sdi;
730
731 struct {
732 int module;
733 } dsi;
734
735 struct {
736 enum omap_dss_venc_type type;
737 bool invert_polarity;
738 } venc;
739 } phy;
740
741 struct {
742 struct omap_video_timings timings;
743
744 enum omap_dss_dsi_pixel_format dsi_pix_fmt;
745 enum omap_dss_dsi_mode dsi_mode;
746 } panel;
747
748 struct {
749 u8 pixel_size;
750 struct rfbi_timings rfbi_timings;
751 } ctrl;
752
753 const char *name;
754
755 /* used to match device to driver */
756 const char *driver_name;
757
758 void *data;
759
760 struct omap_dss_driver *driver;
761
762 union {
763 const struct omapdss_dpi_ops *dpi;
764 const struct omapdss_sdi_ops *sdi;
765 const struct omapdss_dvi_ops *dvi;
766 const struct omapdss_hdmi_ops *hdmi;
767 const struct omapdss_atv_ops *atv;
768 const struct omapdss_dsi_ops *dsi;
769 } ops;
770
771 /* helper variable for driver suspend/resume */
772 bool activate_after_resume;
773
774 enum omap_display_caps caps;
775
776 struct omap_dss_device *src;
777
778 enum omap_dss_display_state state;
779
780 enum omap_dss_audio_state audio_state;
781
782 /* OMAP DSS output specific fields */
783
784 struct list_head list;
785
786 /* DISPC channel for this output */
787 enum omap_channel dispc_channel;
788
789 /* output instance */
790 enum omap_dss_output_id id;
791
792 /* dynamic fields */
793 struct omap_overlay_manager *manager;
794
795 struct omap_dss_device *dst;
796};
797
798struct omap_dss_hdmi_data
799{
800 int ct_cp_hpd_gpio;
801 int ls_oe_gpio;
802 int hpd_gpio;
803};
804
805struct omap_dss_driver {
806 int (*probe)(struct omap_dss_device *);
807 void (*remove)(struct omap_dss_device *);
808
809 int (*connect)(struct omap_dss_device *dssdev);
810 void (*disconnect)(struct omap_dss_device *dssdev);
811
812 int (*enable)(struct omap_dss_device *display);
813 void (*disable)(struct omap_dss_device *display);
814 int (*run_test)(struct omap_dss_device *display, int test);
815
816 int (*update)(struct omap_dss_device *dssdev,
817 u16 x, u16 y, u16 w, u16 h);
818 int (*sync)(struct omap_dss_device *dssdev);
819
820 int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
821 int (*get_te)(struct omap_dss_device *dssdev);
822
823 u8 (*get_rotate)(struct omap_dss_device *dssdev);
824 int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
825
826 bool (*get_mirror)(struct omap_dss_device *dssdev);
827 int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
828
829 int (*memory_read)(struct omap_dss_device *dssdev,
830 void *buf, size_t size,
831 u16 x, u16 y, u16 w, u16 h);
832
833 void (*get_resolution)(struct omap_dss_device *dssdev,
834 u16 *xres, u16 *yres);
835 void (*get_dimensions)(struct omap_dss_device *dssdev,
836 u32 *width, u32 *height);
837 int (*get_recommended_bpp)(struct omap_dss_device *dssdev);
838
839 int (*check_timings)(struct omap_dss_device *dssdev,
840 struct omap_video_timings *timings);
841 void (*set_timings)(struct omap_dss_device *dssdev,
842 struct omap_video_timings *timings);
843 void (*get_timings)(struct omap_dss_device *dssdev,
844 struct omap_video_timings *timings);
845
846 int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
847 u32 (*get_wss)(struct omap_dss_device *dssdev);
848
849 int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len);
850 bool (*detect)(struct omap_dss_device *dssdev);
851
852 /*
853 * For display drivers that support audio. This encompasses
854 * HDMI and DisplayPort at the moment.
855 */
856 /*
857 * Note: These functions might sleep. Do not call while
858 * holding a spinlock/readlock.
859 */
860 int (*audio_enable)(struct omap_dss_device *dssdev);
861 void (*audio_disable)(struct omap_dss_device *dssdev);
862 bool (*audio_supported)(struct omap_dss_device *dssdev);
863 int (*audio_config)(struct omap_dss_device *dssdev,
864 struct omap_dss_audio *audio);
865 /* Note: These functions may not sleep */
866 int (*audio_start)(struct omap_dss_device *dssdev);
867 void (*audio_stop)(struct omap_dss_device *dssdev);
868
869};
870
871enum omapdss_version omapdss_get_version(void);
872bool omapdss_is_initialized(void);
873
874int omap_dss_register_driver(struct omap_dss_driver *);
875void omap_dss_unregister_driver(struct omap_dss_driver *);
876
877int omapdss_register_display(struct omap_dss_device *dssdev);
878void omapdss_unregister_display(struct omap_dss_device *dssdev);
879
880struct omap_dss_device *omap_dss_get_device(struct omap_dss_device *dssdev);
881void omap_dss_put_device(struct omap_dss_device *dssdev);
882#define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
883struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
884struct omap_dss_device *omap_dss_find_device(void *data,
885 int (*match)(struct omap_dss_device *dssdev, void *data));
886const char *omapdss_get_default_display_name(void);
887
888void videomode_to_omap_video_timings(const struct videomode *vm,
889 struct omap_video_timings *ovt);
890void omap_video_timings_to_videomode(const struct omap_video_timings *ovt,
891 struct videomode *vm);
892
893int dss_feat_get_num_mgrs(void);
894int dss_feat_get_num_ovls(void);
895enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel);
896enum omap_dss_output_id dss_feat_get_supported_outputs(enum omap_channel channel);
897enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane);
898
899
900
901int omap_dss_get_num_overlay_managers(void);
902struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
903
904int omap_dss_get_num_overlays(void);
905struct omap_overlay *omap_dss_get_overlay(int num);
906
907int omapdss_register_output(struct omap_dss_device *output);
908void omapdss_unregister_output(struct omap_dss_device *output);
909struct omap_dss_device *omap_dss_get_output(enum omap_dss_output_id id);
910struct omap_dss_device *omap_dss_find_output(const char *name);
911struct omap_dss_device *omap_dss_find_output_by_node(struct device_node *node);
912int omapdss_output_set_device(struct omap_dss_device *out,
913 struct omap_dss_device *dssdev);
914int omapdss_output_unset_device(struct omap_dss_device *out);
915
916struct omap_dss_device *omapdss_find_output_from_display(struct omap_dss_device *dssdev);
917struct omap_overlay_manager *omapdss_find_mgr_from_display(struct omap_dss_device *dssdev);
918
919void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
920 u16 *xres, u16 *yres);
921int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev);
922void omapdss_default_get_timings(struct omap_dss_device *dssdev,
923 struct omap_video_timings *timings);
924
925typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
926int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
927int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
928
929u32 dispc_read_irqstatus(void);
930void dispc_clear_irqstatus(u32 mask);
931u32 dispc_read_irqenable(void);
932void dispc_write_irqenable(u32 mask);
933
934int dispc_request_irq(irq_handler_t handler, void *dev_id);
935void dispc_free_irq(void *dev_id);
936
937int dispc_runtime_get(void);
938void dispc_runtime_put(void);
939
940void dispc_mgr_enable(enum omap_channel channel, bool enable);
941bool dispc_mgr_is_enabled(enum omap_channel channel);
942u32 dispc_mgr_get_vsync_irq(enum omap_channel channel);
943u32 dispc_mgr_get_framedone_irq(enum omap_channel channel);
944u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel);
945bool dispc_mgr_go_busy(enum omap_channel channel);
946void dispc_mgr_go(enum omap_channel channel);
947void dispc_mgr_set_lcd_config(enum omap_channel channel,
948 const struct dss_lcd_mgr_config *config);
949void dispc_mgr_set_timings(enum omap_channel channel,
950 const struct omap_video_timings *timings);
951void dispc_mgr_setup(enum omap_channel channel,
952 const struct omap_overlay_manager_info *info);
953
954int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel,
955 const struct omap_overlay_info *oi,
956 const struct omap_video_timings *timings,
957 int *x_predecim, int *y_predecim);
958
959int dispc_ovl_enable(enum omap_plane plane, bool enable);
960bool dispc_ovl_enabled(enum omap_plane plane);
961void dispc_ovl_set_channel_out(enum omap_plane plane,
962 enum omap_channel channel);
963int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
964 bool replication, const struct omap_video_timings *mgr_timings,
965 bool mem_to_mem);
966
967#define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver)
968#define to_dss_device(x) container_of((x), struct omap_dss_device, old_dev)
969
970int omapdss_compat_init(void);
971void omapdss_compat_uninit(void);
972
973struct dss_mgr_ops {
974 int (*connect)(struct omap_overlay_manager *mgr,
975 struct omap_dss_device *dst);
976 void (*disconnect)(struct omap_overlay_manager *mgr,
977 struct omap_dss_device *dst);
978
979 void (*start_update)(struct omap_overlay_manager *mgr);
980 int (*enable)(struct omap_overlay_manager *mgr);
981 void (*disable)(struct omap_overlay_manager *mgr);
982 void (*set_timings)(struct omap_overlay_manager *mgr,
983 const struct omap_video_timings *timings);
984 void (*set_lcd_config)(struct omap_overlay_manager *mgr,
985 const struct dss_lcd_mgr_config *config);
986 int (*register_framedone_handler)(struct omap_overlay_manager *mgr,
987 void (*handler)(void *), void *data);
988 void (*unregister_framedone_handler)(struct omap_overlay_manager *mgr,
989 void (*handler)(void *), void *data);
990};
991
992int dss_install_mgr_ops(const struct dss_mgr_ops *mgr_ops);
993void dss_uninstall_mgr_ops(void);
994
995int dss_mgr_connect(struct omap_overlay_manager *mgr,
996 struct omap_dss_device *dst);
997void dss_mgr_disconnect(struct omap_overlay_manager *mgr,
998 struct omap_dss_device *dst);
999void dss_mgr_set_timings(struct omap_overlay_manager *mgr,
1000 const struct omap_video_timings *timings);
1001void dss_mgr_set_lcd_config(struct omap_overlay_manager *mgr,
1002 const struct dss_lcd_mgr_config *config);
1003int dss_mgr_enable(struct omap_overlay_manager *mgr);
1004void dss_mgr_disable(struct omap_overlay_manager *mgr);
1005void dss_mgr_start_update(struct omap_overlay_manager *mgr);
1006int dss_mgr_register_framedone_handler(struct omap_overlay_manager *mgr,
1007 void (*handler)(void *), void *data);
1008void dss_mgr_unregister_framedone_handler(struct omap_overlay_manager *mgr,
1009 void (*handler)(void *), void *data);
1010
1011static inline bool omapdss_device_is_connected(struct omap_dss_device *dssdev)
1012{
1013 return dssdev->src;
1014}
1015
1016static inline bool omapdss_device_is_enabled(struct omap_dss_device *dssdev)
1017{
1018 return dssdev->state == OMAP_DSS_DISPLAY_ACTIVE;
1019}
1020
1021struct device_node *
1022omapdss_of_get_next_port(const struct device_node *parent,
1023 struct device_node *prev);
1024
1025struct device_node *
1026omapdss_of_get_next_endpoint(const struct device_node *parent,
1027 struct device_node *prev);
1028
1029struct device_node *
1030omapdss_of_get_first_endpoint(const struct device_node *parent);
1031
1032struct omap_dss_device *
1033omapdss_of_find_source_for_first_ep(struct device_node *node);
1034
1035#endif