Loading...
Note: File does not exist in v3.1.
1#ifndef __LINUX_FUSBH200_H
2#define __LINUX_FUSBH200_H
3
4/* definitions used for the EHCI driver */
5
6/*
7 * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
8 * __leXX (normally) or __beXX (given FUSBH200_BIG_ENDIAN_DESC), depending on
9 * the host controller implementation.
10 *
11 * To facilitate the strongest possible byte-order checking from "sparse"
12 * and so on, we use __leXX unless that's not practical.
13 */
14#define __hc32 __le32
15#define __hc16 __le16
16
17/* statistics can be kept for tuning/monitoring */
18struct fusbh200_stats {
19 /* irq usage */
20 unsigned long normal;
21 unsigned long error;
22 unsigned long iaa;
23 unsigned long lost_iaa;
24
25 /* termination of urbs from core */
26 unsigned long complete;
27 unsigned long unlink;
28};
29
30/* fusbh200_hcd->lock guards shared data against other CPUs:
31 * fusbh200_hcd: async, unlink, periodic (and shadow), ...
32 * usb_host_endpoint: hcpriv
33 * fusbh200_qh: qh_next, qtd_list
34 * fusbh200_qtd: qtd_list
35 *
36 * Also, hold this lock when talking to HC registers or
37 * when updating hw_* fields in shared qh/qtd/... structures.
38 */
39
40#define FUSBH200_MAX_ROOT_PORTS 1 /* see HCS_N_PORTS */
41
42/*
43 * fusbh200_rh_state values of FUSBH200_RH_RUNNING or above mean that the
44 * controller may be doing DMA. Lower values mean there's no DMA.
45 */
46enum fusbh200_rh_state {
47 FUSBH200_RH_HALTED,
48 FUSBH200_RH_SUSPENDED,
49 FUSBH200_RH_RUNNING,
50 FUSBH200_RH_STOPPING
51};
52
53/*
54 * Timer events, ordered by increasing delay length.
55 * Always update event_delays_ns[] and event_handlers[] (defined in
56 * ehci-timer.c) in parallel with this list.
57 */
58enum fusbh200_hrtimer_event {
59 FUSBH200_HRTIMER_POLL_ASS, /* Poll for async schedule off */
60 FUSBH200_HRTIMER_POLL_PSS, /* Poll for periodic schedule off */
61 FUSBH200_HRTIMER_POLL_DEAD, /* Wait for dead controller to stop */
62 FUSBH200_HRTIMER_UNLINK_INTR, /* Wait for interrupt QH unlink */
63 FUSBH200_HRTIMER_FREE_ITDS, /* Wait for unused iTDs and siTDs */
64 FUSBH200_HRTIMER_ASYNC_UNLINKS, /* Unlink empty async QHs */
65 FUSBH200_HRTIMER_IAA_WATCHDOG, /* Handle lost IAA interrupts */
66 FUSBH200_HRTIMER_DISABLE_PERIODIC, /* Wait to disable periodic sched */
67 FUSBH200_HRTIMER_DISABLE_ASYNC, /* Wait to disable async sched */
68 FUSBH200_HRTIMER_IO_WATCHDOG, /* Check for missing IRQs */
69 FUSBH200_HRTIMER_NUM_EVENTS /* Must come last */
70};
71#define FUSBH200_HRTIMER_NO_EVENT 99
72
73struct fusbh200_hcd { /* one per controller */
74 /* timing support */
75 enum fusbh200_hrtimer_event next_hrtimer_event;
76 unsigned enabled_hrtimer_events;
77 ktime_t hr_timeouts[FUSBH200_HRTIMER_NUM_EVENTS];
78 struct hrtimer hrtimer;
79
80 int PSS_poll_count;
81 int ASS_poll_count;
82 int died_poll_count;
83
84 /* glue to PCI and HCD framework */
85 struct fusbh200_caps __iomem *caps;
86 struct fusbh200_regs __iomem *regs;
87 struct fusbh200_dbg_port __iomem *debug;
88
89 __u32 hcs_params; /* cached register copy */
90 spinlock_t lock;
91 enum fusbh200_rh_state rh_state;
92
93 /* general schedule support */
94 bool scanning:1;
95 bool need_rescan:1;
96 bool intr_unlinking:1;
97 bool async_unlinking:1;
98 bool shutdown:1;
99 struct fusbh200_qh *qh_scan_next;
100
101 /* async schedule support */
102 struct fusbh200_qh *async;
103 struct fusbh200_qh *dummy; /* For AMD quirk use */
104 struct fusbh200_qh *async_unlink;
105 struct fusbh200_qh *async_unlink_last;
106 struct fusbh200_qh *async_iaa;
107 unsigned async_unlink_cycle;
108 unsigned async_count; /* async activity count */
109
110 /* periodic schedule support */
111#define DEFAULT_I_TDPS 1024 /* some HCs can do less */
112 unsigned periodic_size;
113 __hc32 *periodic; /* hw periodic table */
114 dma_addr_t periodic_dma;
115 struct list_head intr_qh_list;
116 unsigned i_thresh; /* uframes HC might cache */
117
118 union fusbh200_shadow *pshadow; /* mirror hw periodic table */
119 struct fusbh200_qh *intr_unlink;
120 struct fusbh200_qh *intr_unlink_last;
121 unsigned intr_unlink_cycle;
122 unsigned now_frame; /* frame from HC hardware */
123 unsigned next_frame; /* scan periodic, start here */
124 unsigned intr_count; /* intr activity count */
125 unsigned isoc_count; /* isoc activity count */
126 unsigned periodic_count; /* periodic activity count */
127 unsigned uframe_periodic_max; /* max periodic time per uframe */
128
129
130 /* list of itds completed while now_frame was still active */
131 struct list_head cached_itd_list;
132 struct fusbh200_itd *last_itd_to_free;
133
134 /* per root hub port */
135 unsigned long reset_done [FUSBH200_MAX_ROOT_PORTS];
136
137 /* bit vectors (one bit per port) */
138 unsigned long bus_suspended; /* which ports were
139 already suspended at the start of a bus suspend */
140 unsigned long companion_ports; /* which ports are
141 dedicated to the companion controller */
142 unsigned long owned_ports; /* which ports are
143 owned by the companion during a bus suspend */
144 unsigned long port_c_suspend; /* which ports have
145 the change-suspend feature turned on */
146 unsigned long suspended_ports; /* which ports are
147 suspended */
148 unsigned long resuming_ports; /* which ports have
149 started to resume */
150
151 /* per-HC memory pools (could be per-bus, but ...) */
152 struct dma_pool *qh_pool; /* qh per active urb */
153 struct dma_pool *qtd_pool; /* one or more per qh */
154 struct dma_pool *itd_pool; /* itd per iso urb */
155
156 unsigned random_frame;
157 unsigned long next_statechange;
158 ktime_t last_periodic_enable;
159 u32 command;
160
161 /* SILICON QUIRKS */
162 unsigned need_io_watchdog:1;
163 unsigned fs_i_thresh:1; /* Intel iso scheduling */
164
165 u8 sbrn; /* packed release number */
166
167 /* irq statistics */
168 struct fusbh200_stats stats;
169# define COUNT(x) do { (x)++; } while (0)
170
171 /* debug files */
172 struct dentry *debug_dir;
173};
174
175/* convert between an HCD pointer and the corresponding FUSBH200_HCD */
176static inline struct fusbh200_hcd *hcd_to_fusbh200 (struct usb_hcd *hcd)
177{
178 return (struct fusbh200_hcd *) (hcd->hcd_priv);
179}
180static inline struct usb_hcd *fusbh200_to_hcd (struct fusbh200_hcd *fusbh200)
181{
182 return container_of ((void *) fusbh200, struct usb_hcd, hcd_priv);
183}
184
185/*-------------------------------------------------------------------------*/
186
187/* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
188
189/* Section 2.2 Host Controller Capability Registers */
190struct fusbh200_caps {
191 /* these fields are specified as 8 and 16 bit registers,
192 * but some hosts can't perform 8 or 16 bit PCI accesses.
193 * some hosts treat caplength and hciversion as parts of a 32-bit
194 * register, others treat them as two separate registers, this
195 * affects the memory map for big endian controllers.
196 */
197 u32 hc_capbase;
198#define HC_LENGTH(fusbh200, p) (0x00ff&((p) >> /* bits 7:0 / offset 00h */ \
199 (fusbh200_big_endian_capbase(fusbh200) ? 24 : 0)))
200#define HC_VERSION(fusbh200, p) (0xffff&((p) >> /* bits 31:16 / offset 02h */ \
201 (fusbh200_big_endian_capbase(fusbh200) ? 0 : 16)))
202 u32 hcs_params; /* HCSPARAMS - offset 0x4 */
203#define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */
204
205 u32 hcc_params; /* HCCPARAMS - offset 0x8 */
206#define HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */
207#define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/
208 u8 portroute[8]; /* nibbles for routing - offset 0xC */
209};
210
211
212/* Section 2.3 Host Controller Operational Registers */
213struct fusbh200_regs {
214
215 /* USBCMD: offset 0x00 */
216 u32 command;
217
218/* EHCI 1.1 addendum */
219/* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
220#define CMD_PARK (1<<11) /* enable "park" on async qh */
221#define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */
222#define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */
223#define CMD_ASE (1<<5) /* async schedule enable */
224#define CMD_PSE (1<<4) /* periodic schedule enable */
225/* 3:2 is periodic frame list size */
226#define CMD_RESET (1<<1) /* reset HC not bus */
227#define CMD_RUN (1<<0) /* start/stop HC */
228
229 /* USBSTS: offset 0x04 */
230 u32 status;
231#define STS_ASS (1<<15) /* Async Schedule Status */
232#define STS_PSS (1<<14) /* Periodic Schedule Status */
233#define STS_RECL (1<<13) /* Reclamation */
234#define STS_HALT (1<<12) /* Not running (any reason) */
235/* some bits reserved */
236 /* these STS_* flags are also intr_enable bits (USBINTR) */
237#define STS_IAA (1<<5) /* Interrupted on async advance */
238#define STS_FATAL (1<<4) /* such as some PCI access errors */
239#define STS_FLR (1<<3) /* frame list rolled over */
240#define STS_PCD (1<<2) /* port change detect */
241#define STS_ERR (1<<1) /* "error" completion (overflow, ...) */
242#define STS_INT (1<<0) /* "normal" completion (short, ...) */
243
244 /* USBINTR: offset 0x08 */
245 u32 intr_enable;
246
247 /* FRINDEX: offset 0x0C */
248 u32 frame_index; /* current microframe number */
249 /* CTRLDSSEGMENT: offset 0x10 */
250 u32 segment; /* address bits 63:32 if needed */
251 /* PERIODICLISTBASE: offset 0x14 */
252 u32 frame_list; /* points to periodic list */
253 /* ASYNCLISTADDR: offset 0x18 */
254 u32 async_next; /* address of next async queue head */
255
256 u32 reserved1;
257 /* PORTSC: offset 0x20 */
258 u32 port_status;
259/* 31:23 reserved */
260#define PORT_USB11(x) (((x)&(3<<10)) == (1<<10)) /* USB 1.1 device */
261#define PORT_RESET (1<<8) /* reset port */
262#define PORT_SUSPEND (1<<7) /* suspend port */
263#define PORT_RESUME (1<<6) /* resume it */
264#define PORT_PEC (1<<3) /* port enable change */
265#define PORT_PE (1<<2) /* port enable */
266#define PORT_CSC (1<<1) /* connect status change */
267#define PORT_CONNECT (1<<0) /* device connected */
268#define PORT_RWC_BITS (PORT_CSC | PORT_PEC)
269
270 u32 reserved2[3];
271
272 /* BMCSR: offset 0x30 */
273 u32 bmcsr; /* Bus Moniter Control/Status Register */
274#define BMCSR_HOST_SPD_TYP (3<<9)
275#define BMCSR_VBUS_OFF (1<<4)
276#define BMCSR_INT_POLARITY (1<<3)
277
278 /* BMISR: offset 0x34 */
279 u32 bmisr; /* Bus Moniter Interrupt Status Register*/
280#define BMISR_OVC (1<<1)
281
282 /* BMIER: offset 0x38 */
283 u32 bmier; /* Bus Moniter Interrupt Enable Register */
284#define BMIER_OVC_EN (1<<1)
285#define BMIER_VBUS_ERR_EN (1<<0)
286};
287
288/* Appendix C, Debug port ... intended for use with special "debug devices"
289 * that can help if there's no serial console. (nonstandard enumeration.)
290 */
291struct fusbh200_dbg_port {
292 u32 control;
293#define DBGP_OWNER (1<<30)
294#define DBGP_ENABLED (1<<28)
295#define DBGP_DONE (1<<16)
296#define DBGP_INUSE (1<<10)
297#define DBGP_ERRCODE(x) (((x)>>7)&0x07)
298# define DBGP_ERR_BAD 1
299# define DBGP_ERR_SIGNAL 2
300#define DBGP_ERROR (1<<6)
301#define DBGP_GO (1<<5)
302#define DBGP_OUT (1<<4)
303#define DBGP_LEN(x) (((x)>>0)&0x0f)
304 u32 pids;
305#define DBGP_PID_GET(x) (((x)>>16)&0xff)
306#define DBGP_PID_SET(data, tok) (((data)<<8)|(tok))
307 u32 data03;
308 u32 data47;
309 u32 address;
310#define DBGP_EPADDR(dev, ep) (((dev)<<8)|(ep))
311};
312
313#ifdef CONFIG_EARLY_PRINTK_DBGP
314#include <linux/init.h>
315extern int __init early_dbgp_init(char *s);
316extern struct console early_dbgp_console;
317#endif /* CONFIG_EARLY_PRINTK_DBGP */
318
319struct usb_hcd;
320
321static inline int xen_dbgp_reset_prep(struct usb_hcd *hcd)
322{
323 return 1; /* Shouldn't this be 0? */
324}
325
326static inline int xen_dbgp_external_startup(struct usb_hcd *hcd)
327{
328 return -1;
329}
330
331#ifdef CONFIG_EARLY_PRINTK_DBGP
332/* Call backs from fusbh200 host driver to fusbh200 debug driver */
333extern int dbgp_external_startup(struct usb_hcd *);
334extern int dbgp_reset_prep(struct usb_hcd *hcd);
335#else
336static inline int dbgp_reset_prep(struct usb_hcd *hcd)
337{
338 return xen_dbgp_reset_prep(hcd);
339}
340static inline int dbgp_external_startup(struct usb_hcd *hcd)
341{
342 return xen_dbgp_external_startup(hcd);
343}
344#endif
345
346/*-------------------------------------------------------------------------*/
347
348#define QTD_NEXT(fusbh200, dma) cpu_to_hc32(fusbh200, (u32)dma)
349
350/*
351 * EHCI Specification 0.95 Section 3.5
352 * QTD: describe data transfer components (buffer, direction, ...)
353 * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
354 *
355 * These are associated only with "QH" (Queue Head) structures,
356 * used with control, bulk, and interrupt transfers.
357 */
358struct fusbh200_qtd {
359 /* first part defined by EHCI spec */
360 __hc32 hw_next; /* see EHCI 3.5.1 */
361 __hc32 hw_alt_next; /* see EHCI 3.5.2 */
362 __hc32 hw_token; /* see EHCI 3.5.3 */
363#define QTD_TOGGLE (1 << 31) /* data toggle */
364#define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
365#define QTD_IOC (1 << 15) /* interrupt on complete */
366#define QTD_CERR(tok) (((tok)>>10) & 0x3)
367#define QTD_PID(tok) (((tok)>>8) & 0x3)
368#define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */
369#define QTD_STS_HALT (1 << 6) /* halted on error */
370#define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */
371#define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */
372#define QTD_STS_XACT (1 << 3) /* device gave illegal response */
373#define QTD_STS_MMF (1 << 2) /* incomplete split transaction */
374#define QTD_STS_STS (1 << 1) /* split transaction state */
375#define QTD_STS_PING (1 << 0) /* issue PING? */
376
377#define ACTIVE_BIT(fusbh200) cpu_to_hc32(fusbh200, QTD_STS_ACTIVE)
378#define HALT_BIT(fusbh200) cpu_to_hc32(fusbh200, QTD_STS_HALT)
379#define STATUS_BIT(fusbh200) cpu_to_hc32(fusbh200, QTD_STS_STS)
380
381 __hc32 hw_buf [5]; /* see EHCI 3.5.4 */
382 __hc32 hw_buf_hi [5]; /* Appendix B */
383
384 /* the rest is HCD-private */
385 dma_addr_t qtd_dma; /* qtd address */
386 struct list_head qtd_list; /* sw qtd list */
387 struct urb *urb; /* qtd's urb */
388 size_t length; /* length of buffer */
389} __attribute__ ((aligned (32)));
390
391/* mask NakCnt+T in qh->hw_alt_next */
392#define QTD_MASK(fusbh200) cpu_to_hc32 (fusbh200, ~0x1f)
393
394#define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1)
395
396/*-------------------------------------------------------------------------*/
397
398/* type tag from {qh,itd,fstn}->hw_next */
399#define Q_NEXT_TYPE(fusbh200,dma) ((dma) & cpu_to_hc32(fusbh200, 3 << 1))
400
401/*
402 * Now the following defines are not converted using the
403 * cpu_to_le32() macro anymore, since we have to support
404 * "dynamic" switching between be and le support, so that the driver
405 * can be used on one system with SoC EHCI controller using big-endian
406 * descriptors as well as a normal little-endian PCI EHCI controller.
407 */
408/* values for that type tag */
409#define Q_TYPE_ITD (0 << 1)
410#define Q_TYPE_QH (1 << 1)
411#define Q_TYPE_SITD (2 << 1)
412#define Q_TYPE_FSTN (3 << 1)
413
414/* next async queue entry, or pointer to interrupt/periodic QH */
415#define QH_NEXT(fusbh200,dma) (cpu_to_hc32(fusbh200, (((u32)dma)&~0x01f)|Q_TYPE_QH))
416
417/* for periodic/async schedules and qtd lists, mark end of list */
418#define FUSBH200_LIST_END(fusbh200) cpu_to_hc32(fusbh200, 1) /* "null pointer" to hw */
419
420/*
421 * Entries in periodic shadow table are pointers to one of four kinds
422 * of data structure. That's dictated by the hardware; a type tag is
423 * encoded in the low bits of the hardware's periodic schedule. Use
424 * Q_NEXT_TYPE to get the tag.
425 *
426 * For entries in the async schedule, the type tag always says "qh".
427 */
428union fusbh200_shadow {
429 struct fusbh200_qh *qh; /* Q_TYPE_QH */
430 struct fusbh200_itd *itd; /* Q_TYPE_ITD */
431 struct fusbh200_fstn *fstn; /* Q_TYPE_FSTN */
432 __hc32 *hw_next; /* (all types) */
433 void *ptr;
434};
435
436/*-------------------------------------------------------------------------*/
437
438/*
439 * EHCI Specification 0.95 Section 3.6
440 * QH: describes control/bulk/interrupt endpoints
441 * See Fig 3-7 "Queue Head Structure Layout".
442 *
443 * These appear in both the async and (for interrupt) periodic schedules.
444 */
445
446/* first part defined by EHCI spec */
447struct fusbh200_qh_hw {
448 __hc32 hw_next; /* see EHCI 3.6.1 */
449 __hc32 hw_info1; /* see EHCI 3.6.2 */
450#define QH_CONTROL_EP (1 << 27) /* FS/LS control endpoint */
451#define QH_HEAD (1 << 15) /* Head of async reclamation list */
452#define QH_TOGGLE_CTL (1 << 14) /* Data toggle control */
453#define QH_HIGH_SPEED (2 << 12) /* Endpoint speed */
454#define QH_LOW_SPEED (1 << 12)
455#define QH_FULL_SPEED (0 << 12)
456#define QH_INACTIVATE (1 << 7) /* Inactivate on next transaction */
457 __hc32 hw_info2; /* see EHCI 3.6.2 */
458#define QH_SMASK 0x000000ff
459#define QH_CMASK 0x0000ff00
460#define QH_HUBADDR 0x007f0000
461#define QH_HUBPORT 0x3f800000
462#define QH_MULT 0xc0000000
463 __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */
464
465 /* qtd overlay (hardware parts of a struct fusbh200_qtd) */
466 __hc32 hw_qtd_next;
467 __hc32 hw_alt_next;
468 __hc32 hw_token;
469 __hc32 hw_buf [5];
470 __hc32 hw_buf_hi [5];
471} __attribute__ ((aligned(32)));
472
473struct fusbh200_qh {
474 struct fusbh200_qh_hw *hw; /* Must come first */
475 /* the rest is HCD-private */
476 dma_addr_t qh_dma; /* address of qh */
477 union fusbh200_shadow qh_next; /* ptr to qh; or periodic */
478 struct list_head qtd_list; /* sw qtd list */
479 struct list_head intr_node; /* list of intr QHs */
480 struct fusbh200_qtd *dummy;
481 struct fusbh200_qh *unlink_next; /* next on unlink list */
482
483 unsigned unlink_cycle;
484
485 u8 needs_rescan; /* Dequeue during giveback */
486 u8 qh_state;
487#define QH_STATE_LINKED 1 /* HC sees this */
488#define QH_STATE_UNLINK 2 /* HC may still see this */
489#define QH_STATE_IDLE 3 /* HC doesn't see this */
490#define QH_STATE_UNLINK_WAIT 4 /* LINKED and on unlink q */
491#define QH_STATE_COMPLETING 5 /* don't touch token.HALT */
492
493 u8 xacterrs; /* XactErr retry counter */
494#define QH_XACTERR_MAX 32 /* XactErr retry limit */
495
496 /* periodic schedule info */
497 u8 usecs; /* intr bandwidth */
498 u8 gap_uf; /* uframes split/csplit gap */
499 u8 c_usecs; /* ... split completion bw */
500 u16 tt_usecs; /* tt downstream bandwidth */
501 unsigned short period; /* polling interval */
502 unsigned short start; /* where polling starts */
503#define NO_FRAME ((unsigned short)~0) /* pick new start */
504
505 struct usb_device *dev; /* access to TT */
506 unsigned is_out:1; /* bulk or intr OUT */
507 unsigned clearing_tt:1; /* Clear-TT-Buf in progress */
508};
509
510/*-------------------------------------------------------------------------*/
511
512/* description of one iso transaction (up to 3 KB data if highspeed) */
513struct fusbh200_iso_packet {
514 /* These will be copied to iTD when scheduling */
515 u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */
516 __hc32 transaction; /* itd->hw_transaction[i] |= */
517 u8 cross; /* buf crosses pages */
518 /* for full speed OUT splits */
519 u32 buf1;
520};
521
522/* temporary schedule data for packets from iso urbs (both speeds)
523 * each packet is one logical usb transaction to the device (not TT),
524 * beginning at stream->next_uframe
525 */
526struct fusbh200_iso_sched {
527 struct list_head td_list;
528 unsigned span;
529 struct fusbh200_iso_packet packet [0];
530};
531
532/*
533 * fusbh200_iso_stream - groups all (s)itds for this endpoint.
534 * acts like a qh would, if EHCI had them for ISO.
535 */
536struct fusbh200_iso_stream {
537 /* first field matches fusbh200_hq, but is NULL */
538 struct fusbh200_qh_hw *hw;
539
540 u8 bEndpointAddress;
541 u8 highspeed;
542 struct list_head td_list; /* queued itds */
543 struct list_head free_list; /* list of unused itds */
544 struct usb_device *udev;
545 struct usb_host_endpoint *ep;
546
547 /* output of (re)scheduling */
548 int next_uframe;
549 __hc32 splits;
550
551 /* the rest is derived from the endpoint descriptor,
552 * trusting urb->interval == f(epdesc->bInterval) and
553 * including the extra info for hw_bufp[0..2]
554 */
555 u8 usecs, c_usecs;
556 u16 interval;
557 u16 tt_usecs;
558 u16 maxp;
559 u16 raw_mask;
560 unsigned bandwidth;
561
562 /* This is used to initialize iTD's hw_bufp fields */
563 __hc32 buf0;
564 __hc32 buf1;
565 __hc32 buf2;
566
567 /* this is used to initialize sITD's tt info */
568 __hc32 address;
569};
570
571/*-------------------------------------------------------------------------*/
572
573/*
574 * EHCI Specification 0.95 Section 3.3
575 * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
576 *
577 * Schedule records for high speed iso xfers
578 */
579struct fusbh200_itd {
580 /* first part defined by EHCI spec */
581 __hc32 hw_next; /* see EHCI 3.3.1 */
582 __hc32 hw_transaction [8]; /* see EHCI 3.3.2 */
583#define FUSBH200_ISOC_ACTIVE (1<<31) /* activate transfer this slot */
584#define FUSBH200_ISOC_BUF_ERR (1<<30) /* Data buffer error */
585#define FUSBH200_ISOC_BABBLE (1<<29) /* babble detected */
586#define FUSBH200_ISOC_XACTERR (1<<28) /* XactErr - transaction error */
587#define FUSBH200_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff)
588#define FUSBH200_ITD_IOC (1 << 15) /* interrupt on complete */
589
590#define ITD_ACTIVE(fusbh200) cpu_to_hc32(fusbh200, FUSBH200_ISOC_ACTIVE)
591
592 __hc32 hw_bufp [7]; /* see EHCI 3.3.3 */
593 __hc32 hw_bufp_hi [7]; /* Appendix B */
594
595 /* the rest is HCD-private */
596 dma_addr_t itd_dma; /* for this itd */
597 union fusbh200_shadow itd_next; /* ptr to periodic q entry */
598
599 struct urb *urb;
600 struct fusbh200_iso_stream *stream; /* endpoint's queue */
601 struct list_head itd_list; /* list of stream's itds */
602
603 /* any/all hw_transactions here may be used by that urb */
604 unsigned frame; /* where scheduled */
605 unsigned pg;
606 unsigned index[8]; /* in urb->iso_frame_desc */
607} __attribute__ ((aligned (32)));
608
609/*-------------------------------------------------------------------------*/
610
611/*
612 * EHCI Specification 0.96 Section 3.7
613 * Periodic Frame Span Traversal Node (FSTN)
614 *
615 * Manages split interrupt transactions (using TT) that span frame boundaries
616 * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN
617 * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
618 * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
619 */
620struct fusbh200_fstn {
621 __hc32 hw_next; /* any periodic q entry */
622 __hc32 hw_prev; /* qh or FUSBH200_LIST_END */
623
624 /* the rest is HCD-private */
625 dma_addr_t fstn_dma;
626 union fusbh200_shadow fstn_next; /* ptr to periodic q entry */
627} __attribute__ ((aligned (32)));
628
629/*-------------------------------------------------------------------------*/
630
631/* Prepare the PORTSC wakeup flags during controller suspend/resume */
632
633#define fusbh200_prepare_ports_for_controller_suspend(fusbh200, do_wakeup) \
634 fusbh200_adjust_port_wakeup_flags(fusbh200, true, do_wakeup);
635
636#define fusbh200_prepare_ports_for_controller_resume(fusbh200) \
637 fusbh200_adjust_port_wakeup_flags(fusbh200, false, false);
638
639/*-------------------------------------------------------------------------*/
640
641/*
642 * Some EHCI controllers have a Transaction Translator built into the
643 * root hub. This is a non-standard feature. Each controller will need
644 * to add code to the following inline functions, and call them as
645 * needed (mostly in root hub code).
646 */
647
648static inline unsigned int
649fusbh200_get_speed(struct fusbh200_hcd *fusbh200, unsigned int portsc)
650{
651 return (readl(&fusbh200->regs->bmcsr)
652 & BMCSR_HOST_SPD_TYP) >> 9;
653}
654
655/* Returns the speed of a device attached to a port on the root hub. */
656static inline unsigned int
657fusbh200_port_speed(struct fusbh200_hcd *fusbh200, unsigned int portsc)
658{
659 switch (fusbh200_get_speed(fusbh200, portsc)) {
660 case 0:
661 return 0;
662 case 1:
663 return USB_PORT_STAT_LOW_SPEED;
664 case 2:
665 default:
666 return USB_PORT_STAT_HIGH_SPEED;
667 }
668}
669
670/*-------------------------------------------------------------------------*/
671
672#define fusbh200_has_fsl_portno_bug(e) (0)
673
674/*
675 * While most USB host controllers implement their registers in
676 * little-endian format, a minority (celleb companion chip) implement
677 * them in big endian format.
678 *
679 * This attempts to support either format at compile time without a
680 * runtime penalty, or both formats with the additional overhead
681 * of checking a flag bit.
682 *
683 */
684
685#define fusbh200_big_endian_mmio(e) 0
686#define fusbh200_big_endian_capbase(e) 0
687
688static inline unsigned int fusbh200_readl(const struct fusbh200_hcd *fusbh200,
689 __u32 __iomem * regs)
690{
691 return readl(regs);
692}
693
694static inline void fusbh200_writel(const struct fusbh200_hcd *fusbh200,
695 const unsigned int val, __u32 __iomem *regs)
696{
697 writel(val, regs);
698}
699
700/* cpu to fusbh200 */
701static inline __hc32 cpu_to_hc32 (const struct fusbh200_hcd *fusbh200, const u32 x)
702{
703 return cpu_to_le32(x);
704}
705
706/* fusbh200 to cpu */
707static inline u32 hc32_to_cpu (const struct fusbh200_hcd *fusbh200, const __hc32 x)
708{
709 return le32_to_cpu(x);
710}
711
712static inline u32 hc32_to_cpup (const struct fusbh200_hcd *fusbh200, const __hc32 *x)
713{
714 return le32_to_cpup(x);
715}
716
717/*-------------------------------------------------------------------------*/
718
719static inline unsigned fusbh200_read_frame_index(struct fusbh200_hcd *fusbh200)
720{
721 return fusbh200_readl(fusbh200, &fusbh200->regs->frame_index);
722}
723
724#define fusbh200_itdlen(urb, desc, t) ({ \
725 usb_pipein((urb)->pipe) ? \
726 (desc)->length - FUSBH200_ITD_LENGTH(t) : \
727 FUSBH200_ITD_LENGTH(t); \
728})
729/*-------------------------------------------------------------------------*/
730
731#endif /* __LINUX_FUSBH200_H */