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1/*
2 * Driver for Motorola IMX serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Author: Sascha Hauer <sascha@saschahauer.de>
7 * Copyright (C) 2004 Pengutronix
8 *
9 * Copyright (C) 2009 emlix GmbH
10 * Author: Fabian Godehardt (added IrDA support for iMX)
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 * [29-Mar-2005] Mike Lee
27 * Added hardware handshake
28 */
29
30#if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
31#define SUPPORT_SYSRQ
32#endif
33
34#include <linux/module.h>
35#include <linux/ioport.h>
36#include <linux/init.h>
37#include <linux/console.h>
38#include <linux/sysrq.h>
39#include <linux/platform_device.h>
40#include <linux/tty.h>
41#include <linux/tty_flip.h>
42#include <linux/serial_core.h>
43#include <linux/serial.h>
44#include <linux/clk.h>
45#include <linux/delay.h>
46#include <linux/rational.h>
47#include <linux/slab.h>
48#include <linux/of.h>
49#include <linux/of_device.h>
50
51#include <asm/io.h>
52#include <asm/irq.h>
53#include <mach/imx-uart.h>
54
55/* Register definitions */
56#define URXD0 0x0 /* Receiver Register */
57#define URTX0 0x40 /* Transmitter Register */
58#define UCR1 0x80 /* Control Register 1 */
59#define UCR2 0x84 /* Control Register 2 */
60#define UCR3 0x88 /* Control Register 3 */
61#define UCR4 0x8c /* Control Register 4 */
62#define UFCR 0x90 /* FIFO Control Register */
63#define USR1 0x94 /* Status Register 1 */
64#define USR2 0x98 /* Status Register 2 */
65#define UESC 0x9c /* Escape Character Register */
66#define UTIM 0xa0 /* Escape Timer Register */
67#define UBIR 0xa4 /* BRM Incremental Register */
68#define UBMR 0xa8 /* BRM Modulator Register */
69#define UBRC 0xac /* Baud Rate Count Register */
70#define IMX21_ONEMS 0xb0 /* One Millisecond register */
71#define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
72#define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
73
74/* UART Control Register Bit Fields.*/
75#define URXD_CHARRDY (1<<15)
76#define URXD_ERR (1<<14)
77#define URXD_OVRRUN (1<<13)
78#define URXD_FRMERR (1<<12)
79#define URXD_BRK (1<<11)
80#define URXD_PRERR (1<<10)
81#define UCR1_ADEN (1<<15) /* Auto detect interrupt */
82#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
83#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
84#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
85#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
86#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
87#define UCR1_IREN (1<<7) /* Infrared interface enable */
88#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
89#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
90#define UCR1_SNDBRK (1<<4) /* Send break */
91#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
92#define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
93#define UCR1_DOZE (1<<1) /* Doze */
94#define UCR1_UARTEN (1<<0) /* UART enabled */
95#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
96#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
97#define UCR2_CTSC (1<<13) /* CTS pin control */
98#define UCR2_CTS (1<<12) /* Clear to send */
99#define UCR2_ESCEN (1<<11) /* Escape enable */
100#define UCR2_PREN (1<<8) /* Parity enable */
101#define UCR2_PROE (1<<7) /* Parity odd/even */
102#define UCR2_STPB (1<<6) /* Stop */
103#define UCR2_WS (1<<5) /* Word size */
104#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
105#define UCR2_TXEN (1<<2) /* Transmitter enabled */
106#define UCR2_RXEN (1<<1) /* Receiver enabled */
107#define UCR2_SRST (1<<0) /* SW reset */
108#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
109#define UCR3_PARERREN (1<<12) /* Parity enable */
110#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
111#define UCR3_DSR (1<<10) /* Data set ready */
112#define UCR3_DCD (1<<9) /* Data carrier detect */
113#define UCR3_RI (1<<8) /* Ring indicator */
114#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
115#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
116#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
117#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
118#define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
119#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
120#define UCR3_BPEN (1<<0) /* Preset registers enable */
121#define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
122#define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
123#define UCR4_INVR (1<<9) /* Inverted infrared reception */
124#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
125#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
126#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
127#define UCR4_IRSC (1<<5) /* IR special case */
128#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
129#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
130#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
131#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
132#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
133#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
134#define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
135#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
136#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
137#define USR1_RTSS (1<<14) /* RTS pin status */
138#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
139#define USR1_RTSD (1<<12) /* RTS delta */
140#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
141#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
142#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
143#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
144#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
145#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
146#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
147#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
148#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
149#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
150#define USR2_IDLE (1<<12) /* Idle condition */
151#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
152#define USR2_WAKE (1<<7) /* Wake */
153#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
154#define USR2_TXDC (1<<3) /* Transmitter complete */
155#define USR2_BRCD (1<<2) /* Break condition */
156#define USR2_ORE (1<<1) /* Overrun error */
157#define USR2_RDR (1<<0) /* Recv data ready */
158#define UTS_FRCPERR (1<<13) /* Force parity error */
159#define UTS_LOOP (1<<12) /* Loop tx and rx */
160#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
161#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
162#define UTS_TXFULL (1<<4) /* TxFIFO full */
163#define UTS_RXFULL (1<<3) /* RxFIFO full */
164#define UTS_SOFTRST (1<<0) /* Software reset */
165
166/* We've been assigned a range on the "Low-density serial ports" major */
167#define SERIAL_IMX_MAJOR 207
168#define MINOR_START 16
169#define DEV_NAME "ttymxc"
170#define MAX_INTERNAL_IRQ MXC_INTERNAL_IRQS
171
172/*
173 * This determines how often we check the modem status signals
174 * for any change. They generally aren't connected to an IRQ
175 * so we have to poll them. We also check immediately before
176 * filling the TX fifo incase CTS has been dropped.
177 */
178#define MCTRL_TIMEOUT (250*HZ/1000)
179
180#define DRIVER_NAME "IMX-uart"
181
182#define UART_NR 8
183
184/* i.mx21 type uart runs on all i.mx except i.mx1 */
185enum imx_uart_type {
186 IMX1_UART,
187 IMX21_UART,
188};
189
190/* device type dependent stuff */
191struct imx_uart_data {
192 unsigned uts_reg;
193 enum imx_uart_type devtype;
194};
195
196struct imx_port {
197 struct uart_port port;
198 struct timer_list timer;
199 unsigned int old_status;
200 int txirq,rxirq,rtsirq;
201 unsigned int have_rtscts:1;
202 unsigned int use_irda:1;
203 unsigned int irda_inv_rx:1;
204 unsigned int irda_inv_tx:1;
205 unsigned short trcv_delay; /* transceiver delay */
206 struct clk *clk;
207 struct imx_uart_data *devdata;
208};
209
210#ifdef CONFIG_IRDA
211#define USE_IRDA(sport) ((sport)->use_irda)
212#else
213#define USE_IRDA(sport) (0)
214#endif
215
216static struct imx_uart_data imx_uart_devdata[] = {
217 [IMX1_UART] = {
218 .uts_reg = IMX1_UTS,
219 .devtype = IMX1_UART,
220 },
221 [IMX21_UART] = {
222 .uts_reg = IMX21_UTS,
223 .devtype = IMX21_UART,
224 },
225};
226
227static struct platform_device_id imx_uart_devtype[] = {
228 {
229 .name = "imx1-uart",
230 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
231 }, {
232 .name = "imx21-uart",
233 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
234 }, {
235 /* sentinel */
236 }
237};
238MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
239
240static struct of_device_id imx_uart_dt_ids[] = {
241 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
242 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
243 { /* sentinel */ }
244};
245MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
246
247static inline unsigned uts_reg(struct imx_port *sport)
248{
249 return sport->devdata->uts_reg;
250}
251
252static inline int is_imx1_uart(struct imx_port *sport)
253{
254 return sport->devdata->devtype == IMX1_UART;
255}
256
257static inline int is_imx21_uart(struct imx_port *sport)
258{
259 return sport->devdata->devtype == IMX21_UART;
260}
261
262/*
263 * Handle any change of modem status signal since we were last called.
264 */
265static void imx_mctrl_check(struct imx_port *sport)
266{
267 unsigned int status, changed;
268
269 status = sport->port.ops->get_mctrl(&sport->port);
270 changed = status ^ sport->old_status;
271
272 if (changed == 0)
273 return;
274
275 sport->old_status = status;
276
277 if (changed & TIOCM_RI)
278 sport->port.icount.rng++;
279 if (changed & TIOCM_DSR)
280 sport->port.icount.dsr++;
281 if (changed & TIOCM_CAR)
282 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
283 if (changed & TIOCM_CTS)
284 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
285
286 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
287}
288
289/*
290 * This is our per-port timeout handler, for checking the
291 * modem status signals.
292 */
293static void imx_timeout(unsigned long data)
294{
295 struct imx_port *sport = (struct imx_port *)data;
296 unsigned long flags;
297
298 if (sport->port.state) {
299 spin_lock_irqsave(&sport->port.lock, flags);
300 imx_mctrl_check(sport);
301 spin_unlock_irqrestore(&sport->port.lock, flags);
302
303 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
304 }
305}
306
307/*
308 * interrupts disabled on entry
309 */
310static void imx_stop_tx(struct uart_port *port)
311{
312 struct imx_port *sport = (struct imx_port *)port;
313 unsigned long temp;
314
315 if (USE_IRDA(sport)) {
316 /* half duplex - wait for end of transmission */
317 int n = 256;
318 while ((--n > 0) &&
319 !(readl(sport->port.membase + USR2) & USR2_TXDC)) {
320 udelay(5);
321 barrier();
322 }
323 /*
324 * irda transceiver - wait a bit more to avoid
325 * cutoff, hardware dependent
326 */
327 udelay(sport->trcv_delay);
328
329 /*
330 * half duplex - reactivate receive mode,
331 * flush receive pipe echo crap
332 */
333 if (readl(sport->port.membase + USR2) & USR2_TXDC) {
334 temp = readl(sport->port.membase + UCR1);
335 temp &= ~(UCR1_TXMPTYEN | UCR1_TRDYEN);
336 writel(temp, sport->port.membase + UCR1);
337
338 temp = readl(sport->port.membase + UCR4);
339 temp &= ~(UCR4_TCEN);
340 writel(temp, sport->port.membase + UCR4);
341
342 while (readl(sport->port.membase + URXD0) &
343 URXD_CHARRDY)
344 barrier();
345
346 temp = readl(sport->port.membase + UCR1);
347 temp |= UCR1_RRDYEN;
348 writel(temp, sport->port.membase + UCR1);
349
350 temp = readl(sport->port.membase + UCR4);
351 temp |= UCR4_DREN;
352 writel(temp, sport->port.membase + UCR4);
353 }
354 return;
355 }
356
357 temp = readl(sport->port.membase + UCR1);
358 writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);
359}
360
361/*
362 * interrupts disabled on entry
363 */
364static void imx_stop_rx(struct uart_port *port)
365{
366 struct imx_port *sport = (struct imx_port *)port;
367 unsigned long temp;
368
369 temp = readl(sport->port.membase + UCR2);
370 writel(temp &~ UCR2_RXEN, sport->port.membase + UCR2);
371}
372
373/*
374 * Set the modem control timer to fire immediately.
375 */
376static void imx_enable_ms(struct uart_port *port)
377{
378 struct imx_port *sport = (struct imx_port *)port;
379
380 mod_timer(&sport->timer, jiffies);
381}
382
383static inline void imx_transmit_buffer(struct imx_port *sport)
384{
385 struct circ_buf *xmit = &sport->port.state->xmit;
386
387 while (!uart_circ_empty(xmit) &&
388 !(readl(sport->port.membase + uts_reg(sport))
389 & UTS_TXFULL)) {
390 /* send xmit->buf[xmit->tail]
391 * out the port here */
392 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
393 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
394 sport->port.icount.tx++;
395 }
396
397 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
398 uart_write_wakeup(&sport->port);
399
400 if (uart_circ_empty(xmit))
401 imx_stop_tx(&sport->port);
402}
403
404/*
405 * interrupts disabled on entry
406 */
407static void imx_start_tx(struct uart_port *port)
408{
409 struct imx_port *sport = (struct imx_port *)port;
410 unsigned long temp;
411
412 if (USE_IRDA(sport)) {
413 /* half duplex in IrDA mode; have to disable receive mode */
414 temp = readl(sport->port.membase + UCR4);
415 temp &= ~(UCR4_DREN);
416 writel(temp, sport->port.membase + UCR4);
417
418 temp = readl(sport->port.membase + UCR1);
419 temp &= ~(UCR1_RRDYEN);
420 writel(temp, sport->port.membase + UCR1);
421 }
422
423 temp = readl(sport->port.membase + UCR1);
424 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
425
426 if (USE_IRDA(sport)) {
427 temp = readl(sport->port.membase + UCR1);
428 temp |= UCR1_TRDYEN;
429 writel(temp, sport->port.membase + UCR1);
430
431 temp = readl(sport->port.membase + UCR4);
432 temp |= UCR4_TCEN;
433 writel(temp, sport->port.membase + UCR4);
434 }
435
436 if (readl(sport->port.membase + uts_reg(sport)) & UTS_TXEMPTY)
437 imx_transmit_buffer(sport);
438}
439
440static irqreturn_t imx_rtsint(int irq, void *dev_id)
441{
442 struct imx_port *sport = dev_id;
443 unsigned int val;
444 unsigned long flags;
445
446 spin_lock_irqsave(&sport->port.lock, flags);
447
448 writel(USR1_RTSD, sport->port.membase + USR1);
449 val = readl(sport->port.membase + USR1) & USR1_RTSS;
450 uart_handle_cts_change(&sport->port, !!val);
451 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
452
453 spin_unlock_irqrestore(&sport->port.lock, flags);
454 return IRQ_HANDLED;
455}
456
457static irqreturn_t imx_txint(int irq, void *dev_id)
458{
459 struct imx_port *sport = dev_id;
460 struct circ_buf *xmit = &sport->port.state->xmit;
461 unsigned long flags;
462
463 spin_lock_irqsave(&sport->port.lock,flags);
464 if (sport->port.x_char)
465 {
466 /* Send next char */
467 writel(sport->port.x_char, sport->port.membase + URTX0);
468 goto out;
469 }
470
471 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
472 imx_stop_tx(&sport->port);
473 goto out;
474 }
475
476 imx_transmit_buffer(sport);
477
478 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
479 uart_write_wakeup(&sport->port);
480
481out:
482 spin_unlock_irqrestore(&sport->port.lock,flags);
483 return IRQ_HANDLED;
484}
485
486static irqreturn_t imx_rxint(int irq, void *dev_id)
487{
488 struct imx_port *sport = dev_id;
489 unsigned int rx,flg,ignored = 0;
490 struct tty_struct *tty = sport->port.state->port.tty;
491 unsigned long flags, temp;
492
493 spin_lock_irqsave(&sport->port.lock,flags);
494
495 while (readl(sport->port.membase + USR2) & USR2_RDR) {
496 flg = TTY_NORMAL;
497 sport->port.icount.rx++;
498
499 rx = readl(sport->port.membase + URXD0);
500
501 temp = readl(sport->port.membase + USR2);
502 if (temp & USR2_BRCD) {
503 writel(USR2_BRCD, sport->port.membase + USR2);
504 if (uart_handle_break(&sport->port))
505 continue;
506 }
507
508 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
509 continue;
510
511 if (rx & (URXD_PRERR | URXD_OVRRUN | URXD_FRMERR) ) {
512 if (rx & URXD_PRERR)
513 sport->port.icount.parity++;
514 else if (rx & URXD_FRMERR)
515 sport->port.icount.frame++;
516 if (rx & URXD_OVRRUN)
517 sport->port.icount.overrun++;
518
519 if (rx & sport->port.ignore_status_mask) {
520 if (++ignored > 100)
521 goto out;
522 continue;
523 }
524
525 rx &= sport->port.read_status_mask;
526
527 if (rx & URXD_PRERR)
528 flg = TTY_PARITY;
529 else if (rx & URXD_FRMERR)
530 flg = TTY_FRAME;
531 if (rx & URXD_OVRRUN)
532 flg = TTY_OVERRUN;
533
534#ifdef SUPPORT_SYSRQ
535 sport->port.sysrq = 0;
536#endif
537 }
538
539 tty_insert_flip_char(tty, rx, flg);
540 }
541
542out:
543 spin_unlock_irqrestore(&sport->port.lock,flags);
544 tty_flip_buffer_push(tty);
545 return IRQ_HANDLED;
546}
547
548static irqreturn_t imx_int(int irq, void *dev_id)
549{
550 struct imx_port *sport = dev_id;
551 unsigned int sts;
552
553 sts = readl(sport->port.membase + USR1);
554
555 if (sts & USR1_RRDY)
556 imx_rxint(irq, dev_id);
557
558 if (sts & USR1_TRDY &&
559 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN)
560 imx_txint(irq, dev_id);
561
562 if (sts & USR1_RTSD)
563 imx_rtsint(irq, dev_id);
564
565 return IRQ_HANDLED;
566}
567
568/*
569 * Return TIOCSER_TEMT when transmitter is not busy.
570 */
571static unsigned int imx_tx_empty(struct uart_port *port)
572{
573 struct imx_port *sport = (struct imx_port *)port;
574
575 return (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
576}
577
578/*
579 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
580 */
581static unsigned int imx_get_mctrl(struct uart_port *port)
582{
583 struct imx_port *sport = (struct imx_port *)port;
584 unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
585
586 if (readl(sport->port.membase + USR1) & USR1_RTSS)
587 tmp |= TIOCM_CTS;
588
589 if (readl(sport->port.membase + UCR2) & UCR2_CTS)
590 tmp |= TIOCM_RTS;
591
592 return tmp;
593}
594
595static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
596{
597 struct imx_port *sport = (struct imx_port *)port;
598 unsigned long temp;
599
600 temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS;
601
602 if (mctrl & TIOCM_RTS)
603 temp |= UCR2_CTS;
604
605 writel(temp, sport->port.membase + UCR2);
606}
607
608/*
609 * Interrupts always disabled.
610 */
611static void imx_break_ctl(struct uart_port *port, int break_state)
612{
613 struct imx_port *sport = (struct imx_port *)port;
614 unsigned long flags, temp;
615
616 spin_lock_irqsave(&sport->port.lock, flags);
617
618 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
619
620 if ( break_state != 0 )
621 temp |= UCR1_SNDBRK;
622
623 writel(temp, sport->port.membase + UCR1);
624
625 spin_unlock_irqrestore(&sport->port.lock, flags);
626}
627
628#define TXTL 2 /* reset default */
629#define RXTL 1 /* reset default */
630
631static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
632{
633 unsigned int val;
634 unsigned int ufcr_rfdiv;
635
636 /* set receiver / transmitter trigger level.
637 * RFDIV is set such way to satisfy requested uartclk value
638 */
639 val = TXTL << 10 | RXTL;
640 ufcr_rfdiv = (clk_get_rate(sport->clk) + sport->port.uartclk / 2)
641 / sport->port.uartclk;
642
643 if(!ufcr_rfdiv)
644 ufcr_rfdiv = 1;
645
646 val |= UFCR_RFDIV_REG(ufcr_rfdiv);
647
648 writel(val, sport->port.membase + UFCR);
649
650 return 0;
651}
652
653/* half the RX buffer size */
654#define CTSTL 16
655
656static int imx_startup(struct uart_port *port)
657{
658 struct imx_port *sport = (struct imx_port *)port;
659 int retval;
660 unsigned long flags, temp;
661
662 imx_setup_ufcr(sport, 0);
663
664 /* disable the DREN bit (Data Ready interrupt enable) before
665 * requesting IRQs
666 */
667 temp = readl(sport->port.membase + UCR4);
668
669 if (USE_IRDA(sport))
670 temp |= UCR4_IRSC;
671
672 /* set the trigger level for CTS */
673 temp &= ~(UCR4_CTSTL_MASK<< UCR4_CTSTL_SHF);
674 temp |= CTSTL<< UCR4_CTSTL_SHF;
675
676 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
677
678 if (USE_IRDA(sport)) {
679 /* reset fifo's and state machines */
680 int i = 100;
681 temp = readl(sport->port.membase + UCR2);
682 temp &= ~UCR2_SRST;
683 writel(temp, sport->port.membase + UCR2);
684 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) &&
685 (--i > 0)) {
686 udelay(1);
687 }
688 }
689
690 /*
691 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
692 * chips only have one interrupt.
693 */
694 if (sport->txirq > 0) {
695 retval = request_irq(sport->rxirq, imx_rxint, 0,
696 DRIVER_NAME, sport);
697 if (retval)
698 goto error_out1;
699
700 retval = request_irq(sport->txirq, imx_txint, 0,
701 DRIVER_NAME, sport);
702 if (retval)
703 goto error_out2;
704
705 /* do not use RTS IRQ on IrDA */
706 if (!USE_IRDA(sport)) {
707 retval = request_irq(sport->rtsirq, imx_rtsint,
708 (sport->rtsirq < MAX_INTERNAL_IRQ) ? 0 :
709 IRQF_TRIGGER_FALLING |
710 IRQF_TRIGGER_RISING,
711 DRIVER_NAME, sport);
712 if (retval)
713 goto error_out3;
714 }
715 } else {
716 retval = request_irq(sport->port.irq, imx_int, 0,
717 DRIVER_NAME, sport);
718 if (retval) {
719 free_irq(sport->port.irq, sport);
720 goto error_out1;
721 }
722 }
723
724 /*
725 * Finally, clear and enable interrupts
726 */
727 writel(USR1_RTSD, sport->port.membase + USR1);
728
729 temp = readl(sport->port.membase + UCR1);
730 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
731
732 if (USE_IRDA(sport)) {
733 temp |= UCR1_IREN;
734 temp &= ~(UCR1_RTSDEN);
735 }
736
737 writel(temp, sport->port.membase + UCR1);
738
739 temp = readl(sport->port.membase + UCR2);
740 temp |= (UCR2_RXEN | UCR2_TXEN);
741 writel(temp, sport->port.membase + UCR2);
742
743 if (USE_IRDA(sport)) {
744 /* clear RX-FIFO */
745 int i = 64;
746 while ((--i > 0) &&
747 (readl(sport->port.membase + URXD0) & URXD_CHARRDY)) {
748 barrier();
749 }
750 }
751
752 if (is_imx21_uart(sport)) {
753 temp = readl(sport->port.membase + UCR3);
754 temp |= IMX21_UCR3_RXDMUXSEL;
755 writel(temp, sport->port.membase + UCR3);
756 }
757
758 if (USE_IRDA(sport)) {
759 temp = readl(sport->port.membase + UCR4);
760 if (sport->irda_inv_rx)
761 temp |= UCR4_INVR;
762 else
763 temp &= ~(UCR4_INVR);
764 writel(temp | UCR4_DREN, sport->port.membase + UCR4);
765
766 temp = readl(sport->port.membase + UCR3);
767 if (sport->irda_inv_tx)
768 temp |= UCR3_INVT;
769 else
770 temp &= ~(UCR3_INVT);
771 writel(temp, sport->port.membase + UCR3);
772 }
773
774 /*
775 * Enable modem status interrupts
776 */
777 spin_lock_irqsave(&sport->port.lock,flags);
778 imx_enable_ms(&sport->port);
779 spin_unlock_irqrestore(&sport->port.lock,flags);
780
781 if (USE_IRDA(sport)) {
782 struct imxuart_platform_data *pdata;
783 pdata = sport->port.dev->platform_data;
784 sport->irda_inv_rx = pdata->irda_inv_rx;
785 sport->irda_inv_tx = pdata->irda_inv_tx;
786 sport->trcv_delay = pdata->transceiver_delay;
787 if (pdata->irda_enable)
788 pdata->irda_enable(1);
789 }
790
791 return 0;
792
793error_out3:
794 if (sport->txirq)
795 free_irq(sport->txirq, sport);
796error_out2:
797 if (sport->rxirq)
798 free_irq(sport->rxirq, sport);
799error_out1:
800 return retval;
801}
802
803static void imx_shutdown(struct uart_port *port)
804{
805 struct imx_port *sport = (struct imx_port *)port;
806 unsigned long temp;
807
808 temp = readl(sport->port.membase + UCR2);
809 temp &= ~(UCR2_TXEN);
810 writel(temp, sport->port.membase + UCR2);
811
812 if (USE_IRDA(sport)) {
813 struct imxuart_platform_data *pdata;
814 pdata = sport->port.dev->platform_data;
815 if (pdata->irda_enable)
816 pdata->irda_enable(0);
817 }
818
819 /*
820 * Stop our timer.
821 */
822 del_timer_sync(&sport->timer);
823
824 /*
825 * Free the interrupts
826 */
827 if (sport->txirq > 0) {
828 if (!USE_IRDA(sport))
829 free_irq(sport->rtsirq, sport);
830 free_irq(sport->txirq, sport);
831 free_irq(sport->rxirq, sport);
832 } else
833 free_irq(sport->port.irq, sport);
834
835 /*
836 * Disable all interrupts, port and break condition.
837 */
838
839 temp = readl(sport->port.membase + UCR1);
840 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
841 if (USE_IRDA(sport))
842 temp &= ~(UCR1_IREN);
843
844 writel(temp, sport->port.membase + UCR1);
845}
846
847static void
848imx_set_termios(struct uart_port *port, struct ktermios *termios,
849 struct ktermios *old)
850{
851 struct imx_port *sport = (struct imx_port *)port;
852 unsigned long flags;
853 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
854 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
855 unsigned int div, ufcr;
856 unsigned long num, denom;
857 uint64_t tdiv64;
858
859 /*
860 * If we don't support modem control lines, don't allow
861 * these to be set.
862 */
863 if (0) {
864 termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
865 termios->c_cflag |= CLOCAL;
866 }
867
868 /*
869 * We only support CS7 and CS8.
870 */
871 while ((termios->c_cflag & CSIZE) != CS7 &&
872 (termios->c_cflag & CSIZE) != CS8) {
873 termios->c_cflag &= ~CSIZE;
874 termios->c_cflag |= old_csize;
875 old_csize = CS8;
876 }
877
878 if ((termios->c_cflag & CSIZE) == CS8)
879 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
880 else
881 ucr2 = UCR2_SRST | UCR2_IRTS;
882
883 if (termios->c_cflag & CRTSCTS) {
884 if( sport->have_rtscts ) {
885 ucr2 &= ~UCR2_IRTS;
886 ucr2 |= UCR2_CTSC;
887 } else {
888 termios->c_cflag &= ~CRTSCTS;
889 }
890 }
891
892 if (termios->c_cflag & CSTOPB)
893 ucr2 |= UCR2_STPB;
894 if (termios->c_cflag & PARENB) {
895 ucr2 |= UCR2_PREN;
896 if (termios->c_cflag & PARODD)
897 ucr2 |= UCR2_PROE;
898 }
899
900 /*
901 * Ask the core to calculate the divisor for us.
902 */
903 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
904 quot = uart_get_divisor(port, baud);
905
906 spin_lock_irqsave(&sport->port.lock, flags);
907
908 sport->port.read_status_mask = 0;
909 if (termios->c_iflag & INPCK)
910 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
911 if (termios->c_iflag & (BRKINT | PARMRK))
912 sport->port.read_status_mask |= URXD_BRK;
913
914 /*
915 * Characters to ignore
916 */
917 sport->port.ignore_status_mask = 0;
918 if (termios->c_iflag & IGNPAR)
919 sport->port.ignore_status_mask |= URXD_PRERR;
920 if (termios->c_iflag & IGNBRK) {
921 sport->port.ignore_status_mask |= URXD_BRK;
922 /*
923 * If we're ignoring parity and break indicators,
924 * ignore overruns too (for real raw support).
925 */
926 if (termios->c_iflag & IGNPAR)
927 sport->port.ignore_status_mask |= URXD_OVRRUN;
928 }
929
930 del_timer_sync(&sport->timer);
931
932 /*
933 * Update the per-port timeout.
934 */
935 uart_update_timeout(port, termios->c_cflag, baud);
936
937 /*
938 * disable interrupts and drain transmitter
939 */
940 old_ucr1 = readl(sport->port.membase + UCR1);
941 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
942 sport->port.membase + UCR1);
943
944 while ( !(readl(sport->port.membase + USR2) & USR2_TXDC))
945 barrier();
946
947 /* then, disable everything */
948 old_txrxen = readl(sport->port.membase + UCR2);
949 writel(old_txrxen & ~( UCR2_TXEN | UCR2_RXEN),
950 sport->port.membase + UCR2);
951 old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
952
953 if (USE_IRDA(sport)) {
954 /*
955 * use maximum available submodule frequency to
956 * avoid missing short pulses due to low sampling rate
957 */
958 div = 1;
959 } else {
960 div = sport->port.uartclk / (baud * 16);
961 if (div > 7)
962 div = 7;
963 if (!div)
964 div = 1;
965 }
966
967 rational_best_approximation(16 * div * baud, sport->port.uartclk,
968 1 << 16, 1 << 16, &num, &denom);
969
970 tdiv64 = sport->port.uartclk;
971 tdiv64 *= num;
972 do_div(tdiv64, denom * 16 * div);
973 tty_termios_encode_baud_rate(termios,
974 (speed_t)tdiv64, (speed_t)tdiv64);
975
976 num -= 1;
977 denom -= 1;
978
979 ufcr = readl(sport->port.membase + UFCR);
980 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
981 writel(ufcr, sport->port.membase + UFCR);
982
983 writel(num, sport->port.membase + UBIR);
984 writel(denom, sport->port.membase + UBMR);
985
986 if (is_imx21_uart(sport))
987 writel(sport->port.uartclk / div / 1000,
988 sport->port.membase + IMX21_ONEMS);
989
990 writel(old_ucr1, sport->port.membase + UCR1);
991
992 /* set the parity, stop bits and data size */
993 writel(ucr2 | old_txrxen, sport->port.membase + UCR2);
994
995 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
996 imx_enable_ms(&sport->port);
997
998 spin_unlock_irqrestore(&sport->port.lock, flags);
999}
1000
1001static const char *imx_type(struct uart_port *port)
1002{
1003 struct imx_port *sport = (struct imx_port *)port;
1004
1005 return sport->port.type == PORT_IMX ? "IMX" : NULL;
1006}
1007
1008/*
1009 * Release the memory region(s) being used by 'port'.
1010 */
1011static void imx_release_port(struct uart_port *port)
1012{
1013 struct platform_device *pdev = to_platform_device(port->dev);
1014 struct resource *mmres;
1015
1016 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1017 release_mem_region(mmres->start, resource_size(mmres));
1018}
1019
1020/*
1021 * Request the memory region(s) being used by 'port'.
1022 */
1023static int imx_request_port(struct uart_port *port)
1024{
1025 struct platform_device *pdev = to_platform_device(port->dev);
1026 struct resource *mmres;
1027 void *ret;
1028
1029 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1030 if (!mmres)
1031 return -ENODEV;
1032
1033 ret = request_mem_region(mmres->start, resource_size(mmres), "imx-uart");
1034
1035 return ret ? 0 : -EBUSY;
1036}
1037
1038/*
1039 * Configure/autoconfigure the port.
1040 */
1041static void imx_config_port(struct uart_port *port, int flags)
1042{
1043 struct imx_port *sport = (struct imx_port *)port;
1044
1045 if (flags & UART_CONFIG_TYPE &&
1046 imx_request_port(&sport->port) == 0)
1047 sport->port.type = PORT_IMX;
1048}
1049
1050/*
1051 * Verify the new serial_struct (for TIOCSSERIAL).
1052 * The only change we allow are to the flags and type, and
1053 * even then only between PORT_IMX and PORT_UNKNOWN
1054 */
1055static int
1056imx_verify_port(struct uart_port *port, struct serial_struct *ser)
1057{
1058 struct imx_port *sport = (struct imx_port *)port;
1059 int ret = 0;
1060
1061 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1062 ret = -EINVAL;
1063 if (sport->port.irq != ser->irq)
1064 ret = -EINVAL;
1065 if (ser->io_type != UPIO_MEM)
1066 ret = -EINVAL;
1067 if (sport->port.uartclk / 16 != ser->baud_base)
1068 ret = -EINVAL;
1069 if ((void *)sport->port.mapbase != ser->iomem_base)
1070 ret = -EINVAL;
1071 if (sport->port.iobase != ser->port)
1072 ret = -EINVAL;
1073 if (ser->hub6 != 0)
1074 ret = -EINVAL;
1075 return ret;
1076}
1077
1078static struct uart_ops imx_pops = {
1079 .tx_empty = imx_tx_empty,
1080 .set_mctrl = imx_set_mctrl,
1081 .get_mctrl = imx_get_mctrl,
1082 .stop_tx = imx_stop_tx,
1083 .start_tx = imx_start_tx,
1084 .stop_rx = imx_stop_rx,
1085 .enable_ms = imx_enable_ms,
1086 .break_ctl = imx_break_ctl,
1087 .startup = imx_startup,
1088 .shutdown = imx_shutdown,
1089 .set_termios = imx_set_termios,
1090 .type = imx_type,
1091 .release_port = imx_release_port,
1092 .request_port = imx_request_port,
1093 .config_port = imx_config_port,
1094 .verify_port = imx_verify_port,
1095};
1096
1097static struct imx_port *imx_ports[UART_NR];
1098
1099#ifdef CONFIG_SERIAL_IMX_CONSOLE
1100static void imx_console_putchar(struct uart_port *port, int ch)
1101{
1102 struct imx_port *sport = (struct imx_port *)port;
1103
1104 while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)
1105 barrier();
1106
1107 writel(ch, sport->port.membase + URTX0);
1108}
1109
1110/*
1111 * Interrupts are disabled on entering
1112 */
1113static void
1114imx_console_write(struct console *co, const char *s, unsigned int count)
1115{
1116 struct imx_port *sport = imx_ports[co->index];
1117 unsigned int old_ucr1, old_ucr2, ucr1;
1118
1119 /*
1120 * First, save UCR1/2 and then disable interrupts
1121 */
1122 ucr1 = old_ucr1 = readl(sport->port.membase + UCR1);
1123 old_ucr2 = readl(sport->port.membase + UCR2);
1124
1125 if (is_imx1_uart(sport))
1126 ucr1 |= IMX1_UCR1_UARTCLKEN;
1127 ucr1 |= UCR1_UARTEN;
1128 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1129
1130 writel(ucr1, sport->port.membase + UCR1);
1131
1132 writel(old_ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
1133
1134 uart_console_write(&sport->port, s, count, imx_console_putchar);
1135
1136 /*
1137 * Finally, wait for transmitter to become empty
1138 * and restore UCR1/2
1139 */
1140 while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
1141
1142 writel(old_ucr1, sport->port.membase + UCR1);
1143 writel(old_ucr2, sport->port.membase + UCR2);
1144}
1145
1146/*
1147 * If the port was already initialised (eg, by a boot loader),
1148 * try to determine the current setup.
1149 */
1150static void __init
1151imx_console_get_options(struct imx_port *sport, int *baud,
1152 int *parity, int *bits)
1153{
1154
1155 if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {
1156 /* ok, the port was enabled */
1157 unsigned int ucr2, ubir,ubmr, uartclk;
1158 unsigned int baud_raw;
1159 unsigned int ucfr_rfdiv;
1160
1161 ucr2 = readl(sport->port.membase + UCR2);
1162
1163 *parity = 'n';
1164 if (ucr2 & UCR2_PREN) {
1165 if (ucr2 & UCR2_PROE)
1166 *parity = 'o';
1167 else
1168 *parity = 'e';
1169 }
1170
1171 if (ucr2 & UCR2_WS)
1172 *bits = 8;
1173 else
1174 *bits = 7;
1175
1176 ubir = readl(sport->port.membase + UBIR) & 0xffff;
1177 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
1178
1179 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
1180 if (ucfr_rfdiv == 6)
1181 ucfr_rfdiv = 7;
1182 else
1183 ucfr_rfdiv = 6 - ucfr_rfdiv;
1184
1185 uartclk = clk_get_rate(sport->clk);
1186 uartclk /= ucfr_rfdiv;
1187
1188 { /*
1189 * The next code provides exact computation of
1190 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1191 * without need of float support or long long division,
1192 * which would be required to prevent 32bit arithmetic overflow
1193 */
1194 unsigned int mul = ubir + 1;
1195 unsigned int div = 16 * (ubmr + 1);
1196 unsigned int rem = uartclk % div;
1197
1198 baud_raw = (uartclk / div) * mul;
1199 baud_raw += (rem * mul + div / 2) / div;
1200 *baud = (baud_raw + 50) / 100 * 100;
1201 }
1202
1203 if(*baud != baud_raw)
1204 printk(KERN_INFO "Serial: Console IMX rounded baud rate from %d to %d\n",
1205 baud_raw, *baud);
1206 }
1207}
1208
1209static int __init
1210imx_console_setup(struct console *co, char *options)
1211{
1212 struct imx_port *sport;
1213 int baud = 9600;
1214 int bits = 8;
1215 int parity = 'n';
1216 int flow = 'n';
1217
1218 /*
1219 * Check whether an invalid uart number has been specified, and
1220 * if so, search for the first available port that does have
1221 * console support.
1222 */
1223 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1224 co->index = 0;
1225 sport = imx_ports[co->index];
1226 if(sport == NULL)
1227 return -ENODEV;
1228
1229 if (options)
1230 uart_parse_options(options, &baud, &parity, &bits, &flow);
1231 else
1232 imx_console_get_options(sport, &baud, &parity, &bits);
1233
1234 imx_setup_ufcr(sport, 0);
1235
1236 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
1237}
1238
1239static struct uart_driver imx_reg;
1240static struct console imx_console = {
1241 .name = DEV_NAME,
1242 .write = imx_console_write,
1243 .device = uart_console_device,
1244 .setup = imx_console_setup,
1245 .flags = CON_PRINTBUFFER,
1246 .index = -1,
1247 .data = &imx_reg,
1248};
1249
1250#define IMX_CONSOLE &imx_console
1251#else
1252#define IMX_CONSOLE NULL
1253#endif
1254
1255static struct uart_driver imx_reg = {
1256 .owner = THIS_MODULE,
1257 .driver_name = DRIVER_NAME,
1258 .dev_name = DEV_NAME,
1259 .major = SERIAL_IMX_MAJOR,
1260 .minor = MINOR_START,
1261 .nr = ARRAY_SIZE(imx_ports),
1262 .cons = IMX_CONSOLE,
1263};
1264
1265static int serial_imx_suspend(struct platform_device *dev, pm_message_t state)
1266{
1267 struct imx_port *sport = platform_get_drvdata(dev);
1268
1269 if (sport)
1270 uart_suspend_port(&imx_reg, &sport->port);
1271
1272 return 0;
1273}
1274
1275static int serial_imx_resume(struct platform_device *dev)
1276{
1277 struct imx_port *sport = platform_get_drvdata(dev);
1278
1279 if (sport)
1280 uart_resume_port(&imx_reg, &sport->port);
1281
1282 return 0;
1283}
1284
1285#ifdef CONFIG_OF
1286static int serial_imx_probe_dt(struct imx_port *sport,
1287 struct platform_device *pdev)
1288{
1289 static int portnum = 0;
1290 struct device_node *np = pdev->dev.of_node;
1291 const struct of_device_id *of_id =
1292 of_match_device(imx_uart_dt_ids, &pdev->dev);
1293
1294 if (!np)
1295 return -ENODEV;
1296
1297 sport->port.line = portnum++;
1298 if (sport->port.line >= UART_NR)
1299 return -EINVAL;
1300
1301 if (of_get_property(np, "fsl,uart-has-rtscts", NULL))
1302 sport->have_rtscts = 1;
1303
1304 if (of_get_property(np, "fsl,irda-mode", NULL))
1305 sport->use_irda = 1;
1306
1307 sport->devdata = of_id->data;
1308
1309 return 0;
1310}
1311#else
1312static inline int serial_imx_probe_dt(struct imx_port *sport,
1313 struct platform_device *pdev)
1314{
1315 return -ENODEV;
1316}
1317#endif
1318
1319static void serial_imx_probe_pdata(struct imx_port *sport,
1320 struct platform_device *pdev)
1321{
1322 struct imxuart_platform_data *pdata = pdev->dev.platform_data;
1323
1324 sport->port.line = pdev->id;
1325 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data;
1326
1327 if (!pdata)
1328 return;
1329
1330 if (pdata->flags & IMXUART_HAVE_RTSCTS)
1331 sport->have_rtscts = 1;
1332
1333 if (pdata->flags & IMXUART_IRDA)
1334 sport->use_irda = 1;
1335}
1336
1337static int serial_imx_probe(struct platform_device *pdev)
1338{
1339 struct imx_port *sport;
1340 struct imxuart_platform_data *pdata;
1341 void __iomem *base;
1342 int ret = 0;
1343 struct resource *res;
1344
1345 sport = kzalloc(sizeof(*sport), GFP_KERNEL);
1346 if (!sport)
1347 return -ENOMEM;
1348
1349 ret = serial_imx_probe_dt(sport, pdev);
1350 if (ret == -ENODEV)
1351 serial_imx_probe_pdata(sport, pdev);
1352
1353 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1354 if (!res) {
1355 ret = -ENODEV;
1356 goto free;
1357 }
1358
1359 base = ioremap(res->start, PAGE_SIZE);
1360 if (!base) {
1361 ret = -ENOMEM;
1362 goto free;
1363 }
1364
1365 sport->port.dev = &pdev->dev;
1366 sport->port.mapbase = res->start;
1367 sport->port.membase = base;
1368 sport->port.type = PORT_IMX,
1369 sport->port.iotype = UPIO_MEM;
1370 sport->port.irq = platform_get_irq(pdev, 0);
1371 sport->rxirq = platform_get_irq(pdev, 0);
1372 sport->txirq = platform_get_irq(pdev, 1);
1373 sport->rtsirq = platform_get_irq(pdev, 2);
1374 sport->port.fifosize = 32;
1375 sport->port.ops = &imx_pops;
1376 sport->port.flags = UPF_BOOT_AUTOCONF;
1377 init_timer(&sport->timer);
1378 sport->timer.function = imx_timeout;
1379 sport->timer.data = (unsigned long)sport;
1380
1381 sport->clk = clk_get(&pdev->dev, "uart");
1382 if (IS_ERR(sport->clk)) {
1383 ret = PTR_ERR(sport->clk);
1384 goto unmap;
1385 }
1386 clk_enable(sport->clk);
1387
1388 sport->port.uartclk = clk_get_rate(sport->clk);
1389
1390 imx_ports[sport->port.line] = sport;
1391
1392 pdata = pdev->dev.platform_data;
1393 if (pdata && pdata->init) {
1394 ret = pdata->init(pdev);
1395 if (ret)
1396 goto clkput;
1397 }
1398
1399 ret = uart_add_one_port(&imx_reg, &sport->port);
1400 if (ret)
1401 goto deinit;
1402 platform_set_drvdata(pdev, &sport->port);
1403
1404 return 0;
1405deinit:
1406 if (pdata && pdata->exit)
1407 pdata->exit(pdev);
1408clkput:
1409 clk_put(sport->clk);
1410 clk_disable(sport->clk);
1411unmap:
1412 iounmap(sport->port.membase);
1413free:
1414 kfree(sport);
1415
1416 return ret;
1417}
1418
1419static int serial_imx_remove(struct platform_device *pdev)
1420{
1421 struct imxuart_platform_data *pdata;
1422 struct imx_port *sport = platform_get_drvdata(pdev);
1423
1424 pdata = pdev->dev.platform_data;
1425
1426 platform_set_drvdata(pdev, NULL);
1427
1428 if (sport) {
1429 uart_remove_one_port(&imx_reg, &sport->port);
1430 clk_put(sport->clk);
1431 }
1432
1433 clk_disable(sport->clk);
1434
1435 if (pdata && pdata->exit)
1436 pdata->exit(pdev);
1437
1438 iounmap(sport->port.membase);
1439 kfree(sport);
1440
1441 return 0;
1442}
1443
1444static struct platform_driver serial_imx_driver = {
1445 .probe = serial_imx_probe,
1446 .remove = serial_imx_remove,
1447
1448 .suspend = serial_imx_suspend,
1449 .resume = serial_imx_resume,
1450 .id_table = imx_uart_devtype,
1451 .driver = {
1452 .name = "imx-uart",
1453 .owner = THIS_MODULE,
1454 .of_match_table = imx_uart_dt_ids,
1455 },
1456};
1457
1458static int __init imx_serial_init(void)
1459{
1460 int ret;
1461
1462 printk(KERN_INFO "Serial: IMX driver\n");
1463
1464 ret = uart_register_driver(&imx_reg);
1465 if (ret)
1466 return ret;
1467
1468 ret = platform_driver_register(&serial_imx_driver);
1469 if (ret != 0)
1470 uart_unregister_driver(&imx_reg);
1471
1472 return 0;
1473}
1474
1475static void __exit imx_serial_exit(void)
1476{
1477 platform_driver_unregister(&serial_imx_driver);
1478 uart_unregister_driver(&imx_reg);
1479}
1480
1481module_init(imx_serial_init);
1482module_exit(imx_serial_exit);
1483
1484MODULE_AUTHOR("Sascha Hauer");
1485MODULE_DESCRIPTION("IMX generic serial port driver");
1486MODULE_LICENSE("GPL");
1487MODULE_ALIAS("platform:imx-uart");
1/*
2 * Driver for Motorola IMX serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Author: Sascha Hauer <sascha@saschahauer.de>
7 * Copyright (C) 2004 Pengutronix
8 *
9 * Copyright (C) 2009 emlix GmbH
10 * Author: Fabian Godehardt (added IrDA support for iMX)
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 * [29-Mar-2005] Mike Lee
27 * Added hardware handshake
28 */
29
30#if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
31#define SUPPORT_SYSRQ
32#endif
33
34#include <linux/module.h>
35#include <linux/ioport.h>
36#include <linux/init.h>
37#include <linux/console.h>
38#include <linux/sysrq.h>
39#include <linux/platform_device.h>
40#include <linux/tty.h>
41#include <linux/tty_flip.h>
42#include <linux/serial_core.h>
43#include <linux/serial.h>
44#include <linux/clk.h>
45#include <linux/delay.h>
46#include <linux/rational.h>
47#include <linux/slab.h>
48#include <linux/of.h>
49#include <linux/of_device.h>
50#include <linux/io.h>
51#include <linux/dma-mapping.h>
52
53#include <asm/irq.h>
54#include <linux/platform_data/serial-imx.h>
55#include <linux/platform_data/dma-imx.h>
56
57/* Register definitions */
58#define URXD0 0x0 /* Receiver Register */
59#define URTX0 0x40 /* Transmitter Register */
60#define UCR1 0x80 /* Control Register 1 */
61#define UCR2 0x84 /* Control Register 2 */
62#define UCR3 0x88 /* Control Register 3 */
63#define UCR4 0x8c /* Control Register 4 */
64#define UFCR 0x90 /* FIFO Control Register */
65#define USR1 0x94 /* Status Register 1 */
66#define USR2 0x98 /* Status Register 2 */
67#define UESC 0x9c /* Escape Character Register */
68#define UTIM 0xa0 /* Escape Timer Register */
69#define UBIR 0xa4 /* BRM Incremental Register */
70#define UBMR 0xa8 /* BRM Modulator Register */
71#define UBRC 0xac /* Baud Rate Count Register */
72#define IMX21_ONEMS 0xb0 /* One Millisecond register */
73#define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
74#define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
75
76/* UART Control Register Bit Fields.*/
77#define URXD_CHARRDY (1<<15)
78#define URXD_ERR (1<<14)
79#define URXD_OVRRUN (1<<13)
80#define URXD_FRMERR (1<<12)
81#define URXD_BRK (1<<11)
82#define URXD_PRERR (1<<10)
83#define UCR1_ADEN (1<<15) /* Auto detect interrupt */
84#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
85#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
86#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
87#define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
88#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
89#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
90#define UCR1_IREN (1<<7) /* Infrared interface enable */
91#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
92#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
93#define UCR1_SNDBRK (1<<4) /* Send break */
94#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
95#define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
96#define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
97#define UCR1_DOZE (1<<1) /* Doze */
98#define UCR1_UARTEN (1<<0) /* UART enabled */
99#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
100#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
101#define UCR2_CTSC (1<<13) /* CTS pin control */
102#define UCR2_CTS (1<<12) /* Clear to send */
103#define UCR2_ESCEN (1<<11) /* Escape enable */
104#define UCR2_PREN (1<<8) /* Parity enable */
105#define UCR2_PROE (1<<7) /* Parity odd/even */
106#define UCR2_STPB (1<<6) /* Stop */
107#define UCR2_WS (1<<5) /* Word size */
108#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
109#define UCR2_ATEN (1<<3) /* Aging Timer Enable */
110#define UCR2_TXEN (1<<2) /* Transmitter enabled */
111#define UCR2_RXEN (1<<1) /* Receiver enabled */
112#define UCR2_SRST (1<<0) /* SW reset */
113#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
114#define UCR3_PARERREN (1<<12) /* Parity enable */
115#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
116#define UCR3_DSR (1<<10) /* Data set ready */
117#define UCR3_DCD (1<<9) /* Data carrier detect */
118#define UCR3_RI (1<<8) /* Ring indicator */
119#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
120#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
121#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
122#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
123#define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
124#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
125#define UCR3_BPEN (1<<0) /* Preset registers enable */
126#define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
127#define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
128#define UCR4_INVR (1<<9) /* Inverted infrared reception */
129#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
130#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
131#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
132#define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
133#define UCR4_IRSC (1<<5) /* IR special case */
134#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
135#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
136#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
137#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
138#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
139#define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
140#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
141#define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
142#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
143#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
144#define USR1_RTSS (1<<14) /* RTS pin status */
145#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
146#define USR1_RTSD (1<<12) /* RTS delta */
147#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
148#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
149#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
150#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
151#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
152#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
153#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
154#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
155#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
156#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
157#define USR2_IDLE (1<<12) /* Idle condition */
158#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
159#define USR2_WAKE (1<<7) /* Wake */
160#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
161#define USR2_TXDC (1<<3) /* Transmitter complete */
162#define USR2_BRCD (1<<2) /* Break condition */
163#define USR2_ORE (1<<1) /* Overrun error */
164#define USR2_RDR (1<<0) /* Recv data ready */
165#define UTS_FRCPERR (1<<13) /* Force parity error */
166#define UTS_LOOP (1<<12) /* Loop tx and rx */
167#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
168#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
169#define UTS_TXFULL (1<<4) /* TxFIFO full */
170#define UTS_RXFULL (1<<3) /* RxFIFO full */
171#define UTS_SOFTRST (1<<0) /* Software reset */
172
173/* We've been assigned a range on the "Low-density serial ports" major */
174#define SERIAL_IMX_MAJOR 207
175#define MINOR_START 16
176#define DEV_NAME "ttymxc"
177
178/*
179 * This determines how often we check the modem status signals
180 * for any change. They generally aren't connected to an IRQ
181 * so we have to poll them. We also check immediately before
182 * filling the TX fifo incase CTS has been dropped.
183 */
184#define MCTRL_TIMEOUT (250*HZ/1000)
185
186#define DRIVER_NAME "IMX-uart"
187
188#define UART_NR 8
189
190/* i.mx21 type uart runs on all i.mx except i.mx1 */
191enum imx_uart_type {
192 IMX1_UART,
193 IMX21_UART,
194 IMX6Q_UART,
195};
196
197/* device type dependent stuff */
198struct imx_uart_data {
199 unsigned uts_reg;
200 enum imx_uart_type devtype;
201};
202
203struct imx_port {
204 struct uart_port port;
205 struct timer_list timer;
206 unsigned int old_status;
207 int txirq, rxirq, rtsirq;
208 unsigned int have_rtscts:1;
209 unsigned int dte_mode:1;
210 unsigned int use_irda:1;
211 unsigned int irda_inv_rx:1;
212 unsigned int irda_inv_tx:1;
213 unsigned short trcv_delay; /* transceiver delay */
214 struct clk *clk_ipg;
215 struct clk *clk_per;
216 const struct imx_uart_data *devdata;
217
218 /* DMA fields */
219 unsigned int dma_is_inited:1;
220 unsigned int dma_is_enabled:1;
221 unsigned int dma_is_rxing:1;
222 unsigned int dma_is_txing:1;
223 struct dma_chan *dma_chan_rx, *dma_chan_tx;
224 struct scatterlist rx_sgl, tx_sgl[2];
225 void *rx_buf;
226 unsigned int tx_bytes;
227 unsigned int dma_tx_nents;
228 wait_queue_head_t dma_wait;
229};
230
231struct imx_port_ucrs {
232 unsigned int ucr1;
233 unsigned int ucr2;
234 unsigned int ucr3;
235};
236
237#ifdef CONFIG_IRDA
238#define USE_IRDA(sport) ((sport)->use_irda)
239#else
240#define USE_IRDA(sport) (0)
241#endif
242
243static struct imx_uart_data imx_uart_devdata[] = {
244 [IMX1_UART] = {
245 .uts_reg = IMX1_UTS,
246 .devtype = IMX1_UART,
247 },
248 [IMX21_UART] = {
249 .uts_reg = IMX21_UTS,
250 .devtype = IMX21_UART,
251 },
252 [IMX6Q_UART] = {
253 .uts_reg = IMX21_UTS,
254 .devtype = IMX6Q_UART,
255 },
256};
257
258static struct platform_device_id imx_uart_devtype[] = {
259 {
260 .name = "imx1-uart",
261 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
262 }, {
263 .name = "imx21-uart",
264 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
265 }, {
266 .name = "imx6q-uart",
267 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART],
268 }, {
269 /* sentinel */
270 }
271};
272MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
273
274static struct of_device_id imx_uart_dt_ids[] = {
275 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
276 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
277 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
278 { /* sentinel */ }
279};
280MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
281
282static inline unsigned uts_reg(struct imx_port *sport)
283{
284 return sport->devdata->uts_reg;
285}
286
287static inline int is_imx1_uart(struct imx_port *sport)
288{
289 return sport->devdata->devtype == IMX1_UART;
290}
291
292static inline int is_imx21_uart(struct imx_port *sport)
293{
294 return sport->devdata->devtype == IMX21_UART;
295}
296
297static inline int is_imx6q_uart(struct imx_port *sport)
298{
299 return sport->devdata->devtype == IMX6Q_UART;
300}
301/*
302 * Save and restore functions for UCR1, UCR2 and UCR3 registers
303 */
304#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_IMX_CONSOLE)
305static void imx_port_ucrs_save(struct uart_port *port,
306 struct imx_port_ucrs *ucr)
307{
308 /* save control registers */
309 ucr->ucr1 = readl(port->membase + UCR1);
310 ucr->ucr2 = readl(port->membase + UCR2);
311 ucr->ucr3 = readl(port->membase + UCR3);
312}
313
314static void imx_port_ucrs_restore(struct uart_port *port,
315 struct imx_port_ucrs *ucr)
316{
317 /* restore control registers */
318 writel(ucr->ucr1, port->membase + UCR1);
319 writel(ucr->ucr2, port->membase + UCR2);
320 writel(ucr->ucr3, port->membase + UCR3);
321}
322#endif
323
324/*
325 * Handle any change of modem status signal since we were last called.
326 */
327static void imx_mctrl_check(struct imx_port *sport)
328{
329 unsigned int status, changed;
330
331 status = sport->port.ops->get_mctrl(&sport->port);
332 changed = status ^ sport->old_status;
333
334 if (changed == 0)
335 return;
336
337 sport->old_status = status;
338
339 if (changed & TIOCM_RI)
340 sport->port.icount.rng++;
341 if (changed & TIOCM_DSR)
342 sport->port.icount.dsr++;
343 if (changed & TIOCM_CAR)
344 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
345 if (changed & TIOCM_CTS)
346 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
347
348 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
349}
350
351/*
352 * This is our per-port timeout handler, for checking the
353 * modem status signals.
354 */
355static void imx_timeout(unsigned long data)
356{
357 struct imx_port *sport = (struct imx_port *)data;
358 unsigned long flags;
359
360 if (sport->port.state) {
361 spin_lock_irqsave(&sport->port.lock, flags);
362 imx_mctrl_check(sport);
363 spin_unlock_irqrestore(&sport->port.lock, flags);
364
365 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
366 }
367}
368
369/*
370 * interrupts disabled on entry
371 */
372static void imx_stop_tx(struct uart_port *port)
373{
374 struct imx_port *sport = (struct imx_port *)port;
375 unsigned long temp;
376
377 if (USE_IRDA(sport)) {
378 /* half duplex - wait for end of transmission */
379 int n = 256;
380 while ((--n > 0) &&
381 !(readl(sport->port.membase + USR2) & USR2_TXDC)) {
382 udelay(5);
383 barrier();
384 }
385 /*
386 * irda transceiver - wait a bit more to avoid
387 * cutoff, hardware dependent
388 */
389 udelay(sport->trcv_delay);
390
391 /*
392 * half duplex - reactivate receive mode,
393 * flush receive pipe echo crap
394 */
395 if (readl(sport->port.membase + USR2) & USR2_TXDC) {
396 temp = readl(sport->port.membase + UCR1);
397 temp &= ~(UCR1_TXMPTYEN | UCR1_TRDYEN);
398 writel(temp, sport->port.membase + UCR1);
399
400 temp = readl(sport->port.membase + UCR4);
401 temp &= ~(UCR4_TCEN);
402 writel(temp, sport->port.membase + UCR4);
403
404 while (readl(sport->port.membase + URXD0) &
405 URXD_CHARRDY)
406 barrier();
407
408 temp = readl(sport->port.membase + UCR1);
409 temp |= UCR1_RRDYEN;
410 writel(temp, sport->port.membase + UCR1);
411
412 temp = readl(sport->port.membase + UCR4);
413 temp |= UCR4_DREN;
414 writel(temp, sport->port.membase + UCR4);
415 }
416 return;
417 }
418
419 /*
420 * We are maybe in the SMP context, so if the DMA TX thread is running
421 * on other cpu, we have to wait for it to finish.
422 */
423 if (sport->dma_is_enabled && sport->dma_is_txing)
424 return;
425
426 temp = readl(sport->port.membase + UCR1);
427 writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);
428}
429
430/*
431 * interrupts disabled on entry
432 */
433static void imx_stop_rx(struct uart_port *port)
434{
435 struct imx_port *sport = (struct imx_port *)port;
436 unsigned long temp;
437
438 /*
439 * We are maybe in the SMP context, so if the DMA TX thread is running
440 * on other cpu, we have to wait for it to finish.
441 */
442 if (sport->dma_is_enabled && sport->dma_is_rxing)
443 return;
444
445 temp = readl(sport->port.membase + UCR2);
446 writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2);
447}
448
449/*
450 * Set the modem control timer to fire immediately.
451 */
452static void imx_enable_ms(struct uart_port *port)
453{
454 struct imx_port *sport = (struct imx_port *)port;
455
456 mod_timer(&sport->timer, jiffies);
457}
458
459static inline void imx_transmit_buffer(struct imx_port *sport)
460{
461 struct circ_buf *xmit = &sport->port.state->xmit;
462
463 while (!uart_circ_empty(xmit) &&
464 !(readl(sport->port.membase + uts_reg(sport))
465 & UTS_TXFULL)) {
466 /* send xmit->buf[xmit->tail]
467 * out the port here */
468 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
469 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
470 sport->port.icount.tx++;
471 }
472
473 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
474 uart_write_wakeup(&sport->port);
475
476 if (uart_circ_empty(xmit))
477 imx_stop_tx(&sport->port);
478}
479
480static void dma_tx_callback(void *data)
481{
482 struct imx_port *sport = data;
483 struct scatterlist *sgl = &sport->tx_sgl[0];
484 struct circ_buf *xmit = &sport->port.state->xmit;
485 unsigned long flags;
486
487 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
488
489 sport->dma_is_txing = 0;
490
491 /* update the stat */
492 spin_lock_irqsave(&sport->port.lock, flags);
493 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);
494 sport->port.icount.tx += sport->tx_bytes;
495 spin_unlock_irqrestore(&sport->port.lock, flags);
496
497 dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
498
499 uart_write_wakeup(&sport->port);
500
501 if (waitqueue_active(&sport->dma_wait)) {
502 wake_up(&sport->dma_wait);
503 dev_dbg(sport->port.dev, "exit in %s.\n", __func__);
504 return;
505 }
506}
507
508static void imx_dma_tx(struct imx_port *sport)
509{
510 struct circ_buf *xmit = &sport->port.state->xmit;
511 struct scatterlist *sgl = sport->tx_sgl;
512 struct dma_async_tx_descriptor *desc;
513 struct dma_chan *chan = sport->dma_chan_tx;
514 struct device *dev = sport->port.dev;
515 enum dma_status status;
516 int ret;
517
518 status = dmaengine_tx_status(chan, (dma_cookie_t)0, NULL);
519 if (DMA_IN_PROGRESS == status)
520 return;
521
522 sport->tx_bytes = uart_circ_chars_pending(xmit);
523
524 if (xmit->tail > xmit->head && xmit->head > 0) {
525 sport->dma_tx_nents = 2;
526 sg_init_table(sgl, 2);
527 sg_set_buf(sgl, xmit->buf + xmit->tail,
528 UART_XMIT_SIZE - xmit->tail);
529 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
530 } else {
531 sport->dma_tx_nents = 1;
532 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
533 }
534
535 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
536 if (ret == 0) {
537 dev_err(dev, "DMA mapping error for TX.\n");
538 return;
539 }
540 desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents,
541 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
542 if (!desc) {
543 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
544 return;
545 }
546 desc->callback = dma_tx_callback;
547 desc->callback_param = sport;
548
549 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
550 uart_circ_chars_pending(xmit));
551 /* fire it */
552 sport->dma_is_txing = 1;
553 dmaengine_submit(desc);
554 dma_async_issue_pending(chan);
555 return;
556}
557
558/*
559 * interrupts disabled on entry
560 */
561static void imx_start_tx(struct uart_port *port)
562{
563 struct imx_port *sport = (struct imx_port *)port;
564 unsigned long temp;
565
566 if (USE_IRDA(sport)) {
567 /* half duplex in IrDA mode; have to disable receive mode */
568 temp = readl(sport->port.membase + UCR4);
569 temp &= ~(UCR4_DREN);
570 writel(temp, sport->port.membase + UCR4);
571
572 temp = readl(sport->port.membase + UCR1);
573 temp &= ~(UCR1_RRDYEN);
574 writel(temp, sport->port.membase + UCR1);
575 }
576 /* Clear any pending ORE flag before enabling interrupt */
577 temp = readl(sport->port.membase + USR2);
578 writel(temp | USR2_ORE, sport->port.membase + USR2);
579
580 temp = readl(sport->port.membase + UCR4);
581 temp |= UCR4_OREN;
582 writel(temp, sport->port.membase + UCR4);
583
584 if (!sport->dma_is_enabled) {
585 temp = readl(sport->port.membase + UCR1);
586 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
587 }
588
589 if (USE_IRDA(sport)) {
590 temp = readl(sport->port.membase + UCR1);
591 temp |= UCR1_TRDYEN;
592 writel(temp, sport->port.membase + UCR1);
593
594 temp = readl(sport->port.membase + UCR4);
595 temp |= UCR4_TCEN;
596 writel(temp, sport->port.membase + UCR4);
597 }
598
599 if (sport->dma_is_enabled) {
600 imx_dma_tx(sport);
601 return;
602 }
603
604 if (readl(sport->port.membase + uts_reg(sport)) & UTS_TXEMPTY)
605 imx_transmit_buffer(sport);
606}
607
608static irqreturn_t imx_rtsint(int irq, void *dev_id)
609{
610 struct imx_port *sport = dev_id;
611 unsigned int val;
612 unsigned long flags;
613
614 spin_lock_irqsave(&sport->port.lock, flags);
615
616 writel(USR1_RTSD, sport->port.membase + USR1);
617 val = readl(sport->port.membase + USR1) & USR1_RTSS;
618 uart_handle_cts_change(&sport->port, !!val);
619 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
620
621 spin_unlock_irqrestore(&sport->port.lock, flags);
622 return IRQ_HANDLED;
623}
624
625static irqreturn_t imx_txint(int irq, void *dev_id)
626{
627 struct imx_port *sport = dev_id;
628 struct circ_buf *xmit = &sport->port.state->xmit;
629 unsigned long flags;
630
631 spin_lock_irqsave(&sport->port.lock, flags);
632 if (sport->port.x_char) {
633 /* Send next char */
634 writel(sport->port.x_char, sport->port.membase + URTX0);
635 goto out;
636 }
637
638 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
639 imx_stop_tx(&sport->port);
640 goto out;
641 }
642
643 imx_transmit_buffer(sport);
644
645 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
646 uart_write_wakeup(&sport->port);
647
648out:
649 spin_unlock_irqrestore(&sport->port.lock, flags);
650 return IRQ_HANDLED;
651}
652
653static irqreturn_t imx_rxint(int irq, void *dev_id)
654{
655 struct imx_port *sport = dev_id;
656 unsigned int rx, flg, ignored = 0;
657 struct tty_port *port = &sport->port.state->port;
658 unsigned long flags, temp;
659
660 spin_lock_irqsave(&sport->port.lock, flags);
661
662 while (readl(sport->port.membase + USR2) & USR2_RDR) {
663 flg = TTY_NORMAL;
664 sport->port.icount.rx++;
665
666 rx = readl(sport->port.membase + URXD0);
667
668 temp = readl(sport->port.membase + USR2);
669 if (temp & USR2_BRCD) {
670 writel(USR2_BRCD, sport->port.membase + USR2);
671 if (uart_handle_break(&sport->port))
672 continue;
673 }
674
675 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
676 continue;
677
678 if (unlikely(rx & URXD_ERR)) {
679 if (rx & URXD_BRK)
680 sport->port.icount.brk++;
681 else if (rx & URXD_PRERR)
682 sport->port.icount.parity++;
683 else if (rx & URXD_FRMERR)
684 sport->port.icount.frame++;
685 if (rx & URXD_OVRRUN)
686 sport->port.icount.overrun++;
687
688 if (rx & sport->port.ignore_status_mask) {
689 if (++ignored > 100)
690 goto out;
691 continue;
692 }
693
694 rx &= sport->port.read_status_mask;
695
696 if (rx & URXD_BRK)
697 flg = TTY_BREAK;
698 else if (rx & URXD_PRERR)
699 flg = TTY_PARITY;
700 else if (rx & URXD_FRMERR)
701 flg = TTY_FRAME;
702 if (rx & URXD_OVRRUN)
703 flg = TTY_OVERRUN;
704
705#ifdef SUPPORT_SYSRQ
706 sport->port.sysrq = 0;
707#endif
708 }
709
710 tty_insert_flip_char(port, rx, flg);
711 }
712
713out:
714 spin_unlock_irqrestore(&sport->port.lock, flags);
715 tty_flip_buffer_push(port);
716 return IRQ_HANDLED;
717}
718
719static int start_rx_dma(struct imx_port *sport);
720/*
721 * If the RXFIFO is filled with some data, and then we
722 * arise a DMA operation to receive them.
723 */
724static void imx_dma_rxint(struct imx_port *sport)
725{
726 unsigned long temp;
727
728 temp = readl(sport->port.membase + USR2);
729 if ((temp & USR2_RDR) && !sport->dma_is_rxing) {
730 sport->dma_is_rxing = 1;
731
732 /* disable the `Recerver Ready Interrrupt` */
733 temp = readl(sport->port.membase + UCR1);
734 temp &= ~(UCR1_RRDYEN);
735 writel(temp, sport->port.membase + UCR1);
736
737 /* tell the DMA to receive the data. */
738 start_rx_dma(sport);
739 }
740}
741
742static irqreturn_t imx_int(int irq, void *dev_id)
743{
744 struct imx_port *sport = dev_id;
745 unsigned int sts;
746 unsigned int sts2;
747
748 sts = readl(sport->port.membase + USR1);
749
750 if (sts & USR1_RRDY) {
751 if (sport->dma_is_enabled)
752 imx_dma_rxint(sport);
753 else
754 imx_rxint(irq, dev_id);
755 }
756
757 if (sts & USR1_TRDY &&
758 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN)
759 imx_txint(irq, dev_id);
760
761 if (sts & USR1_RTSD)
762 imx_rtsint(irq, dev_id);
763
764 if (sts & USR1_AWAKE)
765 writel(USR1_AWAKE, sport->port.membase + USR1);
766
767 sts2 = readl(sport->port.membase + USR2);
768 if (sts2 & USR2_ORE) {
769 dev_err(sport->port.dev, "Rx FIFO overrun\n");
770 sport->port.icount.overrun++;
771 writel(sts2 | USR2_ORE, sport->port.membase + USR2);
772 }
773
774 return IRQ_HANDLED;
775}
776
777/*
778 * Return TIOCSER_TEMT when transmitter is not busy.
779 */
780static unsigned int imx_tx_empty(struct uart_port *port)
781{
782 struct imx_port *sport = (struct imx_port *)port;
783 unsigned int ret;
784
785 ret = (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
786
787 /* If the TX DMA is working, return 0. */
788 if (sport->dma_is_enabled && sport->dma_is_txing)
789 ret = 0;
790
791 return ret;
792}
793
794/*
795 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
796 */
797static unsigned int imx_get_mctrl(struct uart_port *port)
798{
799 struct imx_port *sport = (struct imx_port *)port;
800 unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
801
802 if (readl(sport->port.membase + USR1) & USR1_RTSS)
803 tmp |= TIOCM_CTS;
804
805 if (readl(sport->port.membase + UCR2) & UCR2_CTS)
806 tmp |= TIOCM_RTS;
807
808 if (readl(sport->port.membase + uts_reg(sport)) & UTS_LOOP)
809 tmp |= TIOCM_LOOP;
810
811 return tmp;
812}
813
814static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
815{
816 struct imx_port *sport = (struct imx_port *)port;
817 unsigned long temp;
818
819 temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS;
820
821 if (mctrl & TIOCM_RTS)
822 if (!sport->dma_is_enabled)
823 temp |= UCR2_CTS;
824
825 writel(temp, sport->port.membase + UCR2);
826
827 temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP;
828 if (mctrl & TIOCM_LOOP)
829 temp |= UTS_LOOP;
830 writel(temp, sport->port.membase + uts_reg(sport));
831}
832
833/*
834 * Interrupts always disabled.
835 */
836static void imx_break_ctl(struct uart_port *port, int break_state)
837{
838 struct imx_port *sport = (struct imx_port *)port;
839 unsigned long flags, temp;
840
841 spin_lock_irqsave(&sport->port.lock, flags);
842
843 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
844
845 if (break_state != 0)
846 temp |= UCR1_SNDBRK;
847
848 writel(temp, sport->port.membase + UCR1);
849
850 spin_unlock_irqrestore(&sport->port.lock, flags);
851}
852
853#define TXTL 2 /* reset default */
854#define RXTL 1 /* reset default */
855
856static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
857{
858 unsigned int val;
859
860 /* set receiver / transmitter trigger level */
861 val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
862 val |= TXTL << UFCR_TXTL_SHF | RXTL;
863 writel(val, sport->port.membase + UFCR);
864 return 0;
865}
866
867#define RX_BUF_SIZE (PAGE_SIZE)
868static void imx_rx_dma_done(struct imx_port *sport)
869{
870 unsigned long temp;
871
872 /* Enable this interrupt when the RXFIFO is empty. */
873 temp = readl(sport->port.membase + UCR1);
874 temp |= UCR1_RRDYEN;
875 writel(temp, sport->port.membase + UCR1);
876
877 sport->dma_is_rxing = 0;
878
879 /* Is the shutdown waiting for us? */
880 if (waitqueue_active(&sport->dma_wait))
881 wake_up(&sport->dma_wait);
882}
883
884/*
885 * There are three kinds of RX DMA interrupts(such as in the MX6Q):
886 * [1] the RX DMA buffer is full.
887 * [2] the Aging timer expires(wait for 8 bytes long)
888 * [3] the Idle Condition Detect(enabled the UCR4_IDDMAEN).
889 *
890 * The [2] is trigger when a character was been sitting in the FIFO
891 * meanwhile [3] can wait for 32 bytes long when the RX line is
892 * on IDLE state and RxFIFO is empty.
893 */
894static void dma_rx_callback(void *data)
895{
896 struct imx_port *sport = data;
897 struct dma_chan *chan = sport->dma_chan_rx;
898 struct scatterlist *sgl = &sport->rx_sgl;
899 struct tty_port *port = &sport->port.state->port;
900 struct dma_tx_state state;
901 enum dma_status status;
902 unsigned int count;
903
904 /* unmap it first */
905 dma_unmap_sg(sport->port.dev, sgl, 1, DMA_FROM_DEVICE);
906
907 status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state);
908 count = RX_BUF_SIZE - state.residue;
909 dev_dbg(sport->port.dev, "We get %d bytes.\n", count);
910
911 if (count) {
912 tty_insert_flip_string(port, sport->rx_buf, count);
913 tty_flip_buffer_push(port);
914
915 start_rx_dma(sport);
916 } else
917 imx_rx_dma_done(sport);
918}
919
920static int start_rx_dma(struct imx_port *sport)
921{
922 struct scatterlist *sgl = &sport->rx_sgl;
923 struct dma_chan *chan = sport->dma_chan_rx;
924 struct device *dev = sport->port.dev;
925 struct dma_async_tx_descriptor *desc;
926 int ret;
927
928 sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE);
929 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
930 if (ret == 0) {
931 dev_err(dev, "DMA mapping error for RX.\n");
932 return -EINVAL;
933 }
934 desc = dmaengine_prep_slave_sg(chan, sgl, 1, DMA_DEV_TO_MEM,
935 DMA_PREP_INTERRUPT);
936 if (!desc) {
937 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
938 return -EINVAL;
939 }
940 desc->callback = dma_rx_callback;
941 desc->callback_param = sport;
942
943 dev_dbg(dev, "RX: prepare for the DMA.\n");
944 dmaengine_submit(desc);
945 dma_async_issue_pending(chan);
946 return 0;
947}
948
949static void imx_uart_dma_exit(struct imx_port *sport)
950{
951 if (sport->dma_chan_rx) {
952 dma_release_channel(sport->dma_chan_rx);
953 sport->dma_chan_rx = NULL;
954
955 kfree(sport->rx_buf);
956 sport->rx_buf = NULL;
957 }
958
959 if (sport->dma_chan_tx) {
960 dma_release_channel(sport->dma_chan_tx);
961 sport->dma_chan_tx = NULL;
962 }
963
964 sport->dma_is_inited = 0;
965}
966
967static int imx_uart_dma_init(struct imx_port *sport)
968{
969 struct dma_slave_config slave_config = {};
970 struct device *dev = sport->port.dev;
971 int ret;
972
973 /* Prepare for RX : */
974 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
975 if (!sport->dma_chan_rx) {
976 dev_dbg(dev, "cannot get the DMA channel.\n");
977 ret = -EINVAL;
978 goto err;
979 }
980
981 slave_config.direction = DMA_DEV_TO_MEM;
982 slave_config.src_addr = sport->port.mapbase + URXD0;
983 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
984 slave_config.src_maxburst = RXTL;
985 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
986 if (ret) {
987 dev_err(dev, "error in RX dma configuration.\n");
988 goto err;
989 }
990
991 sport->rx_buf = kzalloc(PAGE_SIZE, GFP_KERNEL);
992 if (!sport->rx_buf) {
993 dev_err(dev, "cannot alloc DMA buffer.\n");
994 ret = -ENOMEM;
995 goto err;
996 }
997
998 /* Prepare for TX : */
999 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1000 if (!sport->dma_chan_tx) {
1001 dev_err(dev, "cannot get the TX DMA channel!\n");
1002 ret = -EINVAL;
1003 goto err;
1004 }
1005
1006 slave_config.direction = DMA_MEM_TO_DEV;
1007 slave_config.dst_addr = sport->port.mapbase + URTX0;
1008 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1009 slave_config.dst_maxburst = TXTL;
1010 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1011 if (ret) {
1012 dev_err(dev, "error in TX dma configuration.");
1013 goto err;
1014 }
1015
1016 sport->dma_is_inited = 1;
1017
1018 return 0;
1019err:
1020 imx_uart_dma_exit(sport);
1021 return ret;
1022}
1023
1024static void imx_enable_dma(struct imx_port *sport)
1025{
1026 unsigned long temp;
1027
1028 init_waitqueue_head(&sport->dma_wait);
1029
1030 /* set UCR1 */
1031 temp = readl(sport->port.membase + UCR1);
1032 temp |= UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN |
1033 /* wait for 32 idle frames for IDDMA interrupt */
1034 UCR1_ICD_REG(3);
1035 writel(temp, sport->port.membase + UCR1);
1036
1037 /* set UCR4 */
1038 temp = readl(sport->port.membase + UCR4);
1039 temp |= UCR4_IDDMAEN;
1040 writel(temp, sport->port.membase + UCR4);
1041
1042 sport->dma_is_enabled = 1;
1043}
1044
1045static void imx_disable_dma(struct imx_port *sport)
1046{
1047 unsigned long temp;
1048
1049 /* clear UCR1 */
1050 temp = readl(sport->port.membase + UCR1);
1051 temp &= ~(UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN);
1052 writel(temp, sport->port.membase + UCR1);
1053
1054 /* clear UCR2 */
1055 temp = readl(sport->port.membase + UCR2);
1056 temp &= ~(UCR2_CTSC | UCR2_CTS);
1057 writel(temp, sport->port.membase + UCR2);
1058
1059 /* clear UCR4 */
1060 temp = readl(sport->port.membase + UCR4);
1061 temp &= ~UCR4_IDDMAEN;
1062 writel(temp, sport->port.membase + UCR4);
1063
1064 sport->dma_is_enabled = 0;
1065}
1066
1067/* half the RX buffer size */
1068#define CTSTL 16
1069
1070static int imx_startup(struct uart_port *port)
1071{
1072 struct imx_port *sport = (struct imx_port *)port;
1073 int retval;
1074 unsigned long flags, temp;
1075
1076 retval = clk_prepare_enable(sport->clk_per);
1077 if (retval)
1078 goto error_out1;
1079 retval = clk_prepare_enable(sport->clk_ipg);
1080 if (retval) {
1081 clk_disable_unprepare(sport->clk_per);
1082 goto error_out1;
1083 }
1084
1085 imx_setup_ufcr(sport, 0);
1086
1087 /* disable the DREN bit (Data Ready interrupt enable) before
1088 * requesting IRQs
1089 */
1090 temp = readl(sport->port.membase + UCR4);
1091
1092 if (USE_IRDA(sport))
1093 temp |= UCR4_IRSC;
1094
1095 /* set the trigger level for CTS */
1096 temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1097 temp |= CTSTL << UCR4_CTSTL_SHF;
1098
1099 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
1100
1101 if (USE_IRDA(sport)) {
1102 /* reset fifo's and state machines */
1103 int i = 100;
1104 temp = readl(sport->port.membase + UCR2);
1105 temp &= ~UCR2_SRST;
1106 writel(temp, sport->port.membase + UCR2);
1107 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) &&
1108 (--i > 0)) {
1109 udelay(1);
1110 }
1111 }
1112
1113 /*
1114 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
1115 * chips only have one interrupt.
1116 */
1117 if (sport->txirq > 0) {
1118 retval = request_irq(sport->rxirq, imx_rxint, 0,
1119 dev_name(port->dev), sport);
1120 if (retval)
1121 goto error_out1;
1122
1123 retval = request_irq(sport->txirq, imx_txint, 0,
1124 dev_name(port->dev), sport);
1125 if (retval)
1126 goto error_out2;
1127
1128 /* do not use RTS IRQ on IrDA */
1129 if (!USE_IRDA(sport)) {
1130 retval = request_irq(sport->rtsirq, imx_rtsint, 0,
1131 dev_name(port->dev), sport);
1132 if (retval)
1133 goto error_out3;
1134 }
1135 } else {
1136 retval = request_irq(sport->port.irq, imx_int, 0,
1137 dev_name(port->dev), sport);
1138 if (retval) {
1139 free_irq(sport->port.irq, sport);
1140 goto error_out1;
1141 }
1142 }
1143
1144 spin_lock_irqsave(&sport->port.lock, flags);
1145 /*
1146 * Finally, clear and enable interrupts
1147 */
1148 writel(USR1_RTSD, sport->port.membase + USR1);
1149
1150 temp = readl(sport->port.membase + UCR1);
1151 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
1152
1153 if (USE_IRDA(sport)) {
1154 temp |= UCR1_IREN;
1155 temp &= ~(UCR1_RTSDEN);
1156 }
1157
1158 writel(temp, sport->port.membase + UCR1);
1159
1160 temp = readl(sport->port.membase + UCR2);
1161 temp |= (UCR2_RXEN | UCR2_TXEN);
1162 if (!sport->have_rtscts)
1163 temp |= UCR2_IRTS;
1164 writel(temp, sport->port.membase + UCR2);
1165
1166 if (USE_IRDA(sport)) {
1167 /* clear RX-FIFO */
1168 int i = 64;
1169 while ((--i > 0) &&
1170 (readl(sport->port.membase + URXD0) & URXD_CHARRDY)) {
1171 barrier();
1172 }
1173 }
1174
1175 if (!is_imx1_uart(sport)) {
1176 temp = readl(sport->port.membase + UCR3);
1177 temp |= IMX21_UCR3_RXDMUXSEL;
1178 writel(temp, sport->port.membase + UCR3);
1179 }
1180
1181 if (USE_IRDA(sport)) {
1182 temp = readl(sport->port.membase + UCR4);
1183 if (sport->irda_inv_rx)
1184 temp |= UCR4_INVR;
1185 else
1186 temp &= ~(UCR4_INVR);
1187 writel(temp | UCR4_DREN, sport->port.membase + UCR4);
1188
1189 temp = readl(sport->port.membase + UCR3);
1190 if (sport->irda_inv_tx)
1191 temp |= UCR3_INVT;
1192 else
1193 temp &= ~(UCR3_INVT);
1194 writel(temp, sport->port.membase + UCR3);
1195 }
1196
1197 /*
1198 * Enable modem status interrupts
1199 */
1200 imx_enable_ms(&sport->port);
1201 spin_unlock_irqrestore(&sport->port.lock, flags);
1202
1203 if (USE_IRDA(sport)) {
1204 struct imxuart_platform_data *pdata;
1205 pdata = dev_get_platdata(sport->port.dev);
1206 sport->irda_inv_rx = pdata->irda_inv_rx;
1207 sport->irda_inv_tx = pdata->irda_inv_tx;
1208 sport->trcv_delay = pdata->transceiver_delay;
1209 if (pdata->irda_enable)
1210 pdata->irda_enable(1);
1211 }
1212
1213 return 0;
1214
1215error_out3:
1216 if (sport->txirq)
1217 free_irq(sport->txirq, sport);
1218error_out2:
1219 if (sport->rxirq)
1220 free_irq(sport->rxirq, sport);
1221error_out1:
1222 return retval;
1223}
1224
1225static void imx_shutdown(struct uart_port *port)
1226{
1227 struct imx_port *sport = (struct imx_port *)port;
1228 unsigned long temp;
1229 unsigned long flags;
1230
1231 if (sport->dma_is_enabled) {
1232 /* We have to wait for the DMA to finish. */
1233 wait_event(sport->dma_wait,
1234 !sport->dma_is_rxing && !sport->dma_is_txing);
1235 imx_stop_rx(port);
1236 imx_disable_dma(sport);
1237 imx_uart_dma_exit(sport);
1238 }
1239
1240 spin_lock_irqsave(&sport->port.lock, flags);
1241 temp = readl(sport->port.membase + UCR2);
1242 temp &= ~(UCR2_TXEN);
1243 writel(temp, sport->port.membase + UCR2);
1244 spin_unlock_irqrestore(&sport->port.lock, flags);
1245
1246 if (USE_IRDA(sport)) {
1247 struct imxuart_platform_data *pdata;
1248 pdata = dev_get_platdata(sport->port.dev);
1249 if (pdata->irda_enable)
1250 pdata->irda_enable(0);
1251 }
1252
1253 /*
1254 * Stop our timer.
1255 */
1256 del_timer_sync(&sport->timer);
1257
1258 /*
1259 * Free the interrupts
1260 */
1261 if (sport->txirq > 0) {
1262 if (!USE_IRDA(sport))
1263 free_irq(sport->rtsirq, sport);
1264 free_irq(sport->txirq, sport);
1265 free_irq(sport->rxirq, sport);
1266 } else
1267 free_irq(sport->port.irq, sport);
1268
1269 /*
1270 * Disable all interrupts, port and break condition.
1271 */
1272
1273 spin_lock_irqsave(&sport->port.lock, flags);
1274 temp = readl(sport->port.membase + UCR1);
1275 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
1276 if (USE_IRDA(sport))
1277 temp &= ~(UCR1_IREN);
1278
1279 writel(temp, sport->port.membase + UCR1);
1280 spin_unlock_irqrestore(&sport->port.lock, flags);
1281
1282 clk_disable_unprepare(sport->clk_per);
1283 clk_disable_unprepare(sport->clk_ipg);
1284}
1285
1286static void imx_flush_buffer(struct uart_port *port)
1287{
1288 struct imx_port *sport = (struct imx_port *)port;
1289
1290 if (sport->dma_is_enabled) {
1291 sport->tx_bytes = 0;
1292 dmaengine_terminate_all(sport->dma_chan_tx);
1293 }
1294}
1295
1296static void
1297imx_set_termios(struct uart_port *port, struct ktermios *termios,
1298 struct ktermios *old)
1299{
1300 struct imx_port *sport = (struct imx_port *)port;
1301 unsigned long flags;
1302 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
1303 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1304 unsigned int div, ufcr;
1305 unsigned long num, denom;
1306 uint64_t tdiv64;
1307
1308 /*
1309 * If we don't support modem control lines, don't allow
1310 * these to be set.
1311 */
1312 if (0) {
1313 termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
1314 termios->c_cflag |= CLOCAL;
1315 }
1316
1317 /*
1318 * We only support CS7 and CS8.
1319 */
1320 while ((termios->c_cflag & CSIZE) != CS7 &&
1321 (termios->c_cflag & CSIZE) != CS8) {
1322 termios->c_cflag &= ~CSIZE;
1323 termios->c_cflag |= old_csize;
1324 old_csize = CS8;
1325 }
1326
1327 if ((termios->c_cflag & CSIZE) == CS8)
1328 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
1329 else
1330 ucr2 = UCR2_SRST | UCR2_IRTS;
1331
1332 if (termios->c_cflag & CRTSCTS) {
1333 if (sport->have_rtscts) {
1334 ucr2 &= ~UCR2_IRTS;
1335 ucr2 |= UCR2_CTSC;
1336
1337 /* Can we enable the DMA support? */
1338 if (is_imx6q_uart(sport) && !uart_console(port)
1339 && !sport->dma_is_inited)
1340 imx_uart_dma_init(sport);
1341 } else {
1342 termios->c_cflag &= ~CRTSCTS;
1343 }
1344 }
1345
1346 if (termios->c_cflag & CSTOPB)
1347 ucr2 |= UCR2_STPB;
1348 if (termios->c_cflag & PARENB) {
1349 ucr2 |= UCR2_PREN;
1350 if (termios->c_cflag & PARODD)
1351 ucr2 |= UCR2_PROE;
1352 }
1353
1354 del_timer_sync(&sport->timer);
1355
1356 /*
1357 * Ask the core to calculate the divisor for us.
1358 */
1359 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1360 quot = uart_get_divisor(port, baud);
1361
1362 spin_lock_irqsave(&sport->port.lock, flags);
1363
1364 sport->port.read_status_mask = 0;
1365 if (termios->c_iflag & INPCK)
1366 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1367 if (termios->c_iflag & (BRKINT | PARMRK))
1368 sport->port.read_status_mask |= URXD_BRK;
1369
1370 /*
1371 * Characters to ignore
1372 */
1373 sport->port.ignore_status_mask = 0;
1374 if (termios->c_iflag & IGNPAR)
1375 sport->port.ignore_status_mask |= URXD_PRERR;
1376 if (termios->c_iflag & IGNBRK) {
1377 sport->port.ignore_status_mask |= URXD_BRK;
1378 /*
1379 * If we're ignoring parity and break indicators,
1380 * ignore overruns too (for real raw support).
1381 */
1382 if (termios->c_iflag & IGNPAR)
1383 sport->port.ignore_status_mask |= URXD_OVRRUN;
1384 }
1385
1386 /*
1387 * Update the per-port timeout.
1388 */
1389 uart_update_timeout(port, termios->c_cflag, baud);
1390
1391 /*
1392 * disable interrupts and drain transmitter
1393 */
1394 old_ucr1 = readl(sport->port.membase + UCR1);
1395 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
1396 sport->port.membase + UCR1);
1397
1398 while (!(readl(sport->port.membase + USR2) & USR2_TXDC))
1399 barrier();
1400
1401 /* then, disable everything */
1402 old_txrxen = readl(sport->port.membase + UCR2);
1403 writel(old_txrxen & ~(UCR2_TXEN | UCR2_RXEN),
1404 sport->port.membase + UCR2);
1405 old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
1406
1407 if (USE_IRDA(sport)) {
1408 /*
1409 * use maximum available submodule frequency to
1410 * avoid missing short pulses due to low sampling rate
1411 */
1412 div = 1;
1413 } else {
1414 /* custom-baudrate handling */
1415 div = sport->port.uartclk / (baud * 16);
1416 if (baud == 38400 && quot != div)
1417 baud = sport->port.uartclk / (quot * 16);
1418
1419 div = sport->port.uartclk / (baud * 16);
1420 if (div > 7)
1421 div = 7;
1422 if (!div)
1423 div = 1;
1424 }
1425
1426 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1427 1 << 16, 1 << 16, &num, &denom);
1428
1429 tdiv64 = sport->port.uartclk;
1430 tdiv64 *= num;
1431 do_div(tdiv64, denom * 16 * div);
1432 tty_termios_encode_baud_rate(termios,
1433 (speed_t)tdiv64, (speed_t)tdiv64);
1434
1435 num -= 1;
1436 denom -= 1;
1437
1438 ufcr = readl(sport->port.membase + UFCR);
1439 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1440 if (sport->dte_mode)
1441 ufcr |= UFCR_DCEDTE;
1442 writel(ufcr, sport->port.membase + UFCR);
1443
1444 writel(num, sport->port.membase + UBIR);
1445 writel(denom, sport->port.membase + UBMR);
1446
1447 if (!is_imx1_uart(sport))
1448 writel(sport->port.uartclk / div / 1000,
1449 sport->port.membase + IMX21_ONEMS);
1450
1451 writel(old_ucr1, sport->port.membase + UCR1);
1452
1453 /* set the parity, stop bits and data size */
1454 writel(ucr2 | old_txrxen, sport->port.membase + UCR2);
1455
1456 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1457 imx_enable_ms(&sport->port);
1458
1459 if (sport->dma_is_inited && !sport->dma_is_enabled)
1460 imx_enable_dma(sport);
1461 spin_unlock_irqrestore(&sport->port.lock, flags);
1462}
1463
1464static const char *imx_type(struct uart_port *port)
1465{
1466 struct imx_port *sport = (struct imx_port *)port;
1467
1468 return sport->port.type == PORT_IMX ? "IMX" : NULL;
1469}
1470
1471/*
1472 * Configure/autoconfigure the port.
1473 */
1474static void imx_config_port(struct uart_port *port, int flags)
1475{
1476 struct imx_port *sport = (struct imx_port *)port;
1477
1478 if (flags & UART_CONFIG_TYPE)
1479 sport->port.type = PORT_IMX;
1480}
1481
1482/*
1483 * Verify the new serial_struct (for TIOCSSERIAL).
1484 * The only change we allow are to the flags and type, and
1485 * even then only between PORT_IMX and PORT_UNKNOWN
1486 */
1487static int
1488imx_verify_port(struct uart_port *port, struct serial_struct *ser)
1489{
1490 struct imx_port *sport = (struct imx_port *)port;
1491 int ret = 0;
1492
1493 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1494 ret = -EINVAL;
1495 if (sport->port.irq != ser->irq)
1496 ret = -EINVAL;
1497 if (ser->io_type != UPIO_MEM)
1498 ret = -EINVAL;
1499 if (sport->port.uartclk / 16 != ser->baud_base)
1500 ret = -EINVAL;
1501 if (sport->port.mapbase != (unsigned long)ser->iomem_base)
1502 ret = -EINVAL;
1503 if (sport->port.iobase != ser->port)
1504 ret = -EINVAL;
1505 if (ser->hub6 != 0)
1506 ret = -EINVAL;
1507 return ret;
1508}
1509
1510#if defined(CONFIG_CONSOLE_POLL)
1511static int imx_poll_get_char(struct uart_port *port)
1512{
1513 struct imx_port_ucrs old_ucr;
1514 unsigned int status;
1515 unsigned char c;
1516
1517 /* save control registers */
1518 imx_port_ucrs_save(port, &old_ucr);
1519
1520 /* disable interrupts */
1521 writel(UCR1_UARTEN, port->membase + UCR1);
1522 writel(old_ucr.ucr2 & ~(UCR2_ATEN | UCR2_RTSEN | UCR2_ESCI),
1523 port->membase + UCR2);
1524 writel(old_ucr.ucr3 & ~(UCR3_DCD | UCR3_RI | UCR3_DTREN),
1525 port->membase + UCR3);
1526
1527 /* poll */
1528 do {
1529 status = readl(port->membase + USR2);
1530 } while (~status & USR2_RDR);
1531
1532 /* read */
1533 c = readl(port->membase + URXD0);
1534
1535 /* restore control registers */
1536 imx_port_ucrs_restore(port, &old_ucr);
1537
1538 return c;
1539}
1540
1541static void imx_poll_put_char(struct uart_port *port, unsigned char c)
1542{
1543 struct imx_port_ucrs old_ucr;
1544 unsigned int status;
1545
1546 /* save control registers */
1547 imx_port_ucrs_save(port, &old_ucr);
1548
1549 /* disable interrupts */
1550 writel(UCR1_UARTEN, port->membase + UCR1);
1551 writel(old_ucr.ucr2 & ~(UCR2_ATEN | UCR2_RTSEN | UCR2_ESCI),
1552 port->membase + UCR2);
1553 writel(old_ucr.ucr3 & ~(UCR3_DCD | UCR3_RI | UCR3_DTREN),
1554 port->membase + UCR3);
1555
1556 /* drain */
1557 do {
1558 status = readl(port->membase + USR1);
1559 } while (~status & USR1_TRDY);
1560
1561 /* write */
1562 writel(c, port->membase + URTX0);
1563
1564 /* flush */
1565 do {
1566 status = readl(port->membase + USR2);
1567 } while (~status & USR2_TXDC);
1568
1569 /* restore control registers */
1570 imx_port_ucrs_restore(port, &old_ucr);
1571}
1572#endif
1573
1574static struct uart_ops imx_pops = {
1575 .tx_empty = imx_tx_empty,
1576 .set_mctrl = imx_set_mctrl,
1577 .get_mctrl = imx_get_mctrl,
1578 .stop_tx = imx_stop_tx,
1579 .start_tx = imx_start_tx,
1580 .stop_rx = imx_stop_rx,
1581 .enable_ms = imx_enable_ms,
1582 .break_ctl = imx_break_ctl,
1583 .startup = imx_startup,
1584 .shutdown = imx_shutdown,
1585 .flush_buffer = imx_flush_buffer,
1586 .set_termios = imx_set_termios,
1587 .type = imx_type,
1588 .config_port = imx_config_port,
1589 .verify_port = imx_verify_port,
1590#if defined(CONFIG_CONSOLE_POLL)
1591 .poll_get_char = imx_poll_get_char,
1592 .poll_put_char = imx_poll_put_char,
1593#endif
1594};
1595
1596static struct imx_port *imx_ports[UART_NR];
1597
1598#ifdef CONFIG_SERIAL_IMX_CONSOLE
1599static void imx_console_putchar(struct uart_port *port, int ch)
1600{
1601 struct imx_port *sport = (struct imx_port *)port;
1602
1603 while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)
1604 barrier();
1605
1606 writel(ch, sport->port.membase + URTX0);
1607}
1608
1609/*
1610 * Interrupts are disabled on entering
1611 */
1612static void
1613imx_console_write(struct console *co, const char *s, unsigned int count)
1614{
1615 struct imx_port *sport = imx_ports[co->index];
1616 struct imx_port_ucrs old_ucr;
1617 unsigned int ucr1;
1618 unsigned long flags = 0;
1619 int locked = 1;
1620 int retval;
1621
1622 retval = clk_enable(sport->clk_per);
1623 if (retval)
1624 return;
1625 retval = clk_enable(sport->clk_ipg);
1626 if (retval) {
1627 clk_disable(sport->clk_per);
1628 return;
1629 }
1630
1631 if (sport->port.sysrq)
1632 locked = 0;
1633 else if (oops_in_progress)
1634 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1635 else
1636 spin_lock_irqsave(&sport->port.lock, flags);
1637
1638 /*
1639 * First, save UCR1/2/3 and then disable interrupts
1640 */
1641 imx_port_ucrs_save(&sport->port, &old_ucr);
1642 ucr1 = old_ucr.ucr1;
1643
1644 if (is_imx1_uart(sport))
1645 ucr1 |= IMX1_UCR1_UARTCLKEN;
1646 ucr1 |= UCR1_UARTEN;
1647 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1648
1649 writel(ucr1, sport->port.membase + UCR1);
1650
1651 writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
1652
1653 uart_console_write(&sport->port, s, count, imx_console_putchar);
1654
1655 /*
1656 * Finally, wait for transmitter to become empty
1657 * and restore UCR1/2/3
1658 */
1659 while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
1660
1661 imx_port_ucrs_restore(&sport->port, &old_ucr);
1662
1663 if (locked)
1664 spin_unlock_irqrestore(&sport->port.lock, flags);
1665
1666 clk_disable(sport->clk_ipg);
1667 clk_disable(sport->clk_per);
1668}
1669
1670/*
1671 * If the port was already initialised (eg, by a boot loader),
1672 * try to determine the current setup.
1673 */
1674static void __init
1675imx_console_get_options(struct imx_port *sport, int *baud,
1676 int *parity, int *bits)
1677{
1678
1679 if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {
1680 /* ok, the port was enabled */
1681 unsigned int ucr2, ubir, ubmr, uartclk;
1682 unsigned int baud_raw;
1683 unsigned int ucfr_rfdiv;
1684
1685 ucr2 = readl(sport->port.membase + UCR2);
1686
1687 *parity = 'n';
1688 if (ucr2 & UCR2_PREN) {
1689 if (ucr2 & UCR2_PROE)
1690 *parity = 'o';
1691 else
1692 *parity = 'e';
1693 }
1694
1695 if (ucr2 & UCR2_WS)
1696 *bits = 8;
1697 else
1698 *bits = 7;
1699
1700 ubir = readl(sport->port.membase + UBIR) & 0xffff;
1701 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
1702
1703 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
1704 if (ucfr_rfdiv == 6)
1705 ucfr_rfdiv = 7;
1706 else
1707 ucfr_rfdiv = 6 - ucfr_rfdiv;
1708
1709 uartclk = clk_get_rate(sport->clk_per);
1710 uartclk /= ucfr_rfdiv;
1711
1712 { /*
1713 * The next code provides exact computation of
1714 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1715 * without need of float support or long long division,
1716 * which would be required to prevent 32bit arithmetic overflow
1717 */
1718 unsigned int mul = ubir + 1;
1719 unsigned int div = 16 * (ubmr + 1);
1720 unsigned int rem = uartclk % div;
1721
1722 baud_raw = (uartclk / div) * mul;
1723 baud_raw += (rem * mul + div / 2) / div;
1724 *baud = (baud_raw + 50) / 100 * 100;
1725 }
1726
1727 if (*baud != baud_raw)
1728 pr_info("Console IMX rounded baud rate from %d to %d\n",
1729 baud_raw, *baud);
1730 }
1731}
1732
1733static int __init
1734imx_console_setup(struct console *co, char *options)
1735{
1736 struct imx_port *sport;
1737 int baud = 9600;
1738 int bits = 8;
1739 int parity = 'n';
1740 int flow = 'n';
1741 int retval;
1742
1743 /*
1744 * Check whether an invalid uart number has been specified, and
1745 * if so, search for the first available port that does have
1746 * console support.
1747 */
1748 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1749 co->index = 0;
1750 sport = imx_ports[co->index];
1751 if (sport == NULL)
1752 return -ENODEV;
1753
1754 /* For setting the registers, we only need to enable the ipg clock. */
1755 retval = clk_prepare_enable(sport->clk_ipg);
1756 if (retval)
1757 goto error_console;
1758
1759 if (options)
1760 uart_parse_options(options, &baud, &parity, &bits, &flow);
1761 else
1762 imx_console_get_options(sport, &baud, &parity, &bits);
1763
1764 imx_setup_ufcr(sport, 0);
1765
1766 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
1767
1768 clk_disable(sport->clk_ipg);
1769 if (retval) {
1770 clk_unprepare(sport->clk_ipg);
1771 goto error_console;
1772 }
1773
1774 retval = clk_prepare(sport->clk_per);
1775 if (retval)
1776 clk_disable_unprepare(sport->clk_ipg);
1777
1778error_console:
1779 return retval;
1780}
1781
1782static struct uart_driver imx_reg;
1783static struct console imx_console = {
1784 .name = DEV_NAME,
1785 .write = imx_console_write,
1786 .device = uart_console_device,
1787 .setup = imx_console_setup,
1788 .flags = CON_PRINTBUFFER,
1789 .index = -1,
1790 .data = &imx_reg,
1791};
1792
1793#define IMX_CONSOLE &imx_console
1794#else
1795#define IMX_CONSOLE NULL
1796#endif
1797
1798static struct uart_driver imx_reg = {
1799 .owner = THIS_MODULE,
1800 .driver_name = DRIVER_NAME,
1801 .dev_name = DEV_NAME,
1802 .major = SERIAL_IMX_MAJOR,
1803 .minor = MINOR_START,
1804 .nr = ARRAY_SIZE(imx_ports),
1805 .cons = IMX_CONSOLE,
1806};
1807
1808static int serial_imx_suspend(struct platform_device *dev, pm_message_t state)
1809{
1810 struct imx_port *sport = platform_get_drvdata(dev);
1811 unsigned int val;
1812
1813 /* enable wakeup from i.MX UART */
1814 val = readl(sport->port.membase + UCR3);
1815 val |= UCR3_AWAKEN;
1816 writel(val, sport->port.membase + UCR3);
1817
1818 uart_suspend_port(&imx_reg, &sport->port);
1819
1820 return 0;
1821}
1822
1823static int serial_imx_resume(struct platform_device *dev)
1824{
1825 struct imx_port *sport = platform_get_drvdata(dev);
1826 unsigned int val;
1827
1828 /* disable wakeup from i.MX UART */
1829 val = readl(sport->port.membase + UCR3);
1830 val &= ~UCR3_AWAKEN;
1831 writel(val, sport->port.membase + UCR3);
1832
1833 uart_resume_port(&imx_reg, &sport->port);
1834
1835 return 0;
1836}
1837
1838#ifdef CONFIG_OF
1839/*
1840 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
1841 * could successfully get all information from dt or a negative errno.
1842 */
1843static int serial_imx_probe_dt(struct imx_port *sport,
1844 struct platform_device *pdev)
1845{
1846 struct device_node *np = pdev->dev.of_node;
1847 const struct of_device_id *of_id =
1848 of_match_device(imx_uart_dt_ids, &pdev->dev);
1849 int ret;
1850
1851 if (!np)
1852 /* no device tree device */
1853 return 1;
1854
1855 ret = of_alias_get_id(np, "serial");
1856 if (ret < 0) {
1857 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
1858 return ret;
1859 }
1860 sport->port.line = ret;
1861
1862 if (of_get_property(np, "fsl,uart-has-rtscts", NULL))
1863 sport->have_rtscts = 1;
1864
1865 if (of_get_property(np, "fsl,irda-mode", NULL))
1866 sport->use_irda = 1;
1867
1868 if (of_get_property(np, "fsl,dte-mode", NULL))
1869 sport->dte_mode = 1;
1870
1871 sport->devdata = of_id->data;
1872
1873 return 0;
1874}
1875#else
1876static inline int serial_imx_probe_dt(struct imx_port *sport,
1877 struct platform_device *pdev)
1878{
1879 return 1;
1880}
1881#endif
1882
1883static void serial_imx_probe_pdata(struct imx_port *sport,
1884 struct platform_device *pdev)
1885{
1886 struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev);
1887
1888 sport->port.line = pdev->id;
1889 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data;
1890
1891 if (!pdata)
1892 return;
1893
1894 if (pdata->flags & IMXUART_HAVE_RTSCTS)
1895 sport->have_rtscts = 1;
1896
1897 if (pdata->flags & IMXUART_IRDA)
1898 sport->use_irda = 1;
1899}
1900
1901static int serial_imx_probe(struct platform_device *pdev)
1902{
1903 struct imx_port *sport;
1904 void __iomem *base;
1905 int ret = 0;
1906 struct resource *res;
1907
1908 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
1909 if (!sport)
1910 return -ENOMEM;
1911
1912 ret = serial_imx_probe_dt(sport, pdev);
1913 if (ret > 0)
1914 serial_imx_probe_pdata(sport, pdev);
1915 else if (ret < 0)
1916 return ret;
1917
1918 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1919 base = devm_ioremap_resource(&pdev->dev, res);
1920 if (IS_ERR(base))
1921 return PTR_ERR(base);
1922
1923 sport->port.dev = &pdev->dev;
1924 sport->port.mapbase = res->start;
1925 sport->port.membase = base;
1926 sport->port.type = PORT_IMX,
1927 sport->port.iotype = UPIO_MEM;
1928 sport->port.irq = platform_get_irq(pdev, 0);
1929 sport->rxirq = platform_get_irq(pdev, 0);
1930 sport->txirq = platform_get_irq(pdev, 1);
1931 sport->rtsirq = platform_get_irq(pdev, 2);
1932 sport->port.fifosize = 32;
1933 sport->port.ops = &imx_pops;
1934 sport->port.flags = UPF_BOOT_AUTOCONF;
1935 init_timer(&sport->timer);
1936 sport->timer.function = imx_timeout;
1937 sport->timer.data = (unsigned long)sport;
1938
1939 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1940 if (IS_ERR(sport->clk_ipg)) {
1941 ret = PTR_ERR(sport->clk_ipg);
1942 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
1943 return ret;
1944 }
1945
1946 sport->clk_per = devm_clk_get(&pdev->dev, "per");
1947 if (IS_ERR(sport->clk_per)) {
1948 ret = PTR_ERR(sport->clk_per);
1949 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
1950 return ret;
1951 }
1952
1953 sport->port.uartclk = clk_get_rate(sport->clk_per);
1954
1955 imx_ports[sport->port.line] = sport;
1956
1957 platform_set_drvdata(pdev, sport);
1958
1959 return uart_add_one_port(&imx_reg, &sport->port);
1960}
1961
1962static int serial_imx_remove(struct platform_device *pdev)
1963{
1964 struct imx_port *sport = platform_get_drvdata(pdev);
1965
1966 return uart_remove_one_port(&imx_reg, &sport->port);
1967}
1968
1969static struct platform_driver serial_imx_driver = {
1970 .probe = serial_imx_probe,
1971 .remove = serial_imx_remove,
1972
1973 .suspend = serial_imx_suspend,
1974 .resume = serial_imx_resume,
1975 .id_table = imx_uart_devtype,
1976 .driver = {
1977 .name = "imx-uart",
1978 .owner = THIS_MODULE,
1979 .of_match_table = imx_uart_dt_ids,
1980 },
1981};
1982
1983static int __init imx_serial_init(void)
1984{
1985 int ret;
1986
1987 pr_info("Serial: IMX driver\n");
1988
1989 ret = uart_register_driver(&imx_reg);
1990 if (ret)
1991 return ret;
1992
1993 ret = platform_driver_register(&serial_imx_driver);
1994 if (ret != 0)
1995 uart_unregister_driver(&imx_reg);
1996
1997 return ret;
1998}
1999
2000static void __exit imx_serial_exit(void)
2001{
2002 platform_driver_unregister(&serial_imx_driver);
2003 uart_unregister_driver(&imx_reg);
2004}
2005
2006module_init(imx_serial_init);
2007module_exit(imx_serial_exit);
2008
2009MODULE_AUTHOR("Sascha Hauer");
2010MODULE_DESCRIPTION("IMX generic serial port driver");
2011MODULE_LICENSE("GPL");
2012MODULE_ALIAS("platform:imx-uart");