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1/*
2 * PMC-Sierra SPCv/ve 8088/8089 SAS/SATA based host adapters driver
3 *
4 * Copyright (c) 2008-2009 PMC-Sierra, Inc.,
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
25 *
26 * NO WARRANTY
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
38 *
39 */
40 #include <linux/slab.h>
41 #include "pm8001_sas.h"
42 #include "pm80xx_hwi.h"
43 #include "pm8001_chips.h"
44 #include "pm8001_ctl.h"
45
46#define SMP_DIRECT 1
47#define SMP_INDIRECT 2
48
49
50int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shift_value)
51{
52 u32 reg_val;
53 unsigned long start;
54 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, shift_value);
55 /* confirm the setting is written */
56 start = jiffies + HZ; /* 1 sec */
57 do {
58 reg_val = pm8001_cr32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER);
59 } while ((reg_val != shift_value) && time_before(jiffies, start));
60 if (reg_val != shift_value) {
61 PM8001_FAIL_DBG(pm8001_ha,
62 pm8001_printk("TIMEOUT:MEMBASE_II_SHIFT_REGISTER"
63 " = 0x%x\n", reg_val));
64 return -1;
65 }
66 return 0;
67}
68
69void pm80xx_pci_mem_copy(struct pm8001_hba_info *pm8001_ha, u32 soffset,
70 const void *destination,
71 u32 dw_count, u32 bus_base_number)
72{
73 u32 index, value, offset;
74 u32 *destination1;
75 destination1 = (u32 *)destination;
76
77 for (index = 0; index < dw_count; index += 4, destination1++) {
78 offset = (soffset + index / 4);
79 if (offset < (64 * 1024)) {
80 value = pm8001_cr32(pm8001_ha, bus_base_number, offset);
81 *destination1 = cpu_to_le32(value);
82 }
83 }
84 return;
85}
86
87ssize_t pm80xx_get_fatal_dump(struct device *cdev,
88 struct device_attribute *attr, char *buf)
89{
90 struct Scsi_Host *shost = class_to_shost(cdev);
91 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
92 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
93 void __iomem *fatal_table_address = pm8001_ha->fatal_tbl_addr;
94 u32 accum_len , reg_val, index, *temp;
95 unsigned long start;
96 u8 *direct_data;
97 char *fatal_error_data = buf;
98
99 pm8001_ha->forensic_info.data_buf.direct_data = buf;
100 if (pm8001_ha->chip_id == chip_8001) {
101 pm8001_ha->forensic_info.data_buf.direct_data +=
102 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
103 "Not supported for SPC controller");
104 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
105 (char *)buf;
106 }
107 if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) {
108 PM8001_IO_DBG(pm8001_ha,
109 pm8001_printk("forensic_info TYPE_NON_FATAL..............\n"));
110 direct_data = (u8 *)fatal_error_data;
111 pm8001_ha->forensic_info.data_type = TYPE_NON_FATAL;
112 pm8001_ha->forensic_info.data_buf.direct_len = SYSFS_OFFSET;
113 pm8001_ha->forensic_info.data_buf.read_len = 0;
114
115 pm8001_ha->forensic_info.data_buf.direct_data = direct_data;
116
117 /* start to get data */
118 /* Program the MEMBASE II Shifting Register with 0x00.*/
119 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
120 pm8001_ha->fatal_forensic_shift_offset);
121 pm8001_ha->forensic_last_offset = 0;
122 pm8001_ha->forensic_fatal_step = 0;
123 pm8001_ha->fatal_bar_loc = 0;
124 }
125
126 /* Read until accum_len is retrived */
127 accum_len = pm8001_mr32(fatal_table_address,
128 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);
129 PM8001_IO_DBG(pm8001_ha, pm8001_printk("accum_len 0x%x\n",
130 accum_len));
131 if (accum_len == 0xFFFFFFFF) {
132 PM8001_IO_DBG(pm8001_ha,
133 pm8001_printk("Possible PCI issue 0x%x not expected\n",
134 accum_len));
135 return -EIO;
136 }
137 if (accum_len == 0 || accum_len >= 0x100000) {
138 pm8001_ha->forensic_info.data_buf.direct_data +=
139 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
140 "%08x ", 0xFFFFFFFF);
141 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
142 (char *)buf;
143 }
144 temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr;
145 if (pm8001_ha->forensic_fatal_step == 0) {
146moreData:
147 if (pm8001_ha->forensic_info.data_buf.direct_data) {
148 /* Data is in bar, copy to host memory */
149 pm80xx_pci_mem_copy(pm8001_ha, pm8001_ha->fatal_bar_loc,
150 pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr,
151 pm8001_ha->forensic_info.data_buf.direct_len ,
152 1);
153 }
154 pm8001_ha->fatal_bar_loc +=
155 pm8001_ha->forensic_info.data_buf.direct_len;
156 pm8001_ha->forensic_info.data_buf.direct_offset +=
157 pm8001_ha->forensic_info.data_buf.direct_len;
158 pm8001_ha->forensic_last_offset +=
159 pm8001_ha->forensic_info.data_buf.direct_len;
160 pm8001_ha->forensic_info.data_buf.read_len =
161 pm8001_ha->forensic_info.data_buf.direct_len;
162
163 if (pm8001_ha->forensic_last_offset >= accum_len) {
164 pm8001_ha->forensic_info.data_buf.direct_data +=
165 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
166 "%08x ", 3);
167 for (index = 0; index < (SYSFS_OFFSET / 4); index++) {
168 pm8001_ha->forensic_info.data_buf.direct_data +=
169 sprintf(pm8001_ha->
170 forensic_info.data_buf.direct_data,
171 "%08x ", *(temp + index));
172 }
173
174 pm8001_ha->fatal_bar_loc = 0;
175 pm8001_ha->forensic_fatal_step = 1;
176 pm8001_ha->fatal_forensic_shift_offset = 0;
177 pm8001_ha->forensic_last_offset = 0;
178 return (char *)pm8001_ha->
179 forensic_info.data_buf.direct_data -
180 (char *)buf;
181 }
182 if (pm8001_ha->fatal_bar_loc < (64 * 1024)) {
183 pm8001_ha->forensic_info.data_buf.direct_data +=
184 sprintf(pm8001_ha->
185 forensic_info.data_buf.direct_data,
186 "%08x ", 2);
187 for (index = 0; index < (SYSFS_OFFSET / 4); index++) {
188 pm8001_ha->forensic_info.data_buf.direct_data +=
189 sprintf(pm8001_ha->
190 forensic_info.data_buf.direct_data,
191 "%08x ", *(temp + index));
192 }
193 return (char *)pm8001_ha->
194 forensic_info.data_buf.direct_data -
195 (char *)buf;
196 }
197
198 /* Increment the MEMBASE II Shifting Register value by 0x100.*/
199 pm8001_ha->forensic_info.data_buf.direct_data +=
200 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
201 "%08x ", 2);
202 for (index = 0; index < 256; index++) {
203 pm8001_ha->forensic_info.data_buf.direct_data +=
204 sprintf(pm8001_ha->
205 forensic_info.data_buf.direct_data,
206 "%08x ", *(temp + index));
207 }
208 pm8001_ha->fatal_forensic_shift_offset += 0x100;
209 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
210 pm8001_ha->fatal_forensic_shift_offset);
211 pm8001_ha->fatal_bar_loc = 0;
212 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
213 (char *)buf;
214 }
215 if (pm8001_ha->forensic_fatal_step == 1) {
216 pm8001_ha->fatal_forensic_shift_offset = 0;
217 /* Read 64K of the debug data. */
218 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
219 pm8001_ha->fatal_forensic_shift_offset);
220 pm8001_mw32(fatal_table_address,
221 MPI_FATAL_EDUMP_TABLE_HANDSHAKE,
222 MPI_FATAL_EDUMP_HANDSHAKE_RDY);
223
224 /* Poll FDDHSHK until clear */
225 start = jiffies + (2 * HZ); /* 2 sec */
226
227 do {
228 reg_val = pm8001_mr32(fatal_table_address,
229 MPI_FATAL_EDUMP_TABLE_HANDSHAKE);
230 } while ((reg_val) && time_before(jiffies, start));
231
232 if (reg_val != 0) {
233 PM8001_FAIL_DBG(pm8001_ha,
234 pm8001_printk("TIMEOUT:MEMBASE_II_SHIFT_REGISTER"
235 " = 0x%x\n", reg_val));
236 return -EIO;
237 }
238
239 /* Read the next 64K of the debug data. */
240 pm8001_ha->forensic_fatal_step = 0;
241 if (pm8001_mr32(fatal_table_address,
242 MPI_FATAL_EDUMP_TABLE_STATUS) !=
243 MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) {
244 pm8001_mw32(fatal_table_address,
245 MPI_FATAL_EDUMP_TABLE_HANDSHAKE, 0);
246 goto moreData;
247 } else {
248 pm8001_ha->forensic_info.data_buf.direct_data +=
249 sprintf(pm8001_ha->
250 forensic_info.data_buf.direct_data,
251 "%08x ", 4);
252 pm8001_ha->forensic_info.data_buf.read_len = 0xFFFFFFFF;
253 pm8001_ha->forensic_info.data_buf.direct_len = 0;
254 pm8001_ha->forensic_info.data_buf.direct_offset = 0;
255 pm8001_ha->forensic_info.data_buf.read_len = 0;
256 }
257 }
258
259 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
260 (char *)buf;
261}
262
263/**
264 * read_main_config_table - read the configure table and save it.
265 * @pm8001_ha: our hba card information
266 */
267static void read_main_config_table(struct pm8001_hba_info *pm8001_ha)
268{
269 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
270
271 pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature =
272 pm8001_mr32(address, MAIN_SIGNATURE_OFFSET);
273 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev =
274 pm8001_mr32(address, MAIN_INTERFACE_REVISION);
275 pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev =
276 pm8001_mr32(address, MAIN_FW_REVISION);
277 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io =
278 pm8001_mr32(address, MAIN_MAX_OUTSTANDING_IO_OFFSET);
279 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_sgl =
280 pm8001_mr32(address, MAIN_MAX_SGL_OFFSET);
281 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ctrl_cap_flag =
282 pm8001_mr32(address, MAIN_CNTRL_CAP_OFFSET);
283 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset =
284 pm8001_mr32(address, MAIN_GST_OFFSET);
285 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset =
286 pm8001_mr32(address, MAIN_IBQ_OFFSET);
287 pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset =
288 pm8001_mr32(address, MAIN_OBQ_OFFSET);
289
290 /* read Error Dump Offset and Length */
291 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset0 =
292 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
293 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length0 =
294 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
295 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset1 =
296 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
297 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length1 =
298 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
299
300 /* read GPIO LED settings from the configuration table */
301 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping =
302 pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET);
303
304 /* read analog Setting offset from the configuration table */
305 pm8001_ha->main_cfg_tbl.pm80xx_tbl.analog_setup_table_offset =
306 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
307
308 pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset =
309 pm8001_mr32(address, MAIN_INT_VECTOR_TABLE_OFFSET);
310 pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset =
311 pm8001_mr32(address, MAIN_SAS_PHY_ATTR_TABLE_OFFSET);
312}
313
314/**
315 * read_general_status_table - read the general status table and save it.
316 * @pm8001_ha: our hba card information
317 */
318static void read_general_status_table(struct pm8001_hba_info *pm8001_ha)
319{
320 void __iomem *address = pm8001_ha->general_stat_tbl_addr;
321 pm8001_ha->gs_tbl.pm80xx_tbl.gst_len_mpistate =
322 pm8001_mr32(address, GST_GSTLEN_MPIS_OFFSET);
323 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state0 =
324 pm8001_mr32(address, GST_IQ_FREEZE_STATE0_OFFSET);
325 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state1 =
326 pm8001_mr32(address, GST_IQ_FREEZE_STATE1_OFFSET);
327 pm8001_ha->gs_tbl.pm80xx_tbl.msgu_tcnt =
328 pm8001_mr32(address, GST_MSGUTCNT_OFFSET);
329 pm8001_ha->gs_tbl.pm80xx_tbl.iop_tcnt =
330 pm8001_mr32(address, GST_IOPTCNT_OFFSET);
331 pm8001_ha->gs_tbl.pm80xx_tbl.gpio_input_val =
332 pm8001_mr32(address, GST_GPIO_INPUT_VAL);
333 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[0] =
334 pm8001_mr32(address, GST_RERRINFO_OFFSET0);
335 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[1] =
336 pm8001_mr32(address, GST_RERRINFO_OFFSET1);
337 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[2] =
338 pm8001_mr32(address, GST_RERRINFO_OFFSET2);
339 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[3] =
340 pm8001_mr32(address, GST_RERRINFO_OFFSET3);
341 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[4] =
342 pm8001_mr32(address, GST_RERRINFO_OFFSET4);
343 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[5] =
344 pm8001_mr32(address, GST_RERRINFO_OFFSET5);
345 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[6] =
346 pm8001_mr32(address, GST_RERRINFO_OFFSET6);
347 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[7] =
348 pm8001_mr32(address, GST_RERRINFO_OFFSET7);
349}
350/**
351 * read_phy_attr_table - read the phy attribute table and save it.
352 * @pm8001_ha: our hba card information
353 */
354static void read_phy_attr_table(struct pm8001_hba_info *pm8001_ha)
355{
356 void __iomem *address = pm8001_ha->pspa_q_tbl_addr;
357 pm8001_ha->phy_attr_table.phystart1_16[0] =
358 pm8001_mr32(address, PSPA_PHYSTATE0_OFFSET);
359 pm8001_ha->phy_attr_table.phystart1_16[1] =
360 pm8001_mr32(address, PSPA_PHYSTATE1_OFFSET);
361 pm8001_ha->phy_attr_table.phystart1_16[2] =
362 pm8001_mr32(address, PSPA_PHYSTATE2_OFFSET);
363 pm8001_ha->phy_attr_table.phystart1_16[3] =
364 pm8001_mr32(address, PSPA_PHYSTATE3_OFFSET);
365 pm8001_ha->phy_attr_table.phystart1_16[4] =
366 pm8001_mr32(address, PSPA_PHYSTATE4_OFFSET);
367 pm8001_ha->phy_attr_table.phystart1_16[5] =
368 pm8001_mr32(address, PSPA_PHYSTATE5_OFFSET);
369 pm8001_ha->phy_attr_table.phystart1_16[6] =
370 pm8001_mr32(address, PSPA_PHYSTATE6_OFFSET);
371 pm8001_ha->phy_attr_table.phystart1_16[7] =
372 pm8001_mr32(address, PSPA_PHYSTATE7_OFFSET);
373 pm8001_ha->phy_attr_table.phystart1_16[8] =
374 pm8001_mr32(address, PSPA_PHYSTATE8_OFFSET);
375 pm8001_ha->phy_attr_table.phystart1_16[9] =
376 pm8001_mr32(address, PSPA_PHYSTATE9_OFFSET);
377 pm8001_ha->phy_attr_table.phystart1_16[10] =
378 pm8001_mr32(address, PSPA_PHYSTATE10_OFFSET);
379 pm8001_ha->phy_attr_table.phystart1_16[11] =
380 pm8001_mr32(address, PSPA_PHYSTATE11_OFFSET);
381 pm8001_ha->phy_attr_table.phystart1_16[12] =
382 pm8001_mr32(address, PSPA_PHYSTATE12_OFFSET);
383 pm8001_ha->phy_attr_table.phystart1_16[13] =
384 pm8001_mr32(address, PSPA_PHYSTATE13_OFFSET);
385 pm8001_ha->phy_attr_table.phystart1_16[14] =
386 pm8001_mr32(address, PSPA_PHYSTATE14_OFFSET);
387 pm8001_ha->phy_attr_table.phystart1_16[15] =
388 pm8001_mr32(address, PSPA_PHYSTATE15_OFFSET);
389
390 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[0] =
391 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID0_OFFSET);
392 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[1] =
393 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID1_OFFSET);
394 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[2] =
395 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID2_OFFSET);
396 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[3] =
397 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID3_OFFSET);
398 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[4] =
399 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID4_OFFSET);
400 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[5] =
401 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID5_OFFSET);
402 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[6] =
403 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID6_OFFSET);
404 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[7] =
405 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID7_OFFSET);
406 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[8] =
407 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID8_OFFSET);
408 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[9] =
409 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID9_OFFSET);
410 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[10] =
411 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID10_OFFSET);
412 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[11] =
413 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID11_OFFSET);
414 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[12] =
415 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID12_OFFSET);
416 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[13] =
417 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID13_OFFSET);
418 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[14] =
419 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID14_OFFSET);
420 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[15] =
421 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID15_OFFSET);
422
423}
424
425/**
426 * read_inbnd_queue_table - read the inbound queue table and save it.
427 * @pm8001_ha: our hba card information
428 */
429static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
430{
431 int i;
432 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
433 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
434 u32 offset = i * 0x20;
435 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
436 get_pci_bar_index(pm8001_mr32(address,
437 (offset + IB_PIPCI_BAR)));
438 pm8001_ha->inbnd_q_tbl[i].pi_offset =
439 pm8001_mr32(address, (offset + IB_PIPCI_BAR_OFFSET));
440 }
441}
442
443/**
444 * read_outbnd_queue_table - read the outbound queue table and save it.
445 * @pm8001_ha: our hba card information
446 */
447static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
448{
449 int i;
450 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
451 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
452 u32 offset = i * 0x24;
453 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
454 get_pci_bar_index(pm8001_mr32(address,
455 (offset + OB_CIPCI_BAR)));
456 pm8001_ha->outbnd_q_tbl[i].ci_offset =
457 pm8001_mr32(address, (offset + OB_CIPCI_BAR_OFFSET));
458 }
459}
460
461/**
462 * init_default_table_values - init the default table.
463 * @pm8001_ha: our hba card information
464 */
465static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
466{
467 int i;
468 u32 offsetib, offsetob;
469 void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
470 void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
471
472 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr =
473 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
474 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr =
475 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
476 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size =
477 PM8001_EVENT_LOG_SIZE;
478 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity = 0x01;
479 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr =
480 pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
481 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr =
482 pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
483 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size =
484 PM8001_EVENT_LOG_SIZE;
485 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity = 0x01;
486 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt = 0x01;
487
488 /* Disable end to end CRC checking */
489 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump = (0x1 << 16);
490
491 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
492 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt =
493 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30);
494 pm8001_ha->inbnd_q_tbl[i].upper_base_addr =
495 pm8001_ha->memoryMap.region[IB + i].phys_addr_hi;
496 pm8001_ha->inbnd_q_tbl[i].lower_base_addr =
497 pm8001_ha->memoryMap.region[IB + i].phys_addr_lo;
498 pm8001_ha->inbnd_q_tbl[i].base_virt =
499 (u8 *)pm8001_ha->memoryMap.region[IB + i].virt_ptr;
500 pm8001_ha->inbnd_q_tbl[i].total_length =
501 pm8001_ha->memoryMap.region[IB + i].total_len;
502 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr =
503 pm8001_ha->memoryMap.region[CI + i].phys_addr_hi;
504 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr =
505 pm8001_ha->memoryMap.region[CI + i].phys_addr_lo;
506 pm8001_ha->inbnd_q_tbl[i].ci_virt =
507 pm8001_ha->memoryMap.region[CI + i].virt_ptr;
508 offsetib = i * 0x20;
509 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
510 get_pci_bar_index(pm8001_mr32(addressib,
511 (offsetib + 0x14)));
512 pm8001_ha->inbnd_q_tbl[i].pi_offset =
513 pm8001_mr32(addressib, (offsetib + 0x18));
514 pm8001_ha->inbnd_q_tbl[i].producer_idx = 0;
515 pm8001_ha->inbnd_q_tbl[i].consumer_index = 0;
516 }
517 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
518 pm8001_ha->outbnd_q_tbl[i].element_size_cnt =
519 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30);
520 pm8001_ha->outbnd_q_tbl[i].upper_base_addr =
521 pm8001_ha->memoryMap.region[OB + i].phys_addr_hi;
522 pm8001_ha->outbnd_q_tbl[i].lower_base_addr =
523 pm8001_ha->memoryMap.region[OB + i].phys_addr_lo;
524 pm8001_ha->outbnd_q_tbl[i].base_virt =
525 (u8 *)pm8001_ha->memoryMap.region[OB + i].virt_ptr;
526 pm8001_ha->outbnd_q_tbl[i].total_length =
527 pm8001_ha->memoryMap.region[OB + i].total_len;
528 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr =
529 pm8001_ha->memoryMap.region[PI + i].phys_addr_hi;
530 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr =
531 pm8001_ha->memoryMap.region[PI + i].phys_addr_lo;
532 /* interrupt vector based on oq */
533 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = (i << 24);
534 pm8001_ha->outbnd_q_tbl[i].pi_virt =
535 pm8001_ha->memoryMap.region[PI + i].virt_ptr;
536 offsetob = i * 0x24;
537 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
538 get_pci_bar_index(pm8001_mr32(addressob,
539 offsetob + 0x14));
540 pm8001_ha->outbnd_q_tbl[i].ci_offset =
541 pm8001_mr32(addressob, (offsetob + 0x18));
542 pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0;
543 pm8001_ha->outbnd_q_tbl[i].producer_index = 0;
544 }
545}
546
547/**
548 * update_main_config_table - update the main default table to the HBA.
549 * @pm8001_ha: our hba card information
550 */
551static void update_main_config_table(struct pm8001_hba_info *pm8001_ha)
552{
553 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
554 pm8001_mw32(address, MAIN_IQNPPD_HPPD_OFFSET,
555 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_q_nppd_hppd);
556 pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_HI,
557 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr);
558 pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_LO,
559 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr);
560 pm8001_mw32(address, MAIN_EVENT_LOG_BUFF_SIZE,
561 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size);
562 pm8001_mw32(address, MAIN_EVENT_LOG_OPTION,
563 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity);
564 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_HI,
565 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr);
566 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_LO,
567 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr);
568 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_BUFF_SIZE,
569 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size);
570 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_OPTION,
571 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity);
572 pm8001_mw32(address, MAIN_FATAL_ERROR_INTERRUPT,
573 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt);
574 pm8001_mw32(address, MAIN_EVENT_CRC_CHECK,
575 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump);
576
577 /* SPCv specific */
578 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping &= 0xCFFFFFFF;
579 /* Set GPIOLED to 0x2 for LED indicator */
580 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping |= 0x20000000;
581 pm8001_mw32(address, MAIN_GPIO_LED_FLAGS_OFFSET,
582 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping);
583
584 pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER,
585 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);
586 pm8001_mw32(address, MAIN_INT_REASSERTION_DELAY,
587 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interrupt_reassertion_delay);
588}
589
590/**
591 * update_inbnd_queue_table - update the inbound queue table to the HBA.
592 * @pm8001_ha: our hba card information
593 */
594static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
595 int number)
596{
597 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
598 u16 offset = number * 0x20;
599 pm8001_mw32(address, offset + IB_PROPERITY_OFFSET,
600 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
601 pm8001_mw32(address, offset + IB_BASE_ADDR_HI_OFFSET,
602 pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
603 pm8001_mw32(address, offset + IB_BASE_ADDR_LO_OFFSET,
604 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
605 pm8001_mw32(address, offset + IB_CI_BASE_ADDR_HI_OFFSET,
606 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
607 pm8001_mw32(address, offset + IB_CI_BASE_ADDR_LO_OFFSET,
608 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
609}
610
611/**
612 * update_outbnd_queue_table - update the outbound queue table to the HBA.
613 * @pm8001_ha: our hba card information
614 */
615static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
616 int number)
617{
618 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
619 u16 offset = number * 0x24;
620 pm8001_mw32(address, offset + OB_PROPERITY_OFFSET,
621 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
622 pm8001_mw32(address, offset + OB_BASE_ADDR_HI_OFFSET,
623 pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
624 pm8001_mw32(address, offset + OB_BASE_ADDR_LO_OFFSET,
625 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
626 pm8001_mw32(address, offset + OB_PI_BASE_ADDR_HI_OFFSET,
627 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
628 pm8001_mw32(address, offset + OB_PI_BASE_ADDR_LO_OFFSET,
629 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
630 pm8001_mw32(address, offset + OB_INTERRUPT_COALES_OFFSET,
631 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
632}
633
634/**
635 * mpi_init_check - check firmware initialization status.
636 * @pm8001_ha: our hba card information
637 */
638static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
639{
640 u32 max_wait_count;
641 u32 value;
642 u32 gst_len_mpistate;
643
644 /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
645 table is updated */
646 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_UPDATE);
647 /* wait until Inbound DoorBell Clear Register toggled */
648 if (IS_SPCV_12G(pm8001_ha->pdev)) {
649 max_wait_count = 4 * 1000 * 1000;/* 4 sec */
650 } else {
651 max_wait_count = 2 * 1000 * 1000;/* 2 sec */
652 }
653 do {
654 udelay(1);
655 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
656 value &= SPCv_MSGU_CFG_TABLE_UPDATE;
657 } while ((value != 0) && (--max_wait_count));
658
659 if (!max_wait_count)
660 return -1;
661 /* check the MPI-State for initialization upto 100ms*/
662 max_wait_count = 100 * 1000;/* 100 msec */
663 do {
664 udelay(1);
665 gst_len_mpistate =
666 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
667 GST_GSTLEN_MPIS_OFFSET);
668 } while ((GST_MPI_STATE_INIT !=
669 (gst_len_mpistate & GST_MPI_STATE_MASK)) && (--max_wait_count));
670 if (!max_wait_count)
671 return -1;
672
673 /* check MPI Initialization error */
674 gst_len_mpistate = gst_len_mpistate >> 16;
675 if (0x0000 != gst_len_mpistate)
676 return -1;
677
678 return 0;
679}
680
681/**
682 * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
683 * @pm8001_ha: our hba card information
684 */
685static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
686{
687 u32 value;
688 u32 max_wait_count;
689 u32 max_wait_time;
690 int ret = 0;
691
692 /* reset / PCIe ready */
693 max_wait_time = max_wait_count = 100 * 1000; /* 100 milli sec */
694 do {
695 udelay(1);
696 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
697 } while ((value == 0xFFFFFFFF) && (--max_wait_count));
698
699 /* check ila status */
700 max_wait_time = max_wait_count = 1000 * 1000; /* 1000 milli sec */
701 do {
702 udelay(1);
703 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
704 } while (((value & SCRATCH_PAD_ILA_READY) !=
705 SCRATCH_PAD_ILA_READY) && (--max_wait_count));
706 if (!max_wait_count)
707 ret = -1;
708 else {
709 PM8001_MSG_DBG(pm8001_ha,
710 pm8001_printk(" ila ready status in %d millisec\n",
711 (max_wait_time - max_wait_count)));
712 }
713
714 /* check RAAE status */
715 max_wait_time = max_wait_count = 1800 * 1000; /* 1800 milli sec */
716 do {
717 udelay(1);
718 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
719 } while (((value & SCRATCH_PAD_RAAE_READY) !=
720 SCRATCH_PAD_RAAE_READY) && (--max_wait_count));
721 if (!max_wait_count)
722 ret = -1;
723 else {
724 PM8001_MSG_DBG(pm8001_ha,
725 pm8001_printk(" raae ready status in %d millisec\n",
726 (max_wait_time - max_wait_count)));
727 }
728
729 /* check iop0 status */
730 max_wait_time = max_wait_count = 600 * 1000; /* 600 milli sec */
731 do {
732 udelay(1);
733 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
734 } while (((value & SCRATCH_PAD_IOP0_READY) != SCRATCH_PAD_IOP0_READY) &&
735 (--max_wait_count));
736 if (!max_wait_count)
737 ret = -1;
738 else {
739 PM8001_MSG_DBG(pm8001_ha,
740 pm8001_printk(" iop0 ready status in %d millisec\n",
741 (max_wait_time - max_wait_count)));
742 }
743
744 /* check iop1 status only for 16 port controllers */
745 if ((pm8001_ha->chip_id != chip_8008) &&
746 (pm8001_ha->chip_id != chip_8009)) {
747 /* 200 milli sec */
748 max_wait_time = max_wait_count = 200 * 1000;
749 do {
750 udelay(1);
751 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
752 } while (((value & SCRATCH_PAD_IOP1_READY) !=
753 SCRATCH_PAD_IOP1_READY) && (--max_wait_count));
754 if (!max_wait_count)
755 ret = -1;
756 else {
757 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
758 "iop1 ready status in %d millisec\n",
759 (max_wait_time - max_wait_count)));
760 }
761 }
762
763 return ret;
764}
765
766static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
767{
768 void __iomem *base_addr;
769 u32 value;
770 u32 offset;
771 u32 pcibar;
772 u32 pcilogic;
773
774 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
775 offset = value & 0x03FFFFFF; /* scratch pad 0 TBL address */
776
777 PM8001_INIT_DBG(pm8001_ha,
778 pm8001_printk("Scratchpad 0 Offset: 0x%x value 0x%x\n",
779 offset, value));
780 pcilogic = (value & 0xFC000000) >> 26;
781 pcibar = get_pci_bar_index(pcilogic);
782 PM8001_INIT_DBG(pm8001_ha,
783 pm8001_printk("Scratchpad 0 PCI BAR: %d\n", pcibar));
784 pm8001_ha->main_cfg_tbl_addr = base_addr =
785 pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
786 pm8001_ha->general_stat_tbl_addr =
787 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x18) &
788 0xFFFFFF);
789 pm8001_ha->inbnd_q_tbl_addr =
790 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C) &
791 0xFFFFFF);
792 pm8001_ha->outbnd_q_tbl_addr =
793 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x20) &
794 0xFFFFFF);
795 pm8001_ha->ivt_tbl_addr =
796 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C) &
797 0xFFFFFF);
798 pm8001_ha->pspa_q_tbl_addr =
799 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x90) &
800 0xFFFFFF);
801 pm8001_ha->fatal_tbl_addr =
802 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0xA0) &
803 0xFFFFFF);
804
805 PM8001_INIT_DBG(pm8001_ha,
806 pm8001_printk("GST OFFSET 0x%x\n",
807 pm8001_cr32(pm8001_ha, pcibar, offset + 0x18)));
808 PM8001_INIT_DBG(pm8001_ha,
809 pm8001_printk("INBND OFFSET 0x%x\n",
810 pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C)));
811 PM8001_INIT_DBG(pm8001_ha,
812 pm8001_printk("OBND OFFSET 0x%x\n",
813 pm8001_cr32(pm8001_ha, pcibar, offset + 0x20)));
814 PM8001_INIT_DBG(pm8001_ha,
815 pm8001_printk("IVT OFFSET 0x%x\n",
816 pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C)));
817 PM8001_INIT_DBG(pm8001_ha,
818 pm8001_printk("PSPA OFFSET 0x%x\n",
819 pm8001_cr32(pm8001_ha, pcibar, offset + 0x90)));
820 PM8001_INIT_DBG(pm8001_ha,
821 pm8001_printk("addr - main cfg %p general status %p\n",
822 pm8001_ha->main_cfg_tbl_addr,
823 pm8001_ha->general_stat_tbl_addr));
824 PM8001_INIT_DBG(pm8001_ha,
825 pm8001_printk("addr - inbnd %p obnd %p\n",
826 pm8001_ha->inbnd_q_tbl_addr,
827 pm8001_ha->outbnd_q_tbl_addr));
828 PM8001_INIT_DBG(pm8001_ha,
829 pm8001_printk("addr - pspa %p ivt %p\n",
830 pm8001_ha->pspa_q_tbl_addr,
831 pm8001_ha->ivt_tbl_addr));
832}
833
834/**
835 * pm80xx_set_thermal_config - support the thermal configuration
836 * @pm8001_ha: our hba card information.
837 */
838int
839pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha)
840{
841 struct set_ctrl_cfg_req payload;
842 struct inbound_queue_table *circularQ;
843 int rc;
844 u32 tag;
845 u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
846
847 memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
848 rc = pm8001_tag_alloc(pm8001_ha, &tag);
849 if (rc)
850 return -1;
851
852 circularQ = &pm8001_ha->inbnd_q_tbl[0];
853 payload.tag = cpu_to_le32(tag);
854 payload.cfg_pg[0] = (THERMAL_LOG_ENABLE << 9) |
855 (THERMAL_ENABLE << 8) | THERMAL_OP_CODE;
856 payload.cfg_pg[1] = (LTEMPHIL << 24) | (RTEMPHIL << 8);
857
858 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
859 return rc;
860
861}
862
863/**
864* pm80xx_set_sas_protocol_timer_config - support the SAS Protocol
865* Timer configuration page
866* @pm8001_ha: our hba card information.
867*/
868static int
869pm80xx_set_sas_protocol_timer_config(struct pm8001_hba_info *pm8001_ha)
870{
871 struct set_ctrl_cfg_req payload;
872 struct inbound_queue_table *circularQ;
873 SASProtocolTimerConfig_t SASConfigPage;
874 int rc;
875 u32 tag;
876 u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
877
878 memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
879 memset(&SASConfigPage, 0, sizeof(SASProtocolTimerConfig_t));
880
881 rc = pm8001_tag_alloc(pm8001_ha, &tag);
882
883 if (rc)
884 return -1;
885
886 circularQ = &pm8001_ha->inbnd_q_tbl[0];
887 payload.tag = cpu_to_le32(tag);
888
889 SASConfigPage.pageCode = SAS_PROTOCOL_TIMER_CONFIG_PAGE;
890 SASConfigPage.MST_MSI = 3 << 15;
891 SASConfigPage.STP_SSP_MCT_TMO = (STP_MCT_TMO << 16) | SSP_MCT_TMO;
892 SASConfigPage.STP_FRM_TMO = (SAS_MAX_OPEN_TIME << 24) |
893 (SMP_MAX_CONN_TIMER << 16) | STP_FRM_TIMER;
894 SASConfigPage.STP_IDLE_TMO = STP_IDLE_TIME;
895
896 if (SASConfigPage.STP_IDLE_TMO > 0x3FFFFFF)
897 SASConfigPage.STP_IDLE_TMO = 0x3FFFFFF;
898
899
900 SASConfigPage.OPNRJT_RTRY_INTVL = (SAS_MFD << 16) |
901 SAS_OPNRJT_RTRY_INTVL;
902 SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO = (SAS_DOPNRJT_RTRY_TMO << 16)
903 | SAS_COPNRJT_RTRY_TMO;
904 SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR = (SAS_DOPNRJT_RTRY_THR << 16)
905 | SAS_COPNRJT_RTRY_THR;
906 SASConfigPage.MAX_AIP = SAS_MAX_AIP;
907
908 PM8001_INIT_DBG(pm8001_ha,
909 pm8001_printk("SASConfigPage.pageCode "
910 "0x%08x\n", SASConfigPage.pageCode));
911 PM8001_INIT_DBG(pm8001_ha,
912 pm8001_printk("SASConfigPage.MST_MSI "
913 " 0x%08x\n", SASConfigPage.MST_MSI));
914 PM8001_INIT_DBG(pm8001_ha,
915 pm8001_printk("SASConfigPage.STP_SSP_MCT_TMO "
916 " 0x%08x\n", SASConfigPage.STP_SSP_MCT_TMO));
917 PM8001_INIT_DBG(pm8001_ha,
918 pm8001_printk("SASConfigPage.STP_FRM_TMO "
919 " 0x%08x\n", SASConfigPage.STP_FRM_TMO));
920 PM8001_INIT_DBG(pm8001_ha,
921 pm8001_printk("SASConfigPage.STP_IDLE_TMO "
922 " 0x%08x\n", SASConfigPage.STP_IDLE_TMO));
923 PM8001_INIT_DBG(pm8001_ha,
924 pm8001_printk("SASConfigPage.OPNRJT_RTRY_INTVL "
925 " 0x%08x\n", SASConfigPage.OPNRJT_RTRY_INTVL));
926 PM8001_INIT_DBG(pm8001_ha,
927 pm8001_printk("SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO "
928 " 0x%08x\n", SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO));
929 PM8001_INIT_DBG(pm8001_ha,
930 pm8001_printk("SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR "
931 " 0x%08x\n", SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR));
932 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("SASConfigPage.MAX_AIP "
933 " 0x%08x\n", SASConfigPage.MAX_AIP));
934
935 memcpy(&payload.cfg_pg, &SASConfigPage,
936 sizeof(SASProtocolTimerConfig_t));
937
938 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
939
940 return rc;
941}
942
943/**
944 * pm80xx_get_encrypt_info - Check for encryption
945 * @pm8001_ha: our hba card information.
946 */
947static int
948pm80xx_get_encrypt_info(struct pm8001_hba_info *pm8001_ha)
949{
950 u32 scratch3_value;
951 int ret;
952
953 /* Read encryption status from SCRATCH PAD 3 */
954 scratch3_value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
955
956 if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
957 SCRATCH_PAD3_ENC_READY) {
958 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
959 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
960 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
961 SCRATCH_PAD3_SMF_ENABLED)
962 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
963 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
964 SCRATCH_PAD3_SMA_ENABLED)
965 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
966 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
967 SCRATCH_PAD3_SMB_ENABLED)
968 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
969 pm8001_ha->encrypt_info.status = 0;
970 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
971 "Encryption: SCRATCH_PAD3_ENC_READY 0x%08X."
972 "Cipher mode 0x%x Sec mode 0x%x status 0x%x\n",
973 scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
974 pm8001_ha->encrypt_info.sec_mode,
975 pm8001_ha->encrypt_info.status));
976 ret = 0;
977 } else if ((scratch3_value & SCRATCH_PAD3_ENC_READY) ==
978 SCRATCH_PAD3_ENC_DISABLED) {
979 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
980 "Encryption: SCRATCH_PAD3_ENC_DISABLED 0x%08X\n",
981 scratch3_value));
982 pm8001_ha->encrypt_info.status = 0xFFFFFFFF;
983 pm8001_ha->encrypt_info.cipher_mode = 0;
984 pm8001_ha->encrypt_info.sec_mode = 0;
985 return 0;
986 } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
987 SCRATCH_PAD3_ENC_DIS_ERR) {
988 pm8001_ha->encrypt_info.status =
989 (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
990 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
991 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
992 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
993 SCRATCH_PAD3_SMF_ENABLED)
994 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
995 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
996 SCRATCH_PAD3_SMA_ENABLED)
997 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
998 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
999 SCRATCH_PAD3_SMB_ENABLED)
1000 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1001 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1002 "Encryption: SCRATCH_PAD3_DIS_ERR 0x%08X."
1003 "Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
1004 scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
1005 pm8001_ha->encrypt_info.sec_mode,
1006 pm8001_ha->encrypt_info.status));
1007 ret = -1;
1008 } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1009 SCRATCH_PAD3_ENC_ENA_ERR) {
1010
1011 pm8001_ha->encrypt_info.status =
1012 (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
1013 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1014 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1015 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1016 SCRATCH_PAD3_SMF_ENABLED)
1017 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1018 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1019 SCRATCH_PAD3_SMA_ENABLED)
1020 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1021 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1022 SCRATCH_PAD3_SMB_ENABLED)
1023 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1024
1025 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1026 "Encryption: SCRATCH_PAD3_ENA_ERR 0x%08X."
1027 "Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
1028 scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
1029 pm8001_ha->encrypt_info.sec_mode,
1030 pm8001_ha->encrypt_info.status));
1031 ret = -1;
1032 }
1033 return ret;
1034}
1035
1036/**
1037 * pm80xx_encrypt_update - update flash with encryption informtion
1038 * @pm8001_ha: our hba card information.
1039 */
1040static int pm80xx_encrypt_update(struct pm8001_hba_info *pm8001_ha)
1041{
1042 struct kek_mgmt_req payload;
1043 struct inbound_queue_table *circularQ;
1044 int rc;
1045 u32 tag;
1046 u32 opc = OPC_INB_KEK_MANAGEMENT;
1047
1048 memset(&payload, 0, sizeof(struct kek_mgmt_req));
1049 rc = pm8001_tag_alloc(pm8001_ha, &tag);
1050 if (rc)
1051 return -1;
1052
1053 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1054 payload.tag = cpu_to_le32(tag);
1055 /* Currently only one key is used. New KEK index is 1.
1056 * Current KEK index is 1. Store KEK to NVRAM is 1.
1057 */
1058 payload.new_curidx_ksop = ((1 << 24) | (1 << 16) | (1 << 8) |
1059 KEK_MGMT_SUBOP_KEYCARDUPDATE);
1060
1061 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
1062
1063 return rc;
1064}
1065
1066/**
1067 * pm8001_chip_init - the main init function that initialize whole PM8001 chip.
1068 * @pm8001_ha: our hba card information
1069 */
1070static int pm80xx_chip_init(struct pm8001_hba_info *pm8001_ha)
1071{
1072 int ret;
1073 u8 i = 0;
1074
1075 /* check the firmware status */
1076 if (-1 == check_fw_ready(pm8001_ha)) {
1077 PM8001_FAIL_DBG(pm8001_ha,
1078 pm8001_printk("Firmware is not ready!\n"));
1079 return -EBUSY;
1080 }
1081
1082 /* Initialize pci space address eg: mpi offset */
1083 init_pci_device_addresses(pm8001_ha);
1084 init_default_table_values(pm8001_ha);
1085 read_main_config_table(pm8001_ha);
1086 read_general_status_table(pm8001_ha);
1087 read_inbnd_queue_table(pm8001_ha);
1088 read_outbnd_queue_table(pm8001_ha);
1089 read_phy_attr_table(pm8001_ha);
1090
1091 /* update main config table ,inbound table and outbound table */
1092 update_main_config_table(pm8001_ha);
1093 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++)
1094 update_inbnd_queue_table(pm8001_ha, i);
1095 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++)
1096 update_outbnd_queue_table(pm8001_ha, i);
1097
1098 /* notify firmware update finished and check initialization status */
1099 if (0 == mpi_init_check(pm8001_ha)) {
1100 PM8001_INIT_DBG(pm8001_ha,
1101 pm8001_printk("MPI initialize successful!\n"));
1102 } else
1103 return -EBUSY;
1104
1105 /* send SAS protocol timer configuration page to FW */
1106 ret = pm80xx_set_sas_protocol_timer_config(pm8001_ha);
1107
1108 /* Check for encryption */
1109 if (pm8001_ha->chip->encrypt) {
1110 PM8001_INIT_DBG(pm8001_ha,
1111 pm8001_printk("Checking for encryption\n"));
1112 ret = pm80xx_get_encrypt_info(pm8001_ha);
1113 if (ret == -1) {
1114 PM8001_INIT_DBG(pm8001_ha,
1115 pm8001_printk("Encryption error !!\n"));
1116 if (pm8001_ha->encrypt_info.status == 0x81) {
1117 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1118 "Encryption enabled with error."
1119 "Saving encryption key to flash\n"));
1120 pm80xx_encrypt_update(pm8001_ha);
1121 }
1122 }
1123 }
1124 return 0;
1125}
1126
1127static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
1128{
1129 u32 max_wait_count;
1130 u32 value;
1131 u32 gst_len_mpistate;
1132 init_pci_device_addresses(pm8001_ha);
1133 /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
1134 table is stop */
1135 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_RESET);
1136
1137 /* wait until Inbound DoorBell Clear Register toggled */
1138 if (IS_SPCV_12G(pm8001_ha->pdev)) {
1139 max_wait_count = 4 * 1000 * 1000;/* 4 sec */
1140 } else {
1141 max_wait_count = 2 * 1000 * 1000;/* 2 sec */
1142 }
1143 do {
1144 udelay(1);
1145 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
1146 value &= SPCv_MSGU_CFG_TABLE_RESET;
1147 } while ((value != 0) && (--max_wait_count));
1148
1149 if (!max_wait_count) {
1150 PM8001_FAIL_DBG(pm8001_ha,
1151 pm8001_printk("TIMEOUT:IBDB value/=%x\n", value));
1152 return -1;
1153 }
1154
1155 /* check the MPI-State for termination in progress */
1156 /* wait until Inbound DoorBell Clear Register toggled */
1157 max_wait_count = 2 * 1000 * 1000; /* 2 sec for spcv/ve */
1158 do {
1159 udelay(1);
1160 gst_len_mpistate =
1161 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
1162 GST_GSTLEN_MPIS_OFFSET);
1163 if (GST_MPI_STATE_UNINIT ==
1164 (gst_len_mpistate & GST_MPI_STATE_MASK))
1165 break;
1166 } while (--max_wait_count);
1167 if (!max_wait_count) {
1168 PM8001_FAIL_DBG(pm8001_ha,
1169 pm8001_printk(" TIME OUT MPI State = 0x%x\n",
1170 gst_len_mpistate & GST_MPI_STATE_MASK));
1171 return -1;
1172 }
1173
1174 return 0;
1175}
1176
1177/**
1178 * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
1179 * the FW register status to the originated status.
1180 * @pm8001_ha: our hba card information
1181 */
1182
1183static int
1184pm80xx_chip_soft_rst(struct pm8001_hba_info *pm8001_ha)
1185{
1186 u32 regval;
1187 u32 bootloader_state;
1188 u32 ibutton0, ibutton1;
1189
1190 /* Check if MPI is in ready state to reset */
1191 if (mpi_uninit_check(pm8001_ha) != 0) {
1192 PM8001_FAIL_DBG(pm8001_ha,
1193 pm8001_printk("MPI state is not ready\n"));
1194 return -1;
1195 }
1196
1197 /* checked for reset register normal state; 0x0 */
1198 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
1199 PM8001_INIT_DBG(pm8001_ha,
1200 pm8001_printk("reset register before write : 0x%x\n", regval));
1201
1202 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, SPCv_NORMAL_RESET_VALUE);
1203 mdelay(500);
1204
1205 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
1206 PM8001_INIT_DBG(pm8001_ha,
1207 pm8001_printk("reset register after write 0x%x\n", regval));
1208
1209 if ((regval & SPCv_SOFT_RESET_READ_MASK) ==
1210 SPCv_SOFT_RESET_NORMAL_RESET_OCCURED) {
1211 PM8001_MSG_DBG(pm8001_ha,
1212 pm8001_printk(" soft reset successful [regval: 0x%x]\n",
1213 regval));
1214 } else {
1215 PM8001_MSG_DBG(pm8001_ha,
1216 pm8001_printk(" soft reset failed [regval: 0x%x]\n",
1217 regval));
1218
1219 /* check bootloader is successfully executed or in HDA mode */
1220 bootloader_state =
1221 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
1222 SCRATCH_PAD1_BOOTSTATE_MASK;
1223
1224 if (bootloader_state == SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM) {
1225 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1226 "Bootloader state - HDA mode SEEPROM\n"));
1227 } else if (bootloader_state ==
1228 SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP) {
1229 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1230 "Bootloader state - HDA mode Bootstrap Pin\n"));
1231 } else if (bootloader_state ==
1232 SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET) {
1233 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1234 "Bootloader state - HDA mode soft reset\n"));
1235 } else if (bootloader_state ==
1236 SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR) {
1237 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1238 "Bootloader state-HDA mode critical error\n"));
1239 }
1240 return -EBUSY;
1241 }
1242
1243 /* check the firmware status after reset */
1244 if (-1 == check_fw_ready(pm8001_ha)) {
1245 PM8001_FAIL_DBG(pm8001_ha,
1246 pm8001_printk("Firmware is not ready!\n"));
1247 /* check iButton feature support for motherboard controller */
1248 if (pm8001_ha->pdev->subsystem_vendor !=
1249 PCI_VENDOR_ID_ADAPTEC2 &&
1250 pm8001_ha->pdev->subsystem_vendor != 0) {
1251 ibutton0 = pm8001_cr32(pm8001_ha, 0,
1252 MSGU_HOST_SCRATCH_PAD_6);
1253 ibutton1 = pm8001_cr32(pm8001_ha, 0,
1254 MSGU_HOST_SCRATCH_PAD_7);
1255 if (!ibutton0 && !ibutton1) {
1256 PM8001_FAIL_DBG(pm8001_ha,
1257 pm8001_printk("iButton Feature is"
1258 " not Available!!!\n"));
1259 return -EBUSY;
1260 }
1261 if (ibutton0 == 0xdeadbeef && ibutton1 == 0xdeadbeef) {
1262 PM8001_FAIL_DBG(pm8001_ha,
1263 pm8001_printk("CRC Check for iButton"
1264 " Feature Failed!!!\n"));
1265 return -EBUSY;
1266 }
1267 }
1268 }
1269 PM8001_INIT_DBG(pm8001_ha,
1270 pm8001_printk("SPCv soft reset Complete\n"));
1271 return 0;
1272}
1273
1274static void pm80xx_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
1275{
1276 u32 i;
1277
1278 PM8001_INIT_DBG(pm8001_ha,
1279 pm8001_printk("chip reset start\n"));
1280
1281 /* do SPCv chip reset. */
1282 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, 0x11);
1283 PM8001_INIT_DBG(pm8001_ha,
1284 pm8001_printk("SPC soft reset Complete\n"));
1285
1286 /* Check this ..whether delay is required or no */
1287 /* delay 10 usec */
1288 udelay(10);
1289
1290 /* wait for 20 msec until the firmware gets reloaded */
1291 i = 20;
1292 do {
1293 mdelay(1);
1294 } while ((--i) != 0);
1295
1296 PM8001_INIT_DBG(pm8001_ha,
1297 pm8001_printk("chip reset finished\n"));
1298}
1299
1300/**
1301 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1302 * @pm8001_ha: our hba card information
1303 */
1304static void
1305pm80xx_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1306{
1307 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1308 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1309}
1310
1311/**
1312 * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1313 * @pm8001_ha: our hba card information
1314 */
1315static void
1316pm80xx_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1317{
1318 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL);
1319}
1320
1321/**
1322 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1323 * @pm8001_ha: our hba card information
1324 */
1325static void
1326pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1327{
1328#ifdef PM8001_USE_MSIX
1329 u32 mask;
1330 mask = (u32)(1 << vec);
1331
1332 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, (u32)(mask & 0xFFFFFFFF));
1333 return;
1334#endif
1335 pm80xx_chip_intx_interrupt_enable(pm8001_ha);
1336
1337}
1338
1339/**
1340 * pm8001_chip_interrupt_disable- disable PM8001 chip interrupt
1341 * @pm8001_ha: our hba card information
1342 */
1343static void
1344pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1345{
1346#ifdef PM8001_USE_MSIX
1347 u32 mask;
1348 if (vec == 0xFF)
1349 mask = 0xFFFFFFFF;
1350 else
1351 mask = (u32)(1 << vec);
1352 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, (u32)(mask & 0xFFFFFFFF));
1353 return;
1354#endif
1355 pm80xx_chip_intx_interrupt_disable(pm8001_ha);
1356}
1357
1358static void pm80xx_send_abort_all(struct pm8001_hba_info *pm8001_ha,
1359 struct pm8001_device *pm8001_ha_dev)
1360{
1361 int res;
1362 u32 ccb_tag;
1363 struct pm8001_ccb_info *ccb;
1364 struct sas_task *task = NULL;
1365 struct task_abort_req task_abort;
1366 struct inbound_queue_table *circularQ;
1367 u32 opc = OPC_INB_SATA_ABORT;
1368 int ret;
1369
1370 if (!pm8001_ha_dev) {
1371 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("dev is null\n"));
1372 return;
1373 }
1374
1375 task = sas_alloc_slow_task(GFP_ATOMIC);
1376
1377 if (!task) {
1378 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("cannot "
1379 "allocate task\n"));
1380 return;
1381 }
1382
1383 task->task_done = pm8001_task_done;
1384
1385 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1386 if (res)
1387 return;
1388
1389 ccb = &pm8001_ha->ccb_info[ccb_tag];
1390 ccb->device = pm8001_ha_dev;
1391 ccb->ccb_tag = ccb_tag;
1392 ccb->task = task;
1393
1394 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1395
1396 memset(&task_abort, 0, sizeof(task_abort));
1397 task_abort.abort_all = cpu_to_le32(1);
1398 task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1399 task_abort.tag = cpu_to_le32(ccb_tag);
1400
1401 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort, 0);
1402
1403}
1404
1405static void pm80xx_send_read_log(struct pm8001_hba_info *pm8001_ha,
1406 struct pm8001_device *pm8001_ha_dev)
1407{
1408 struct sata_start_req sata_cmd;
1409 int res;
1410 u32 ccb_tag;
1411 struct pm8001_ccb_info *ccb;
1412 struct sas_task *task = NULL;
1413 struct host_to_dev_fis fis;
1414 struct domain_device *dev;
1415 struct inbound_queue_table *circularQ;
1416 u32 opc = OPC_INB_SATA_HOST_OPSTART;
1417
1418 task = sas_alloc_slow_task(GFP_ATOMIC);
1419
1420 if (!task) {
1421 PM8001_FAIL_DBG(pm8001_ha,
1422 pm8001_printk("cannot allocate task !!!\n"));
1423 return;
1424 }
1425 task->task_done = pm8001_task_done;
1426
1427 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1428 if (res) {
1429 PM8001_FAIL_DBG(pm8001_ha,
1430 pm8001_printk("cannot allocate tag !!!\n"));
1431 return;
1432 }
1433
1434 /* allocate domain device by ourselves as libsas
1435 * is not going to provide any
1436 */
1437 dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC);
1438 if (!dev) {
1439 PM8001_FAIL_DBG(pm8001_ha,
1440 pm8001_printk("Domain device cannot be allocated\n"));
1441 sas_free_task(task);
1442 return;
1443 } else {
1444 task->dev = dev;
1445 task->dev->lldd_dev = pm8001_ha_dev;
1446 }
1447
1448 ccb = &pm8001_ha->ccb_info[ccb_tag];
1449 ccb->device = pm8001_ha_dev;
1450 ccb->ccb_tag = ccb_tag;
1451 ccb->task = task;
1452 pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG;
1453 pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG;
1454
1455 memset(&sata_cmd, 0, sizeof(sata_cmd));
1456 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1457
1458 /* construct read log FIS */
1459 memset(&fis, 0, sizeof(struct host_to_dev_fis));
1460 fis.fis_type = 0x27;
1461 fis.flags = 0x80;
1462 fis.command = ATA_CMD_READ_LOG_EXT;
1463 fis.lbal = 0x10;
1464 fis.sector_count = 0x1;
1465
1466 sata_cmd.tag = cpu_to_le32(ccb_tag);
1467 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1468 sata_cmd.ncqtag_atap_dir_m_dad |= ((0x1 << 7) | (0x5 << 9));
1469 memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis));
1470
1471 res = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd, 0);
1472
1473}
1474
1475/**
1476 * mpi_ssp_completion- process the event that FW response to the SSP request.
1477 * @pm8001_ha: our hba card information
1478 * @piomb: the message contents of this outbound message.
1479 *
1480 * When FW has completed a ssp request for example a IO request, after it has
1481 * filled the SG data with the data, it will trigger this event represent
1482 * that he has finished the job,please check the coresponding buffer.
1483 * So we will tell the caller who maybe waiting the result to tell upper layer
1484 * that the task has been finished.
1485 */
1486static void
1487mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb)
1488{
1489 struct sas_task *t;
1490 struct pm8001_ccb_info *ccb;
1491 unsigned long flags;
1492 u32 status;
1493 u32 param;
1494 u32 tag;
1495 struct ssp_completion_resp *psspPayload;
1496 struct task_status_struct *ts;
1497 struct ssp_response_iu *iu;
1498 struct pm8001_device *pm8001_dev;
1499 psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1500 status = le32_to_cpu(psspPayload->status);
1501 tag = le32_to_cpu(psspPayload->tag);
1502 ccb = &pm8001_ha->ccb_info[tag];
1503 if ((status == IO_ABORTED) && ccb->open_retry) {
1504 /* Being completed by another */
1505 ccb->open_retry = 0;
1506 return;
1507 }
1508 pm8001_dev = ccb->device;
1509 param = le32_to_cpu(psspPayload->param);
1510 t = ccb->task;
1511
1512 if (status && status != IO_UNDERFLOW)
1513 PM8001_FAIL_DBG(pm8001_ha,
1514 pm8001_printk("sas IO status 0x%x\n", status));
1515 if (unlikely(!t || !t->lldd_task || !t->dev))
1516 return;
1517 ts = &t->task_status;
1518 /* Print sas address of IO failed device */
1519 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
1520 (status != IO_UNDERFLOW))
1521 PM8001_FAIL_DBG(pm8001_ha,
1522 pm8001_printk("SAS Address of IO Failure Drive"
1523 ":%016llx", SAS_ADDR(t->dev->sas_addr)));
1524
1525 switch (status) {
1526 case IO_SUCCESS:
1527 PM8001_IO_DBG(pm8001_ha,
1528 pm8001_printk("IO_SUCCESS ,param = 0x%x\n",
1529 param));
1530 if (param == 0) {
1531 ts->resp = SAS_TASK_COMPLETE;
1532 ts->stat = SAM_STAT_GOOD;
1533 } else {
1534 ts->resp = SAS_TASK_COMPLETE;
1535 ts->stat = SAS_PROTO_RESPONSE;
1536 ts->residual = param;
1537 iu = &psspPayload->ssp_resp_iu;
1538 sas_ssp_task_response(pm8001_ha->dev, t, iu);
1539 }
1540 if (pm8001_dev)
1541 pm8001_dev->running_req--;
1542 break;
1543 case IO_ABORTED:
1544 PM8001_IO_DBG(pm8001_ha,
1545 pm8001_printk("IO_ABORTED IOMB Tag\n"));
1546 ts->resp = SAS_TASK_COMPLETE;
1547 ts->stat = SAS_ABORTED_TASK;
1548 break;
1549 case IO_UNDERFLOW:
1550 /* SSP Completion with error */
1551 PM8001_IO_DBG(pm8001_ha,
1552 pm8001_printk("IO_UNDERFLOW ,param = 0x%x\n",
1553 param));
1554 ts->resp = SAS_TASK_COMPLETE;
1555 ts->stat = SAS_DATA_UNDERRUN;
1556 ts->residual = param;
1557 if (pm8001_dev)
1558 pm8001_dev->running_req--;
1559 break;
1560 case IO_NO_DEVICE:
1561 PM8001_IO_DBG(pm8001_ha,
1562 pm8001_printk("IO_NO_DEVICE\n"));
1563 ts->resp = SAS_TASK_UNDELIVERED;
1564 ts->stat = SAS_PHY_DOWN;
1565 break;
1566 case IO_XFER_ERROR_BREAK:
1567 PM8001_IO_DBG(pm8001_ha,
1568 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1569 ts->resp = SAS_TASK_COMPLETE;
1570 ts->stat = SAS_OPEN_REJECT;
1571 /* Force the midlayer to retry */
1572 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1573 break;
1574 case IO_XFER_ERROR_PHY_NOT_READY:
1575 PM8001_IO_DBG(pm8001_ha,
1576 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1577 ts->resp = SAS_TASK_COMPLETE;
1578 ts->stat = SAS_OPEN_REJECT;
1579 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1580 break;
1581 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1582 PM8001_IO_DBG(pm8001_ha,
1583 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1584 ts->resp = SAS_TASK_COMPLETE;
1585 ts->stat = SAS_OPEN_REJECT;
1586 ts->open_rej_reason = SAS_OREJ_EPROTO;
1587 break;
1588 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1589 PM8001_IO_DBG(pm8001_ha,
1590 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1591 ts->resp = SAS_TASK_COMPLETE;
1592 ts->stat = SAS_OPEN_REJECT;
1593 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1594 break;
1595 case IO_OPEN_CNX_ERROR_BREAK:
1596 PM8001_IO_DBG(pm8001_ha,
1597 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1598 ts->resp = SAS_TASK_COMPLETE;
1599 ts->stat = SAS_OPEN_REJECT;
1600 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1601 break;
1602 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1603 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
1604 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
1605 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
1606 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
1607 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
1608 PM8001_IO_DBG(pm8001_ha,
1609 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1610 ts->resp = SAS_TASK_COMPLETE;
1611 ts->stat = SAS_OPEN_REJECT;
1612 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1613 if (!t->uldd_task)
1614 pm8001_handle_event(pm8001_ha,
1615 pm8001_dev,
1616 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1617 break;
1618 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1619 PM8001_IO_DBG(pm8001_ha,
1620 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1621 ts->resp = SAS_TASK_COMPLETE;
1622 ts->stat = SAS_OPEN_REJECT;
1623 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1624 break;
1625 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1626 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1627 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
1628 ts->resp = SAS_TASK_COMPLETE;
1629 ts->stat = SAS_OPEN_REJECT;
1630 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1631 break;
1632 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1633 PM8001_IO_DBG(pm8001_ha,
1634 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1635 ts->resp = SAS_TASK_UNDELIVERED;
1636 ts->stat = SAS_OPEN_REJECT;
1637 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1638 break;
1639 case IO_XFER_ERROR_NAK_RECEIVED:
1640 PM8001_IO_DBG(pm8001_ha,
1641 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1642 ts->resp = SAS_TASK_COMPLETE;
1643 ts->stat = SAS_OPEN_REJECT;
1644 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1645 break;
1646 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1647 PM8001_IO_DBG(pm8001_ha,
1648 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1649 ts->resp = SAS_TASK_COMPLETE;
1650 ts->stat = SAS_NAK_R_ERR;
1651 break;
1652 case IO_XFER_ERROR_DMA:
1653 PM8001_IO_DBG(pm8001_ha,
1654 pm8001_printk("IO_XFER_ERROR_DMA\n"));
1655 ts->resp = SAS_TASK_COMPLETE;
1656 ts->stat = SAS_OPEN_REJECT;
1657 break;
1658 case IO_XFER_OPEN_RETRY_TIMEOUT:
1659 PM8001_IO_DBG(pm8001_ha,
1660 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1661 ts->resp = SAS_TASK_COMPLETE;
1662 ts->stat = SAS_OPEN_REJECT;
1663 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1664 break;
1665 case IO_XFER_ERROR_OFFSET_MISMATCH:
1666 PM8001_IO_DBG(pm8001_ha,
1667 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
1668 ts->resp = SAS_TASK_COMPLETE;
1669 ts->stat = SAS_OPEN_REJECT;
1670 break;
1671 case IO_PORT_IN_RESET:
1672 PM8001_IO_DBG(pm8001_ha,
1673 pm8001_printk("IO_PORT_IN_RESET\n"));
1674 ts->resp = SAS_TASK_COMPLETE;
1675 ts->stat = SAS_OPEN_REJECT;
1676 break;
1677 case IO_DS_NON_OPERATIONAL:
1678 PM8001_IO_DBG(pm8001_ha,
1679 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
1680 ts->resp = SAS_TASK_COMPLETE;
1681 ts->stat = SAS_OPEN_REJECT;
1682 if (!t->uldd_task)
1683 pm8001_handle_event(pm8001_ha,
1684 pm8001_dev,
1685 IO_DS_NON_OPERATIONAL);
1686 break;
1687 case IO_DS_IN_RECOVERY:
1688 PM8001_IO_DBG(pm8001_ha,
1689 pm8001_printk("IO_DS_IN_RECOVERY\n"));
1690 ts->resp = SAS_TASK_COMPLETE;
1691 ts->stat = SAS_OPEN_REJECT;
1692 break;
1693 case IO_TM_TAG_NOT_FOUND:
1694 PM8001_IO_DBG(pm8001_ha,
1695 pm8001_printk("IO_TM_TAG_NOT_FOUND\n"));
1696 ts->resp = SAS_TASK_COMPLETE;
1697 ts->stat = SAS_OPEN_REJECT;
1698 break;
1699 case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
1700 PM8001_IO_DBG(pm8001_ha,
1701 pm8001_printk("IO_SSP_EXT_IU_ZERO_LEN_ERROR\n"));
1702 ts->resp = SAS_TASK_COMPLETE;
1703 ts->stat = SAS_OPEN_REJECT;
1704 break;
1705 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
1706 PM8001_IO_DBG(pm8001_ha,
1707 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
1708 ts->resp = SAS_TASK_COMPLETE;
1709 ts->stat = SAS_OPEN_REJECT;
1710 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1711 break;
1712 default:
1713 PM8001_IO_DBG(pm8001_ha,
1714 pm8001_printk("Unknown status 0x%x\n", status));
1715 /* not allowed case. Therefore, return failed status */
1716 ts->resp = SAS_TASK_COMPLETE;
1717 ts->stat = SAS_OPEN_REJECT;
1718 break;
1719 }
1720 PM8001_IO_DBG(pm8001_ha,
1721 pm8001_printk("scsi_status = 0x%x\n ",
1722 psspPayload->ssp_resp_iu.status));
1723 spin_lock_irqsave(&t->task_state_lock, flags);
1724 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1725 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1726 t->task_state_flags |= SAS_TASK_STATE_DONE;
1727 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1728 spin_unlock_irqrestore(&t->task_state_lock, flags);
1729 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1730 "task 0x%p done with io_status 0x%x resp 0x%x "
1731 "stat 0x%x but aborted by upper layer!\n",
1732 t, status, ts->resp, ts->stat));
1733 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1734 } else {
1735 spin_unlock_irqrestore(&t->task_state_lock, flags);
1736 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1737 mb();/* in order to force CPU ordering */
1738 t->task_done(t);
1739 }
1740}
1741
1742/*See the comments for mpi_ssp_completion */
1743static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
1744{
1745 struct sas_task *t;
1746 unsigned long flags;
1747 struct task_status_struct *ts;
1748 struct pm8001_ccb_info *ccb;
1749 struct pm8001_device *pm8001_dev;
1750 struct ssp_event_resp *psspPayload =
1751 (struct ssp_event_resp *)(piomb + 4);
1752 u32 event = le32_to_cpu(psspPayload->event);
1753 u32 tag = le32_to_cpu(psspPayload->tag);
1754 u32 port_id = le32_to_cpu(psspPayload->port_id);
1755
1756 ccb = &pm8001_ha->ccb_info[tag];
1757 t = ccb->task;
1758 pm8001_dev = ccb->device;
1759 if (event)
1760 PM8001_FAIL_DBG(pm8001_ha,
1761 pm8001_printk("sas IO status 0x%x\n", event));
1762 if (unlikely(!t || !t->lldd_task || !t->dev))
1763 return;
1764 ts = &t->task_status;
1765 PM8001_IO_DBG(pm8001_ha,
1766 pm8001_printk("port_id:0x%x, tag:0x%x, event:0x%x\n",
1767 port_id, tag, event));
1768 switch (event) {
1769 case IO_OVERFLOW:
1770 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n");)
1771 ts->resp = SAS_TASK_COMPLETE;
1772 ts->stat = SAS_DATA_OVERRUN;
1773 ts->residual = 0;
1774 if (pm8001_dev)
1775 pm8001_dev->running_req--;
1776 break;
1777 case IO_XFER_ERROR_BREAK:
1778 PM8001_IO_DBG(pm8001_ha,
1779 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1780 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK);
1781 return;
1782 case IO_XFER_ERROR_PHY_NOT_READY:
1783 PM8001_IO_DBG(pm8001_ha,
1784 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1785 ts->resp = SAS_TASK_COMPLETE;
1786 ts->stat = SAS_OPEN_REJECT;
1787 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1788 break;
1789 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1790 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1791 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1792 ts->resp = SAS_TASK_COMPLETE;
1793 ts->stat = SAS_OPEN_REJECT;
1794 ts->open_rej_reason = SAS_OREJ_EPROTO;
1795 break;
1796 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1797 PM8001_IO_DBG(pm8001_ha,
1798 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1799 ts->resp = SAS_TASK_COMPLETE;
1800 ts->stat = SAS_OPEN_REJECT;
1801 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1802 break;
1803 case IO_OPEN_CNX_ERROR_BREAK:
1804 PM8001_IO_DBG(pm8001_ha,
1805 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1806 ts->resp = SAS_TASK_COMPLETE;
1807 ts->stat = SAS_OPEN_REJECT;
1808 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1809 break;
1810 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1811 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
1812 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
1813 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
1814 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
1815 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
1816 PM8001_IO_DBG(pm8001_ha,
1817 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1818 ts->resp = SAS_TASK_COMPLETE;
1819 ts->stat = SAS_OPEN_REJECT;
1820 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1821 if (!t->uldd_task)
1822 pm8001_handle_event(pm8001_ha,
1823 pm8001_dev,
1824 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1825 break;
1826 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1827 PM8001_IO_DBG(pm8001_ha,
1828 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1829 ts->resp = SAS_TASK_COMPLETE;
1830 ts->stat = SAS_OPEN_REJECT;
1831 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1832 break;
1833 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1834 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1835 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
1836 ts->resp = SAS_TASK_COMPLETE;
1837 ts->stat = SAS_OPEN_REJECT;
1838 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1839 break;
1840 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1841 PM8001_IO_DBG(pm8001_ha,
1842 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1843 ts->resp = SAS_TASK_COMPLETE;
1844 ts->stat = SAS_OPEN_REJECT;
1845 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1846 break;
1847 case IO_XFER_ERROR_NAK_RECEIVED:
1848 PM8001_IO_DBG(pm8001_ha,
1849 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1850 ts->resp = SAS_TASK_COMPLETE;
1851 ts->stat = SAS_OPEN_REJECT;
1852 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1853 break;
1854 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1855 PM8001_IO_DBG(pm8001_ha,
1856 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1857 ts->resp = SAS_TASK_COMPLETE;
1858 ts->stat = SAS_NAK_R_ERR;
1859 break;
1860 case IO_XFER_OPEN_RETRY_TIMEOUT:
1861 PM8001_IO_DBG(pm8001_ha,
1862 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1863 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT);
1864 return;
1865 case IO_XFER_ERROR_UNEXPECTED_PHASE:
1866 PM8001_IO_DBG(pm8001_ha,
1867 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
1868 ts->resp = SAS_TASK_COMPLETE;
1869 ts->stat = SAS_DATA_OVERRUN;
1870 break;
1871 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
1872 PM8001_IO_DBG(pm8001_ha,
1873 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
1874 ts->resp = SAS_TASK_COMPLETE;
1875 ts->stat = SAS_DATA_OVERRUN;
1876 break;
1877 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
1878 PM8001_IO_DBG(pm8001_ha,
1879 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
1880 ts->resp = SAS_TASK_COMPLETE;
1881 ts->stat = SAS_DATA_OVERRUN;
1882 break;
1883 case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
1884 PM8001_IO_DBG(pm8001_ha,
1885 pm8001_printk("IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n"));
1886 ts->resp = SAS_TASK_COMPLETE;
1887 ts->stat = SAS_DATA_OVERRUN;
1888 break;
1889 case IO_XFER_ERROR_OFFSET_MISMATCH:
1890 PM8001_IO_DBG(pm8001_ha,
1891 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
1892 ts->resp = SAS_TASK_COMPLETE;
1893 ts->stat = SAS_DATA_OVERRUN;
1894 break;
1895 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
1896 PM8001_IO_DBG(pm8001_ha,
1897 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
1898 ts->resp = SAS_TASK_COMPLETE;
1899 ts->stat = SAS_DATA_OVERRUN;
1900 break;
1901 case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
1902 PM8001_IO_DBG(pm8001_ha,
1903 pm8001_printk("IO_XFR_ERROR_INTERNAL_CRC_ERROR\n"));
1904 /* TBC: used default set values */
1905 ts->resp = SAS_TASK_COMPLETE;
1906 ts->stat = SAS_DATA_OVERRUN;
1907 break;
1908 case IO_XFER_CMD_FRAME_ISSUED:
1909 PM8001_IO_DBG(pm8001_ha,
1910 pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
1911 return;
1912 default:
1913 PM8001_IO_DBG(pm8001_ha,
1914 pm8001_printk("Unknown status 0x%x\n", event));
1915 /* not allowed case. Therefore, return failed status */
1916 ts->resp = SAS_TASK_COMPLETE;
1917 ts->stat = SAS_DATA_OVERRUN;
1918 break;
1919 }
1920 spin_lock_irqsave(&t->task_state_lock, flags);
1921 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1922 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1923 t->task_state_flags |= SAS_TASK_STATE_DONE;
1924 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1925 spin_unlock_irqrestore(&t->task_state_lock, flags);
1926 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1927 "task 0x%p done with event 0x%x resp 0x%x "
1928 "stat 0x%x but aborted by upper layer!\n",
1929 t, event, ts->resp, ts->stat));
1930 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1931 } else {
1932 spin_unlock_irqrestore(&t->task_state_lock, flags);
1933 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1934 mb();/* in order to force CPU ordering */
1935 t->task_done(t);
1936 }
1937}
1938
1939/*See the comments for mpi_ssp_completion */
1940static void
1941mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
1942{
1943 struct sas_task *t;
1944 struct pm8001_ccb_info *ccb;
1945 u32 param;
1946 u32 status;
1947 u32 tag;
1948 int i, j;
1949 u8 sata_addr_low[4];
1950 u32 temp_sata_addr_low, temp_sata_addr_hi;
1951 u8 sata_addr_hi[4];
1952 struct sata_completion_resp *psataPayload;
1953 struct task_status_struct *ts;
1954 struct ata_task_resp *resp ;
1955 u32 *sata_resp;
1956 struct pm8001_device *pm8001_dev;
1957 unsigned long flags;
1958
1959 psataPayload = (struct sata_completion_resp *)(piomb + 4);
1960 status = le32_to_cpu(psataPayload->status);
1961 tag = le32_to_cpu(psataPayload->tag);
1962
1963 if (!tag) {
1964 PM8001_FAIL_DBG(pm8001_ha,
1965 pm8001_printk("tag null\n"));
1966 return;
1967 }
1968 ccb = &pm8001_ha->ccb_info[tag];
1969 param = le32_to_cpu(psataPayload->param);
1970 if (ccb) {
1971 t = ccb->task;
1972 pm8001_dev = ccb->device;
1973 } else {
1974 PM8001_FAIL_DBG(pm8001_ha,
1975 pm8001_printk("ccb null\n"));
1976 return;
1977 }
1978
1979 if (t) {
1980 if (t->dev && (t->dev->lldd_dev))
1981 pm8001_dev = t->dev->lldd_dev;
1982 } else {
1983 PM8001_FAIL_DBG(pm8001_ha,
1984 pm8001_printk("task null\n"));
1985 return;
1986 }
1987
1988 if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG))
1989 && unlikely(!t || !t->lldd_task || !t->dev)) {
1990 PM8001_FAIL_DBG(pm8001_ha,
1991 pm8001_printk("task or dev null\n"));
1992 return;
1993 }
1994
1995 ts = &t->task_status;
1996 if (!ts) {
1997 PM8001_FAIL_DBG(pm8001_ha,
1998 pm8001_printk("ts null\n"));
1999 return;
2000 }
2001 /* Print sas address of IO failed device */
2002 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
2003 (status != IO_UNDERFLOW)) {
2004 if (!((t->dev->parent) &&
2005 (DEV_IS_EXPANDER(t->dev->parent->dev_type)))) {
2006 for (i = 0 , j = 4; i <= 3 && j <= 7; i++ , j++)
2007 sata_addr_low[i] = pm8001_ha->sas_addr[j];
2008 for (i = 0 , j = 0; i <= 3 && j <= 3; i++ , j++)
2009 sata_addr_hi[i] = pm8001_ha->sas_addr[j];
2010 memcpy(&temp_sata_addr_low, sata_addr_low,
2011 sizeof(sata_addr_low));
2012 memcpy(&temp_sata_addr_hi, sata_addr_hi,
2013 sizeof(sata_addr_hi));
2014 temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff)
2015 |((temp_sata_addr_hi << 8) &
2016 0xff0000) |
2017 ((temp_sata_addr_hi >> 8)
2018 & 0xff00) |
2019 ((temp_sata_addr_hi << 24) &
2020 0xff000000));
2021 temp_sata_addr_low = ((((temp_sata_addr_low >> 24)
2022 & 0xff) |
2023 ((temp_sata_addr_low << 8)
2024 & 0xff0000) |
2025 ((temp_sata_addr_low >> 8)
2026 & 0xff00) |
2027 ((temp_sata_addr_low << 24)
2028 & 0xff000000)) +
2029 pm8001_dev->attached_phy +
2030 0x10);
2031 PM8001_FAIL_DBG(pm8001_ha,
2032 pm8001_printk("SAS Address of IO Failure Drive:"
2033 "%08x%08x", temp_sata_addr_hi,
2034 temp_sata_addr_low));
2035
2036 } else {
2037 PM8001_FAIL_DBG(pm8001_ha,
2038 pm8001_printk("SAS Address of IO Failure Drive:"
2039 "%016llx", SAS_ADDR(t->dev->sas_addr)));
2040 }
2041 }
2042 switch (status) {
2043 case IO_SUCCESS:
2044 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2045 if (param == 0) {
2046 ts->resp = SAS_TASK_COMPLETE;
2047 ts->stat = SAM_STAT_GOOD;
2048 /* check if response is for SEND READ LOG */
2049 if (pm8001_dev &&
2050 (pm8001_dev->id & NCQ_READ_LOG_FLAG)) {
2051 /* set new bit for abort_all */
2052 pm8001_dev->id |= NCQ_ABORT_ALL_FLAG;
2053 /* clear bit for read log */
2054 pm8001_dev->id = pm8001_dev->id & 0x7FFFFFFF;
2055 pm80xx_send_abort_all(pm8001_ha, pm8001_dev);
2056 /* Free the tag */
2057 pm8001_tag_free(pm8001_ha, tag);
2058 sas_free_task(t);
2059 return;
2060 }
2061 } else {
2062 u8 len;
2063 ts->resp = SAS_TASK_COMPLETE;
2064 ts->stat = SAS_PROTO_RESPONSE;
2065 ts->residual = param;
2066 PM8001_IO_DBG(pm8001_ha,
2067 pm8001_printk("SAS_PROTO_RESPONSE len = %d\n",
2068 param));
2069 sata_resp = &psataPayload->sata_resp[0];
2070 resp = (struct ata_task_resp *)ts->buf;
2071 if (t->ata_task.dma_xfer == 0 &&
2072 t->data_dir == PCI_DMA_FROMDEVICE) {
2073 len = sizeof(struct pio_setup_fis);
2074 PM8001_IO_DBG(pm8001_ha,
2075 pm8001_printk("PIO read len = %d\n", len));
2076 } else if (t->ata_task.use_ncq) {
2077 len = sizeof(struct set_dev_bits_fis);
2078 PM8001_IO_DBG(pm8001_ha,
2079 pm8001_printk("FPDMA len = %d\n", len));
2080 } else {
2081 len = sizeof(struct dev_to_host_fis);
2082 PM8001_IO_DBG(pm8001_ha,
2083 pm8001_printk("other len = %d\n", len));
2084 }
2085 if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
2086 resp->frame_len = len;
2087 memcpy(&resp->ending_fis[0], sata_resp, len);
2088 ts->buf_valid_size = sizeof(*resp);
2089 } else
2090 PM8001_IO_DBG(pm8001_ha,
2091 pm8001_printk("response to large\n"));
2092 }
2093 if (pm8001_dev)
2094 pm8001_dev->running_req--;
2095 break;
2096 case IO_ABORTED:
2097 PM8001_IO_DBG(pm8001_ha,
2098 pm8001_printk("IO_ABORTED IOMB Tag\n"));
2099 ts->resp = SAS_TASK_COMPLETE;
2100 ts->stat = SAS_ABORTED_TASK;
2101 if (pm8001_dev)
2102 pm8001_dev->running_req--;
2103 break;
2104 /* following cases are to do cases */
2105 case IO_UNDERFLOW:
2106 /* SATA Completion with error */
2107 PM8001_IO_DBG(pm8001_ha,
2108 pm8001_printk("IO_UNDERFLOW param = %d\n", param));
2109 ts->resp = SAS_TASK_COMPLETE;
2110 ts->stat = SAS_DATA_UNDERRUN;
2111 ts->residual = param;
2112 if (pm8001_dev)
2113 pm8001_dev->running_req--;
2114 break;
2115 case IO_NO_DEVICE:
2116 PM8001_IO_DBG(pm8001_ha,
2117 pm8001_printk("IO_NO_DEVICE\n"));
2118 ts->resp = SAS_TASK_UNDELIVERED;
2119 ts->stat = SAS_PHY_DOWN;
2120 break;
2121 case IO_XFER_ERROR_BREAK:
2122 PM8001_IO_DBG(pm8001_ha,
2123 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2124 ts->resp = SAS_TASK_COMPLETE;
2125 ts->stat = SAS_INTERRUPTED;
2126 break;
2127 case IO_XFER_ERROR_PHY_NOT_READY:
2128 PM8001_IO_DBG(pm8001_ha,
2129 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2130 ts->resp = SAS_TASK_COMPLETE;
2131 ts->stat = SAS_OPEN_REJECT;
2132 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2133 break;
2134 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2135 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2136 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2137 ts->resp = SAS_TASK_COMPLETE;
2138 ts->stat = SAS_OPEN_REJECT;
2139 ts->open_rej_reason = SAS_OREJ_EPROTO;
2140 break;
2141 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2142 PM8001_IO_DBG(pm8001_ha,
2143 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2144 ts->resp = SAS_TASK_COMPLETE;
2145 ts->stat = SAS_OPEN_REJECT;
2146 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2147 break;
2148 case IO_OPEN_CNX_ERROR_BREAK:
2149 PM8001_IO_DBG(pm8001_ha,
2150 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2151 ts->resp = SAS_TASK_COMPLETE;
2152 ts->stat = SAS_OPEN_REJECT;
2153 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2154 break;
2155 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2156 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2157 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2158 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2159 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2160 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2161 PM8001_IO_DBG(pm8001_ha,
2162 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2163 ts->resp = SAS_TASK_COMPLETE;
2164 ts->stat = SAS_DEV_NO_RESPONSE;
2165 if (!t->uldd_task) {
2166 pm8001_handle_event(pm8001_ha,
2167 pm8001_dev,
2168 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2169 ts->resp = SAS_TASK_UNDELIVERED;
2170 ts->stat = SAS_QUEUE_FULL;
2171 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2172 return;
2173 }
2174 break;
2175 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2176 PM8001_IO_DBG(pm8001_ha,
2177 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2178 ts->resp = SAS_TASK_UNDELIVERED;
2179 ts->stat = SAS_OPEN_REJECT;
2180 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2181 if (!t->uldd_task) {
2182 pm8001_handle_event(pm8001_ha,
2183 pm8001_dev,
2184 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2185 ts->resp = SAS_TASK_UNDELIVERED;
2186 ts->stat = SAS_QUEUE_FULL;
2187 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2188 return;
2189 }
2190 break;
2191 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2192 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2193 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2194 ts->resp = SAS_TASK_COMPLETE;
2195 ts->stat = SAS_OPEN_REJECT;
2196 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2197 break;
2198 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
2199 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2200 "IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n"));
2201 ts->resp = SAS_TASK_COMPLETE;
2202 ts->stat = SAS_DEV_NO_RESPONSE;
2203 if (!t->uldd_task) {
2204 pm8001_handle_event(pm8001_ha,
2205 pm8001_dev,
2206 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
2207 ts->resp = SAS_TASK_UNDELIVERED;
2208 ts->stat = SAS_QUEUE_FULL;
2209 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2210 return;
2211 }
2212 break;
2213 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2214 PM8001_IO_DBG(pm8001_ha,
2215 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2216 ts->resp = SAS_TASK_COMPLETE;
2217 ts->stat = SAS_OPEN_REJECT;
2218 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2219 break;
2220 case IO_XFER_ERROR_NAK_RECEIVED:
2221 PM8001_IO_DBG(pm8001_ha,
2222 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2223 ts->resp = SAS_TASK_COMPLETE;
2224 ts->stat = SAS_NAK_R_ERR;
2225 break;
2226 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2227 PM8001_IO_DBG(pm8001_ha,
2228 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2229 ts->resp = SAS_TASK_COMPLETE;
2230 ts->stat = SAS_NAK_R_ERR;
2231 break;
2232 case IO_XFER_ERROR_DMA:
2233 PM8001_IO_DBG(pm8001_ha,
2234 pm8001_printk("IO_XFER_ERROR_DMA\n"));
2235 ts->resp = SAS_TASK_COMPLETE;
2236 ts->stat = SAS_ABORTED_TASK;
2237 break;
2238 case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
2239 PM8001_IO_DBG(pm8001_ha,
2240 pm8001_printk("IO_XFER_ERROR_SATA_LINK_TIMEOUT\n"));
2241 ts->resp = SAS_TASK_UNDELIVERED;
2242 ts->stat = SAS_DEV_NO_RESPONSE;
2243 break;
2244 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2245 PM8001_IO_DBG(pm8001_ha,
2246 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2247 ts->resp = SAS_TASK_COMPLETE;
2248 ts->stat = SAS_DATA_UNDERRUN;
2249 break;
2250 case IO_XFER_OPEN_RETRY_TIMEOUT:
2251 PM8001_IO_DBG(pm8001_ha,
2252 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2253 ts->resp = SAS_TASK_COMPLETE;
2254 ts->stat = SAS_OPEN_TO;
2255 break;
2256 case IO_PORT_IN_RESET:
2257 PM8001_IO_DBG(pm8001_ha,
2258 pm8001_printk("IO_PORT_IN_RESET\n"));
2259 ts->resp = SAS_TASK_COMPLETE;
2260 ts->stat = SAS_DEV_NO_RESPONSE;
2261 break;
2262 case IO_DS_NON_OPERATIONAL:
2263 PM8001_IO_DBG(pm8001_ha,
2264 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2265 ts->resp = SAS_TASK_COMPLETE;
2266 ts->stat = SAS_DEV_NO_RESPONSE;
2267 if (!t->uldd_task) {
2268 pm8001_handle_event(pm8001_ha, pm8001_dev,
2269 IO_DS_NON_OPERATIONAL);
2270 ts->resp = SAS_TASK_UNDELIVERED;
2271 ts->stat = SAS_QUEUE_FULL;
2272 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2273 return;
2274 }
2275 break;
2276 case IO_DS_IN_RECOVERY:
2277 PM8001_IO_DBG(pm8001_ha,
2278 pm8001_printk("IO_DS_IN_RECOVERY\n"));
2279 ts->resp = SAS_TASK_COMPLETE;
2280 ts->stat = SAS_DEV_NO_RESPONSE;
2281 break;
2282 case IO_DS_IN_ERROR:
2283 PM8001_IO_DBG(pm8001_ha,
2284 pm8001_printk("IO_DS_IN_ERROR\n"));
2285 ts->resp = SAS_TASK_COMPLETE;
2286 ts->stat = SAS_DEV_NO_RESPONSE;
2287 if (!t->uldd_task) {
2288 pm8001_handle_event(pm8001_ha, pm8001_dev,
2289 IO_DS_IN_ERROR);
2290 ts->resp = SAS_TASK_UNDELIVERED;
2291 ts->stat = SAS_QUEUE_FULL;
2292 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2293 return;
2294 }
2295 break;
2296 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2297 PM8001_IO_DBG(pm8001_ha,
2298 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2299 ts->resp = SAS_TASK_COMPLETE;
2300 ts->stat = SAS_OPEN_REJECT;
2301 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2302 default:
2303 PM8001_IO_DBG(pm8001_ha,
2304 pm8001_printk("Unknown status 0x%x\n", status));
2305 /* not allowed case. Therefore, return failed status */
2306 ts->resp = SAS_TASK_COMPLETE;
2307 ts->stat = SAS_DEV_NO_RESPONSE;
2308 break;
2309 }
2310 spin_lock_irqsave(&t->task_state_lock, flags);
2311 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2312 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2313 t->task_state_flags |= SAS_TASK_STATE_DONE;
2314 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2315 spin_unlock_irqrestore(&t->task_state_lock, flags);
2316 PM8001_FAIL_DBG(pm8001_ha,
2317 pm8001_printk("task 0x%p done with io_status 0x%x"
2318 " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2319 t, status, ts->resp, ts->stat));
2320 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2321 } else {
2322 spin_unlock_irqrestore(&t->task_state_lock, flags);
2323 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2324 }
2325}
2326
2327/*See the comments for mpi_ssp_completion */
2328static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
2329{
2330 struct sas_task *t;
2331 struct task_status_struct *ts;
2332 struct pm8001_ccb_info *ccb;
2333 struct pm8001_device *pm8001_dev;
2334 struct sata_event_resp *psataPayload =
2335 (struct sata_event_resp *)(piomb + 4);
2336 u32 event = le32_to_cpu(psataPayload->event);
2337 u32 tag = le32_to_cpu(psataPayload->tag);
2338 u32 port_id = le32_to_cpu(psataPayload->port_id);
2339 u32 dev_id = le32_to_cpu(psataPayload->device_id);
2340 unsigned long flags;
2341
2342 ccb = &pm8001_ha->ccb_info[tag];
2343
2344 if (ccb) {
2345 t = ccb->task;
2346 pm8001_dev = ccb->device;
2347 } else {
2348 PM8001_FAIL_DBG(pm8001_ha,
2349 pm8001_printk("No CCB !!!. returning\n"));
2350 return;
2351 }
2352 if (event)
2353 PM8001_FAIL_DBG(pm8001_ha,
2354 pm8001_printk("SATA EVENT 0x%x\n", event));
2355
2356 /* Check if this is NCQ error */
2357 if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) {
2358 /* find device using device id */
2359 pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id);
2360 /* send read log extension */
2361 if (pm8001_dev)
2362 pm80xx_send_read_log(pm8001_ha, pm8001_dev);
2363 return;
2364 }
2365
2366 if (unlikely(!t || !t->lldd_task || !t->dev)) {
2367 PM8001_FAIL_DBG(pm8001_ha,
2368 pm8001_printk("task or dev null\n"));
2369 return;
2370 }
2371
2372 ts = &t->task_status;
2373 PM8001_IO_DBG(pm8001_ha,
2374 pm8001_printk("port_id:0x%x, tag:0x%x, event:0x%x\n",
2375 port_id, tag, event));
2376 switch (event) {
2377 case IO_OVERFLOW:
2378 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2379 ts->resp = SAS_TASK_COMPLETE;
2380 ts->stat = SAS_DATA_OVERRUN;
2381 ts->residual = 0;
2382 if (pm8001_dev)
2383 pm8001_dev->running_req--;
2384 break;
2385 case IO_XFER_ERROR_BREAK:
2386 PM8001_IO_DBG(pm8001_ha,
2387 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2388 ts->resp = SAS_TASK_COMPLETE;
2389 ts->stat = SAS_INTERRUPTED;
2390 break;
2391 case IO_XFER_ERROR_PHY_NOT_READY:
2392 PM8001_IO_DBG(pm8001_ha,
2393 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2394 ts->resp = SAS_TASK_COMPLETE;
2395 ts->stat = SAS_OPEN_REJECT;
2396 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2397 break;
2398 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2399 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2400 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2401 ts->resp = SAS_TASK_COMPLETE;
2402 ts->stat = SAS_OPEN_REJECT;
2403 ts->open_rej_reason = SAS_OREJ_EPROTO;
2404 break;
2405 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2406 PM8001_IO_DBG(pm8001_ha,
2407 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2408 ts->resp = SAS_TASK_COMPLETE;
2409 ts->stat = SAS_OPEN_REJECT;
2410 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2411 break;
2412 case IO_OPEN_CNX_ERROR_BREAK:
2413 PM8001_IO_DBG(pm8001_ha,
2414 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2415 ts->resp = SAS_TASK_COMPLETE;
2416 ts->stat = SAS_OPEN_REJECT;
2417 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2418 break;
2419 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2420 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2421 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2422 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2423 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2424 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2425 PM8001_FAIL_DBG(pm8001_ha,
2426 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2427 ts->resp = SAS_TASK_UNDELIVERED;
2428 ts->stat = SAS_DEV_NO_RESPONSE;
2429 if (!t->uldd_task) {
2430 pm8001_handle_event(pm8001_ha,
2431 pm8001_dev,
2432 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2433 ts->resp = SAS_TASK_COMPLETE;
2434 ts->stat = SAS_QUEUE_FULL;
2435 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2436 return;
2437 }
2438 break;
2439 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2440 PM8001_IO_DBG(pm8001_ha,
2441 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2442 ts->resp = SAS_TASK_UNDELIVERED;
2443 ts->stat = SAS_OPEN_REJECT;
2444 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2445 break;
2446 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2447 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2448 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2449 ts->resp = SAS_TASK_COMPLETE;
2450 ts->stat = SAS_OPEN_REJECT;
2451 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2452 break;
2453 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2454 PM8001_IO_DBG(pm8001_ha,
2455 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2456 ts->resp = SAS_TASK_COMPLETE;
2457 ts->stat = SAS_OPEN_REJECT;
2458 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2459 break;
2460 case IO_XFER_ERROR_NAK_RECEIVED:
2461 PM8001_IO_DBG(pm8001_ha,
2462 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2463 ts->resp = SAS_TASK_COMPLETE;
2464 ts->stat = SAS_NAK_R_ERR;
2465 break;
2466 case IO_XFER_ERROR_PEER_ABORTED:
2467 PM8001_IO_DBG(pm8001_ha,
2468 pm8001_printk("IO_XFER_ERROR_PEER_ABORTED\n"));
2469 ts->resp = SAS_TASK_COMPLETE;
2470 ts->stat = SAS_NAK_R_ERR;
2471 break;
2472 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2473 PM8001_IO_DBG(pm8001_ha,
2474 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2475 ts->resp = SAS_TASK_COMPLETE;
2476 ts->stat = SAS_DATA_UNDERRUN;
2477 break;
2478 case IO_XFER_OPEN_RETRY_TIMEOUT:
2479 PM8001_IO_DBG(pm8001_ha,
2480 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2481 ts->resp = SAS_TASK_COMPLETE;
2482 ts->stat = SAS_OPEN_TO;
2483 break;
2484 case IO_XFER_ERROR_UNEXPECTED_PHASE:
2485 PM8001_IO_DBG(pm8001_ha,
2486 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2487 ts->resp = SAS_TASK_COMPLETE;
2488 ts->stat = SAS_OPEN_TO;
2489 break;
2490 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2491 PM8001_IO_DBG(pm8001_ha,
2492 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2493 ts->resp = SAS_TASK_COMPLETE;
2494 ts->stat = SAS_OPEN_TO;
2495 break;
2496 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2497 PM8001_IO_DBG(pm8001_ha,
2498 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2499 ts->resp = SAS_TASK_COMPLETE;
2500 ts->stat = SAS_OPEN_TO;
2501 break;
2502 case IO_XFER_ERROR_OFFSET_MISMATCH:
2503 PM8001_IO_DBG(pm8001_ha,
2504 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2505 ts->resp = SAS_TASK_COMPLETE;
2506 ts->stat = SAS_OPEN_TO;
2507 break;
2508 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2509 PM8001_IO_DBG(pm8001_ha,
2510 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2511 ts->resp = SAS_TASK_COMPLETE;
2512 ts->stat = SAS_OPEN_TO;
2513 break;
2514 case IO_XFER_CMD_FRAME_ISSUED:
2515 PM8001_IO_DBG(pm8001_ha,
2516 pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
2517 break;
2518 case IO_XFER_PIO_SETUP_ERROR:
2519 PM8001_IO_DBG(pm8001_ha,
2520 pm8001_printk("IO_XFER_PIO_SETUP_ERROR\n"));
2521 ts->resp = SAS_TASK_COMPLETE;
2522 ts->stat = SAS_OPEN_TO;
2523 break;
2524 case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
2525 PM8001_FAIL_DBG(pm8001_ha,
2526 pm8001_printk("IO_XFR_ERROR_INTERNAL_CRC_ERROR\n"));
2527 /* TBC: used default set values */
2528 ts->resp = SAS_TASK_COMPLETE;
2529 ts->stat = SAS_OPEN_TO;
2530 break;
2531 case IO_XFER_DMA_ACTIVATE_TIMEOUT:
2532 PM8001_FAIL_DBG(pm8001_ha,
2533 pm8001_printk("IO_XFR_DMA_ACTIVATE_TIMEOUT\n"));
2534 /* TBC: used default set values */
2535 ts->resp = SAS_TASK_COMPLETE;
2536 ts->stat = SAS_OPEN_TO;
2537 break;
2538 default:
2539 PM8001_IO_DBG(pm8001_ha,
2540 pm8001_printk("Unknown status 0x%x\n", event));
2541 /* not allowed case. Therefore, return failed status */
2542 ts->resp = SAS_TASK_COMPLETE;
2543 ts->stat = SAS_OPEN_TO;
2544 break;
2545 }
2546 spin_lock_irqsave(&t->task_state_lock, flags);
2547 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2548 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2549 t->task_state_flags |= SAS_TASK_STATE_DONE;
2550 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2551 spin_unlock_irqrestore(&t->task_state_lock, flags);
2552 PM8001_FAIL_DBG(pm8001_ha,
2553 pm8001_printk("task 0x%p done with io_status 0x%x"
2554 " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2555 t, event, ts->resp, ts->stat));
2556 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2557 } else {
2558 spin_unlock_irqrestore(&t->task_state_lock, flags);
2559 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2560 }
2561}
2562
2563/*See the comments for mpi_ssp_completion */
2564static void
2565mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2566{
2567 u32 param, i;
2568 struct sas_task *t;
2569 struct pm8001_ccb_info *ccb;
2570 unsigned long flags;
2571 u32 status;
2572 u32 tag;
2573 struct smp_completion_resp *psmpPayload;
2574 struct task_status_struct *ts;
2575 struct pm8001_device *pm8001_dev;
2576 char *pdma_respaddr = NULL;
2577
2578 psmpPayload = (struct smp_completion_resp *)(piomb + 4);
2579 status = le32_to_cpu(psmpPayload->status);
2580 tag = le32_to_cpu(psmpPayload->tag);
2581
2582 ccb = &pm8001_ha->ccb_info[tag];
2583 param = le32_to_cpu(psmpPayload->param);
2584 t = ccb->task;
2585 ts = &t->task_status;
2586 pm8001_dev = ccb->device;
2587 if (status)
2588 PM8001_FAIL_DBG(pm8001_ha,
2589 pm8001_printk("smp IO status 0x%x\n", status));
2590 if (unlikely(!t || !t->lldd_task || !t->dev))
2591 return;
2592
2593 switch (status) {
2594
2595 case IO_SUCCESS:
2596 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2597 ts->resp = SAS_TASK_COMPLETE;
2598 ts->stat = SAM_STAT_GOOD;
2599 if (pm8001_dev)
2600 pm8001_dev->running_req--;
2601 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
2602 PM8001_IO_DBG(pm8001_ha,
2603 pm8001_printk("DIRECT RESPONSE Length:%d\n",
2604 param));
2605 pdma_respaddr = (char *)(phys_to_virt(cpu_to_le64
2606 ((u64)sg_dma_address
2607 (&t->smp_task.smp_resp))));
2608 for (i = 0; i < param; i++) {
2609 *(pdma_respaddr+i) = psmpPayload->_r_a[i];
2610 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2611 "SMP Byte%d DMA data 0x%x psmp 0x%x\n",
2612 i, *(pdma_respaddr+i),
2613 psmpPayload->_r_a[i]));
2614 }
2615 }
2616 break;
2617 case IO_ABORTED:
2618 PM8001_IO_DBG(pm8001_ha,
2619 pm8001_printk("IO_ABORTED IOMB\n"));
2620 ts->resp = SAS_TASK_COMPLETE;
2621 ts->stat = SAS_ABORTED_TASK;
2622 if (pm8001_dev)
2623 pm8001_dev->running_req--;
2624 break;
2625 case IO_OVERFLOW:
2626 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2627 ts->resp = SAS_TASK_COMPLETE;
2628 ts->stat = SAS_DATA_OVERRUN;
2629 ts->residual = 0;
2630 if (pm8001_dev)
2631 pm8001_dev->running_req--;
2632 break;
2633 case IO_NO_DEVICE:
2634 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NO_DEVICE\n"));
2635 ts->resp = SAS_TASK_COMPLETE;
2636 ts->stat = SAS_PHY_DOWN;
2637 break;
2638 case IO_ERROR_HW_TIMEOUT:
2639 PM8001_IO_DBG(pm8001_ha,
2640 pm8001_printk("IO_ERROR_HW_TIMEOUT\n"));
2641 ts->resp = SAS_TASK_COMPLETE;
2642 ts->stat = SAM_STAT_BUSY;
2643 break;
2644 case IO_XFER_ERROR_BREAK:
2645 PM8001_IO_DBG(pm8001_ha,
2646 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2647 ts->resp = SAS_TASK_COMPLETE;
2648 ts->stat = SAM_STAT_BUSY;
2649 break;
2650 case IO_XFER_ERROR_PHY_NOT_READY:
2651 PM8001_IO_DBG(pm8001_ha,
2652 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2653 ts->resp = SAS_TASK_COMPLETE;
2654 ts->stat = SAM_STAT_BUSY;
2655 break;
2656 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2657 PM8001_IO_DBG(pm8001_ha,
2658 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2659 ts->resp = SAS_TASK_COMPLETE;
2660 ts->stat = SAS_OPEN_REJECT;
2661 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2662 break;
2663 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2664 PM8001_IO_DBG(pm8001_ha,
2665 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2666 ts->resp = SAS_TASK_COMPLETE;
2667 ts->stat = SAS_OPEN_REJECT;
2668 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2669 break;
2670 case IO_OPEN_CNX_ERROR_BREAK:
2671 PM8001_IO_DBG(pm8001_ha,
2672 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2673 ts->resp = SAS_TASK_COMPLETE;
2674 ts->stat = SAS_OPEN_REJECT;
2675 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2676 break;
2677 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2678 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2679 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2680 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2681 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2682 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2683 PM8001_IO_DBG(pm8001_ha,
2684 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2685 ts->resp = SAS_TASK_COMPLETE;
2686 ts->stat = SAS_OPEN_REJECT;
2687 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2688 pm8001_handle_event(pm8001_ha,
2689 pm8001_dev,
2690 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2691 break;
2692 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2693 PM8001_IO_DBG(pm8001_ha,
2694 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2695 ts->resp = SAS_TASK_COMPLETE;
2696 ts->stat = SAS_OPEN_REJECT;
2697 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2698 break;
2699 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2700 PM8001_IO_DBG(pm8001_ha, pm8001_printk(\
2701 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2702 ts->resp = SAS_TASK_COMPLETE;
2703 ts->stat = SAS_OPEN_REJECT;
2704 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2705 break;
2706 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2707 PM8001_IO_DBG(pm8001_ha,
2708 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2709 ts->resp = SAS_TASK_COMPLETE;
2710 ts->stat = SAS_OPEN_REJECT;
2711 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2712 break;
2713 case IO_XFER_ERROR_RX_FRAME:
2714 PM8001_IO_DBG(pm8001_ha,
2715 pm8001_printk("IO_XFER_ERROR_RX_FRAME\n"));
2716 ts->resp = SAS_TASK_COMPLETE;
2717 ts->stat = SAS_DEV_NO_RESPONSE;
2718 break;
2719 case IO_XFER_OPEN_RETRY_TIMEOUT:
2720 PM8001_IO_DBG(pm8001_ha,
2721 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2722 ts->resp = SAS_TASK_COMPLETE;
2723 ts->stat = SAS_OPEN_REJECT;
2724 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2725 break;
2726 case IO_ERROR_INTERNAL_SMP_RESOURCE:
2727 PM8001_IO_DBG(pm8001_ha,
2728 pm8001_printk("IO_ERROR_INTERNAL_SMP_RESOURCE\n"));
2729 ts->resp = SAS_TASK_COMPLETE;
2730 ts->stat = SAS_QUEUE_FULL;
2731 break;
2732 case IO_PORT_IN_RESET:
2733 PM8001_IO_DBG(pm8001_ha,
2734 pm8001_printk("IO_PORT_IN_RESET\n"));
2735 ts->resp = SAS_TASK_COMPLETE;
2736 ts->stat = SAS_OPEN_REJECT;
2737 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2738 break;
2739 case IO_DS_NON_OPERATIONAL:
2740 PM8001_IO_DBG(pm8001_ha,
2741 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2742 ts->resp = SAS_TASK_COMPLETE;
2743 ts->stat = SAS_DEV_NO_RESPONSE;
2744 break;
2745 case IO_DS_IN_RECOVERY:
2746 PM8001_IO_DBG(pm8001_ha,
2747 pm8001_printk("IO_DS_IN_RECOVERY\n"));
2748 ts->resp = SAS_TASK_COMPLETE;
2749 ts->stat = SAS_OPEN_REJECT;
2750 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2751 break;
2752 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2753 PM8001_IO_DBG(pm8001_ha,
2754 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2755 ts->resp = SAS_TASK_COMPLETE;
2756 ts->stat = SAS_OPEN_REJECT;
2757 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2758 break;
2759 default:
2760 PM8001_IO_DBG(pm8001_ha,
2761 pm8001_printk("Unknown status 0x%x\n", status));
2762 ts->resp = SAS_TASK_COMPLETE;
2763 ts->stat = SAS_DEV_NO_RESPONSE;
2764 /* not allowed case. Therefore, return failed status */
2765 break;
2766 }
2767 spin_lock_irqsave(&t->task_state_lock, flags);
2768 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2769 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2770 t->task_state_flags |= SAS_TASK_STATE_DONE;
2771 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2772 spin_unlock_irqrestore(&t->task_state_lock, flags);
2773 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
2774 "task 0x%p done with io_status 0x%x resp 0x%x"
2775 "stat 0x%x but aborted by upper layer!\n",
2776 t, status, ts->resp, ts->stat));
2777 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2778 } else {
2779 spin_unlock_irqrestore(&t->task_state_lock, flags);
2780 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2781 mb();/* in order to force CPU ordering */
2782 t->task_done(t);
2783 }
2784}
2785
2786/**
2787 * pm80xx_hw_event_ack_req- For PM8001,some events need to acknowage to FW.
2788 * @pm8001_ha: our hba card information
2789 * @Qnum: the outbound queue message number.
2790 * @SEA: source of event to ack
2791 * @port_id: port id.
2792 * @phyId: phy id.
2793 * @param0: parameter 0.
2794 * @param1: parameter 1.
2795 */
2796static void pm80xx_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
2797 u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
2798{
2799 struct hw_event_ack_req payload;
2800 u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
2801
2802 struct inbound_queue_table *circularQ;
2803
2804 memset((u8 *)&payload, 0, sizeof(payload));
2805 circularQ = &pm8001_ha->inbnd_q_tbl[Qnum];
2806 payload.tag = cpu_to_le32(1);
2807 payload.phyid_sea_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
2808 ((phyId & 0xFF) << 24) | (port_id & 0xFF));
2809 payload.param0 = cpu_to_le32(param0);
2810 payload.param1 = cpu_to_le32(param1);
2811 pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
2812}
2813
2814static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
2815 u32 phyId, u32 phy_op);
2816
2817/**
2818 * hw_event_sas_phy_up -FW tells me a SAS phy up event.
2819 * @pm8001_ha: our hba card information
2820 * @piomb: IO message buffer
2821 */
2822static void
2823hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
2824{
2825 struct hw_event_resp *pPayload =
2826 (struct hw_event_resp *)(piomb + 4);
2827 u32 lr_status_evt_portid =
2828 le32_to_cpu(pPayload->lr_status_evt_portid);
2829 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
2830
2831 u8 link_rate =
2832 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
2833 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
2834 u8 phy_id =
2835 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
2836 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
2837
2838 struct pm8001_port *port = &pm8001_ha->port[port_id];
2839 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
2840 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2841 unsigned long flags;
2842 u8 deviceType = pPayload->sas_identify.dev_type;
2843 port->port_state = portstate;
2844 phy->phy_state = PHY_STATE_LINK_UP_SPCV;
2845 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
2846 "portid:%d; phyid:%d; linkrate:%d; "
2847 "portstate:%x; devicetype:%x\n",
2848 port_id, phy_id, link_rate, portstate, deviceType));
2849
2850 switch (deviceType) {
2851 case SAS_PHY_UNUSED:
2852 PM8001_MSG_DBG(pm8001_ha,
2853 pm8001_printk("device type no device.\n"));
2854 break;
2855 case SAS_END_DEVICE:
2856 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("end device.\n"));
2857 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id,
2858 PHY_NOTIFY_ENABLE_SPINUP);
2859 port->port_attached = 1;
2860 pm8001_get_lrate_mode(phy, link_rate);
2861 break;
2862 case SAS_EDGE_EXPANDER_DEVICE:
2863 PM8001_MSG_DBG(pm8001_ha,
2864 pm8001_printk("expander device.\n"));
2865 port->port_attached = 1;
2866 pm8001_get_lrate_mode(phy, link_rate);
2867 break;
2868 case SAS_FANOUT_EXPANDER_DEVICE:
2869 PM8001_MSG_DBG(pm8001_ha,
2870 pm8001_printk("fanout expander device.\n"));
2871 port->port_attached = 1;
2872 pm8001_get_lrate_mode(phy, link_rate);
2873 break;
2874 default:
2875 PM8001_MSG_DBG(pm8001_ha,
2876 pm8001_printk("unknown device type(%x)\n", deviceType));
2877 break;
2878 }
2879 phy->phy_type |= PORT_TYPE_SAS;
2880 phy->identify.device_type = deviceType;
2881 phy->phy_attached = 1;
2882 if (phy->identify.device_type == SAS_END_DEVICE)
2883 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
2884 else if (phy->identify.device_type != SAS_PHY_UNUSED)
2885 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
2886 phy->sas_phy.oob_mode = SAS_OOB_MODE;
2887 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
2888 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
2889 memcpy(phy->frame_rcvd, &pPayload->sas_identify,
2890 sizeof(struct sas_identify_frame)-4);
2891 phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
2892 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
2893 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
2894 if (pm8001_ha->flags == PM8001F_RUN_TIME)
2895 mdelay(200);/*delay a moment to wait disk to spinup*/
2896 pm8001_bytes_dmaed(pm8001_ha, phy_id);
2897}
2898
2899/**
2900 * hw_event_sata_phy_up -FW tells me a SATA phy up event.
2901 * @pm8001_ha: our hba card information
2902 * @piomb: IO message buffer
2903 */
2904static void
2905hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
2906{
2907 struct hw_event_resp *pPayload =
2908 (struct hw_event_resp *)(piomb + 4);
2909 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
2910 u32 lr_status_evt_portid =
2911 le32_to_cpu(pPayload->lr_status_evt_portid);
2912 u8 link_rate =
2913 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
2914 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
2915 u8 phy_id =
2916 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
2917
2918 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
2919
2920 struct pm8001_port *port = &pm8001_ha->port[port_id];
2921 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
2922 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2923 unsigned long flags;
2924 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
2925 "port id %d, phy id %d link_rate %d portstate 0x%x\n",
2926 port_id, phy_id, link_rate, portstate));
2927
2928 port->port_state = portstate;
2929 phy->phy_state = PHY_STATE_LINK_UP_SPCV;
2930 port->port_attached = 1;
2931 pm8001_get_lrate_mode(phy, link_rate);
2932 phy->phy_type |= PORT_TYPE_SATA;
2933 phy->phy_attached = 1;
2934 phy->sas_phy.oob_mode = SATA_OOB_MODE;
2935 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
2936 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
2937 memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
2938 sizeof(struct dev_to_host_fis));
2939 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
2940 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
2941 phy->identify.device_type = SAS_SATA_DEV;
2942 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
2943 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
2944 pm8001_bytes_dmaed(pm8001_ha, phy_id);
2945}
2946
2947/**
2948 * hw_event_phy_down -we should notify the libsas the phy is down.
2949 * @pm8001_ha: our hba card information
2950 * @piomb: IO message buffer
2951 */
2952static void
2953hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
2954{
2955 struct hw_event_resp *pPayload =
2956 (struct hw_event_resp *)(piomb + 4);
2957
2958 u32 lr_status_evt_portid =
2959 le32_to_cpu(pPayload->lr_status_evt_portid);
2960 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
2961 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
2962 u8 phy_id =
2963 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
2964 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
2965
2966 struct pm8001_port *port = &pm8001_ha->port[port_id];
2967 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2968 port->port_state = portstate;
2969 phy->phy_type = 0;
2970 phy->identify.device_type = 0;
2971 phy->phy_attached = 0;
2972 memset(&phy->dev_sas_addr, 0, SAS_ADDR_SIZE);
2973 switch (portstate) {
2974 case PORT_VALID:
2975 break;
2976 case PORT_INVALID:
2977 PM8001_MSG_DBG(pm8001_ha,
2978 pm8001_printk(" PortInvalid portID %d\n", port_id));
2979 PM8001_MSG_DBG(pm8001_ha,
2980 pm8001_printk(" Last phy Down and port invalid\n"));
2981 port->port_attached = 0;
2982 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
2983 port_id, phy_id, 0, 0);
2984 break;
2985 case PORT_IN_RESET:
2986 PM8001_MSG_DBG(pm8001_ha,
2987 pm8001_printk(" Port In Reset portID %d\n", port_id));
2988 break;
2989 case PORT_NOT_ESTABLISHED:
2990 PM8001_MSG_DBG(pm8001_ha,
2991 pm8001_printk(" phy Down and PORT_NOT_ESTABLISHED\n"));
2992 port->port_attached = 0;
2993 break;
2994 case PORT_LOSTCOMM:
2995 PM8001_MSG_DBG(pm8001_ha,
2996 pm8001_printk(" phy Down and PORT_LOSTCOMM\n"));
2997 PM8001_MSG_DBG(pm8001_ha,
2998 pm8001_printk(" Last phy Down and port invalid\n"));
2999 port->port_attached = 0;
3000 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3001 port_id, phy_id, 0, 0);
3002 break;
3003 default:
3004 port->port_attached = 0;
3005 PM8001_MSG_DBG(pm8001_ha,
3006 pm8001_printk(" phy Down and(default) = 0x%x\n",
3007 portstate));
3008 break;
3009
3010 }
3011}
3012
3013static int mpi_phy_start_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3014{
3015 struct phy_start_resp *pPayload =
3016 (struct phy_start_resp *)(piomb + 4);
3017 u32 status =
3018 le32_to_cpu(pPayload->status);
3019 u32 phy_id =
3020 le32_to_cpu(pPayload->phyid);
3021 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3022
3023 PM8001_INIT_DBG(pm8001_ha,
3024 pm8001_printk("phy start resp status:0x%x, phyid:0x%x\n",
3025 status, phy_id));
3026 if (status == 0) {
3027 phy->phy_state = 1;
3028 if (pm8001_ha->flags == PM8001F_RUN_TIME)
3029 complete(phy->enable_completion);
3030 }
3031 return 0;
3032
3033}
3034
3035/**
3036 * mpi_thermal_hw_event -The hw event has come.
3037 * @pm8001_ha: our hba card information
3038 * @piomb: IO message buffer
3039 */
3040static int mpi_thermal_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3041{
3042 struct thermal_hw_event *pPayload =
3043 (struct thermal_hw_event *)(piomb + 4);
3044
3045 u32 thermal_event = le32_to_cpu(pPayload->thermal_event);
3046 u32 rht_lht = le32_to_cpu(pPayload->rht_lht);
3047
3048 if (thermal_event & 0x40) {
3049 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3050 "Thermal Event: Local high temperature violated!\n"));
3051 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3052 "Thermal Event: Measured local high temperature %d\n",
3053 ((rht_lht & 0xFF00) >> 8)));
3054 }
3055 if (thermal_event & 0x10) {
3056 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3057 "Thermal Event: Remote high temperature violated!\n"));
3058 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3059 "Thermal Event: Measured remote high temperature %d\n",
3060 ((rht_lht & 0xFF000000) >> 24)));
3061 }
3062 return 0;
3063}
3064
3065/**
3066 * mpi_hw_event -The hw event has come.
3067 * @pm8001_ha: our hba card information
3068 * @piomb: IO message buffer
3069 */
3070static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3071{
3072 unsigned long flags;
3073 struct hw_event_resp *pPayload =
3074 (struct hw_event_resp *)(piomb + 4);
3075 u32 lr_status_evt_portid =
3076 le32_to_cpu(pPayload->lr_status_evt_portid);
3077 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3078 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3079 u8 phy_id =
3080 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3081 u16 eventType =
3082 (u16)((lr_status_evt_portid & 0x00FFFF00) >> 8);
3083 u8 status =
3084 (u8)((lr_status_evt_portid & 0x0F000000) >> 24);
3085
3086 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3087 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3088 struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
3089 PM8001_MSG_DBG(pm8001_ha,
3090 pm8001_printk("portid:%d phyid:%d event:0x%x status:0x%x\n",
3091 port_id, phy_id, eventType, status));
3092
3093 switch (eventType) {
3094
3095 case HW_EVENT_SAS_PHY_UP:
3096 PM8001_MSG_DBG(pm8001_ha,
3097 pm8001_printk("HW_EVENT_PHY_START_STATUS\n"));
3098 hw_event_sas_phy_up(pm8001_ha, piomb);
3099 break;
3100 case HW_EVENT_SATA_PHY_UP:
3101 PM8001_MSG_DBG(pm8001_ha,
3102 pm8001_printk("HW_EVENT_SATA_PHY_UP\n"));
3103 hw_event_sata_phy_up(pm8001_ha, piomb);
3104 break;
3105 case HW_EVENT_SATA_SPINUP_HOLD:
3106 PM8001_MSG_DBG(pm8001_ha,
3107 pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD\n"));
3108 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD);
3109 break;
3110 case HW_EVENT_PHY_DOWN:
3111 PM8001_MSG_DBG(pm8001_ha,
3112 pm8001_printk("HW_EVENT_PHY_DOWN\n"));
3113 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL);
3114 phy->phy_attached = 0;
3115 phy->phy_state = 0;
3116 hw_event_phy_down(pm8001_ha, piomb);
3117 break;
3118 case HW_EVENT_PORT_INVALID:
3119 PM8001_MSG_DBG(pm8001_ha,
3120 pm8001_printk("HW_EVENT_PORT_INVALID\n"));
3121 sas_phy_disconnected(sas_phy);
3122 phy->phy_attached = 0;
3123 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3124 break;
3125 /* the broadcast change primitive received, tell the LIBSAS this event
3126 to revalidate the sas domain*/
3127 case HW_EVENT_BROADCAST_CHANGE:
3128 PM8001_MSG_DBG(pm8001_ha,
3129 pm8001_printk("HW_EVENT_BROADCAST_CHANGE\n"));
3130 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
3131 port_id, phy_id, 1, 0);
3132 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3133 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
3134 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3135 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3136 break;
3137 case HW_EVENT_PHY_ERROR:
3138 PM8001_MSG_DBG(pm8001_ha,
3139 pm8001_printk("HW_EVENT_PHY_ERROR\n"));
3140 sas_phy_disconnected(&phy->sas_phy);
3141 phy->phy_attached = 0;
3142 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR);
3143 break;
3144 case HW_EVENT_BROADCAST_EXP:
3145 PM8001_MSG_DBG(pm8001_ha,
3146 pm8001_printk("HW_EVENT_BROADCAST_EXP\n"));
3147 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3148 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
3149 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3150 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3151 break;
3152 case HW_EVENT_LINK_ERR_INVALID_DWORD:
3153 PM8001_MSG_DBG(pm8001_ha,
3154 pm8001_printk("HW_EVENT_LINK_ERR_INVALID_DWORD\n"));
3155 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3156 HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
3157 sas_phy_disconnected(sas_phy);
3158 phy->phy_attached = 0;
3159 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3160 break;
3161 case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
3162 PM8001_MSG_DBG(pm8001_ha,
3163 pm8001_printk("HW_EVENT_LINK_ERR_DISPARITY_ERROR\n"));
3164 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3165 HW_EVENT_LINK_ERR_DISPARITY_ERROR,
3166 port_id, phy_id, 0, 0);
3167 sas_phy_disconnected(sas_phy);
3168 phy->phy_attached = 0;
3169 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3170 break;
3171 case HW_EVENT_LINK_ERR_CODE_VIOLATION:
3172 PM8001_MSG_DBG(pm8001_ha,
3173 pm8001_printk("HW_EVENT_LINK_ERR_CODE_VIOLATION\n"));
3174 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3175 HW_EVENT_LINK_ERR_CODE_VIOLATION,
3176 port_id, phy_id, 0, 0);
3177 sas_phy_disconnected(sas_phy);
3178 phy->phy_attached = 0;
3179 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3180 break;
3181 case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
3182 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3183 "HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n"));
3184 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3185 HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
3186 port_id, phy_id, 0, 0);
3187 sas_phy_disconnected(sas_phy);
3188 phy->phy_attached = 0;
3189 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3190 break;
3191 case HW_EVENT_MALFUNCTION:
3192 PM8001_MSG_DBG(pm8001_ha,
3193 pm8001_printk("HW_EVENT_MALFUNCTION\n"));
3194 break;
3195 case HW_EVENT_BROADCAST_SES:
3196 PM8001_MSG_DBG(pm8001_ha,
3197 pm8001_printk("HW_EVENT_BROADCAST_SES\n"));
3198 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3199 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
3200 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3201 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3202 break;
3203 case HW_EVENT_INBOUND_CRC_ERROR:
3204 PM8001_MSG_DBG(pm8001_ha,
3205 pm8001_printk("HW_EVENT_INBOUND_CRC_ERROR\n"));
3206 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3207 HW_EVENT_INBOUND_CRC_ERROR,
3208 port_id, phy_id, 0, 0);
3209 break;
3210 case HW_EVENT_HARD_RESET_RECEIVED:
3211 PM8001_MSG_DBG(pm8001_ha,
3212 pm8001_printk("HW_EVENT_HARD_RESET_RECEIVED\n"));
3213 sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET);
3214 break;
3215 case HW_EVENT_ID_FRAME_TIMEOUT:
3216 PM8001_MSG_DBG(pm8001_ha,
3217 pm8001_printk("HW_EVENT_ID_FRAME_TIMEOUT\n"));
3218 sas_phy_disconnected(sas_phy);
3219 phy->phy_attached = 0;
3220 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3221 break;
3222 case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
3223 PM8001_MSG_DBG(pm8001_ha,
3224 pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n"));
3225 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3226 HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
3227 port_id, phy_id, 0, 0);
3228 sas_phy_disconnected(sas_phy);
3229 phy->phy_attached = 0;
3230 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3231 break;
3232 case HW_EVENT_PORT_RESET_TIMER_TMO:
3233 PM8001_MSG_DBG(pm8001_ha,
3234 pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO\n"));
3235 sas_phy_disconnected(sas_phy);
3236 phy->phy_attached = 0;
3237 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3238 break;
3239 case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
3240 PM8001_MSG_DBG(pm8001_ha,
3241 pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO\n"));
3242 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3243 HW_EVENT_PORT_RECOVERY_TIMER_TMO,
3244 port_id, phy_id, 0, 0);
3245 sas_phy_disconnected(sas_phy);
3246 phy->phy_attached = 0;
3247 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3248 break;
3249 case HW_EVENT_PORT_RECOVER:
3250 PM8001_MSG_DBG(pm8001_ha,
3251 pm8001_printk("HW_EVENT_PORT_RECOVER\n"));
3252 break;
3253 case HW_EVENT_PORT_RESET_COMPLETE:
3254 PM8001_MSG_DBG(pm8001_ha,
3255 pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE\n"));
3256 break;
3257 case EVENT_BROADCAST_ASYNCH_EVENT:
3258 PM8001_MSG_DBG(pm8001_ha,
3259 pm8001_printk("EVENT_BROADCAST_ASYNCH_EVENT\n"));
3260 break;
3261 default:
3262 PM8001_MSG_DBG(pm8001_ha,
3263 pm8001_printk("Unknown event type 0x%x\n", eventType));
3264 break;
3265 }
3266 return 0;
3267}
3268
3269/**
3270 * mpi_phy_stop_resp - SPCv specific
3271 * @pm8001_ha: our hba card information
3272 * @piomb: IO message buffer
3273 */
3274static int mpi_phy_stop_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3275{
3276 struct phy_stop_resp *pPayload =
3277 (struct phy_stop_resp *)(piomb + 4);
3278 u32 status =
3279 le32_to_cpu(pPayload->status);
3280 u32 phyid =
3281 le32_to_cpu(pPayload->phyid);
3282 struct pm8001_phy *phy = &pm8001_ha->phy[phyid];
3283 PM8001_MSG_DBG(pm8001_ha,
3284 pm8001_printk("phy:0x%x status:0x%x\n",
3285 phyid, status));
3286 if (status == 0)
3287 phy->phy_state = 0;
3288 return 0;
3289}
3290
3291/**
3292 * mpi_set_controller_config_resp - SPCv specific
3293 * @pm8001_ha: our hba card information
3294 * @piomb: IO message buffer
3295 */
3296static int mpi_set_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
3297 void *piomb)
3298{
3299 struct set_ctrl_cfg_resp *pPayload =
3300 (struct set_ctrl_cfg_resp *)(piomb + 4);
3301 u32 status = le32_to_cpu(pPayload->status);
3302 u32 err_qlfr_pgcd = le32_to_cpu(pPayload->err_qlfr_pgcd);
3303
3304 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3305 "SET CONTROLLER RESP: status 0x%x qlfr_pgcd 0x%x\n",
3306 status, err_qlfr_pgcd));
3307
3308 return 0;
3309}
3310
3311/**
3312 * mpi_get_controller_config_resp - SPCv specific
3313 * @pm8001_ha: our hba card information
3314 * @piomb: IO message buffer
3315 */
3316static int mpi_get_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
3317 void *piomb)
3318{
3319 PM8001_MSG_DBG(pm8001_ha,
3320 pm8001_printk(" pm80xx_addition_functionality\n"));
3321
3322 return 0;
3323}
3324
3325/**
3326 * mpi_get_phy_profile_resp - SPCv specific
3327 * @pm8001_ha: our hba card information
3328 * @piomb: IO message buffer
3329 */
3330static int mpi_get_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
3331 void *piomb)
3332{
3333 PM8001_MSG_DBG(pm8001_ha,
3334 pm8001_printk(" pm80xx_addition_functionality\n"));
3335
3336 return 0;
3337}
3338
3339/**
3340 * mpi_flash_op_ext_resp - SPCv specific
3341 * @pm8001_ha: our hba card information
3342 * @piomb: IO message buffer
3343 */
3344static int mpi_flash_op_ext_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3345{
3346 PM8001_MSG_DBG(pm8001_ha,
3347 pm8001_printk(" pm80xx_addition_functionality\n"));
3348
3349 return 0;
3350}
3351
3352/**
3353 * mpi_set_phy_profile_resp - SPCv specific
3354 * @pm8001_ha: our hba card information
3355 * @piomb: IO message buffer
3356 */
3357static int mpi_set_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
3358 void *piomb)
3359{
3360 u8 page_code;
3361 struct set_phy_profile_resp *pPayload =
3362 (struct set_phy_profile_resp *)(piomb + 4);
3363 u32 ppc_phyid = le32_to_cpu(pPayload->ppc_phyid);
3364 u32 status = le32_to_cpu(pPayload->status);
3365
3366 page_code = (u8)((ppc_phyid & 0xFF00) >> 8);
3367 if (status) {
3368 /* status is FAILED */
3369 PM8001_FAIL_DBG(pm8001_ha,
3370 pm8001_printk("PhyProfile command failed with status "
3371 "0x%08X \n", status));
3372 return -1;
3373 } else {
3374 if (page_code != SAS_PHY_ANALOG_SETTINGS_PAGE) {
3375 PM8001_FAIL_DBG(pm8001_ha,
3376 pm8001_printk("Invalid page code 0x%X\n",
3377 page_code));
3378 return -1;
3379 }
3380 }
3381 return 0;
3382}
3383
3384/**
3385 * mpi_kek_management_resp - SPCv specific
3386 * @pm8001_ha: our hba card information
3387 * @piomb: IO message buffer
3388 */
3389static int mpi_kek_management_resp(struct pm8001_hba_info *pm8001_ha,
3390 void *piomb)
3391{
3392 struct kek_mgmt_resp *pPayload = (struct kek_mgmt_resp *)(piomb + 4);
3393
3394 u32 status = le32_to_cpu(pPayload->status);
3395 u32 kidx_new_curr_ksop = le32_to_cpu(pPayload->kidx_new_curr_ksop);
3396 u32 err_qlfr = le32_to_cpu(pPayload->err_qlfr);
3397
3398 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3399 "KEK MGMT RESP. Status 0x%x idx_ksop 0x%x err_qlfr 0x%x\n",
3400 status, kidx_new_curr_ksop, err_qlfr));
3401
3402 return 0;
3403}
3404
3405/**
3406 * mpi_dek_management_resp - SPCv specific
3407 * @pm8001_ha: our hba card information
3408 * @piomb: IO message buffer
3409 */
3410static int mpi_dek_management_resp(struct pm8001_hba_info *pm8001_ha,
3411 void *piomb)
3412{
3413 PM8001_MSG_DBG(pm8001_ha,
3414 pm8001_printk(" pm80xx_addition_functionality\n"));
3415
3416 return 0;
3417}
3418
3419/**
3420 * ssp_coalesced_comp_resp - SPCv specific
3421 * @pm8001_ha: our hba card information
3422 * @piomb: IO message buffer
3423 */
3424static int ssp_coalesced_comp_resp(struct pm8001_hba_info *pm8001_ha,
3425 void *piomb)
3426{
3427 PM8001_MSG_DBG(pm8001_ha,
3428 pm8001_printk(" pm80xx_addition_functionality\n"));
3429
3430 return 0;
3431}
3432
3433/**
3434 * process_one_iomb - process one outbound Queue memory block
3435 * @pm8001_ha: our hba card information
3436 * @piomb: IO message buffer
3437 */
3438static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb)
3439{
3440 __le32 pHeader = *(__le32 *)piomb;
3441 u32 opc = (u32)((le32_to_cpu(pHeader)) & 0xFFF);
3442
3443 switch (opc) {
3444 case OPC_OUB_ECHO:
3445 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO\n"));
3446 break;
3447 case OPC_OUB_HW_EVENT:
3448 PM8001_MSG_DBG(pm8001_ha,
3449 pm8001_printk("OPC_OUB_HW_EVENT\n"));
3450 mpi_hw_event(pm8001_ha, piomb);
3451 break;
3452 case OPC_OUB_THERM_HW_EVENT:
3453 PM8001_MSG_DBG(pm8001_ha,
3454 pm8001_printk("OPC_OUB_THERMAL_EVENT\n"));
3455 mpi_thermal_hw_event(pm8001_ha, piomb);
3456 break;
3457 case OPC_OUB_SSP_COMP:
3458 PM8001_MSG_DBG(pm8001_ha,
3459 pm8001_printk("OPC_OUB_SSP_COMP\n"));
3460 mpi_ssp_completion(pm8001_ha, piomb);
3461 break;
3462 case OPC_OUB_SMP_COMP:
3463 PM8001_MSG_DBG(pm8001_ha,
3464 pm8001_printk("OPC_OUB_SMP_COMP\n"));
3465 mpi_smp_completion(pm8001_ha, piomb);
3466 break;
3467 case OPC_OUB_LOCAL_PHY_CNTRL:
3468 PM8001_MSG_DBG(pm8001_ha,
3469 pm8001_printk("OPC_OUB_LOCAL_PHY_CNTRL\n"));
3470 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb);
3471 break;
3472 case OPC_OUB_DEV_REGIST:
3473 PM8001_MSG_DBG(pm8001_ha,
3474 pm8001_printk("OPC_OUB_DEV_REGIST\n"));
3475 pm8001_mpi_reg_resp(pm8001_ha, piomb);
3476 break;
3477 case OPC_OUB_DEREG_DEV:
3478 PM8001_MSG_DBG(pm8001_ha,
3479 pm8001_printk("unregister the device\n"));
3480 pm8001_mpi_dereg_resp(pm8001_ha, piomb);
3481 break;
3482 case OPC_OUB_GET_DEV_HANDLE:
3483 PM8001_MSG_DBG(pm8001_ha,
3484 pm8001_printk("OPC_OUB_GET_DEV_HANDLE\n"));
3485 break;
3486 case OPC_OUB_SATA_COMP:
3487 PM8001_MSG_DBG(pm8001_ha,
3488 pm8001_printk("OPC_OUB_SATA_COMP\n"));
3489 mpi_sata_completion(pm8001_ha, piomb);
3490 break;
3491 case OPC_OUB_SATA_EVENT:
3492 PM8001_MSG_DBG(pm8001_ha,
3493 pm8001_printk("OPC_OUB_SATA_EVENT\n"));
3494 mpi_sata_event(pm8001_ha, piomb);
3495 break;
3496 case OPC_OUB_SSP_EVENT:
3497 PM8001_MSG_DBG(pm8001_ha,
3498 pm8001_printk("OPC_OUB_SSP_EVENT\n"));
3499 mpi_ssp_event(pm8001_ha, piomb);
3500 break;
3501 case OPC_OUB_DEV_HANDLE_ARRIV:
3502 PM8001_MSG_DBG(pm8001_ha,
3503 pm8001_printk("OPC_OUB_DEV_HANDLE_ARRIV\n"));
3504 /*This is for target*/
3505 break;
3506 case OPC_OUB_SSP_RECV_EVENT:
3507 PM8001_MSG_DBG(pm8001_ha,
3508 pm8001_printk("OPC_OUB_SSP_RECV_EVENT\n"));
3509 /*This is for target*/
3510 break;
3511 case OPC_OUB_FW_FLASH_UPDATE:
3512 PM8001_MSG_DBG(pm8001_ha,
3513 pm8001_printk("OPC_OUB_FW_FLASH_UPDATE\n"));
3514 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb);
3515 break;
3516 case OPC_OUB_GPIO_RESPONSE:
3517 PM8001_MSG_DBG(pm8001_ha,
3518 pm8001_printk("OPC_OUB_GPIO_RESPONSE\n"));
3519 break;
3520 case OPC_OUB_GPIO_EVENT:
3521 PM8001_MSG_DBG(pm8001_ha,
3522 pm8001_printk("OPC_OUB_GPIO_EVENT\n"));
3523 break;
3524 case OPC_OUB_GENERAL_EVENT:
3525 PM8001_MSG_DBG(pm8001_ha,
3526 pm8001_printk("OPC_OUB_GENERAL_EVENT\n"));
3527 pm8001_mpi_general_event(pm8001_ha, piomb);
3528 break;
3529 case OPC_OUB_SSP_ABORT_RSP:
3530 PM8001_MSG_DBG(pm8001_ha,
3531 pm8001_printk("OPC_OUB_SSP_ABORT_RSP\n"));
3532 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3533 break;
3534 case OPC_OUB_SATA_ABORT_RSP:
3535 PM8001_MSG_DBG(pm8001_ha,
3536 pm8001_printk("OPC_OUB_SATA_ABORT_RSP\n"));
3537 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3538 break;
3539 case OPC_OUB_SAS_DIAG_MODE_START_END:
3540 PM8001_MSG_DBG(pm8001_ha,
3541 pm8001_printk("OPC_OUB_SAS_DIAG_MODE_START_END\n"));
3542 break;
3543 case OPC_OUB_SAS_DIAG_EXECUTE:
3544 PM8001_MSG_DBG(pm8001_ha,
3545 pm8001_printk("OPC_OUB_SAS_DIAG_EXECUTE\n"));
3546 break;
3547 case OPC_OUB_GET_TIME_STAMP:
3548 PM8001_MSG_DBG(pm8001_ha,
3549 pm8001_printk("OPC_OUB_GET_TIME_STAMP\n"));
3550 break;
3551 case OPC_OUB_SAS_HW_EVENT_ACK:
3552 PM8001_MSG_DBG(pm8001_ha,
3553 pm8001_printk("OPC_OUB_SAS_HW_EVENT_ACK\n"));
3554 break;
3555 case OPC_OUB_PORT_CONTROL:
3556 PM8001_MSG_DBG(pm8001_ha,
3557 pm8001_printk("OPC_OUB_PORT_CONTROL\n"));
3558 break;
3559 case OPC_OUB_SMP_ABORT_RSP:
3560 PM8001_MSG_DBG(pm8001_ha,
3561 pm8001_printk("OPC_OUB_SMP_ABORT_RSP\n"));
3562 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3563 break;
3564 case OPC_OUB_GET_NVMD_DATA:
3565 PM8001_MSG_DBG(pm8001_ha,
3566 pm8001_printk("OPC_OUB_GET_NVMD_DATA\n"));
3567 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb);
3568 break;
3569 case OPC_OUB_SET_NVMD_DATA:
3570 PM8001_MSG_DBG(pm8001_ha,
3571 pm8001_printk("OPC_OUB_SET_NVMD_DATA\n"));
3572 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb);
3573 break;
3574 case OPC_OUB_DEVICE_HANDLE_REMOVAL:
3575 PM8001_MSG_DBG(pm8001_ha,
3576 pm8001_printk("OPC_OUB_DEVICE_HANDLE_REMOVAL\n"));
3577 break;
3578 case OPC_OUB_SET_DEVICE_STATE:
3579 PM8001_MSG_DBG(pm8001_ha,
3580 pm8001_printk("OPC_OUB_SET_DEVICE_STATE\n"));
3581 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb);
3582 break;
3583 case OPC_OUB_GET_DEVICE_STATE:
3584 PM8001_MSG_DBG(pm8001_ha,
3585 pm8001_printk("OPC_OUB_GET_DEVICE_STATE\n"));
3586 break;
3587 case OPC_OUB_SET_DEV_INFO:
3588 PM8001_MSG_DBG(pm8001_ha,
3589 pm8001_printk("OPC_OUB_SET_DEV_INFO\n"));
3590 break;
3591 /* spcv specifc commands */
3592 case OPC_OUB_PHY_START_RESP:
3593 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3594 "OPC_OUB_PHY_START_RESP opcode:%x\n", opc));
3595 mpi_phy_start_resp(pm8001_ha, piomb);
3596 break;
3597 case OPC_OUB_PHY_STOP_RESP:
3598 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3599 "OPC_OUB_PHY_STOP_RESP opcode:%x\n", opc));
3600 mpi_phy_stop_resp(pm8001_ha, piomb);
3601 break;
3602 case OPC_OUB_SET_CONTROLLER_CONFIG:
3603 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3604 "OPC_OUB_SET_CONTROLLER_CONFIG opcode:%x\n", opc));
3605 mpi_set_controller_config_resp(pm8001_ha, piomb);
3606 break;
3607 case OPC_OUB_GET_CONTROLLER_CONFIG:
3608 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3609 "OPC_OUB_GET_CONTROLLER_CONFIG opcode:%x\n", opc));
3610 mpi_get_controller_config_resp(pm8001_ha, piomb);
3611 break;
3612 case OPC_OUB_GET_PHY_PROFILE:
3613 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3614 "OPC_OUB_GET_PHY_PROFILE opcode:%x\n", opc));
3615 mpi_get_phy_profile_resp(pm8001_ha, piomb);
3616 break;
3617 case OPC_OUB_FLASH_OP_EXT:
3618 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3619 "OPC_OUB_FLASH_OP_EXT opcode:%x\n", opc));
3620 mpi_flash_op_ext_resp(pm8001_ha, piomb);
3621 break;
3622 case OPC_OUB_SET_PHY_PROFILE:
3623 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3624 "OPC_OUB_SET_PHY_PROFILE opcode:%x\n", opc));
3625 mpi_set_phy_profile_resp(pm8001_ha, piomb);
3626 break;
3627 case OPC_OUB_KEK_MANAGEMENT_RESP:
3628 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3629 "OPC_OUB_KEK_MANAGEMENT_RESP opcode:%x\n", opc));
3630 mpi_kek_management_resp(pm8001_ha, piomb);
3631 break;
3632 case OPC_OUB_DEK_MANAGEMENT_RESP:
3633 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3634 "OPC_OUB_DEK_MANAGEMENT_RESP opcode:%x\n", opc));
3635 mpi_dek_management_resp(pm8001_ha, piomb);
3636 break;
3637 case OPC_OUB_SSP_COALESCED_COMP_RESP:
3638 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3639 "OPC_OUB_SSP_COALESCED_COMP_RESP opcode:%x\n", opc));
3640 ssp_coalesced_comp_resp(pm8001_ha, piomb);
3641 break;
3642 default:
3643 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3644 "Unknown outbound Queue IOMB OPC = 0x%x\n", opc));
3645 break;
3646 }
3647}
3648
3649static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec)
3650{
3651 struct outbound_queue_table *circularQ;
3652 void *pMsg1 = NULL;
3653 u8 uninitialized_var(bc);
3654 u32 ret = MPI_IO_STATUS_FAIL;
3655 unsigned long flags;
3656
3657 spin_lock_irqsave(&pm8001_ha->lock, flags);
3658 circularQ = &pm8001_ha->outbnd_q_tbl[vec];
3659 do {
3660 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
3661 if (MPI_IO_STATUS_SUCCESS == ret) {
3662 /* process the outbound message */
3663 process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4));
3664 /* free the message from the outbound circular buffer */
3665 pm8001_mpi_msg_free_set(pm8001_ha, pMsg1,
3666 circularQ, bc);
3667 }
3668 if (MPI_IO_STATUS_BUSY == ret) {
3669 /* Update the producer index from SPC */
3670 circularQ->producer_index =
3671 cpu_to_le32(pm8001_read_32(circularQ->pi_virt));
3672 if (le32_to_cpu(circularQ->producer_index) ==
3673 circularQ->consumer_idx)
3674 /* OQ is empty */
3675 break;
3676 }
3677 } while (1);
3678 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
3679 return ret;
3680}
3681
3682/* PCI_DMA_... to our direction translation. */
3683static const u8 data_dir_flags[] = {
3684 [PCI_DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT,/* UNSPECIFIED */
3685 [PCI_DMA_TODEVICE] = DATA_DIR_OUT,/* OUTBOUND */
3686 [PCI_DMA_FROMDEVICE] = DATA_DIR_IN,/* INBOUND */
3687 [PCI_DMA_NONE] = DATA_DIR_NONE,/* NO TRANSFER */
3688};
3689
3690static void build_smp_cmd(u32 deviceID, __le32 hTag,
3691 struct smp_req *psmp_cmd, int mode, int length)
3692{
3693 psmp_cmd->tag = hTag;
3694 psmp_cmd->device_id = cpu_to_le32(deviceID);
3695 if (mode == SMP_DIRECT) {
3696 length = length - 4; /* subtract crc */
3697 psmp_cmd->len_ip_ir = cpu_to_le32(length << 16);
3698 } else {
3699 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
3700 }
3701}
3702
3703/**
3704 * pm8001_chip_smp_req - send a SMP task to FW
3705 * @pm8001_ha: our hba card information.
3706 * @ccb: the ccb information this request used.
3707 */
3708static int pm80xx_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
3709 struct pm8001_ccb_info *ccb)
3710{
3711 int elem, rc;
3712 struct sas_task *task = ccb->task;
3713 struct domain_device *dev = task->dev;
3714 struct pm8001_device *pm8001_dev = dev->lldd_dev;
3715 struct scatterlist *sg_req, *sg_resp;
3716 u32 req_len, resp_len;
3717 struct smp_req smp_cmd;
3718 u32 opc;
3719 struct inbound_queue_table *circularQ;
3720 char *preq_dma_addr = NULL;
3721 __le64 tmp_addr;
3722 u32 i, length;
3723
3724 memset(&smp_cmd, 0, sizeof(smp_cmd));
3725 /*
3726 * DMA-map SMP request, response buffers
3727 */
3728 sg_req = &task->smp_task.smp_req;
3729 elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, PCI_DMA_TODEVICE);
3730 if (!elem)
3731 return -ENOMEM;
3732 req_len = sg_dma_len(sg_req);
3733
3734 sg_resp = &task->smp_task.smp_resp;
3735 elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, PCI_DMA_FROMDEVICE);
3736 if (!elem) {
3737 rc = -ENOMEM;
3738 goto err_out;
3739 }
3740 resp_len = sg_dma_len(sg_resp);
3741 /* must be in dwords */
3742 if ((req_len & 0x3) || (resp_len & 0x3)) {
3743 rc = -EINVAL;
3744 goto err_out_2;
3745 }
3746
3747 opc = OPC_INB_SMP_REQUEST;
3748 circularQ = &pm8001_ha->inbnd_q_tbl[0];
3749 smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
3750
3751 length = sg_req->length;
3752 PM8001_IO_DBG(pm8001_ha,
3753 pm8001_printk("SMP Frame Length %d\n", sg_req->length));
3754 if (!(length - 8))
3755 pm8001_ha->smp_exp_mode = SMP_DIRECT;
3756 else
3757 pm8001_ha->smp_exp_mode = SMP_INDIRECT;
3758
3759
3760 tmp_addr = cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req));
3761 preq_dma_addr = (char *)phys_to_virt(tmp_addr);
3762
3763 /* INDIRECT MODE command settings. Use DMA */
3764 if (pm8001_ha->smp_exp_mode == SMP_INDIRECT) {
3765 PM8001_IO_DBG(pm8001_ha,
3766 pm8001_printk("SMP REQUEST INDIRECT MODE\n"));
3767 /* for SPCv indirect mode. Place the top 4 bytes of
3768 * SMP Request header here. */
3769 for (i = 0; i < 4; i++)
3770 smp_cmd.smp_req16[i] = *(preq_dma_addr + i);
3771 /* exclude top 4 bytes for SMP req header */
3772 smp_cmd.long_smp_req.long_req_addr =
3773 cpu_to_le64((u64)sg_dma_address
3774 (&task->smp_task.smp_req) + 4);
3775 /* exclude 4 bytes for SMP req header and CRC */
3776 smp_cmd.long_smp_req.long_req_size =
3777 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-8);
3778 smp_cmd.long_smp_req.long_resp_addr =
3779 cpu_to_le64((u64)sg_dma_address
3780 (&task->smp_task.smp_resp));
3781 smp_cmd.long_smp_req.long_resp_size =
3782 cpu_to_le32((u32)sg_dma_len
3783 (&task->smp_task.smp_resp)-4);
3784 } else { /* DIRECT MODE */
3785 smp_cmd.long_smp_req.long_req_addr =
3786 cpu_to_le64((u64)sg_dma_address
3787 (&task->smp_task.smp_req));
3788 smp_cmd.long_smp_req.long_req_size =
3789 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
3790 smp_cmd.long_smp_req.long_resp_addr =
3791 cpu_to_le64((u64)sg_dma_address
3792 (&task->smp_task.smp_resp));
3793 smp_cmd.long_smp_req.long_resp_size =
3794 cpu_to_le32
3795 ((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
3796 }
3797 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
3798 PM8001_IO_DBG(pm8001_ha,
3799 pm8001_printk("SMP REQUEST DIRECT MODE\n"));
3800 for (i = 0; i < length; i++)
3801 if (i < 16) {
3802 smp_cmd.smp_req16[i] = *(preq_dma_addr+i);
3803 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3804 "Byte[%d]:%x (DMA data:%x)\n",
3805 i, smp_cmd.smp_req16[i],
3806 *(preq_dma_addr)));
3807 } else {
3808 smp_cmd.smp_req[i] = *(preq_dma_addr+i);
3809 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3810 "Byte[%d]:%x (DMA data:%x)\n",
3811 i, smp_cmd.smp_req[i],
3812 *(preq_dma_addr)));
3813 }
3814 }
3815
3816 build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag,
3817 &smp_cmd, pm8001_ha->smp_exp_mode, length);
3818 pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, (u32 *)&smp_cmd, 0);
3819 return 0;
3820
3821err_out_2:
3822 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
3823 PCI_DMA_FROMDEVICE);
3824err_out:
3825 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
3826 PCI_DMA_TODEVICE);
3827 return rc;
3828}
3829
3830static int check_enc_sas_cmd(struct sas_task *task)
3831{
3832 u8 cmd = task->ssp_task.cmd->cmnd[0];
3833
3834 if (cmd == READ_10 || cmd == WRITE_10 || cmd == WRITE_VERIFY)
3835 return 1;
3836 else
3837 return 0;
3838}
3839
3840static int check_enc_sat_cmd(struct sas_task *task)
3841{
3842 int ret = 0;
3843 switch (task->ata_task.fis.command) {
3844 case ATA_CMD_FPDMA_READ:
3845 case ATA_CMD_READ_EXT:
3846 case ATA_CMD_READ:
3847 case ATA_CMD_FPDMA_WRITE:
3848 case ATA_CMD_WRITE_EXT:
3849 case ATA_CMD_WRITE:
3850 case ATA_CMD_PIO_READ:
3851 case ATA_CMD_PIO_READ_EXT:
3852 case ATA_CMD_PIO_WRITE:
3853 case ATA_CMD_PIO_WRITE_EXT:
3854 ret = 1;
3855 break;
3856 default:
3857 ret = 0;
3858 break;
3859 }
3860 return ret;
3861}
3862
3863/**
3864 * pm80xx_chip_ssp_io_req - send a SSP task to FW
3865 * @pm8001_ha: our hba card information.
3866 * @ccb: the ccb information this request used.
3867 */
3868static int pm80xx_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
3869 struct pm8001_ccb_info *ccb)
3870{
3871 struct sas_task *task = ccb->task;
3872 struct domain_device *dev = task->dev;
3873 struct pm8001_device *pm8001_dev = dev->lldd_dev;
3874 struct ssp_ini_io_start_req ssp_cmd;
3875 u32 tag = ccb->ccb_tag;
3876 int ret;
3877 u64 phys_addr, start_addr, end_addr;
3878 u32 end_addr_high, end_addr_low;
3879 struct inbound_queue_table *circularQ;
3880 u32 q_index;
3881 u32 opc = OPC_INB_SSPINIIOSTART;
3882 memset(&ssp_cmd, 0, sizeof(ssp_cmd));
3883 memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
3884 /* data address domain added for spcv; set to 0 by host,
3885 * used internally by controller
3886 * 0 for SAS 1.1 and SAS 2.0 compatible TLR
3887 */
3888 ssp_cmd.dad_dir_m_tlr =
3889 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);
3890 ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
3891 ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
3892 ssp_cmd.tag = cpu_to_le32(tag);
3893 if (task->ssp_task.enable_first_burst)
3894 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80;
3895 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
3896 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
3897 memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd,
3898 task->ssp_task.cmd->cmd_len);
3899 q_index = (u32) (pm8001_dev->id & 0x00ffffff) % PM8001_MAX_INB_NUM;
3900 circularQ = &pm8001_ha->inbnd_q_tbl[q_index];
3901
3902 /* Check if encryption is set */
3903 if (pm8001_ha->chip->encrypt &&
3904 !(pm8001_ha->encrypt_info.status) && check_enc_sas_cmd(task)) {
3905 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3906 "Encryption enabled.Sending Encrypt SAS command 0x%x\n",
3907 task->ssp_task.cmd->cmnd[0]));
3908 opc = OPC_INB_SSP_INI_DIF_ENC_IO;
3909 /* enable encryption. 0 for SAS 1.1 and SAS 2.0 compatible TLR*/
3910 ssp_cmd.dad_dir_m_tlr = cpu_to_le32
3911 ((data_dir_flags[task->data_dir] << 8) | 0x20 | 0x0);
3912
3913 /* fill in PRD (scatter/gather) table, if any */
3914 if (task->num_scatter > 1) {
3915 pm8001_chip_make_sg(task->scatter,
3916 ccb->n_elem, ccb->buf_prd);
3917 phys_addr = ccb->ccb_dma_handle +
3918 offsetof(struct pm8001_ccb_info, buf_prd[0]);
3919 ssp_cmd.enc_addr_low =
3920 cpu_to_le32(lower_32_bits(phys_addr));
3921 ssp_cmd.enc_addr_high =
3922 cpu_to_le32(upper_32_bits(phys_addr));
3923 ssp_cmd.enc_esgl = cpu_to_le32(1<<31);
3924 } else if (task->num_scatter == 1) {
3925 u64 dma_addr = sg_dma_address(task->scatter);
3926 ssp_cmd.enc_addr_low =
3927 cpu_to_le32(lower_32_bits(dma_addr));
3928 ssp_cmd.enc_addr_high =
3929 cpu_to_le32(upper_32_bits(dma_addr));
3930 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
3931 ssp_cmd.enc_esgl = 0;
3932 /* Check 4G Boundary */
3933 start_addr = cpu_to_le64(dma_addr);
3934 end_addr = (start_addr + ssp_cmd.enc_len) - 1;
3935 end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
3936 end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
3937 if (end_addr_high != ssp_cmd.enc_addr_high) {
3938 PM8001_FAIL_DBG(pm8001_ha,
3939 pm8001_printk("The sg list address "
3940 "start_addr=0x%016llx data_len=0x%x "
3941 "end_addr_high=0x%08x end_addr_low="
3942 "0x%08x has crossed 4G boundary\n",
3943 start_addr, ssp_cmd.enc_len,
3944 end_addr_high, end_addr_low));
3945 pm8001_chip_make_sg(task->scatter, 1,
3946 ccb->buf_prd);
3947 phys_addr = ccb->ccb_dma_handle +
3948 offsetof(struct pm8001_ccb_info,
3949 buf_prd[0]);
3950 ssp_cmd.enc_addr_low =
3951 cpu_to_le32(lower_32_bits(phys_addr));
3952 ssp_cmd.enc_addr_high =
3953 cpu_to_le32(upper_32_bits(phys_addr));
3954 ssp_cmd.enc_esgl = cpu_to_le32(1<<31);
3955 }
3956 } else if (task->num_scatter == 0) {
3957 ssp_cmd.enc_addr_low = 0;
3958 ssp_cmd.enc_addr_high = 0;
3959 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
3960 ssp_cmd.enc_esgl = 0;
3961 }
3962 /* XTS mode. All other fields are 0 */
3963 ssp_cmd.key_cmode = 0x6 << 4;
3964 /* set tweak values. Should be the start lba */
3965 ssp_cmd.twk_val0 = cpu_to_le32((task->ssp_task.cmd->cmnd[2] << 24) |
3966 (task->ssp_task.cmd->cmnd[3] << 16) |
3967 (task->ssp_task.cmd->cmnd[4] << 8) |
3968 (task->ssp_task.cmd->cmnd[5]));
3969 } else {
3970 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3971 "Sending Normal SAS command 0x%x inb q %x\n",
3972 task->ssp_task.cmd->cmnd[0], q_index));
3973 /* fill in PRD (scatter/gather) table, if any */
3974 if (task->num_scatter > 1) {
3975 pm8001_chip_make_sg(task->scatter, ccb->n_elem,
3976 ccb->buf_prd);
3977 phys_addr = ccb->ccb_dma_handle +
3978 offsetof(struct pm8001_ccb_info, buf_prd[0]);
3979 ssp_cmd.addr_low =
3980 cpu_to_le32(lower_32_bits(phys_addr));
3981 ssp_cmd.addr_high =
3982 cpu_to_le32(upper_32_bits(phys_addr));
3983 ssp_cmd.esgl = cpu_to_le32(1<<31);
3984 } else if (task->num_scatter == 1) {
3985 u64 dma_addr = sg_dma_address(task->scatter);
3986 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr));
3987 ssp_cmd.addr_high =
3988 cpu_to_le32(upper_32_bits(dma_addr));
3989 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
3990 ssp_cmd.esgl = 0;
3991 /* Check 4G Boundary */
3992 start_addr = cpu_to_le64(dma_addr);
3993 end_addr = (start_addr + ssp_cmd.len) - 1;
3994 end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
3995 end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
3996 if (end_addr_high != ssp_cmd.addr_high) {
3997 PM8001_FAIL_DBG(pm8001_ha,
3998 pm8001_printk("The sg list address "
3999 "start_addr=0x%016llx data_len=0x%x "
4000 "end_addr_high=0x%08x end_addr_low="
4001 "0x%08x has crossed 4G boundary\n",
4002 start_addr, ssp_cmd.len,
4003 end_addr_high, end_addr_low));
4004 pm8001_chip_make_sg(task->scatter, 1,
4005 ccb->buf_prd);
4006 phys_addr = ccb->ccb_dma_handle +
4007 offsetof(struct pm8001_ccb_info,
4008 buf_prd[0]);
4009 ssp_cmd.addr_low =
4010 cpu_to_le32(lower_32_bits(phys_addr));
4011 ssp_cmd.addr_high =
4012 cpu_to_le32(upper_32_bits(phys_addr));
4013 ssp_cmd.esgl = cpu_to_le32(1<<31);
4014 }
4015 } else if (task->num_scatter == 0) {
4016 ssp_cmd.addr_low = 0;
4017 ssp_cmd.addr_high = 0;
4018 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4019 ssp_cmd.esgl = 0;
4020 }
4021 }
4022 q_index = (u32) (pm8001_dev->id & 0x00ffffff) % PM8001_MAX_OUTB_NUM;
4023 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
4024 &ssp_cmd, q_index);
4025 return ret;
4026}
4027
4028static int pm80xx_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
4029 struct pm8001_ccb_info *ccb)
4030{
4031 struct sas_task *task = ccb->task;
4032 struct domain_device *dev = task->dev;
4033 struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
4034 u32 tag = ccb->ccb_tag;
4035 int ret;
4036 u32 q_index;
4037 struct sata_start_req sata_cmd;
4038 u32 hdr_tag, ncg_tag = 0;
4039 u64 phys_addr, start_addr, end_addr;
4040 u32 end_addr_high, end_addr_low;
4041 u32 ATAP = 0x0;
4042 u32 dir;
4043 struct inbound_queue_table *circularQ;
4044 unsigned long flags;
4045 u32 opc = OPC_INB_SATA_HOST_OPSTART;
4046 memset(&sata_cmd, 0, sizeof(sata_cmd));
4047 q_index = (u32) (pm8001_ha_dev->id & 0x00ffffff) % PM8001_MAX_INB_NUM;
4048 circularQ = &pm8001_ha->inbnd_q_tbl[q_index];
4049
4050 if (task->data_dir == PCI_DMA_NONE) {
4051 ATAP = 0x04; /* no data*/
4052 PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data\n"));
4053 } else if (likely(!task->ata_task.device_control_reg_update)) {
4054 if (task->ata_task.dma_xfer) {
4055 ATAP = 0x06; /* DMA */
4056 PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA\n"));
4057 } else {
4058 ATAP = 0x05; /* PIO*/
4059 PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO\n"));
4060 }
4061 if (task->ata_task.use_ncq &&
4062 dev->sata_dev.command_set != ATAPI_COMMAND_SET) {
4063 ATAP = 0x07; /* FPDMA */
4064 PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA\n"));
4065 }
4066 }
4067 if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) {
4068 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
4069 ncg_tag = hdr_tag;
4070 }
4071 dir = data_dir_flags[task->data_dir] << 8;
4072 sata_cmd.tag = cpu_to_le32(tag);
4073 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
4074 sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4075
4076 sata_cmd.sata_fis = task->ata_task.fis;
4077 if (likely(!task->ata_task.device_control_reg_update))
4078 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
4079 sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
4080
4081 /* Check if encryption is set */
4082 if (pm8001_ha->chip->encrypt &&
4083 !(pm8001_ha->encrypt_info.status) && check_enc_sat_cmd(task)) {
4084 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4085 "Encryption enabled.Sending Encrypt SATA cmd 0x%x\n",
4086 sata_cmd.sata_fis.command));
4087 opc = OPC_INB_SATA_DIF_ENC_IO;
4088
4089 /* set encryption bit */
4090 sata_cmd.ncqtag_atap_dir_m_dad =
4091 cpu_to_le32(((ncg_tag & 0xff)<<16)|
4092 ((ATAP & 0x3f) << 10) | 0x20 | dir);
4093 /* dad (bit 0-1) is 0 */
4094 /* fill in PRD (scatter/gather) table, if any */
4095 if (task->num_scatter > 1) {
4096 pm8001_chip_make_sg(task->scatter,
4097 ccb->n_elem, ccb->buf_prd);
4098 phys_addr = ccb->ccb_dma_handle +
4099 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4100 sata_cmd.enc_addr_low = lower_32_bits(phys_addr);
4101 sata_cmd.enc_addr_high = upper_32_bits(phys_addr);
4102 sata_cmd.enc_esgl = cpu_to_le32(1 << 31);
4103 } else if (task->num_scatter == 1) {
4104 u64 dma_addr = sg_dma_address(task->scatter);
4105 sata_cmd.enc_addr_low = lower_32_bits(dma_addr);
4106 sata_cmd.enc_addr_high = upper_32_bits(dma_addr);
4107 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4108 sata_cmd.enc_esgl = 0;
4109 /* Check 4G Boundary */
4110 start_addr = cpu_to_le64(dma_addr);
4111 end_addr = (start_addr + sata_cmd.enc_len) - 1;
4112 end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4113 end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4114 if (end_addr_high != sata_cmd.enc_addr_high) {
4115 PM8001_FAIL_DBG(pm8001_ha,
4116 pm8001_printk("The sg list address "
4117 "start_addr=0x%016llx data_len=0x%x "
4118 "end_addr_high=0x%08x end_addr_low"
4119 "=0x%08x has crossed 4G boundary\n",
4120 start_addr, sata_cmd.enc_len,
4121 end_addr_high, end_addr_low));
4122 pm8001_chip_make_sg(task->scatter, 1,
4123 ccb->buf_prd);
4124 phys_addr = ccb->ccb_dma_handle +
4125 offsetof(struct pm8001_ccb_info,
4126 buf_prd[0]);
4127 sata_cmd.enc_addr_low =
4128 lower_32_bits(phys_addr);
4129 sata_cmd.enc_addr_high =
4130 upper_32_bits(phys_addr);
4131 sata_cmd.enc_esgl =
4132 cpu_to_le32(1 << 31);
4133 }
4134 } else if (task->num_scatter == 0) {
4135 sata_cmd.enc_addr_low = 0;
4136 sata_cmd.enc_addr_high = 0;
4137 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4138 sata_cmd.enc_esgl = 0;
4139 }
4140 /* XTS mode. All other fields are 0 */
4141 sata_cmd.key_index_mode = 0x6 << 4;
4142 /* set tweak values. Should be the start lba */
4143 sata_cmd.twk_val0 =
4144 cpu_to_le32((sata_cmd.sata_fis.lbal_exp << 24) |
4145 (sata_cmd.sata_fis.lbah << 16) |
4146 (sata_cmd.sata_fis.lbam << 8) |
4147 (sata_cmd.sata_fis.lbal));
4148 sata_cmd.twk_val1 =
4149 cpu_to_le32((sata_cmd.sata_fis.lbah_exp << 8) |
4150 (sata_cmd.sata_fis.lbam_exp));
4151 } else {
4152 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4153 "Sending Normal SATA command 0x%x inb %x\n",
4154 sata_cmd.sata_fis.command, q_index));
4155 /* dad (bit 0-1) is 0 */
4156 sata_cmd.ncqtag_atap_dir_m_dad =
4157 cpu_to_le32(((ncg_tag & 0xff)<<16) |
4158 ((ATAP & 0x3f) << 10) | dir);
4159
4160 /* fill in PRD (scatter/gather) table, if any */
4161 if (task->num_scatter > 1) {
4162 pm8001_chip_make_sg(task->scatter,
4163 ccb->n_elem, ccb->buf_prd);
4164 phys_addr = ccb->ccb_dma_handle +
4165 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4166 sata_cmd.addr_low = lower_32_bits(phys_addr);
4167 sata_cmd.addr_high = upper_32_bits(phys_addr);
4168 sata_cmd.esgl = cpu_to_le32(1 << 31);
4169 } else if (task->num_scatter == 1) {
4170 u64 dma_addr = sg_dma_address(task->scatter);
4171 sata_cmd.addr_low = lower_32_bits(dma_addr);
4172 sata_cmd.addr_high = upper_32_bits(dma_addr);
4173 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4174 sata_cmd.esgl = 0;
4175 /* Check 4G Boundary */
4176 start_addr = cpu_to_le64(dma_addr);
4177 end_addr = (start_addr + sata_cmd.len) - 1;
4178 end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4179 end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4180 if (end_addr_high != sata_cmd.addr_high) {
4181 PM8001_FAIL_DBG(pm8001_ha,
4182 pm8001_printk("The sg list address "
4183 "start_addr=0x%016llx data_len=0x%x"
4184 "end_addr_high=0x%08x end_addr_low="
4185 "0x%08x has crossed 4G boundary\n",
4186 start_addr, sata_cmd.len,
4187 end_addr_high, end_addr_low));
4188 pm8001_chip_make_sg(task->scatter, 1,
4189 ccb->buf_prd);
4190 phys_addr = ccb->ccb_dma_handle +
4191 offsetof(struct pm8001_ccb_info,
4192 buf_prd[0]);
4193 sata_cmd.addr_low =
4194 lower_32_bits(phys_addr);
4195 sata_cmd.addr_high =
4196 upper_32_bits(phys_addr);
4197 sata_cmd.esgl = cpu_to_le32(1 << 31);
4198 }
4199 } else if (task->num_scatter == 0) {
4200 sata_cmd.addr_low = 0;
4201 sata_cmd.addr_high = 0;
4202 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4203 sata_cmd.esgl = 0;
4204 }
4205 /* scsi cdb */
4206 sata_cmd.atapi_scsi_cdb[0] =
4207 cpu_to_le32(((task->ata_task.atapi_packet[0]) |
4208 (task->ata_task.atapi_packet[1] << 8) |
4209 (task->ata_task.atapi_packet[2] << 16) |
4210 (task->ata_task.atapi_packet[3] << 24)));
4211 sata_cmd.atapi_scsi_cdb[1] =
4212 cpu_to_le32(((task->ata_task.atapi_packet[4]) |
4213 (task->ata_task.atapi_packet[5] << 8) |
4214 (task->ata_task.atapi_packet[6] << 16) |
4215 (task->ata_task.atapi_packet[7] << 24)));
4216 sata_cmd.atapi_scsi_cdb[2] =
4217 cpu_to_le32(((task->ata_task.atapi_packet[8]) |
4218 (task->ata_task.atapi_packet[9] << 8) |
4219 (task->ata_task.atapi_packet[10] << 16) |
4220 (task->ata_task.atapi_packet[11] << 24)));
4221 sata_cmd.atapi_scsi_cdb[3] =
4222 cpu_to_le32(((task->ata_task.atapi_packet[12]) |
4223 (task->ata_task.atapi_packet[13] << 8) |
4224 (task->ata_task.atapi_packet[14] << 16) |
4225 (task->ata_task.atapi_packet[15] << 24)));
4226 }
4227
4228 /* Check for read log for failed drive and return */
4229 if (sata_cmd.sata_fis.command == 0x2f) {
4230 if (pm8001_ha_dev && ((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) ||
4231 (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) ||
4232 (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) {
4233 struct task_status_struct *ts;
4234
4235 pm8001_ha_dev->id &= 0xDFFFFFFF;
4236 ts = &task->task_status;
4237
4238 spin_lock_irqsave(&task->task_state_lock, flags);
4239 ts->resp = SAS_TASK_COMPLETE;
4240 ts->stat = SAM_STAT_GOOD;
4241 task->task_state_flags &= ~SAS_TASK_STATE_PENDING;
4242 task->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
4243 task->task_state_flags |= SAS_TASK_STATE_DONE;
4244 if (unlikely((task->task_state_flags &
4245 SAS_TASK_STATE_ABORTED))) {
4246 spin_unlock_irqrestore(&task->task_state_lock,
4247 flags);
4248 PM8001_FAIL_DBG(pm8001_ha,
4249 pm8001_printk("task 0x%p resp 0x%x "
4250 " stat 0x%x but aborted by upper layer "
4251 "\n", task, ts->resp, ts->stat));
4252 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
4253 return 0;
4254 } else {
4255 spin_unlock_irqrestore(&task->task_state_lock,
4256 flags);
4257 pm8001_ccb_task_free_done(pm8001_ha, task,
4258 ccb, tag);
4259 return 0;
4260 }
4261 }
4262 }
4263 q_index = (u32) (pm8001_ha_dev->id & 0x00ffffff) % PM8001_MAX_OUTB_NUM;
4264 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
4265 &sata_cmd, q_index);
4266 return ret;
4267}
4268
4269/**
4270 * pm80xx_chip_phy_start_req - start phy via PHY_START COMMAND
4271 * @pm8001_ha: our hba card information.
4272 * @num: the inbound queue number
4273 * @phy_id: the phy id which we wanted to start up.
4274 */
4275static int
4276pm80xx_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
4277{
4278 struct phy_start_req payload;
4279 struct inbound_queue_table *circularQ;
4280 int ret;
4281 u32 tag = 0x01;
4282 u32 opcode = OPC_INB_PHYSTART;
4283 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4284 memset(&payload, 0, sizeof(payload));
4285 payload.tag = cpu_to_le32(tag);
4286
4287 PM8001_INIT_DBG(pm8001_ha,
4288 pm8001_printk("PHY START REQ for phy_id %d\n", phy_id));
4289 /*
4290 ** [0:7] PHY Identifier
4291 ** [8:11] link rate 1.5G, 3G, 6G
4292 ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b Auto mode
4293 ** [14] 0b disable spin up hold; 1b enable spin up hold
4294 ** [15] ob no change in current PHY analig setup 1b enable using SPAST
4295 */
4296 if (!IS_SPCV_12G(pm8001_ha->pdev))
4297 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4298 LINKMODE_AUTO | LINKRATE_15 |
4299 LINKRATE_30 | LINKRATE_60 | phy_id);
4300 else
4301 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4302 LINKMODE_AUTO | LINKRATE_15 |
4303 LINKRATE_30 | LINKRATE_60 | LINKRATE_120 |
4304 phy_id);
4305
4306 /* SSC Disable and SAS Analog ST configuration */
4307 /**
4308 payload.ase_sh_lm_slr_phyid =
4309 cpu_to_le32(SSC_DISABLE_30 | SAS_ASE | SPINHOLD_DISABLE |
4310 LINKMODE_AUTO | LINKRATE_15 | LINKRATE_30 | LINKRATE_60 |
4311 phy_id);
4312 Have to add "SAS PHY Analog Setup SPASTI 1 Byte" Based on need
4313 **/
4314
4315 payload.sas_identify.dev_type = SAS_END_DEVICE;
4316 payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
4317 memcpy(payload.sas_identify.sas_addr,
4318 pm8001_ha->sas_addr, SAS_ADDR_SIZE);
4319 payload.sas_identify.phy_id = phy_id;
4320 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0);
4321 return ret;
4322}
4323
4324/**
4325 * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND
4326 * @pm8001_ha: our hba card information.
4327 * @num: the inbound queue number
4328 * @phy_id: the phy id which we wanted to start up.
4329 */
4330static int pm80xx_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
4331 u8 phy_id)
4332{
4333 struct phy_stop_req payload;
4334 struct inbound_queue_table *circularQ;
4335 int ret;
4336 u32 tag = 0x01;
4337 u32 opcode = OPC_INB_PHYSTOP;
4338 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4339 memset(&payload, 0, sizeof(payload));
4340 payload.tag = cpu_to_le32(tag);
4341 payload.phy_id = cpu_to_le32(phy_id);
4342 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0);
4343 return ret;
4344}
4345
4346/**
4347 * see comments on pm8001_mpi_reg_resp.
4348 */
4349static int pm80xx_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
4350 struct pm8001_device *pm8001_dev, u32 flag)
4351{
4352 struct reg_dev_req payload;
4353 u32 opc;
4354 u32 stp_sspsmp_sata = 0x4;
4355 struct inbound_queue_table *circularQ;
4356 u32 linkrate, phy_id;
4357 int rc, tag = 0xdeadbeef;
4358 struct pm8001_ccb_info *ccb;
4359 u8 retryFlag = 0x1;
4360 u16 firstBurstSize = 0;
4361 u16 ITNT = 2000;
4362 struct domain_device *dev = pm8001_dev->sas_device;
4363 struct domain_device *parent_dev = dev->parent;
4364 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4365
4366 memset(&payload, 0, sizeof(payload));
4367 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4368 if (rc)
4369 return rc;
4370 ccb = &pm8001_ha->ccb_info[tag];
4371 ccb->device = pm8001_dev;
4372 ccb->ccb_tag = tag;
4373 payload.tag = cpu_to_le32(tag);
4374
4375 if (flag == 1) {
4376 stp_sspsmp_sata = 0x02; /*direct attached sata */
4377 } else {
4378 if (pm8001_dev->dev_type == SAS_SATA_DEV)
4379 stp_sspsmp_sata = 0x00; /* stp*/
4380 else if (pm8001_dev->dev_type == SAS_END_DEVICE ||
4381 pm8001_dev->dev_type == SAS_EDGE_EXPANDER_DEVICE ||
4382 pm8001_dev->dev_type == SAS_FANOUT_EXPANDER_DEVICE)
4383 stp_sspsmp_sata = 0x01; /*ssp or smp*/
4384 }
4385 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
4386 phy_id = parent_dev->ex_dev.ex_phy->phy_id;
4387 else
4388 phy_id = pm8001_dev->attached_phy;
4389
4390 opc = OPC_INB_REG_DEV;
4391
4392 linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
4393 pm8001_dev->sas_device->linkrate : dev->port->linkrate;
4394
4395 payload.phyid_portid =
4396 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0xFF) |
4397 ((phy_id & 0xFF) << 8));
4398
4399 payload.dtype_dlr_mcn_ir_retry = cpu_to_le32((retryFlag & 0x01) |
4400 ((linkrate & 0x0F) << 24) |
4401 ((stp_sspsmp_sata & 0x03) << 28));
4402 payload.firstburstsize_ITNexustimeout =
4403 cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
4404
4405 memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
4406 SAS_ADDR_SIZE);
4407
4408 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4409
4410 return rc;
4411}
4412
4413/**
4414 * pm80xx_chip_phy_ctl_req - support the local phy operation
4415 * @pm8001_ha: our hba card information.
4416 * @num: the inbound queue number
4417 * @phy_id: the phy id which we wanted to operate
4418 * @phy_op:
4419 */
4420static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
4421 u32 phyId, u32 phy_op)
4422{
4423 struct local_phy_ctl_req payload;
4424 struct inbound_queue_table *circularQ;
4425 int ret;
4426 u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
4427 memset(&payload, 0, sizeof(payload));
4428 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4429 payload.tag = cpu_to_le32(1);
4430 payload.phyop_phyid =
4431 cpu_to_le32(((phy_op & 0xFF) << 8) | (phyId & 0xFF));
4432 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4433 return ret;
4434}
4435
4436static u32 pm80xx_chip_is_our_interupt(struct pm8001_hba_info *pm8001_ha)
4437{
4438 u32 value;
4439#ifdef PM8001_USE_MSIX
4440 return 1;
4441#endif
4442 value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
4443 if (value)
4444 return 1;
4445 return 0;
4446
4447}
4448
4449/**
4450 * pm8001_chip_isr - PM8001 isr handler.
4451 * @pm8001_ha: our hba card information.
4452 * @irq: irq number.
4453 * @stat: stat.
4454 */
4455static irqreturn_t
4456pm80xx_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec)
4457{
4458 pm80xx_chip_interrupt_disable(pm8001_ha, vec);
4459 process_oq(pm8001_ha, vec);
4460 pm80xx_chip_interrupt_enable(pm8001_ha, vec);
4461 return IRQ_HANDLED;
4462}
4463
4464void mpi_set_phy_profile_req(struct pm8001_hba_info *pm8001_ha,
4465 u32 operation, u32 phyid, u32 length, u32 *buf)
4466{
4467 u32 tag , i, j = 0;
4468 int rc;
4469 struct set_phy_profile_req payload;
4470 struct inbound_queue_table *circularQ;
4471 u32 opc = OPC_INB_SET_PHY_PROFILE;
4472
4473 memset(&payload, 0, sizeof(payload));
4474 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4475 if (rc)
4476 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("Invalid tag\n"));
4477 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4478 payload.tag = cpu_to_le32(tag);
4479 payload.ppc_phyid = (((operation & 0xF) << 8) | (phyid & 0xFF));
4480 PM8001_INIT_DBG(pm8001_ha,
4481 pm8001_printk(" phy profile command for phy %x ,length is %d\n",
4482 payload.ppc_phyid, length));
4483 for (i = length; i < (length + PHY_DWORD_LENGTH - 1); i++) {
4484 payload.reserved[j] = cpu_to_le32(*((u32 *)buf + i));
4485 j++;
4486 }
4487 pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4488}
4489
4490void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha,
4491 u32 length, u8 *buf)
4492{
4493 u32 page_code, i;
4494
4495 page_code = SAS_PHY_ANALOG_SETTINGS_PAGE;
4496 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
4497 mpi_set_phy_profile_req(pm8001_ha,
4498 SAS_PHY_ANALOG_SETTINGS_PAGE, i, length, (u32 *)buf);
4499 length = length + PHY_DWORD_LENGTH;
4500 }
4501 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("phy settings completed\n"));
4502}
4503const struct pm8001_dispatch pm8001_80xx_dispatch = {
4504 .name = "pmc80xx",
4505 .chip_init = pm80xx_chip_init,
4506 .chip_soft_rst = pm80xx_chip_soft_rst,
4507 .chip_rst = pm80xx_hw_chip_rst,
4508 .chip_iounmap = pm8001_chip_iounmap,
4509 .isr = pm80xx_chip_isr,
4510 .is_our_interupt = pm80xx_chip_is_our_interupt,
4511 .isr_process_oq = process_oq,
4512 .interrupt_enable = pm80xx_chip_interrupt_enable,
4513 .interrupt_disable = pm80xx_chip_interrupt_disable,
4514 .make_prd = pm8001_chip_make_sg,
4515 .smp_req = pm80xx_chip_smp_req,
4516 .ssp_io_req = pm80xx_chip_ssp_io_req,
4517 .sata_req = pm80xx_chip_sata_req,
4518 .phy_start_req = pm80xx_chip_phy_start_req,
4519 .phy_stop_req = pm80xx_chip_phy_stop_req,
4520 .reg_dev_req = pm80xx_chip_reg_dev_req,
4521 .dereg_dev_req = pm8001_chip_dereg_dev_req,
4522 .phy_ctl_req = pm80xx_chip_phy_ctl_req,
4523 .task_abort = pm8001_chip_abort_task,
4524 .ssp_tm_req = pm8001_chip_ssp_tm_req,
4525 .get_nvmd_req = pm8001_chip_get_nvmd_req,
4526 .set_nvmd_req = pm8001_chip_set_nvmd_req,
4527 .fw_flash_update_req = pm8001_chip_fw_flash_update_req,
4528 .set_dev_state_req = pm8001_chip_set_dev_state_req,
4529};