Loading...
1/*
2 * Copyright (c) 2009-2010 Intel Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc.,
15 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
16 *
17 * The full GNU General Public License is included in this distribution in
18 * the file called "COPYING".
19 *
20 * Authors:
21 * Jesse Barnes <jbarnes@virtuousgeek.org>
22 */
23
24/*
25 * Some Intel Ibex Peak based platforms support so-called "intelligent
26 * power sharing", which allows the CPU and GPU to cooperate to maximize
27 * performance within a given TDP (thermal design point). This driver
28 * performs the coordination between the CPU and GPU, monitors thermal and
29 * power statistics in the platform, and initializes power monitoring
30 * hardware. It also provides a few tunables to control behavior. Its
31 * primary purpose is to safely allow CPU and GPU turbo modes to be enabled
32 * by tracking power and thermal budget; secondarily it can boost turbo
33 * performance by allocating more power or thermal budget to the CPU or GPU
34 * based on available headroom and activity.
35 *
36 * The basic algorithm is driven by a 5s moving average of tempurature. If
37 * thermal headroom is available, the CPU and/or GPU power clamps may be
38 * adjusted upwards. If we hit the thermal ceiling or a thermal trigger,
39 * we scale back the clamp. Aside from trigger events (when we're critically
40 * close or over our TDP) we don't adjust the clamps more than once every
41 * five seconds.
42 *
43 * The thermal device (device 31, function 6) has a set of registers that
44 * are updated by the ME firmware. The ME should also take the clamp values
45 * written to those registers and write them to the CPU, but we currently
46 * bypass that functionality and write the CPU MSR directly.
47 *
48 * UNSUPPORTED:
49 * - dual MCP configs
50 *
51 * TODO:
52 * - handle CPU hotplug
53 * - provide turbo enable/disable api
54 *
55 * Related documents:
56 * - CDI 403777, 403778 - Auburndale EDS vol 1 & 2
57 * - CDI 401376 - Ibex Peak EDS
58 * - ref 26037, 26641 - IPS BIOS spec
59 * - ref 26489 - Nehalem BIOS writer's guide
60 * - ref 26921 - Ibex Peak BIOS Specification
61 */
62
63#include <linux/debugfs.h>
64#include <linux/delay.h>
65#include <linux/interrupt.h>
66#include <linux/kernel.h>
67#include <linux/kthread.h>
68#include <linux/module.h>
69#include <linux/pci.h>
70#include <linux/sched.h>
71#include <linux/seq_file.h>
72#include <linux/string.h>
73#include <linux/tick.h>
74#include <linux/timer.h>
75#include <drm/i915_drm.h>
76#include <asm/msr.h>
77#include <asm/processor.h>
78#include "intel_ips.h"
79
80#define PCI_DEVICE_ID_INTEL_THERMAL_SENSOR 0x3b32
81
82/*
83 * Package level MSRs for monitor/control
84 */
85#define PLATFORM_INFO 0xce
86#define PLATFORM_TDP (1<<29)
87#define PLATFORM_RATIO (1<<28)
88
89#define IA32_MISC_ENABLE 0x1a0
90#define IA32_MISC_TURBO_EN (1ULL<<38)
91
92#define TURBO_POWER_CURRENT_LIMIT 0x1ac
93#define TURBO_TDC_OVR_EN (1UL<<31)
94#define TURBO_TDC_MASK (0x000000007fff0000UL)
95#define TURBO_TDC_SHIFT (16)
96#define TURBO_TDP_OVR_EN (1UL<<15)
97#define TURBO_TDP_MASK (0x0000000000003fffUL)
98
99/*
100 * Core/thread MSRs for monitoring
101 */
102#define IA32_PERF_CTL 0x199
103#define IA32_PERF_TURBO_DIS (1ULL<<32)
104
105/*
106 * Thermal PCI device regs
107 */
108#define THM_CFG_TBAR 0x10
109#define THM_CFG_TBAR_HI 0x14
110
111#define THM_TSIU 0x00
112#define THM_TSE 0x01
113#define TSE_EN 0xb8
114#define THM_TSS 0x02
115#define THM_TSTR 0x03
116#define THM_TSTTP 0x04
117#define THM_TSCO 0x08
118#define THM_TSES 0x0c
119#define THM_TSGPEN 0x0d
120#define TSGPEN_HOT_LOHI (1<<1)
121#define TSGPEN_CRIT_LOHI (1<<2)
122#define THM_TSPC 0x0e
123#define THM_PPEC 0x10
124#define THM_CTA 0x12
125#define THM_PTA 0x14
126#define PTA_SLOPE_MASK (0xff00)
127#define PTA_SLOPE_SHIFT 8
128#define PTA_OFFSET_MASK (0x00ff)
129#define THM_MGTA 0x16
130#define MGTA_SLOPE_MASK (0xff00)
131#define MGTA_SLOPE_SHIFT 8
132#define MGTA_OFFSET_MASK (0x00ff)
133#define THM_TRC 0x1a
134#define TRC_CORE2_EN (1<<15)
135#define TRC_THM_EN (1<<12)
136#define TRC_C6_WAR (1<<8)
137#define TRC_CORE1_EN (1<<7)
138#define TRC_CORE_PWR (1<<6)
139#define TRC_PCH_EN (1<<5)
140#define TRC_MCH_EN (1<<4)
141#define TRC_DIMM4 (1<<3)
142#define TRC_DIMM3 (1<<2)
143#define TRC_DIMM2 (1<<1)
144#define TRC_DIMM1 (1<<0)
145#define THM_TES 0x20
146#define THM_TEN 0x21
147#define TEN_UPDATE_EN 1
148#define THM_PSC 0x24
149#define PSC_NTG (1<<0) /* No GFX turbo support */
150#define PSC_NTPC (1<<1) /* No CPU turbo support */
151#define PSC_PP_DEF (0<<2) /* Perf policy up to driver */
152#define PSP_PP_PC (1<<2) /* BIOS prefers CPU perf */
153#define PSP_PP_BAL (2<<2) /* BIOS wants balanced perf */
154#define PSP_PP_GFX (3<<2) /* BIOS prefers GFX perf */
155#define PSP_PBRT (1<<4) /* BIOS run time support */
156#define THM_CTV1 0x30
157#define CTV_TEMP_ERROR (1<<15)
158#define CTV_TEMP_MASK 0x3f
159#define CTV_
160#define THM_CTV2 0x32
161#define THM_CEC 0x34 /* undocumented power accumulator in joules */
162#define THM_AE 0x3f
163#define THM_HTS 0x50 /* 32 bits */
164#define HTS_PCPL_MASK (0x7fe00000)
165#define HTS_PCPL_SHIFT 21
166#define HTS_GPL_MASK (0x001ff000)
167#define HTS_GPL_SHIFT 12
168#define HTS_PP_MASK (0x00000c00)
169#define HTS_PP_SHIFT 10
170#define HTS_PP_DEF 0
171#define HTS_PP_PROC 1
172#define HTS_PP_BAL 2
173#define HTS_PP_GFX 3
174#define HTS_PCTD_DIS (1<<9)
175#define HTS_GTD_DIS (1<<8)
176#define HTS_PTL_MASK (0x000000fe)
177#define HTS_PTL_SHIFT 1
178#define HTS_NVV (1<<0)
179#define THM_HTSHI 0x54 /* 16 bits */
180#define HTS2_PPL_MASK (0x03ff)
181#define HTS2_PRST_MASK (0x3c00)
182#define HTS2_PRST_SHIFT 10
183#define HTS2_PRST_UNLOADED 0
184#define HTS2_PRST_RUNNING 1
185#define HTS2_PRST_TDISOP 2 /* turbo disabled due to power */
186#define HTS2_PRST_TDISHT 3 /* turbo disabled due to high temp */
187#define HTS2_PRST_TDISUSR 4 /* user disabled turbo */
188#define HTS2_PRST_TDISPLAT 5 /* platform disabled turbo */
189#define HTS2_PRST_TDISPM 6 /* power management disabled turbo */
190#define HTS2_PRST_TDISERR 7 /* some kind of error disabled turbo */
191#define THM_PTL 0x56
192#define THM_MGTV 0x58
193#define TV_MASK 0x000000000000ff00
194#define TV_SHIFT 8
195#define THM_PTV 0x60
196#define PTV_MASK 0x00ff
197#define THM_MMGPC 0x64
198#define THM_MPPC 0x66
199#define THM_MPCPC 0x68
200#define THM_TSPIEN 0x82
201#define TSPIEN_AUX_LOHI (1<<0)
202#define TSPIEN_HOT_LOHI (1<<1)
203#define TSPIEN_CRIT_LOHI (1<<2)
204#define TSPIEN_AUX2_LOHI (1<<3)
205#define THM_TSLOCK 0x83
206#define THM_ATR 0x84
207#define THM_TOF 0x87
208#define THM_STS 0x98
209#define STS_PCPL_MASK (0x7fe00000)
210#define STS_PCPL_SHIFT 21
211#define STS_GPL_MASK (0x001ff000)
212#define STS_GPL_SHIFT 12
213#define STS_PP_MASK (0x00000c00)
214#define STS_PP_SHIFT 10
215#define STS_PP_DEF 0
216#define STS_PP_PROC 1
217#define STS_PP_BAL 2
218#define STS_PP_GFX 3
219#define STS_PCTD_DIS (1<<9)
220#define STS_GTD_DIS (1<<8)
221#define STS_PTL_MASK (0x000000fe)
222#define STS_PTL_SHIFT 1
223#define STS_NVV (1<<0)
224#define THM_SEC 0x9c
225#define SEC_ACK (1<<0)
226#define THM_TC3 0xa4
227#define THM_TC1 0xa8
228#define STS_PPL_MASK (0x0003ff00)
229#define STS_PPL_SHIFT 16
230#define THM_TC2 0xac
231#define THM_DTV 0xb0
232#define THM_ITV 0xd8
233#define ITV_ME_SEQNO_MASK 0x00ff0000 /* ME should update every ~200ms */
234#define ITV_ME_SEQNO_SHIFT (16)
235#define ITV_MCH_TEMP_MASK 0x0000ff00
236#define ITV_MCH_TEMP_SHIFT (8)
237#define ITV_PCH_TEMP_MASK 0x000000ff
238
239#define thm_readb(off) readb(ips->regmap + (off))
240#define thm_readw(off) readw(ips->regmap + (off))
241#define thm_readl(off) readl(ips->regmap + (off))
242#define thm_readq(off) readq(ips->regmap + (off))
243
244#define thm_writeb(off, val) writeb((val), ips->regmap + (off))
245#define thm_writew(off, val) writew((val), ips->regmap + (off))
246#define thm_writel(off, val) writel((val), ips->regmap + (off))
247
248static const int IPS_ADJUST_PERIOD = 5000; /* ms */
249static bool late_i915_load = false;
250
251/* For initial average collection */
252static const int IPS_SAMPLE_PERIOD = 200; /* ms */
253static const int IPS_SAMPLE_WINDOW = 5000; /* 5s moving window of samples */
254#define IPS_SAMPLE_COUNT (IPS_SAMPLE_WINDOW / IPS_SAMPLE_PERIOD)
255
256/* Per-SKU limits */
257struct ips_mcp_limits {
258 int cpu_family;
259 int cpu_model; /* includes extended model... */
260 int mcp_power_limit; /* mW units */
261 int core_power_limit;
262 int mch_power_limit;
263 int core_temp_limit; /* degrees C */
264 int mch_temp_limit;
265};
266
267/* Max temps are -10 degrees C to avoid PROCHOT# */
268
269struct ips_mcp_limits ips_sv_limits = {
270 .mcp_power_limit = 35000,
271 .core_power_limit = 29000,
272 .mch_power_limit = 20000,
273 .core_temp_limit = 95,
274 .mch_temp_limit = 90
275};
276
277struct ips_mcp_limits ips_lv_limits = {
278 .mcp_power_limit = 25000,
279 .core_power_limit = 21000,
280 .mch_power_limit = 13000,
281 .core_temp_limit = 95,
282 .mch_temp_limit = 90
283};
284
285struct ips_mcp_limits ips_ulv_limits = {
286 .mcp_power_limit = 18000,
287 .core_power_limit = 14000,
288 .mch_power_limit = 11000,
289 .core_temp_limit = 95,
290 .mch_temp_limit = 90
291};
292
293struct ips_driver {
294 struct pci_dev *dev;
295 void *regmap;
296 struct task_struct *monitor;
297 struct task_struct *adjust;
298 struct dentry *debug_root;
299
300 /* Average CPU core temps (all averages in .01 degrees C for precision) */
301 u16 ctv1_avg_temp;
302 u16 ctv2_avg_temp;
303 /* GMCH average */
304 u16 mch_avg_temp;
305 /* Average for the CPU (both cores?) */
306 u16 mcp_avg_temp;
307 /* Average power consumption (in mW) */
308 u32 cpu_avg_power;
309 u32 mch_avg_power;
310
311 /* Offset values */
312 u16 cta_val;
313 u16 pta_val;
314 u16 mgta_val;
315
316 /* Maximums & prefs, protected by turbo status lock */
317 spinlock_t turbo_status_lock;
318 u16 mcp_temp_limit;
319 u16 mcp_power_limit;
320 u16 core_power_limit;
321 u16 mch_power_limit;
322 bool cpu_turbo_enabled;
323 bool __cpu_turbo_on;
324 bool gpu_turbo_enabled;
325 bool __gpu_turbo_on;
326 bool gpu_preferred;
327 bool poll_turbo_status;
328 bool second_cpu;
329 bool turbo_toggle_allowed;
330 struct ips_mcp_limits *limits;
331
332 /* Optional MCH interfaces for if i915 is in use */
333 unsigned long (*read_mch_val)(void);
334 bool (*gpu_raise)(void);
335 bool (*gpu_lower)(void);
336 bool (*gpu_busy)(void);
337 bool (*gpu_turbo_disable)(void);
338
339 /* For restoration at unload */
340 u64 orig_turbo_limit;
341 u64 orig_turbo_ratios;
342};
343
344static bool
345ips_gpu_turbo_enabled(struct ips_driver *ips);
346
347#ifndef readq
348static inline __u64 readq(const volatile void __iomem *addr)
349{
350 const volatile u32 __iomem *p = addr;
351 u32 low, high;
352
353 low = readl(p);
354 high = readl(p + 1);
355
356 return low + ((u64)high << 32);
357}
358#endif
359
360/**
361 * ips_cpu_busy - is CPU busy?
362 * @ips: IPS driver struct
363 *
364 * Check CPU for load to see whether we should increase its thermal budget.
365 *
366 * RETURNS:
367 * True if the CPU could use more power, false otherwise.
368 */
369static bool ips_cpu_busy(struct ips_driver *ips)
370{
371 if ((avenrun[0] >> FSHIFT) > 1)
372 return true;
373
374 return false;
375}
376
377/**
378 * ips_cpu_raise - raise CPU power clamp
379 * @ips: IPS driver struct
380 *
381 * Raise the CPU power clamp by %IPS_CPU_STEP, in accordance with TDP for
382 * this platform.
383 *
384 * We do this by adjusting the TURBO_POWER_CURRENT_LIMIT MSR upwards (as
385 * long as we haven't hit the TDP limit for the SKU).
386 */
387static void ips_cpu_raise(struct ips_driver *ips)
388{
389 u64 turbo_override;
390 u16 cur_tdp_limit, new_tdp_limit;
391
392 if (!ips->cpu_turbo_enabled)
393 return;
394
395 rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override);
396
397 cur_tdp_limit = turbo_override & TURBO_TDP_MASK;
398 new_tdp_limit = cur_tdp_limit + 8; /* 1W increase */
399
400 /* Clamp to SKU TDP limit */
401 if (((new_tdp_limit * 10) / 8) > ips->core_power_limit)
402 new_tdp_limit = cur_tdp_limit;
403
404 thm_writew(THM_MPCPC, (new_tdp_limit * 10) / 8);
405
406 turbo_override |= TURBO_TDC_OVR_EN | TURBO_TDP_OVR_EN;
407 wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override);
408
409 turbo_override &= ~TURBO_TDP_MASK;
410 turbo_override |= new_tdp_limit;
411
412 wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override);
413}
414
415/**
416 * ips_cpu_lower - lower CPU power clamp
417 * @ips: IPS driver struct
418 *
419 * Lower CPU power clamp b %IPS_CPU_STEP if possible.
420 *
421 * We do this by adjusting the TURBO_POWER_CURRENT_LIMIT MSR down, going
422 * as low as the platform limits will allow (though we could go lower there
423 * wouldn't be much point).
424 */
425static void ips_cpu_lower(struct ips_driver *ips)
426{
427 u64 turbo_override;
428 u16 cur_limit, new_limit;
429
430 rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override);
431
432 cur_limit = turbo_override & TURBO_TDP_MASK;
433 new_limit = cur_limit - 8; /* 1W decrease */
434
435 /* Clamp to SKU TDP limit */
436 if (new_limit < (ips->orig_turbo_limit & TURBO_TDP_MASK))
437 new_limit = ips->orig_turbo_limit & TURBO_TDP_MASK;
438
439 thm_writew(THM_MPCPC, (new_limit * 10) / 8);
440
441 turbo_override |= TURBO_TDC_OVR_EN | TURBO_TDP_OVR_EN;
442 wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override);
443
444 turbo_override &= ~TURBO_TDP_MASK;
445 turbo_override |= new_limit;
446
447 wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override);
448}
449
450/**
451 * do_enable_cpu_turbo - internal turbo enable function
452 * @data: unused
453 *
454 * Internal function for actually updating MSRs. When we enable/disable
455 * turbo, we need to do it on each CPU; this function is the one called
456 * by on_each_cpu() when needed.
457 */
458static void do_enable_cpu_turbo(void *data)
459{
460 u64 perf_ctl;
461
462 rdmsrl(IA32_PERF_CTL, perf_ctl);
463 if (perf_ctl & IA32_PERF_TURBO_DIS) {
464 perf_ctl &= ~IA32_PERF_TURBO_DIS;
465 wrmsrl(IA32_PERF_CTL, perf_ctl);
466 }
467}
468
469/**
470 * ips_enable_cpu_turbo - enable turbo mode on all CPUs
471 * @ips: IPS driver struct
472 *
473 * Enable turbo mode by clearing the disable bit in IA32_PERF_CTL on
474 * all logical threads.
475 */
476static void ips_enable_cpu_turbo(struct ips_driver *ips)
477{
478 /* Already on, no need to mess with MSRs */
479 if (ips->__cpu_turbo_on)
480 return;
481
482 if (ips->turbo_toggle_allowed)
483 on_each_cpu(do_enable_cpu_turbo, ips, 1);
484
485 ips->__cpu_turbo_on = true;
486}
487
488/**
489 * do_disable_cpu_turbo - internal turbo disable function
490 * @data: unused
491 *
492 * Internal function for actually updating MSRs. When we enable/disable
493 * turbo, we need to do it on each CPU; this function is the one called
494 * by on_each_cpu() when needed.
495 */
496static void do_disable_cpu_turbo(void *data)
497{
498 u64 perf_ctl;
499
500 rdmsrl(IA32_PERF_CTL, perf_ctl);
501 if (!(perf_ctl & IA32_PERF_TURBO_DIS)) {
502 perf_ctl |= IA32_PERF_TURBO_DIS;
503 wrmsrl(IA32_PERF_CTL, perf_ctl);
504 }
505}
506
507/**
508 * ips_disable_cpu_turbo - disable turbo mode on all CPUs
509 * @ips: IPS driver struct
510 *
511 * Disable turbo mode by setting the disable bit in IA32_PERF_CTL on
512 * all logical threads.
513 */
514static void ips_disable_cpu_turbo(struct ips_driver *ips)
515{
516 /* Already off, leave it */
517 if (!ips->__cpu_turbo_on)
518 return;
519
520 if (ips->turbo_toggle_allowed)
521 on_each_cpu(do_disable_cpu_turbo, ips, 1);
522
523 ips->__cpu_turbo_on = false;
524}
525
526/**
527 * ips_gpu_busy - is GPU busy?
528 * @ips: IPS driver struct
529 *
530 * Check GPU for load to see whether we should increase its thermal budget.
531 * We need to call into the i915 driver in this case.
532 *
533 * RETURNS:
534 * True if the GPU could use more power, false otherwise.
535 */
536static bool ips_gpu_busy(struct ips_driver *ips)
537{
538 if (!ips_gpu_turbo_enabled(ips))
539 return false;
540
541 return ips->gpu_busy();
542}
543
544/**
545 * ips_gpu_raise - raise GPU power clamp
546 * @ips: IPS driver struct
547 *
548 * Raise the GPU frequency/power if possible. We need to call into the
549 * i915 driver in this case.
550 */
551static void ips_gpu_raise(struct ips_driver *ips)
552{
553 if (!ips_gpu_turbo_enabled(ips))
554 return;
555
556 if (!ips->gpu_raise())
557 ips->gpu_turbo_enabled = false;
558
559 return;
560}
561
562/**
563 * ips_gpu_lower - lower GPU power clamp
564 * @ips: IPS driver struct
565 *
566 * Lower GPU frequency/power if possible. Need to call i915.
567 */
568static void ips_gpu_lower(struct ips_driver *ips)
569{
570 if (!ips_gpu_turbo_enabled(ips))
571 return;
572
573 if (!ips->gpu_lower())
574 ips->gpu_turbo_enabled = false;
575
576 return;
577}
578
579/**
580 * ips_enable_gpu_turbo - notify the gfx driver turbo is available
581 * @ips: IPS driver struct
582 *
583 * Call into the graphics driver indicating that it can safely use
584 * turbo mode.
585 */
586static void ips_enable_gpu_turbo(struct ips_driver *ips)
587{
588 if (ips->__gpu_turbo_on)
589 return;
590 ips->__gpu_turbo_on = true;
591}
592
593/**
594 * ips_disable_gpu_turbo - notify the gfx driver to disable turbo mode
595 * @ips: IPS driver struct
596 *
597 * Request that the graphics driver disable turbo mode.
598 */
599static void ips_disable_gpu_turbo(struct ips_driver *ips)
600{
601 /* Avoid calling i915 if turbo is already disabled */
602 if (!ips->__gpu_turbo_on)
603 return;
604
605 if (!ips->gpu_turbo_disable())
606 dev_err(&ips->dev->dev, "failed to disable graphis turbo\n");
607 else
608 ips->__gpu_turbo_on = false;
609}
610
611/**
612 * mcp_exceeded - check whether we're outside our thermal & power limits
613 * @ips: IPS driver struct
614 *
615 * Check whether the MCP is over its thermal or power budget.
616 */
617static bool mcp_exceeded(struct ips_driver *ips)
618{
619 unsigned long flags;
620 bool ret = false;
621 u32 temp_limit;
622 u32 avg_power;
623 const char *msg = "MCP limit exceeded: ";
624
625 spin_lock_irqsave(&ips->turbo_status_lock, flags);
626
627 temp_limit = ips->mcp_temp_limit * 100;
628 if (ips->mcp_avg_temp > temp_limit) {
629 dev_info(&ips->dev->dev,
630 "%sAvg temp %u, limit %u\n", msg, ips->mcp_avg_temp,
631 temp_limit);
632 ret = true;
633 }
634
635 avg_power = ips->cpu_avg_power + ips->mch_avg_power;
636 if (avg_power > ips->mcp_power_limit) {
637 dev_info(&ips->dev->dev,
638 "%sAvg power %u, limit %u\n", msg, avg_power,
639 ips->mcp_power_limit);
640 ret = true;
641 }
642
643 spin_unlock_irqrestore(&ips->turbo_status_lock, flags);
644
645 return ret;
646}
647
648/**
649 * cpu_exceeded - check whether a CPU core is outside its limits
650 * @ips: IPS driver struct
651 * @cpu: CPU number to check
652 *
653 * Check a given CPU's average temp or power is over its limit.
654 */
655static bool cpu_exceeded(struct ips_driver *ips, int cpu)
656{
657 unsigned long flags;
658 int avg;
659 bool ret = false;
660
661 spin_lock_irqsave(&ips->turbo_status_lock, flags);
662 avg = cpu ? ips->ctv2_avg_temp : ips->ctv1_avg_temp;
663 if (avg > (ips->limits->core_temp_limit * 100))
664 ret = true;
665 if (ips->cpu_avg_power > ips->core_power_limit * 100)
666 ret = true;
667 spin_unlock_irqrestore(&ips->turbo_status_lock, flags);
668
669 if (ret)
670 dev_info(&ips->dev->dev,
671 "CPU power or thermal limit exceeded\n");
672
673 return ret;
674}
675
676/**
677 * mch_exceeded - check whether the GPU is over budget
678 * @ips: IPS driver struct
679 *
680 * Check the MCH temp & power against their maximums.
681 */
682static bool mch_exceeded(struct ips_driver *ips)
683{
684 unsigned long flags;
685 bool ret = false;
686
687 spin_lock_irqsave(&ips->turbo_status_lock, flags);
688 if (ips->mch_avg_temp > (ips->limits->mch_temp_limit * 100))
689 ret = true;
690 if (ips->mch_avg_power > ips->mch_power_limit)
691 ret = true;
692 spin_unlock_irqrestore(&ips->turbo_status_lock, flags);
693
694 return ret;
695}
696
697/**
698 * verify_limits - verify BIOS provided limits
699 * @ips: IPS structure
700 *
701 * BIOS can optionally provide non-default limits for power and temp. Check
702 * them here and use the defaults if the BIOS values are not provided or
703 * are otherwise unusable.
704 */
705static void verify_limits(struct ips_driver *ips)
706{
707 if (ips->mcp_power_limit < ips->limits->mcp_power_limit ||
708 ips->mcp_power_limit > 35000)
709 ips->mcp_power_limit = ips->limits->mcp_power_limit;
710
711 if (ips->mcp_temp_limit < ips->limits->core_temp_limit ||
712 ips->mcp_temp_limit < ips->limits->mch_temp_limit ||
713 ips->mcp_temp_limit > 150)
714 ips->mcp_temp_limit = min(ips->limits->core_temp_limit,
715 ips->limits->mch_temp_limit);
716}
717
718/**
719 * update_turbo_limits - get various limits & settings from regs
720 * @ips: IPS driver struct
721 *
722 * Update the IPS power & temp limits, along with turbo enable flags,
723 * based on latest register contents.
724 *
725 * Used at init time and for runtime BIOS support, which requires polling
726 * the regs for updates (as a result of AC->DC transition for example).
727 *
728 * LOCKING:
729 * Caller must hold turbo_status_lock (outside of init)
730 */
731static void update_turbo_limits(struct ips_driver *ips)
732{
733 u32 hts = thm_readl(THM_HTS);
734
735 ips->cpu_turbo_enabled = !(hts & HTS_PCTD_DIS);
736 /*
737 * Disable turbo for now, until we can figure out why the power figures
738 * are wrong
739 */
740 ips->cpu_turbo_enabled = false;
741
742 if (ips->gpu_busy)
743 ips->gpu_turbo_enabled = !(hts & HTS_GTD_DIS);
744
745 ips->core_power_limit = thm_readw(THM_MPCPC);
746 ips->mch_power_limit = thm_readw(THM_MMGPC);
747 ips->mcp_temp_limit = thm_readw(THM_PTL);
748 ips->mcp_power_limit = thm_readw(THM_MPPC);
749
750 verify_limits(ips);
751 /* Ignore BIOS CPU vs GPU pref */
752}
753
754/**
755 * ips_adjust - adjust power clamp based on thermal state
756 * @data: ips driver structure
757 *
758 * Wake up every 5s or so and check whether we should adjust the power clamp.
759 * Check CPU and GPU load to determine which needs adjustment. There are
760 * several things to consider here:
761 * - do we need to adjust up or down?
762 * - is CPU busy?
763 * - is GPU busy?
764 * - is CPU in turbo?
765 * - is GPU in turbo?
766 * - is CPU or GPU preferred? (CPU is default)
767 *
768 * So, given the above, we do the following:
769 * - up (TDP available)
770 * - CPU not busy, GPU not busy - nothing
771 * - CPU busy, GPU not busy - adjust CPU up
772 * - CPU not busy, GPU busy - adjust GPU up
773 * - CPU busy, GPU busy - adjust preferred unit up, taking headroom from
774 * non-preferred unit if necessary
775 * - down (at TDP limit)
776 * - adjust both CPU and GPU down if possible
777 *
778 cpu+ gpu+ cpu+gpu- cpu-gpu+ cpu-gpu-
779cpu < gpu < cpu+gpu+ cpu+ gpu+ nothing
780cpu < gpu >= cpu+gpu-(mcp<) cpu+gpu-(mcp<) gpu- gpu-
781cpu >= gpu < cpu-gpu+(mcp<) cpu- cpu-gpu+(mcp<) cpu-
782cpu >= gpu >= cpu-gpu- cpu-gpu- cpu-gpu- cpu-gpu-
783 *
784 */
785static int ips_adjust(void *data)
786{
787 struct ips_driver *ips = data;
788 unsigned long flags;
789
790 dev_dbg(&ips->dev->dev, "starting ips-adjust thread\n");
791
792 /*
793 * Adjust CPU and GPU clamps every 5s if needed. Doing it more
794 * often isn't recommended due to ME interaction.
795 */
796 do {
797 bool cpu_busy = ips_cpu_busy(ips);
798 bool gpu_busy = ips_gpu_busy(ips);
799
800 spin_lock_irqsave(&ips->turbo_status_lock, flags);
801 if (ips->poll_turbo_status)
802 update_turbo_limits(ips);
803 spin_unlock_irqrestore(&ips->turbo_status_lock, flags);
804
805 /* Update turbo status if necessary */
806 if (ips->cpu_turbo_enabled)
807 ips_enable_cpu_turbo(ips);
808 else
809 ips_disable_cpu_turbo(ips);
810
811 if (ips->gpu_turbo_enabled)
812 ips_enable_gpu_turbo(ips);
813 else
814 ips_disable_gpu_turbo(ips);
815
816 /* We're outside our comfort zone, crank them down */
817 if (mcp_exceeded(ips)) {
818 ips_cpu_lower(ips);
819 ips_gpu_lower(ips);
820 goto sleep;
821 }
822
823 if (!cpu_exceeded(ips, 0) && cpu_busy)
824 ips_cpu_raise(ips);
825 else
826 ips_cpu_lower(ips);
827
828 if (!mch_exceeded(ips) && gpu_busy)
829 ips_gpu_raise(ips);
830 else
831 ips_gpu_lower(ips);
832
833sleep:
834 schedule_timeout_interruptible(msecs_to_jiffies(IPS_ADJUST_PERIOD));
835 } while (!kthread_should_stop());
836
837 dev_dbg(&ips->dev->dev, "ips-adjust thread stopped\n");
838
839 return 0;
840}
841
842/*
843 * Helpers for reading out temp/power values and calculating their
844 * averages for the decision making and monitoring functions.
845 */
846
847static u16 calc_avg_temp(struct ips_driver *ips, u16 *array)
848{
849 u64 total = 0;
850 int i;
851 u16 avg;
852
853 for (i = 0; i < IPS_SAMPLE_COUNT; i++)
854 total += (u64)(array[i] * 100);
855
856 do_div(total, IPS_SAMPLE_COUNT);
857
858 avg = (u16)total;
859
860 return avg;
861}
862
863static u16 read_mgtv(struct ips_driver *ips)
864{
865 u16 ret;
866 u64 slope, offset;
867 u64 val;
868
869 val = thm_readq(THM_MGTV);
870 val = (val & TV_MASK) >> TV_SHIFT;
871
872 slope = offset = thm_readw(THM_MGTA);
873 slope = (slope & MGTA_SLOPE_MASK) >> MGTA_SLOPE_SHIFT;
874 offset = offset & MGTA_OFFSET_MASK;
875
876 ret = ((val * slope + 0x40) >> 7) + offset;
877
878 return 0; /* MCH temp reporting buggy */
879}
880
881static u16 read_ptv(struct ips_driver *ips)
882{
883 u16 val, slope, offset;
884
885 slope = (ips->pta_val & PTA_SLOPE_MASK) >> PTA_SLOPE_SHIFT;
886 offset = ips->pta_val & PTA_OFFSET_MASK;
887
888 val = thm_readw(THM_PTV) & PTV_MASK;
889
890 return val;
891}
892
893static u16 read_ctv(struct ips_driver *ips, int cpu)
894{
895 int reg = cpu ? THM_CTV2 : THM_CTV1;
896 u16 val;
897
898 val = thm_readw(reg);
899 if (!(val & CTV_TEMP_ERROR))
900 val = (val) >> 6; /* discard fractional component */
901 else
902 val = 0;
903
904 return val;
905}
906
907static u32 get_cpu_power(struct ips_driver *ips, u32 *last, int period)
908{
909 u32 val;
910 u32 ret;
911
912 /*
913 * CEC is in joules/65535. Take difference over time to
914 * get watts.
915 */
916 val = thm_readl(THM_CEC);
917
918 /* period is in ms and we want mW */
919 ret = (((val - *last) * 1000) / period);
920 ret = (ret * 1000) / 65535;
921 *last = val;
922
923 return 0;
924}
925
926static const u16 temp_decay_factor = 2;
927static u16 update_average_temp(u16 avg, u16 val)
928{
929 u16 ret;
930
931 /* Multiply by 100 for extra precision */
932 ret = (val * 100 / temp_decay_factor) +
933 (((temp_decay_factor - 1) * avg) / temp_decay_factor);
934 return ret;
935}
936
937static const u16 power_decay_factor = 2;
938static u16 update_average_power(u32 avg, u32 val)
939{
940 u32 ret;
941
942 ret = (val / power_decay_factor) +
943 (((power_decay_factor - 1) * avg) / power_decay_factor);
944
945 return ret;
946}
947
948static u32 calc_avg_power(struct ips_driver *ips, u32 *array)
949{
950 u64 total = 0;
951 u32 avg;
952 int i;
953
954 for (i = 0; i < IPS_SAMPLE_COUNT; i++)
955 total += array[i];
956
957 do_div(total, IPS_SAMPLE_COUNT);
958 avg = (u32)total;
959
960 return avg;
961}
962
963static void monitor_timeout(unsigned long arg)
964{
965 wake_up_process((struct task_struct *)arg);
966}
967
968/**
969 * ips_monitor - temp/power monitoring thread
970 * @data: ips driver structure
971 *
972 * This is the main function for the IPS driver. It monitors power and
973 * tempurature in the MCP and adjusts CPU and GPU power clams accordingly.
974 *
975 * We keep a 5s moving average of power consumption and tempurature. Using
976 * that data, along with CPU vs GPU preference, we adjust the power clamps
977 * up or down.
978 */
979static int ips_monitor(void *data)
980{
981 struct ips_driver *ips = data;
982 struct timer_list timer;
983 unsigned long seqno_timestamp, expire, last_msecs, last_sample_period;
984 int i;
985 u32 *cpu_samples, *mchp_samples, old_cpu_power;
986 u16 *mcp_samples, *ctv1_samples, *ctv2_samples, *mch_samples;
987 u8 cur_seqno, last_seqno;
988
989 mcp_samples = kzalloc(sizeof(u16) * IPS_SAMPLE_COUNT, GFP_KERNEL);
990 ctv1_samples = kzalloc(sizeof(u16) * IPS_SAMPLE_COUNT, GFP_KERNEL);
991 ctv2_samples = kzalloc(sizeof(u16) * IPS_SAMPLE_COUNT, GFP_KERNEL);
992 mch_samples = kzalloc(sizeof(u16) * IPS_SAMPLE_COUNT, GFP_KERNEL);
993 cpu_samples = kzalloc(sizeof(u32) * IPS_SAMPLE_COUNT, GFP_KERNEL);
994 mchp_samples = kzalloc(sizeof(u32) * IPS_SAMPLE_COUNT, GFP_KERNEL);
995 if (!mcp_samples || !ctv1_samples || !ctv2_samples || !mch_samples ||
996 !cpu_samples || !mchp_samples) {
997 dev_err(&ips->dev->dev,
998 "failed to allocate sample array, ips disabled\n");
999 kfree(mcp_samples);
1000 kfree(ctv1_samples);
1001 kfree(ctv2_samples);
1002 kfree(mch_samples);
1003 kfree(cpu_samples);
1004 kfree(mchp_samples);
1005 return -ENOMEM;
1006 }
1007
1008 last_seqno = (thm_readl(THM_ITV) & ITV_ME_SEQNO_MASK) >>
1009 ITV_ME_SEQNO_SHIFT;
1010 seqno_timestamp = get_jiffies_64();
1011
1012 old_cpu_power = thm_readl(THM_CEC);
1013 schedule_timeout_interruptible(msecs_to_jiffies(IPS_SAMPLE_PERIOD));
1014
1015 /* Collect an initial average */
1016 for (i = 0; i < IPS_SAMPLE_COUNT; i++) {
1017 u32 mchp, cpu_power;
1018 u16 val;
1019
1020 mcp_samples[i] = read_ptv(ips);
1021
1022 val = read_ctv(ips, 0);
1023 ctv1_samples[i] = val;
1024
1025 val = read_ctv(ips, 1);
1026 ctv2_samples[i] = val;
1027
1028 val = read_mgtv(ips);
1029 mch_samples[i] = val;
1030
1031 cpu_power = get_cpu_power(ips, &old_cpu_power,
1032 IPS_SAMPLE_PERIOD);
1033 cpu_samples[i] = cpu_power;
1034
1035 if (ips->read_mch_val) {
1036 mchp = ips->read_mch_val();
1037 mchp_samples[i] = mchp;
1038 }
1039
1040 schedule_timeout_interruptible(msecs_to_jiffies(IPS_SAMPLE_PERIOD));
1041 if (kthread_should_stop())
1042 break;
1043 }
1044
1045 ips->mcp_avg_temp = calc_avg_temp(ips, mcp_samples);
1046 ips->ctv1_avg_temp = calc_avg_temp(ips, ctv1_samples);
1047 ips->ctv2_avg_temp = calc_avg_temp(ips, ctv2_samples);
1048 ips->mch_avg_temp = calc_avg_temp(ips, mch_samples);
1049 ips->cpu_avg_power = calc_avg_power(ips, cpu_samples);
1050 ips->mch_avg_power = calc_avg_power(ips, mchp_samples);
1051 kfree(mcp_samples);
1052 kfree(ctv1_samples);
1053 kfree(ctv2_samples);
1054 kfree(mch_samples);
1055 kfree(cpu_samples);
1056 kfree(mchp_samples);
1057
1058 /* Start the adjustment thread now that we have data */
1059 wake_up_process(ips->adjust);
1060
1061 /*
1062 * Ok, now we have an initial avg. From here on out, we track the
1063 * running avg using a decaying average calculation. This allows
1064 * us to reduce the sample frequency if the CPU and GPU are idle.
1065 */
1066 old_cpu_power = thm_readl(THM_CEC);
1067 schedule_timeout_interruptible(msecs_to_jiffies(IPS_SAMPLE_PERIOD));
1068 last_sample_period = IPS_SAMPLE_PERIOD;
1069
1070 setup_deferrable_timer_on_stack(&timer, monitor_timeout,
1071 (unsigned long)current);
1072 do {
1073 u32 cpu_val, mch_val;
1074 u16 val;
1075
1076 /* MCP itself */
1077 val = read_ptv(ips);
1078 ips->mcp_avg_temp = update_average_temp(ips->mcp_avg_temp, val);
1079
1080 /* Processor 0 */
1081 val = read_ctv(ips, 0);
1082 ips->ctv1_avg_temp =
1083 update_average_temp(ips->ctv1_avg_temp, val);
1084 /* Power */
1085 cpu_val = get_cpu_power(ips, &old_cpu_power,
1086 last_sample_period);
1087 ips->cpu_avg_power =
1088 update_average_power(ips->cpu_avg_power, cpu_val);
1089
1090 if (ips->second_cpu) {
1091 /* Processor 1 */
1092 val = read_ctv(ips, 1);
1093 ips->ctv2_avg_temp =
1094 update_average_temp(ips->ctv2_avg_temp, val);
1095 }
1096
1097 /* MCH */
1098 val = read_mgtv(ips);
1099 ips->mch_avg_temp = update_average_temp(ips->mch_avg_temp, val);
1100 /* Power */
1101 if (ips->read_mch_val) {
1102 mch_val = ips->read_mch_val();
1103 ips->mch_avg_power =
1104 update_average_power(ips->mch_avg_power,
1105 mch_val);
1106 }
1107
1108 /*
1109 * Make sure ME is updating thermal regs.
1110 * Note:
1111 * If it's been more than a second since the last update,
1112 * the ME is probably hung.
1113 */
1114 cur_seqno = (thm_readl(THM_ITV) & ITV_ME_SEQNO_MASK) >>
1115 ITV_ME_SEQNO_SHIFT;
1116 if (cur_seqno == last_seqno &&
1117 time_after(jiffies, seqno_timestamp + HZ)) {
1118 dev_warn(&ips->dev->dev, "ME failed to update for more than 1s, likely hung\n");
1119 } else {
1120 seqno_timestamp = get_jiffies_64();
1121 last_seqno = cur_seqno;
1122 }
1123
1124 last_msecs = jiffies_to_msecs(jiffies);
1125 expire = jiffies + msecs_to_jiffies(IPS_SAMPLE_PERIOD);
1126
1127 __set_current_state(TASK_INTERRUPTIBLE);
1128 mod_timer(&timer, expire);
1129 schedule();
1130
1131 /* Calculate actual sample period for power averaging */
1132 last_sample_period = jiffies_to_msecs(jiffies) - last_msecs;
1133 if (!last_sample_period)
1134 last_sample_period = 1;
1135 } while (!kthread_should_stop());
1136
1137 del_timer_sync(&timer);
1138 destroy_timer_on_stack(&timer);
1139
1140 dev_dbg(&ips->dev->dev, "ips-monitor thread stopped\n");
1141
1142 return 0;
1143}
1144
1145#if 0
1146#define THM_DUMPW(reg) \
1147 { \
1148 u16 val = thm_readw(reg); \
1149 dev_dbg(&ips->dev->dev, #reg ": 0x%04x\n", val); \
1150 }
1151#define THM_DUMPL(reg) \
1152 { \
1153 u32 val = thm_readl(reg); \
1154 dev_dbg(&ips->dev->dev, #reg ": 0x%08x\n", val); \
1155 }
1156#define THM_DUMPQ(reg) \
1157 { \
1158 u64 val = thm_readq(reg); \
1159 dev_dbg(&ips->dev->dev, #reg ": 0x%016x\n", val); \
1160 }
1161
1162static void dump_thermal_info(struct ips_driver *ips)
1163{
1164 u16 ptl;
1165
1166 ptl = thm_readw(THM_PTL);
1167 dev_dbg(&ips->dev->dev, "Processor temp limit: %d\n", ptl);
1168
1169 THM_DUMPW(THM_CTA);
1170 THM_DUMPW(THM_TRC);
1171 THM_DUMPW(THM_CTV1);
1172 THM_DUMPL(THM_STS);
1173 THM_DUMPW(THM_PTV);
1174 THM_DUMPQ(THM_MGTV);
1175}
1176#endif
1177
1178/**
1179 * ips_irq_handler - handle temperature triggers and other IPS events
1180 * @irq: irq number
1181 * @arg: unused
1182 *
1183 * Handle temperature limit trigger events, generally by lowering the clamps.
1184 * If we're at a critical limit, we clamp back to the lowest possible value
1185 * to prevent emergency shutdown.
1186 */
1187static irqreturn_t ips_irq_handler(int irq, void *arg)
1188{
1189 struct ips_driver *ips = arg;
1190 u8 tses = thm_readb(THM_TSES);
1191 u8 tes = thm_readb(THM_TES);
1192
1193 if (!tses && !tes)
1194 return IRQ_NONE;
1195
1196 dev_info(&ips->dev->dev, "TSES: 0x%02x\n", tses);
1197 dev_info(&ips->dev->dev, "TES: 0x%02x\n", tes);
1198
1199 /* STS update from EC? */
1200 if (tes & 1) {
1201 u32 sts, tc1;
1202
1203 sts = thm_readl(THM_STS);
1204 tc1 = thm_readl(THM_TC1);
1205
1206 if (sts & STS_NVV) {
1207 spin_lock(&ips->turbo_status_lock);
1208 ips->core_power_limit = (sts & STS_PCPL_MASK) >>
1209 STS_PCPL_SHIFT;
1210 ips->mch_power_limit = (sts & STS_GPL_MASK) >>
1211 STS_GPL_SHIFT;
1212 /* ignore EC CPU vs GPU pref */
1213 ips->cpu_turbo_enabled = !(sts & STS_PCTD_DIS);
1214 /*
1215 * Disable turbo for now, until we can figure
1216 * out why the power figures are wrong
1217 */
1218 ips->cpu_turbo_enabled = false;
1219 if (ips->gpu_busy)
1220 ips->gpu_turbo_enabled = !(sts & STS_GTD_DIS);
1221 ips->mcp_temp_limit = (sts & STS_PTL_MASK) >>
1222 STS_PTL_SHIFT;
1223 ips->mcp_power_limit = (tc1 & STS_PPL_MASK) >>
1224 STS_PPL_SHIFT;
1225 verify_limits(ips);
1226 spin_unlock(&ips->turbo_status_lock);
1227
1228 thm_writeb(THM_SEC, SEC_ACK);
1229 }
1230 thm_writeb(THM_TES, tes);
1231 }
1232
1233 /* Thermal trip */
1234 if (tses) {
1235 dev_warn(&ips->dev->dev,
1236 "thermal trip occurred, tses: 0x%04x\n", tses);
1237 thm_writeb(THM_TSES, tses);
1238 }
1239
1240 return IRQ_HANDLED;
1241}
1242
1243#ifndef CONFIG_DEBUG_FS
1244static void ips_debugfs_init(struct ips_driver *ips) { return; }
1245static void ips_debugfs_cleanup(struct ips_driver *ips) { return; }
1246#else
1247
1248/* Expose current state and limits in debugfs if possible */
1249
1250struct ips_debugfs_node {
1251 struct ips_driver *ips;
1252 char *name;
1253 int (*show)(struct seq_file *m, void *data);
1254};
1255
1256static int show_cpu_temp(struct seq_file *m, void *data)
1257{
1258 struct ips_driver *ips = m->private;
1259
1260 seq_printf(m, "%d.%02d\n", ips->ctv1_avg_temp / 100,
1261 ips->ctv1_avg_temp % 100);
1262
1263 return 0;
1264}
1265
1266static int show_cpu_power(struct seq_file *m, void *data)
1267{
1268 struct ips_driver *ips = m->private;
1269
1270 seq_printf(m, "%dmW\n", ips->cpu_avg_power);
1271
1272 return 0;
1273}
1274
1275static int show_cpu_clamp(struct seq_file *m, void *data)
1276{
1277 u64 turbo_override;
1278 int tdp, tdc;
1279
1280 rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override);
1281
1282 tdp = (int)(turbo_override & TURBO_TDP_MASK);
1283 tdc = (int)((turbo_override & TURBO_TDC_MASK) >> TURBO_TDC_SHIFT);
1284
1285 /* Convert to .1W/A units */
1286 tdp = tdp * 10 / 8;
1287 tdc = tdc * 10 / 8;
1288
1289 /* Watts Amperes */
1290 seq_printf(m, "%d.%dW %d.%dA\n", tdp / 10, tdp % 10,
1291 tdc / 10, tdc % 10);
1292
1293 return 0;
1294}
1295
1296static int show_mch_temp(struct seq_file *m, void *data)
1297{
1298 struct ips_driver *ips = m->private;
1299
1300 seq_printf(m, "%d.%02d\n", ips->mch_avg_temp / 100,
1301 ips->mch_avg_temp % 100);
1302
1303 return 0;
1304}
1305
1306static int show_mch_power(struct seq_file *m, void *data)
1307{
1308 struct ips_driver *ips = m->private;
1309
1310 seq_printf(m, "%dmW\n", ips->mch_avg_power);
1311
1312 return 0;
1313}
1314
1315static struct ips_debugfs_node ips_debug_files[] = {
1316 { NULL, "cpu_temp", show_cpu_temp },
1317 { NULL, "cpu_power", show_cpu_power },
1318 { NULL, "cpu_clamp", show_cpu_clamp },
1319 { NULL, "mch_temp", show_mch_temp },
1320 { NULL, "mch_power", show_mch_power },
1321};
1322
1323static int ips_debugfs_open(struct inode *inode, struct file *file)
1324{
1325 struct ips_debugfs_node *node = inode->i_private;
1326
1327 return single_open(file, node->show, node->ips);
1328}
1329
1330static const struct file_operations ips_debugfs_ops = {
1331 .owner = THIS_MODULE,
1332 .open = ips_debugfs_open,
1333 .read = seq_read,
1334 .llseek = seq_lseek,
1335 .release = single_release,
1336};
1337
1338static void ips_debugfs_cleanup(struct ips_driver *ips)
1339{
1340 if (ips->debug_root)
1341 debugfs_remove_recursive(ips->debug_root);
1342 return;
1343}
1344
1345static void ips_debugfs_init(struct ips_driver *ips)
1346{
1347 int i;
1348
1349 ips->debug_root = debugfs_create_dir("ips", NULL);
1350 if (!ips->debug_root) {
1351 dev_err(&ips->dev->dev,
1352 "failed to create debugfs entries: %ld\n",
1353 PTR_ERR(ips->debug_root));
1354 return;
1355 }
1356
1357 for (i = 0; i < ARRAY_SIZE(ips_debug_files); i++) {
1358 struct dentry *ent;
1359 struct ips_debugfs_node *node = &ips_debug_files[i];
1360
1361 node->ips = ips;
1362 ent = debugfs_create_file(node->name, S_IFREG | S_IRUGO,
1363 ips->debug_root, node,
1364 &ips_debugfs_ops);
1365 if (!ent) {
1366 dev_err(&ips->dev->dev,
1367 "failed to create debug file: %ld\n",
1368 PTR_ERR(ent));
1369 goto err_cleanup;
1370 }
1371 }
1372
1373 return;
1374
1375err_cleanup:
1376 ips_debugfs_cleanup(ips);
1377 return;
1378}
1379#endif /* CONFIG_DEBUG_FS */
1380
1381/**
1382 * ips_detect_cpu - detect whether CPU supports IPS
1383 *
1384 * Walk our list and see if we're on a supported CPU. If we find one,
1385 * return the limits for it.
1386 */
1387static struct ips_mcp_limits *ips_detect_cpu(struct ips_driver *ips)
1388{
1389 u64 turbo_power, misc_en;
1390 struct ips_mcp_limits *limits = NULL;
1391 u16 tdp;
1392
1393 if (!(boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 37)) {
1394 dev_info(&ips->dev->dev, "Non-IPS CPU detected.\n");
1395 goto out;
1396 }
1397
1398 rdmsrl(IA32_MISC_ENABLE, misc_en);
1399 /*
1400 * If the turbo enable bit isn't set, we shouldn't try to enable/disable
1401 * turbo manually or we'll get an illegal MSR access, even though
1402 * turbo will still be available.
1403 */
1404 if (misc_en & IA32_MISC_TURBO_EN)
1405 ips->turbo_toggle_allowed = true;
1406 else
1407 ips->turbo_toggle_allowed = false;
1408
1409 if (strstr(boot_cpu_data.x86_model_id, "CPU M"))
1410 limits = &ips_sv_limits;
1411 else if (strstr(boot_cpu_data.x86_model_id, "CPU L"))
1412 limits = &ips_lv_limits;
1413 else if (strstr(boot_cpu_data.x86_model_id, "CPU U"))
1414 limits = &ips_ulv_limits;
1415 else {
1416 dev_info(&ips->dev->dev, "No CPUID match found.\n");
1417 goto out;
1418 }
1419
1420 rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_power);
1421 tdp = turbo_power & TURBO_TDP_MASK;
1422
1423 /* Sanity check TDP against CPU */
1424 if (limits->core_power_limit != (tdp / 8) * 1000) {
1425 dev_info(&ips->dev->dev, "CPU TDP doesn't match expected value (found %d, expected %d)\n",
1426 tdp / 8, limits->core_power_limit / 1000);
1427 limits->core_power_limit = (tdp / 8) * 1000;
1428 }
1429
1430out:
1431 return limits;
1432}
1433
1434/**
1435 * ips_get_i915_syms - try to get GPU control methods from i915 driver
1436 * @ips: IPS driver
1437 *
1438 * The i915 driver exports several interfaces to allow the IPS driver to
1439 * monitor and control graphics turbo mode. If we can find them, we can
1440 * enable graphics turbo, otherwise we must disable it to avoid exceeding
1441 * thermal and power limits in the MCP.
1442 */
1443static bool ips_get_i915_syms(struct ips_driver *ips)
1444{
1445 ips->read_mch_val = symbol_get(i915_read_mch_val);
1446 if (!ips->read_mch_val)
1447 goto out_err;
1448 ips->gpu_raise = symbol_get(i915_gpu_raise);
1449 if (!ips->gpu_raise)
1450 goto out_put_mch;
1451 ips->gpu_lower = symbol_get(i915_gpu_lower);
1452 if (!ips->gpu_lower)
1453 goto out_put_raise;
1454 ips->gpu_busy = symbol_get(i915_gpu_busy);
1455 if (!ips->gpu_busy)
1456 goto out_put_lower;
1457 ips->gpu_turbo_disable = symbol_get(i915_gpu_turbo_disable);
1458 if (!ips->gpu_turbo_disable)
1459 goto out_put_busy;
1460
1461 return true;
1462
1463out_put_busy:
1464 symbol_put(i915_gpu_busy);
1465out_put_lower:
1466 symbol_put(i915_gpu_lower);
1467out_put_raise:
1468 symbol_put(i915_gpu_raise);
1469out_put_mch:
1470 symbol_put(i915_read_mch_val);
1471out_err:
1472 return false;
1473}
1474
1475static bool
1476ips_gpu_turbo_enabled(struct ips_driver *ips)
1477{
1478 if (!ips->gpu_busy && late_i915_load) {
1479 if (ips_get_i915_syms(ips)) {
1480 dev_info(&ips->dev->dev,
1481 "i915 driver attached, reenabling gpu turbo\n");
1482 ips->gpu_turbo_enabled = !(thm_readl(THM_HTS) & HTS_GTD_DIS);
1483 }
1484 }
1485
1486 return ips->gpu_turbo_enabled;
1487}
1488
1489void
1490ips_link_to_i915_driver(void)
1491{
1492 /* We can't cleanly get at the various ips_driver structs from
1493 * this caller (the i915 driver), so just set a flag saying
1494 * that it's time to try getting the symbols again.
1495 */
1496 late_i915_load = true;
1497}
1498EXPORT_SYMBOL_GPL(ips_link_to_i915_driver);
1499
1500static DEFINE_PCI_DEVICE_TABLE(ips_id_table) = {
1501 { PCI_DEVICE(PCI_VENDOR_ID_INTEL,
1502 PCI_DEVICE_ID_INTEL_THERMAL_SENSOR), },
1503 { 0, }
1504};
1505
1506MODULE_DEVICE_TABLE(pci, ips_id_table);
1507
1508static int ips_probe(struct pci_dev *dev, const struct pci_device_id *id)
1509{
1510 u64 platform_info;
1511 struct ips_driver *ips;
1512 u32 hts;
1513 int ret = 0;
1514 u16 htshi, trc, trc_required_mask;
1515 u8 tse;
1516
1517 ips = kzalloc(sizeof(struct ips_driver), GFP_KERNEL);
1518 if (!ips)
1519 return -ENOMEM;
1520
1521 pci_set_drvdata(dev, ips);
1522 ips->dev = dev;
1523
1524 ips->limits = ips_detect_cpu(ips);
1525 if (!ips->limits) {
1526 dev_info(&dev->dev, "IPS not supported on this CPU\n");
1527 ret = -ENXIO;
1528 goto error_free;
1529 }
1530
1531 spin_lock_init(&ips->turbo_status_lock);
1532
1533 ret = pci_enable_device(dev);
1534 if (ret) {
1535 dev_err(&dev->dev, "can't enable PCI device, aborting\n");
1536 goto error_free;
1537 }
1538
1539 if (!pci_resource_start(dev, 0)) {
1540 dev_err(&dev->dev, "TBAR not assigned, aborting\n");
1541 ret = -ENXIO;
1542 goto error_free;
1543 }
1544
1545 ret = pci_request_regions(dev, "ips thermal sensor");
1546 if (ret) {
1547 dev_err(&dev->dev, "thermal resource busy, aborting\n");
1548 goto error_free;
1549 }
1550
1551
1552 ips->regmap = ioremap(pci_resource_start(dev, 0),
1553 pci_resource_len(dev, 0));
1554 if (!ips->regmap) {
1555 dev_err(&dev->dev, "failed to map thermal regs, aborting\n");
1556 ret = -EBUSY;
1557 goto error_release;
1558 }
1559
1560 tse = thm_readb(THM_TSE);
1561 if (tse != TSE_EN) {
1562 dev_err(&dev->dev, "thermal device not enabled (0x%02x), aborting\n", tse);
1563 ret = -ENXIO;
1564 goto error_unmap;
1565 }
1566
1567 trc = thm_readw(THM_TRC);
1568 trc_required_mask = TRC_CORE1_EN | TRC_CORE_PWR | TRC_MCH_EN;
1569 if ((trc & trc_required_mask) != trc_required_mask) {
1570 dev_err(&dev->dev, "thermal reporting for required devices not enabled, aborting\n");
1571 ret = -ENXIO;
1572 goto error_unmap;
1573 }
1574
1575 if (trc & TRC_CORE2_EN)
1576 ips->second_cpu = true;
1577
1578 update_turbo_limits(ips);
1579 dev_dbg(&dev->dev, "max cpu power clamp: %dW\n",
1580 ips->mcp_power_limit / 10);
1581 dev_dbg(&dev->dev, "max core power clamp: %dW\n",
1582 ips->core_power_limit / 10);
1583 /* BIOS may update limits at runtime */
1584 if (thm_readl(THM_PSC) & PSP_PBRT)
1585 ips->poll_turbo_status = true;
1586
1587 if (!ips_get_i915_syms(ips)) {
1588 dev_err(&dev->dev, "failed to get i915 symbols, graphics turbo disabled\n");
1589 ips->gpu_turbo_enabled = false;
1590 } else {
1591 dev_dbg(&dev->dev, "graphics turbo enabled\n");
1592 ips->gpu_turbo_enabled = true;
1593 }
1594
1595 /*
1596 * Check PLATFORM_INFO MSR to make sure this chip is
1597 * turbo capable.
1598 */
1599 rdmsrl(PLATFORM_INFO, platform_info);
1600 if (!(platform_info & PLATFORM_TDP)) {
1601 dev_err(&dev->dev, "platform indicates TDP override unavailable, aborting\n");
1602 ret = -ENODEV;
1603 goto error_unmap;
1604 }
1605
1606 /*
1607 * IRQ handler for ME interaction
1608 * Note: don't use MSI here as the PCH has bugs.
1609 */
1610 pci_disable_msi(dev);
1611 ret = request_irq(dev->irq, ips_irq_handler, IRQF_SHARED, "ips",
1612 ips);
1613 if (ret) {
1614 dev_err(&dev->dev, "request irq failed, aborting\n");
1615 goto error_unmap;
1616 }
1617
1618 /* Enable aux, hot & critical interrupts */
1619 thm_writeb(THM_TSPIEN, TSPIEN_AUX2_LOHI | TSPIEN_CRIT_LOHI |
1620 TSPIEN_HOT_LOHI | TSPIEN_AUX_LOHI);
1621 thm_writeb(THM_TEN, TEN_UPDATE_EN);
1622
1623 /* Collect adjustment values */
1624 ips->cta_val = thm_readw(THM_CTA);
1625 ips->pta_val = thm_readw(THM_PTA);
1626 ips->mgta_val = thm_readw(THM_MGTA);
1627
1628 /* Save turbo limits & ratios */
1629 rdmsrl(TURBO_POWER_CURRENT_LIMIT, ips->orig_turbo_limit);
1630
1631 ips_disable_cpu_turbo(ips);
1632 ips->cpu_turbo_enabled = false;
1633
1634 /* Create thermal adjust thread */
1635 ips->adjust = kthread_create(ips_adjust, ips, "ips-adjust");
1636 if (IS_ERR(ips->adjust)) {
1637 dev_err(&dev->dev,
1638 "failed to create thermal adjust thread, aborting\n");
1639 ret = -ENOMEM;
1640 goto error_free_irq;
1641
1642 }
1643
1644 /*
1645 * Set up the work queue and monitor thread. The monitor thread
1646 * will wake up ips_adjust thread.
1647 */
1648 ips->monitor = kthread_run(ips_monitor, ips, "ips-monitor");
1649 if (IS_ERR(ips->monitor)) {
1650 dev_err(&dev->dev,
1651 "failed to create thermal monitor thread, aborting\n");
1652 ret = -ENOMEM;
1653 goto error_thread_cleanup;
1654 }
1655
1656 hts = (ips->core_power_limit << HTS_PCPL_SHIFT) |
1657 (ips->mcp_temp_limit << HTS_PTL_SHIFT) | HTS_NVV;
1658 htshi = HTS2_PRST_RUNNING << HTS2_PRST_SHIFT;
1659
1660 thm_writew(THM_HTSHI, htshi);
1661 thm_writel(THM_HTS, hts);
1662
1663 ips_debugfs_init(ips);
1664
1665 dev_info(&dev->dev, "IPS driver initialized, MCP temp limit %d\n",
1666 ips->mcp_temp_limit);
1667 return ret;
1668
1669error_thread_cleanup:
1670 kthread_stop(ips->adjust);
1671error_free_irq:
1672 free_irq(ips->dev->irq, ips);
1673error_unmap:
1674 iounmap(ips->regmap);
1675error_release:
1676 pci_release_regions(dev);
1677error_free:
1678 kfree(ips);
1679 return ret;
1680}
1681
1682static void ips_remove(struct pci_dev *dev)
1683{
1684 struct ips_driver *ips = pci_get_drvdata(dev);
1685 u64 turbo_override;
1686
1687 if (!ips)
1688 return;
1689
1690 ips_debugfs_cleanup(ips);
1691
1692 /* Release i915 driver */
1693 if (ips->read_mch_val)
1694 symbol_put(i915_read_mch_val);
1695 if (ips->gpu_raise)
1696 symbol_put(i915_gpu_raise);
1697 if (ips->gpu_lower)
1698 symbol_put(i915_gpu_lower);
1699 if (ips->gpu_busy)
1700 symbol_put(i915_gpu_busy);
1701 if (ips->gpu_turbo_disable)
1702 symbol_put(i915_gpu_turbo_disable);
1703
1704 rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override);
1705 turbo_override &= ~(TURBO_TDC_OVR_EN | TURBO_TDP_OVR_EN);
1706 wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override);
1707 wrmsrl(TURBO_POWER_CURRENT_LIMIT, ips->orig_turbo_limit);
1708
1709 free_irq(ips->dev->irq, ips);
1710 if (ips->adjust)
1711 kthread_stop(ips->adjust);
1712 if (ips->monitor)
1713 kthread_stop(ips->monitor);
1714 iounmap(ips->regmap);
1715 pci_release_regions(dev);
1716 kfree(ips);
1717 dev_dbg(&dev->dev, "IPS driver removed\n");
1718}
1719
1720#ifdef CONFIG_PM
1721static int ips_suspend(struct pci_dev *dev, pm_message_t state)
1722{
1723 return 0;
1724}
1725
1726static int ips_resume(struct pci_dev *dev)
1727{
1728 return 0;
1729}
1730#else
1731#define ips_suspend NULL
1732#define ips_resume NULL
1733#endif /* CONFIG_PM */
1734
1735static void ips_shutdown(struct pci_dev *dev)
1736{
1737}
1738
1739static struct pci_driver ips_pci_driver = {
1740 .name = "intel ips",
1741 .id_table = ips_id_table,
1742 .probe = ips_probe,
1743 .remove = ips_remove,
1744 .suspend = ips_suspend,
1745 .resume = ips_resume,
1746 .shutdown = ips_shutdown,
1747};
1748
1749static int __init ips_init(void)
1750{
1751 return pci_register_driver(&ips_pci_driver);
1752}
1753module_init(ips_init);
1754
1755static void ips_exit(void)
1756{
1757 pci_unregister_driver(&ips_pci_driver);
1758 return;
1759}
1760module_exit(ips_exit);
1761
1762MODULE_LICENSE("GPL");
1763MODULE_AUTHOR("Jesse Barnes <jbarnes@virtuousgeek.org>");
1764MODULE_DESCRIPTION("Intelligent Power Sharing Driver");
1/*
2 * Copyright (c) 2009-2010 Intel Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc.,
15 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
16 *
17 * The full GNU General Public License is included in this distribution in
18 * the file called "COPYING".
19 *
20 * Authors:
21 * Jesse Barnes <jbarnes@virtuousgeek.org>
22 */
23
24/*
25 * Some Intel Ibex Peak based platforms support so-called "intelligent
26 * power sharing", which allows the CPU and GPU to cooperate to maximize
27 * performance within a given TDP (thermal design point). This driver
28 * performs the coordination between the CPU and GPU, monitors thermal and
29 * power statistics in the platform, and initializes power monitoring
30 * hardware. It also provides a few tunables to control behavior. Its
31 * primary purpose is to safely allow CPU and GPU turbo modes to be enabled
32 * by tracking power and thermal budget; secondarily it can boost turbo
33 * performance by allocating more power or thermal budget to the CPU or GPU
34 * based on available headroom and activity.
35 *
36 * The basic algorithm is driven by a 5s moving average of tempurature. If
37 * thermal headroom is available, the CPU and/or GPU power clamps may be
38 * adjusted upwards. If we hit the thermal ceiling or a thermal trigger,
39 * we scale back the clamp. Aside from trigger events (when we're critically
40 * close or over our TDP) we don't adjust the clamps more than once every
41 * five seconds.
42 *
43 * The thermal device (device 31, function 6) has a set of registers that
44 * are updated by the ME firmware. The ME should also take the clamp values
45 * written to those registers and write them to the CPU, but we currently
46 * bypass that functionality and write the CPU MSR directly.
47 *
48 * UNSUPPORTED:
49 * - dual MCP configs
50 *
51 * TODO:
52 * - handle CPU hotplug
53 * - provide turbo enable/disable api
54 *
55 * Related documents:
56 * - CDI 403777, 403778 - Auburndale EDS vol 1 & 2
57 * - CDI 401376 - Ibex Peak EDS
58 * - ref 26037, 26641 - IPS BIOS spec
59 * - ref 26489 - Nehalem BIOS writer's guide
60 * - ref 26921 - Ibex Peak BIOS Specification
61 */
62
63#include <linux/debugfs.h>
64#include <linux/delay.h>
65#include <linux/interrupt.h>
66#include <linux/kernel.h>
67#include <linux/kthread.h>
68#include <linux/module.h>
69#include <linux/pci.h>
70#include <linux/sched.h>
71#include <linux/seq_file.h>
72#include <linux/string.h>
73#include <linux/tick.h>
74#include <linux/timer.h>
75#include <linux/dmi.h>
76#include <drm/i915_drm.h>
77#include <asm/msr.h>
78#include <asm/processor.h>
79#include "intel_ips.h"
80
81#include <asm-generic/io-64-nonatomic-lo-hi.h>
82
83#define PCI_DEVICE_ID_INTEL_THERMAL_SENSOR 0x3b32
84
85/*
86 * Package level MSRs for monitor/control
87 */
88#define PLATFORM_INFO 0xce
89#define PLATFORM_TDP (1<<29)
90#define PLATFORM_RATIO (1<<28)
91
92#define IA32_MISC_ENABLE 0x1a0
93#define IA32_MISC_TURBO_EN (1ULL<<38)
94
95#define TURBO_POWER_CURRENT_LIMIT 0x1ac
96#define TURBO_TDC_OVR_EN (1UL<<31)
97#define TURBO_TDC_MASK (0x000000007fff0000UL)
98#define TURBO_TDC_SHIFT (16)
99#define TURBO_TDP_OVR_EN (1UL<<15)
100#define TURBO_TDP_MASK (0x0000000000003fffUL)
101
102/*
103 * Core/thread MSRs for monitoring
104 */
105#define IA32_PERF_CTL 0x199
106#define IA32_PERF_TURBO_DIS (1ULL<<32)
107
108/*
109 * Thermal PCI device regs
110 */
111#define THM_CFG_TBAR 0x10
112#define THM_CFG_TBAR_HI 0x14
113
114#define THM_TSIU 0x00
115#define THM_TSE 0x01
116#define TSE_EN 0xb8
117#define THM_TSS 0x02
118#define THM_TSTR 0x03
119#define THM_TSTTP 0x04
120#define THM_TSCO 0x08
121#define THM_TSES 0x0c
122#define THM_TSGPEN 0x0d
123#define TSGPEN_HOT_LOHI (1<<1)
124#define TSGPEN_CRIT_LOHI (1<<2)
125#define THM_TSPC 0x0e
126#define THM_PPEC 0x10
127#define THM_CTA 0x12
128#define THM_PTA 0x14
129#define PTA_SLOPE_MASK (0xff00)
130#define PTA_SLOPE_SHIFT 8
131#define PTA_OFFSET_MASK (0x00ff)
132#define THM_MGTA 0x16
133#define MGTA_SLOPE_MASK (0xff00)
134#define MGTA_SLOPE_SHIFT 8
135#define MGTA_OFFSET_MASK (0x00ff)
136#define THM_TRC 0x1a
137#define TRC_CORE2_EN (1<<15)
138#define TRC_THM_EN (1<<12)
139#define TRC_C6_WAR (1<<8)
140#define TRC_CORE1_EN (1<<7)
141#define TRC_CORE_PWR (1<<6)
142#define TRC_PCH_EN (1<<5)
143#define TRC_MCH_EN (1<<4)
144#define TRC_DIMM4 (1<<3)
145#define TRC_DIMM3 (1<<2)
146#define TRC_DIMM2 (1<<1)
147#define TRC_DIMM1 (1<<0)
148#define THM_TES 0x20
149#define THM_TEN 0x21
150#define TEN_UPDATE_EN 1
151#define THM_PSC 0x24
152#define PSC_NTG (1<<0) /* No GFX turbo support */
153#define PSC_NTPC (1<<1) /* No CPU turbo support */
154#define PSC_PP_DEF (0<<2) /* Perf policy up to driver */
155#define PSP_PP_PC (1<<2) /* BIOS prefers CPU perf */
156#define PSP_PP_BAL (2<<2) /* BIOS wants balanced perf */
157#define PSP_PP_GFX (3<<2) /* BIOS prefers GFX perf */
158#define PSP_PBRT (1<<4) /* BIOS run time support */
159#define THM_CTV1 0x30
160#define CTV_TEMP_ERROR (1<<15)
161#define CTV_TEMP_MASK 0x3f
162#define CTV_
163#define THM_CTV2 0x32
164#define THM_CEC 0x34 /* undocumented power accumulator in joules */
165#define THM_AE 0x3f
166#define THM_HTS 0x50 /* 32 bits */
167#define HTS_PCPL_MASK (0x7fe00000)
168#define HTS_PCPL_SHIFT 21
169#define HTS_GPL_MASK (0x001ff000)
170#define HTS_GPL_SHIFT 12
171#define HTS_PP_MASK (0x00000c00)
172#define HTS_PP_SHIFT 10
173#define HTS_PP_DEF 0
174#define HTS_PP_PROC 1
175#define HTS_PP_BAL 2
176#define HTS_PP_GFX 3
177#define HTS_PCTD_DIS (1<<9)
178#define HTS_GTD_DIS (1<<8)
179#define HTS_PTL_MASK (0x000000fe)
180#define HTS_PTL_SHIFT 1
181#define HTS_NVV (1<<0)
182#define THM_HTSHI 0x54 /* 16 bits */
183#define HTS2_PPL_MASK (0x03ff)
184#define HTS2_PRST_MASK (0x3c00)
185#define HTS2_PRST_SHIFT 10
186#define HTS2_PRST_UNLOADED 0
187#define HTS2_PRST_RUNNING 1
188#define HTS2_PRST_TDISOP 2 /* turbo disabled due to power */
189#define HTS2_PRST_TDISHT 3 /* turbo disabled due to high temp */
190#define HTS2_PRST_TDISUSR 4 /* user disabled turbo */
191#define HTS2_PRST_TDISPLAT 5 /* platform disabled turbo */
192#define HTS2_PRST_TDISPM 6 /* power management disabled turbo */
193#define HTS2_PRST_TDISERR 7 /* some kind of error disabled turbo */
194#define THM_PTL 0x56
195#define THM_MGTV 0x58
196#define TV_MASK 0x000000000000ff00
197#define TV_SHIFT 8
198#define THM_PTV 0x60
199#define PTV_MASK 0x00ff
200#define THM_MMGPC 0x64
201#define THM_MPPC 0x66
202#define THM_MPCPC 0x68
203#define THM_TSPIEN 0x82
204#define TSPIEN_AUX_LOHI (1<<0)
205#define TSPIEN_HOT_LOHI (1<<1)
206#define TSPIEN_CRIT_LOHI (1<<2)
207#define TSPIEN_AUX2_LOHI (1<<3)
208#define THM_TSLOCK 0x83
209#define THM_ATR 0x84
210#define THM_TOF 0x87
211#define THM_STS 0x98
212#define STS_PCPL_MASK (0x7fe00000)
213#define STS_PCPL_SHIFT 21
214#define STS_GPL_MASK (0x001ff000)
215#define STS_GPL_SHIFT 12
216#define STS_PP_MASK (0x00000c00)
217#define STS_PP_SHIFT 10
218#define STS_PP_DEF 0
219#define STS_PP_PROC 1
220#define STS_PP_BAL 2
221#define STS_PP_GFX 3
222#define STS_PCTD_DIS (1<<9)
223#define STS_GTD_DIS (1<<8)
224#define STS_PTL_MASK (0x000000fe)
225#define STS_PTL_SHIFT 1
226#define STS_NVV (1<<0)
227#define THM_SEC 0x9c
228#define SEC_ACK (1<<0)
229#define THM_TC3 0xa4
230#define THM_TC1 0xa8
231#define STS_PPL_MASK (0x0003ff00)
232#define STS_PPL_SHIFT 16
233#define THM_TC2 0xac
234#define THM_DTV 0xb0
235#define THM_ITV 0xd8
236#define ITV_ME_SEQNO_MASK 0x00ff0000 /* ME should update every ~200ms */
237#define ITV_ME_SEQNO_SHIFT (16)
238#define ITV_MCH_TEMP_MASK 0x0000ff00
239#define ITV_MCH_TEMP_SHIFT (8)
240#define ITV_PCH_TEMP_MASK 0x000000ff
241
242#define thm_readb(off) readb(ips->regmap + (off))
243#define thm_readw(off) readw(ips->regmap + (off))
244#define thm_readl(off) readl(ips->regmap + (off))
245#define thm_readq(off) readq(ips->regmap + (off))
246
247#define thm_writeb(off, val) writeb((val), ips->regmap + (off))
248#define thm_writew(off, val) writew((val), ips->regmap + (off))
249#define thm_writel(off, val) writel((val), ips->regmap + (off))
250
251static const int IPS_ADJUST_PERIOD = 5000; /* ms */
252static bool late_i915_load = false;
253
254/* For initial average collection */
255static const int IPS_SAMPLE_PERIOD = 200; /* ms */
256static const int IPS_SAMPLE_WINDOW = 5000; /* 5s moving window of samples */
257#define IPS_SAMPLE_COUNT (IPS_SAMPLE_WINDOW / IPS_SAMPLE_PERIOD)
258
259/* Per-SKU limits */
260struct ips_mcp_limits {
261 int cpu_family;
262 int cpu_model; /* includes extended model... */
263 int mcp_power_limit; /* mW units */
264 int core_power_limit;
265 int mch_power_limit;
266 int core_temp_limit; /* degrees C */
267 int mch_temp_limit;
268};
269
270/* Max temps are -10 degrees C to avoid PROCHOT# */
271
272struct ips_mcp_limits ips_sv_limits = {
273 .mcp_power_limit = 35000,
274 .core_power_limit = 29000,
275 .mch_power_limit = 20000,
276 .core_temp_limit = 95,
277 .mch_temp_limit = 90
278};
279
280struct ips_mcp_limits ips_lv_limits = {
281 .mcp_power_limit = 25000,
282 .core_power_limit = 21000,
283 .mch_power_limit = 13000,
284 .core_temp_limit = 95,
285 .mch_temp_limit = 90
286};
287
288struct ips_mcp_limits ips_ulv_limits = {
289 .mcp_power_limit = 18000,
290 .core_power_limit = 14000,
291 .mch_power_limit = 11000,
292 .core_temp_limit = 95,
293 .mch_temp_limit = 90
294};
295
296struct ips_driver {
297 struct pci_dev *dev;
298 void *regmap;
299 struct task_struct *monitor;
300 struct task_struct *adjust;
301 struct dentry *debug_root;
302
303 /* Average CPU core temps (all averages in .01 degrees C for precision) */
304 u16 ctv1_avg_temp;
305 u16 ctv2_avg_temp;
306 /* GMCH average */
307 u16 mch_avg_temp;
308 /* Average for the CPU (both cores?) */
309 u16 mcp_avg_temp;
310 /* Average power consumption (in mW) */
311 u32 cpu_avg_power;
312 u32 mch_avg_power;
313
314 /* Offset values */
315 u16 cta_val;
316 u16 pta_val;
317 u16 mgta_val;
318
319 /* Maximums & prefs, protected by turbo status lock */
320 spinlock_t turbo_status_lock;
321 u16 mcp_temp_limit;
322 u16 mcp_power_limit;
323 u16 core_power_limit;
324 u16 mch_power_limit;
325 bool cpu_turbo_enabled;
326 bool __cpu_turbo_on;
327 bool gpu_turbo_enabled;
328 bool __gpu_turbo_on;
329 bool gpu_preferred;
330 bool poll_turbo_status;
331 bool second_cpu;
332 bool turbo_toggle_allowed;
333 struct ips_mcp_limits *limits;
334
335 /* Optional MCH interfaces for if i915 is in use */
336 unsigned long (*read_mch_val)(void);
337 bool (*gpu_raise)(void);
338 bool (*gpu_lower)(void);
339 bool (*gpu_busy)(void);
340 bool (*gpu_turbo_disable)(void);
341
342 /* For restoration at unload */
343 u64 orig_turbo_limit;
344 u64 orig_turbo_ratios;
345};
346
347static bool
348ips_gpu_turbo_enabled(struct ips_driver *ips);
349
350/**
351 * ips_cpu_busy - is CPU busy?
352 * @ips: IPS driver struct
353 *
354 * Check CPU for load to see whether we should increase its thermal budget.
355 *
356 * RETURNS:
357 * True if the CPU could use more power, false otherwise.
358 */
359static bool ips_cpu_busy(struct ips_driver *ips)
360{
361 if ((avenrun[0] >> FSHIFT) > 1)
362 return true;
363
364 return false;
365}
366
367/**
368 * ips_cpu_raise - raise CPU power clamp
369 * @ips: IPS driver struct
370 *
371 * Raise the CPU power clamp by %IPS_CPU_STEP, in accordance with TDP for
372 * this platform.
373 *
374 * We do this by adjusting the TURBO_POWER_CURRENT_LIMIT MSR upwards (as
375 * long as we haven't hit the TDP limit for the SKU).
376 */
377static void ips_cpu_raise(struct ips_driver *ips)
378{
379 u64 turbo_override;
380 u16 cur_tdp_limit, new_tdp_limit;
381
382 if (!ips->cpu_turbo_enabled)
383 return;
384
385 rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override);
386
387 cur_tdp_limit = turbo_override & TURBO_TDP_MASK;
388 new_tdp_limit = cur_tdp_limit + 8; /* 1W increase */
389
390 /* Clamp to SKU TDP limit */
391 if (((new_tdp_limit * 10) / 8) > ips->core_power_limit)
392 new_tdp_limit = cur_tdp_limit;
393
394 thm_writew(THM_MPCPC, (new_tdp_limit * 10) / 8);
395
396 turbo_override |= TURBO_TDC_OVR_EN | TURBO_TDP_OVR_EN;
397 wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override);
398
399 turbo_override &= ~TURBO_TDP_MASK;
400 turbo_override |= new_tdp_limit;
401
402 wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override);
403}
404
405/**
406 * ips_cpu_lower - lower CPU power clamp
407 * @ips: IPS driver struct
408 *
409 * Lower CPU power clamp b %IPS_CPU_STEP if possible.
410 *
411 * We do this by adjusting the TURBO_POWER_CURRENT_LIMIT MSR down, going
412 * as low as the platform limits will allow (though we could go lower there
413 * wouldn't be much point).
414 */
415static void ips_cpu_lower(struct ips_driver *ips)
416{
417 u64 turbo_override;
418 u16 cur_limit, new_limit;
419
420 rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override);
421
422 cur_limit = turbo_override & TURBO_TDP_MASK;
423 new_limit = cur_limit - 8; /* 1W decrease */
424
425 /* Clamp to SKU TDP limit */
426 if (new_limit < (ips->orig_turbo_limit & TURBO_TDP_MASK))
427 new_limit = ips->orig_turbo_limit & TURBO_TDP_MASK;
428
429 thm_writew(THM_MPCPC, (new_limit * 10) / 8);
430
431 turbo_override |= TURBO_TDC_OVR_EN | TURBO_TDP_OVR_EN;
432 wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override);
433
434 turbo_override &= ~TURBO_TDP_MASK;
435 turbo_override |= new_limit;
436
437 wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override);
438}
439
440/**
441 * do_enable_cpu_turbo - internal turbo enable function
442 * @data: unused
443 *
444 * Internal function for actually updating MSRs. When we enable/disable
445 * turbo, we need to do it on each CPU; this function is the one called
446 * by on_each_cpu() when needed.
447 */
448static void do_enable_cpu_turbo(void *data)
449{
450 u64 perf_ctl;
451
452 rdmsrl(IA32_PERF_CTL, perf_ctl);
453 if (perf_ctl & IA32_PERF_TURBO_DIS) {
454 perf_ctl &= ~IA32_PERF_TURBO_DIS;
455 wrmsrl(IA32_PERF_CTL, perf_ctl);
456 }
457}
458
459/**
460 * ips_enable_cpu_turbo - enable turbo mode on all CPUs
461 * @ips: IPS driver struct
462 *
463 * Enable turbo mode by clearing the disable bit in IA32_PERF_CTL on
464 * all logical threads.
465 */
466static void ips_enable_cpu_turbo(struct ips_driver *ips)
467{
468 /* Already on, no need to mess with MSRs */
469 if (ips->__cpu_turbo_on)
470 return;
471
472 if (ips->turbo_toggle_allowed)
473 on_each_cpu(do_enable_cpu_turbo, ips, 1);
474
475 ips->__cpu_turbo_on = true;
476}
477
478/**
479 * do_disable_cpu_turbo - internal turbo disable function
480 * @data: unused
481 *
482 * Internal function for actually updating MSRs. When we enable/disable
483 * turbo, we need to do it on each CPU; this function is the one called
484 * by on_each_cpu() when needed.
485 */
486static void do_disable_cpu_turbo(void *data)
487{
488 u64 perf_ctl;
489
490 rdmsrl(IA32_PERF_CTL, perf_ctl);
491 if (!(perf_ctl & IA32_PERF_TURBO_DIS)) {
492 perf_ctl |= IA32_PERF_TURBO_DIS;
493 wrmsrl(IA32_PERF_CTL, perf_ctl);
494 }
495}
496
497/**
498 * ips_disable_cpu_turbo - disable turbo mode on all CPUs
499 * @ips: IPS driver struct
500 *
501 * Disable turbo mode by setting the disable bit in IA32_PERF_CTL on
502 * all logical threads.
503 */
504static void ips_disable_cpu_turbo(struct ips_driver *ips)
505{
506 /* Already off, leave it */
507 if (!ips->__cpu_turbo_on)
508 return;
509
510 if (ips->turbo_toggle_allowed)
511 on_each_cpu(do_disable_cpu_turbo, ips, 1);
512
513 ips->__cpu_turbo_on = false;
514}
515
516/**
517 * ips_gpu_busy - is GPU busy?
518 * @ips: IPS driver struct
519 *
520 * Check GPU for load to see whether we should increase its thermal budget.
521 * We need to call into the i915 driver in this case.
522 *
523 * RETURNS:
524 * True if the GPU could use more power, false otherwise.
525 */
526static bool ips_gpu_busy(struct ips_driver *ips)
527{
528 if (!ips_gpu_turbo_enabled(ips))
529 return false;
530
531 return ips->gpu_busy();
532}
533
534/**
535 * ips_gpu_raise - raise GPU power clamp
536 * @ips: IPS driver struct
537 *
538 * Raise the GPU frequency/power if possible. We need to call into the
539 * i915 driver in this case.
540 */
541static void ips_gpu_raise(struct ips_driver *ips)
542{
543 if (!ips_gpu_turbo_enabled(ips))
544 return;
545
546 if (!ips->gpu_raise())
547 ips->gpu_turbo_enabled = false;
548
549 return;
550}
551
552/**
553 * ips_gpu_lower - lower GPU power clamp
554 * @ips: IPS driver struct
555 *
556 * Lower GPU frequency/power if possible. Need to call i915.
557 */
558static void ips_gpu_lower(struct ips_driver *ips)
559{
560 if (!ips_gpu_turbo_enabled(ips))
561 return;
562
563 if (!ips->gpu_lower())
564 ips->gpu_turbo_enabled = false;
565
566 return;
567}
568
569/**
570 * ips_enable_gpu_turbo - notify the gfx driver turbo is available
571 * @ips: IPS driver struct
572 *
573 * Call into the graphics driver indicating that it can safely use
574 * turbo mode.
575 */
576static void ips_enable_gpu_turbo(struct ips_driver *ips)
577{
578 if (ips->__gpu_turbo_on)
579 return;
580 ips->__gpu_turbo_on = true;
581}
582
583/**
584 * ips_disable_gpu_turbo - notify the gfx driver to disable turbo mode
585 * @ips: IPS driver struct
586 *
587 * Request that the graphics driver disable turbo mode.
588 */
589static void ips_disable_gpu_turbo(struct ips_driver *ips)
590{
591 /* Avoid calling i915 if turbo is already disabled */
592 if (!ips->__gpu_turbo_on)
593 return;
594
595 if (!ips->gpu_turbo_disable())
596 dev_err(&ips->dev->dev, "failed to disable graphis turbo\n");
597 else
598 ips->__gpu_turbo_on = false;
599}
600
601/**
602 * mcp_exceeded - check whether we're outside our thermal & power limits
603 * @ips: IPS driver struct
604 *
605 * Check whether the MCP is over its thermal or power budget.
606 */
607static bool mcp_exceeded(struct ips_driver *ips)
608{
609 unsigned long flags;
610 bool ret = false;
611 u32 temp_limit;
612 u32 avg_power;
613
614 spin_lock_irqsave(&ips->turbo_status_lock, flags);
615
616 temp_limit = ips->mcp_temp_limit * 100;
617 if (ips->mcp_avg_temp > temp_limit)
618 ret = true;
619
620 avg_power = ips->cpu_avg_power + ips->mch_avg_power;
621 if (avg_power > ips->mcp_power_limit)
622 ret = true;
623
624 spin_unlock_irqrestore(&ips->turbo_status_lock, flags);
625
626 return ret;
627}
628
629/**
630 * cpu_exceeded - check whether a CPU core is outside its limits
631 * @ips: IPS driver struct
632 * @cpu: CPU number to check
633 *
634 * Check a given CPU's average temp or power is over its limit.
635 */
636static bool cpu_exceeded(struct ips_driver *ips, int cpu)
637{
638 unsigned long flags;
639 int avg;
640 bool ret = false;
641
642 spin_lock_irqsave(&ips->turbo_status_lock, flags);
643 avg = cpu ? ips->ctv2_avg_temp : ips->ctv1_avg_temp;
644 if (avg > (ips->limits->core_temp_limit * 100))
645 ret = true;
646 if (ips->cpu_avg_power > ips->core_power_limit * 100)
647 ret = true;
648 spin_unlock_irqrestore(&ips->turbo_status_lock, flags);
649
650 if (ret)
651 dev_info(&ips->dev->dev,
652 "CPU power or thermal limit exceeded\n");
653
654 return ret;
655}
656
657/**
658 * mch_exceeded - check whether the GPU is over budget
659 * @ips: IPS driver struct
660 *
661 * Check the MCH temp & power against their maximums.
662 */
663static bool mch_exceeded(struct ips_driver *ips)
664{
665 unsigned long flags;
666 bool ret = false;
667
668 spin_lock_irqsave(&ips->turbo_status_lock, flags);
669 if (ips->mch_avg_temp > (ips->limits->mch_temp_limit * 100))
670 ret = true;
671 if (ips->mch_avg_power > ips->mch_power_limit)
672 ret = true;
673 spin_unlock_irqrestore(&ips->turbo_status_lock, flags);
674
675 return ret;
676}
677
678/**
679 * verify_limits - verify BIOS provided limits
680 * @ips: IPS structure
681 *
682 * BIOS can optionally provide non-default limits for power and temp. Check
683 * them here and use the defaults if the BIOS values are not provided or
684 * are otherwise unusable.
685 */
686static void verify_limits(struct ips_driver *ips)
687{
688 if (ips->mcp_power_limit < ips->limits->mcp_power_limit ||
689 ips->mcp_power_limit > 35000)
690 ips->mcp_power_limit = ips->limits->mcp_power_limit;
691
692 if (ips->mcp_temp_limit < ips->limits->core_temp_limit ||
693 ips->mcp_temp_limit < ips->limits->mch_temp_limit ||
694 ips->mcp_temp_limit > 150)
695 ips->mcp_temp_limit = min(ips->limits->core_temp_limit,
696 ips->limits->mch_temp_limit);
697}
698
699/**
700 * update_turbo_limits - get various limits & settings from regs
701 * @ips: IPS driver struct
702 *
703 * Update the IPS power & temp limits, along with turbo enable flags,
704 * based on latest register contents.
705 *
706 * Used at init time and for runtime BIOS support, which requires polling
707 * the regs for updates (as a result of AC->DC transition for example).
708 *
709 * LOCKING:
710 * Caller must hold turbo_status_lock (outside of init)
711 */
712static void update_turbo_limits(struct ips_driver *ips)
713{
714 u32 hts = thm_readl(THM_HTS);
715
716 ips->cpu_turbo_enabled = !(hts & HTS_PCTD_DIS);
717 /*
718 * Disable turbo for now, until we can figure out why the power figures
719 * are wrong
720 */
721 ips->cpu_turbo_enabled = false;
722
723 if (ips->gpu_busy)
724 ips->gpu_turbo_enabled = !(hts & HTS_GTD_DIS);
725
726 ips->core_power_limit = thm_readw(THM_MPCPC);
727 ips->mch_power_limit = thm_readw(THM_MMGPC);
728 ips->mcp_temp_limit = thm_readw(THM_PTL);
729 ips->mcp_power_limit = thm_readw(THM_MPPC);
730
731 verify_limits(ips);
732 /* Ignore BIOS CPU vs GPU pref */
733}
734
735/**
736 * ips_adjust - adjust power clamp based on thermal state
737 * @data: ips driver structure
738 *
739 * Wake up every 5s or so and check whether we should adjust the power clamp.
740 * Check CPU and GPU load to determine which needs adjustment. There are
741 * several things to consider here:
742 * - do we need to adjust up or down?
743 * - is CPU busy?
744 * - is GPU busy?
745 * - is CPU in turbo?
746 * - is GPU in turbo?
747 * - is CPU or GPU preferred? (CPU is default)
748 *
749 * So, given the above, we do the following:
750 * - up (TDP available)
751 * - CPU not busy, GPU not busy - nothing
752 * - CPU busy, GPU not busy - adjust CPU up
753 * - CPU not busy, GPU busy - adjust GPU up
754 * - CPU busy, GPU busy - adjust preferred unit up, taking headroom from
755 * non-preferred unit if necessary
756 * - down (at TDP limit)
757 * - adjust both CPU and GPU down if possible
758 *
759 cpu+ gpu+ cpu+gpu- cpu-gpu+ cpu-gpu-
760cpu < gpu < cpu+gpu+ cpu+ gpu+ nothing
761cpu < gpu >= cpu+gpu-(mcp<) cpu+gpu-(mcp<) gpu- gpu-
762cpu >= gpu < cpu-gpu+(mcp<) cpu- cpu-gpu+(mcp<) cpu-
763cpu >= gpu >= cpu-gpu- cpu-gpu- cpu-gpu- cpu-gpu-
764 *
765 */
766static int ips_adjust(void *data)
767{
768 struct ips_driver *ips = data;
769 unsigned long flags;
770
771 dev_dbg(&ips->dev->dev, "starting ips-adjust thread\n");
772
773 /*
774 * Adjust CPU and GPU clamps every 5s if needed. Doing it more
775 * often isn't recommended due to ME interaction.
776 */
777 do {
778 bool cpu_busy = ips_cpu_busy(ips);
779 bool gpu_busy = ips_gpu_busy(ips);
780
781 spin_lock_irqsave(&ips->turbo_status_lock, flags);
782 if (ips->poll_turbo_status)
783 update_turbo_limits(ips);
784 spin_unlock_irqrestore(&ips->turbo_status_lock, flags);
785
786 /* Update turbo status if necessary */
787 if (ips->cpu_turbo_enabled)
788 ips_enable_cpu_turbo(ips);
789 else
790 ips_disable_cpu_turbo(ips);
791
792 if (ips->gpu_turbo_enabled)
793 ips_enable_gpu_turbo(ips);
794 else
795 ips_disable_gpu_turbo(ips);
796
797 /* We're outside our comfort zone, crank them down */
798 if (mcp_exceeded(ips)) {
799 ips_cpu_lower(ips);
800 ips_gpu_lower(ips);
801 goto sleep;
802 }
803
804 if (!cpu_exceeded(ips, 0) && cpu_busy)
805 ips_cpu_raise(ips);
806 else
807 ips_cpu_lower(ips);
808
809 if (!mch_exceeded(ips) && gpu_busy)
810 ips_gpu_raise(ips);
811 else
812 ips_gpu_lower(ips);
813
814sleep:
815 schedule_timeout_interruptible(msecs_to_jiffies(IPS_ADJUST_PERIOD));
816 } while (!kthread_should_stop());
817
818 dev_dbg(&ips->dev->dev, "ips-adjust thread stopped\n");
819
820 return 0;
821}
822
823/*
824 * Helpers for reading out temp/power values and calculating their
825 * averages for the decision making and monitoring functions.
826 */
827
828static u16 calc_avg_temp(struct ips_driver *ips, u16 *array)
829{
830 u64 total = 0;
831 int i;
832 u16 avg;
833
834 for (i = 0; i < IPS_SAMPLE_COUNT; i++)
835 total += (u64)(array[i] * 100);
836
837 do_div(total, IPS_SAMPLE_COUNT);
838
839 avg = (u16)total;
840
841 return avg;
842}
843
844static u16 read_mgtv(struct ips_driver *ips)
845{
846 u16 ret;
847 u64 slope, offset;
848 u64 val;
849
850 val = thm_readq(THM_MGTV);
851 val = (val & TV_MASK) >> TV_SHIFT;
852
853 slope = offset = thm_readw(THM_MGTA);
854 slope = (slope & MGTA_SLOPE_MASK) >> MGTA_SLOPE_SHIFT;
855 offset = offset & MGTA_OFFSET_MASK;
856
857 ret = ((val * slope + 0x40) >> 7) + offset;
858
859 return 0; /* MCH temp reporting buggy */
860}
861
862static u16 read_ptv(struct ips_driver *ips)
863{
864 u16 val, slope, offset;
865
866 slope = (ips->pta_val & PTA_SLOPE_MASK) >> PTA_SLOPE_SHIFT;
867 offset = ips->pta_val & PTA_OFFSET_MASK;
868
869 val = thm_readw(THM_PTV) & PTV_MASK;
870
871 return val;
872}
873
874static u16 read_ctv(struct ips_driver *ips, int cpu)
875{
876 int reg = cpu ? THM_CTV2 : THM_CTV1;
877 u16 val;
878
879 val = thm_readw(reg);
880 if (!(val & CTV_TEMP_ERROR))
881 val = (val) >> 6; /* discard fractional component */
882 else
883 val = 0;
884
885 return val;
886}
887
888static u32 get_cpu_power(struct ips_driver *ips, u32 *last, int period)
889{
890 u32 val;
891 u32 ret;
892
893 /*
894 * CEC is in joules/65535. Take difference over time to
895 * get watts.
896 */
897 val = thm_readl(THM_CEC);
898
899 /* period is in ms and we want mW */
900 ret = (((val - *last) * 1000) / period);
901 ret = (ret * 1000) / 65535;
902 *last = val;
903
904 return 0;
905}
906
907static const u16 temp_decay_factor = 2;
908static u16 update_average_temp(u16 avg, u16 val)
909{
910 u16 ret;
911
912 /* Multiply by 100 for extra precision */
913 ret = (val * 100 / temp_decay_factor) +
914 (((temp_decay_factor - 1) * avg) / temp_decay_factor);
915 return ret;
916}
917
918static const u16 power_decay_factor = 2;
919static u16 update_average_power(u32 avg, u32 val)
920{
921 u32 ret;
922
923 ret = (val / power_decay_factor) +
924 (((power_decay_factor - 1) * avg) / power_decay_factor);
925
926 return ret;
927}
928
929static u32 calc_avg_power(struct ips_driver *ips, u32 *array)
930{
931 u64 total = 0;
932 u32 avg;
933 int i;
934
935 for (i = 0; i < IPS_SAMPLE_COUNT; i++)
936 total += array[i];
937
938 do_div(total, IPS_SAMPLE_COUNT);
939 avg = (u32)total;
940
941 return avg;
942}
943
944static void monitor_timeout(unsigned long arg)
945{
946 wake_up_process((struct task_struct *)arg);
947}
948
949/**
950 * ips_monitor - temp/power monitoring thread
951 * @data: ips driver structure
952 *
953 * This is the main function for the IPS driver. It monitors power and
954 * tempurature in the MCP and adjusts CPU and GPU power clams accordingly.
955 *
956 * We keep a 5s moving average of power consumption and tempurature. Using
957 * that data, along with CPU vs GPU preference, we adjust the power clamps
958 * up or down.
959 */
960static int ips_monitor(void *data)
961{
962 struct ips_driver *ips = data;
963 struct timer_list timer;
964 unsigned long seqno_timestamp, expire, last_msecs, last_sample_period;
965 int i;
966 u32 *cpu_samples, *mchp_samples, old_cpu_power;
967 u16 *mcp_samples, *ctv1_samples, *ctv2_samples, *mch_samples;
968 u8 cur_seqno, last_seqno;
969
970 mcp_samples = kzalloc(sizeof(u16) * IPS_SAMPLE_COUNT, GFP_KERNEL);
971 ctv1_samples = kzalloc(sizeof(u16) * IPS_SAMPLE_COUNT, GFP_KERNEL);
972 ctv2_samples = kzalloc(sizeof(u16) * IPS_SAMPLE_COUNT, GFP_KERNEL);
973 mch_samples = kzalloc(sizeof(u16) * IPS_SAMPLE_COUNT, GFP_KERNEL);
974 cpu_samples = kzalloc(sizeof(u32) * IPS_SAMPLE_COUNT, GFP_KERNEL);
975 mchp_samples = kzalloc(sizeof(u32) * IPS_SAMPLE_COUNT, GFP_KERNEL);
976 if (!mcp_samples || !ctv1_samples || !ctv2_samples || !mch_samples ||
977 !cpu_samples || !mchp_samples) {
978 dev_err(&ips->dev->dev,
979 "failed to allocate sample array, ips disabled\n");
980 kfree(mcp_samples);
981 kfree(ctv1_samples);
982 kfree(ctv2_samples);
983 kfree(mch_samples);
984 kfree(cpu_samples);
985 kfree(mchp_samples);
986 return -ENOMEM;
987 }
988
989 last_seqno = (thm_readl(THM_ITV) & ITV_ME_SEQNO_MASK) >>
990 ITV_ME_SEQNO_SHIFT;
991 seqno_timestamp = get_jiffies_64();
992
993 old_cpu_power = thm_readl(THM_CEC);
994 schedule_timeout_interruptible(msecs_to_jiffies(IPS_SAMPLE_PERIOD));
995
996 /* Collect an initial average */
997 for (i = 0; i < IPS_SAMPLE_COUNT; i++) {
998 u32 mchp, cpu_power;
999 u16 val;
1000
1001 mcp_samples[i] = read_ptv(ips);
1002
1003 val = read_ctv(ips, 0);
1004 ctv1_samples[i] = val;
1005
1006 val = read_ctv(ips, 1);
1007 ctv2_samples[i] = val;
1008
1009 val = read_mgtv(ips);
1010 mch_samples[i] = val;
1011
1012 cpu_power = get_cpu_power(ips, &old_cpu_power,
1013 IPS_SAMPLE_PERIOD);
1014 cpu_samples[i] = cpu_power;
1015
1016 if (ips->read_mch_val) {
1017 mchp = ips->read_mch_val();
1018 mchp_samples[i] = mchp;
1019 }
1020
1021 schedule_timeout_interruptible(msecs_to_jiffies(IPS_SAMPLE_PERIOD));
1022 if (kthread_should_stop())
1023 break;
1024 }
1025
1026 ips->mcp_avg_temp = calc_avg_temp(ips, mcp_samples);
1027 ips->ctv1_avg_temp = calc_avg_temp(ips, ctv1_samples);
1028 ips->ctv2_avg_temp = calc_avg_temp(ips, ctv2_samples);
1029 ips->mch_avg_temp = calc_avg_temp(ips, mch_samples);
1030 ips->cpu_avg_power = calc_avg_power(ips, cpu_samples);
1031 ips->mch_avg_power = calc_avg_power(ips, mchp_samples);
1032 kfree(mcp_samples);
1033 kfree(ctv1_samples);
1034 kfree(ctv2_samples);
1035 kfree(mch_samples);
1036 kfree(cpu_samples);
1037 kfree(mchp_samples);
1038
1039 /* Start the adjustment thread now that we have data */
1040 wake_up_process(ips->adjust);
1041
1042 /*
1043 * Ok, now we have an initial avg. From here on out, we track the
1044 * running avg using a decaying average calculation. This allows
1045 * us to reduce the sample frequency if the CPU and GPU are idle.
1046 */
1047 old_cpu_power = thm_readl(THM_CEC);
1048 schedule_timeout_interruptible(msecs_to_jiffies(IPS_SAMPLE_PERIOD));
1049 last_sample_period = IPS_SAMPLE_PERIOD;
1050
1051 setup_deferrable_timer_on_stack(&timer, monitor_timeout,
1052 (unsigned long)current);
1053 do {
1054 u32 cpu_val, mch_val;
1055 u16 val;
1056
1057 /* MCP itself */
1058 val = read_ptv(ips);
1059 ips->mcp_avg_temp = update_average_temp(ips->mcp_avg_temp, val);
1060
1061 /* Processor 0 */
1062 val = read_ctv(ips, 0);
1063 ips->ctv1_avg_temp =
1064 update_average_temp(ips->ctv1_avg_temp, val);
1065 /* Power */
1066 cpu_val = get_cpu_power(ips, &old_cpu_power,
1067 last_sample_period);
1068 ips->cpu_avg_power =
1069 update_average_power(ips->cpu_avg_power, cpu_val);
1070
1071 if (ips->second_cpu) {
1072 /* Processor 1 */
1073 val = read_ctv(ips, 1);
1074 ips->ctv2_avg_temp =
1075 update_average_temp(ips->ctv2_avg_temp, val);
1076 }
1077
1078 /* MCH */
1079 val = read_mgtv(ips);
1080 ips->mch_avg_temp = update_average_temp(ips->mch_avg_temp, val);
1081 /* Power */
1082 if (ips->read_mch_val) {
1083 mch_val = ips->read_mch_val();
1084 ips->mch_avg_power =
1085 update_average_power(ips->mch_avg_power,
1086 mch_val);
1087 }
1088
1089 /*
1090 * Make sure ME is updating thermal regs.
1091 * Note:
1092 * If it's been more than a second since the last update,
1093 * the ME is probably hung.
1094 */
1095 cur_seqno = (thm_readl(THM_ITV) & ITV_ME_SEQNO_MASK) >>
1096 ITV_ME_SEQNO_SHIFT;
1097 if (cur_seqno == last_seqno &&
1098 time_after(jiffies, seqno_timestamp + HZ)) {
1099 dev_warn(&ips->dev->dev, "ME failed to update for more than 1s, likely hung\n");
1100 } else {
1101 seqno_timestamp = get_jiffies_64();
1102 last_seqno = cur_seqno;
1103 }
1104
1105 last_msecs = jiffies_to_msecs(jiffies);
1106 expire = jiffies + msecs_to_jiffies(IPS_SAMPLE_PERIOD);
1107
1108 __set_current_state(TASK_INTERRUPTIBLE);
1109 mod_timer(&timer, expire);
1110 schedule();
1111
1112 /* Calculate actual sample period for power averaging */
1113 last_sample_period = jiffies_to_msecs(jiffies) - last_msecs;
1114 if (!last_sample_period)
1115 last_sample_period = 1;
1116 } while (!kthread_should_stop());
1117
1118 del_timer_sync(&timer);
1119 destroy_timer_on_stack(&timer);
1120
1121 dev_dbg(&ips->dev->dev, "ips-monitor thread stopped\n");
1122
1123 return 0;
1124}
1125
1126#if 0
1127#define THM_DUMPW(reg) \
1128 { \
1129 u16 val = thm_readw(reg); \
1130 dev_dbg(&ips->dev->dev, #reg ": 0x%04x\n", val); \
1131 }
1132#define THM_DUMPL(reg) \
1133 { \
1134 u32 val = thm_readl(reg); \
1135 dev_dbg(&ips->dev->dev, #reg ": 0x%08x\n", val); \
1136 }
1137#define THM_DUMPQ(reg) \
1138 { \
1139 u64 val = thm_readq(reg); \
1140 dev_dbg(&ips->dev->dev, #reg ": 0x%016x\n", val); \
1141 }
1142
1143static void dump_thermal_info(struct ips_driver *ips)
1144{
1145 u16 ptl;
1146
1147 ptl = thm_readw(THM_PTL);
1148 dev_dbg(&ips->dev->dev, "Processor temp limit: %d\n", ptl);
1149
1150 THM_DUMPW(THM_CTA);
1151 THM_DUMPW(THM_TRC);
1152 THM_DUMPW(THM_CTV1);
1153 THM_DUMPL(THM_STS);
1154 THM_DUMPW(THM_PTV);
1155 THM_DUMPQ(THM_MGTV);
1156}
1157#endif
1158
1159/**
1160 * ips_irq_handler - handle temperature triggers and other IPS events
1161 * @irq: irq number
1162 * @arg: unused
1163 *
1164 * Handle temperature limit trigger events, generally by lowering the clamps.
1165 * If we're at a critical limit, we clamp back to the lowest possible value
1166 * to prevent emergency shutdown.
1167 */
1168static irqreturn_t ips_irq_handler(int irq, void *arg)
1169{
1170 struct ips_driver *ips = arg;
1171 u8 tses = thm_readb(THM_TSES);
1172 u8 tes = thm_readb(THM_TES);
1173
1174 if (!tses && !tes)
1175 return IRQ_NONE;
1176
1177 dev_info(&ips->dev->dev, "TSES: 0x%02x\n", tses);
1178 dev_info(&ips->dev->dev, "TES: 0x%02x\n", tes);
1179
1180 /* STS update from EC? */
1181 if (tes & 1) {
1182 u32 sts, tc1;
1183
1184 sts = thm_readl(THM_STS);
1185 tc1 = thm_readl(THM_TC1);
1186
1187 if (sts & STS_NVV) {
1188 spin_lock(&ips->turbo_status_lock);
1189 ips->core_power_limit = (sts & STS_PCPL_MASK) >>
1190 STS_PCPL_SHIFT;
1191 ips->mch_power_limit = (sts & STS_GPL_MASK) >>
1192 STS_GPL_SHIFT;
1193 /* ignore EC CPU vs GPU pref */
1194 ips->cpu_turbo_enabled = !(sts & STS_PCTD_DIS);
1195 /*
1196 * Disable turbo for now, until we can figure
1197 * out why the power figures are wrong
1198 */
1199 ips->cpu_turbo_enabled = false;
1200 if (ips->gpu_busy)
1201 ips->gpu_turbo_enabled = !(sts & STS_GTD_DIS);
1202 ips->mcp_temp_limit = (sts & STS_PTL_MASK) >>
1203 STS_PTL_SHIFT;
1204 ips->mcp_power_limit = (tc1 & STS_PPL_MASK) >>
1205 STS_PPL_SHIFT;
1206 verify_limits(ips);
1207 spin_unlock(&ips->turbo_status_lock);
1208
1209 thm_writeb(THM_SEC, SEC_ACK);
1210 }
1211 thm_writeb(THM_TES, tes);
1212 }
1213
1214 /* Thermal trip */
1215 if (tses) {
1216 dev_warn(&ips->dev->dev,
1217 "thermal trip occurred, tses: 0x%04x\n", tses);
1218 thm_writeb(THM_TSES, tses);
1219 }
1220
1221 return IRQ_HANDLED;
1222}
1223
1224#ifndef CONFIG_DEBUG_FS
1225static void ips_debugfs_init(struct ips_driver *ips) { return; }
1226static void ips_debugfs_cleanup(struct ips_driver *ips) { return; }
1227#else
1228
1229/* Expose current state and limits in debugfs if possible */
1230
1231struct ips_debugfs_node {
1232 struct ips_driver *ips;
1233 char *name;
1234 int (*show)(struct seq_file *m, void *data);
1235};
1236
1237static int show_cpu_temp(struct seq_file *m, void *data)
1238{
1239 struct ips_driver *ips = m->private;
1240
1241 seq_printf(m, "%d.%02d\n", ips->ctv1_avg_temp / 100,
1242 ips->ctv1_avg_temp % 100);
1243
1244 return 0;
1245}
1246
1247static int show_cpu_power(struct seq_file *m, void *data)
1248{
1249 struct ips_driver *ips = m->private;
1250
1251 seq_printf(m, "%dmW\n", ips->cpu_avg_power);
1252
1253 return 0;
1254}
1255
1256static int show_cpu_clamp(struct seq_file *m, void *data)
1257{
1258 u64 turbo_override;
1259 int tdp, tdc;
1260
1261 rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override);
1262
1263 tdp = (int)(turbo_override & TURBO_TDP_MASK);
1264 tdc = (int)((turbo_override & TURBO_TDC_MASK) >> TURBO_TDC_SHIFT);
1265
1266 /* Convert to .1W/A units */
1267 tdp = tdp * 10 / 8;
1268 tdc = tdc * 10 / 8;
1269
1270 /* Watts Amperes */
1271 seq_printf(m, "%d.%dW %d.%dA\n", tdp / 10, tdp % 10,
1272 tdc / 10, tdc % 10);
1273
1274 return 0;
1275}
1276
1277static int show_mch_temp(struct seq_file *m, void *data)
1278{
1279 struct ips_driver *ips = m->private;
1280
1281 seq_printf(m, "%d.%02d\n", ips->mch_avg_temp / 100,
1282 ips->mch_avg_temp % 100);
1283
1284 return 0;
1285}
1286
1287static int show_mch_power(struct seq_file *m, void *data)
1288{
1289 struct ips_driver *ips = m->private;
1290
1291 seq_printf(m, "%dmW\n", ips->mch_avg_power);
1292
1293 return 0;
1294}
1295
1296static struct ips_debugfs_node ips_debug_files[] = {
1297 { NULL, "cpu_temp", show_cpu_temp },
1298 { NULL, "cpu_power", show_cpu_power },
1299 { NULL, "cpu_clamp", show_cpu_clamp },
1300 { NULL, "mch_temp", show_mch_temp },
1301 { NULL, "mch_power", show_mch_power },
1302};
1303
1304static int ips_debugfs_open(struct inode *inode, struct file *file)
1305{
1306 struct ips_debugfs_node *node = inode->i_private;
1307
1308 return single_open(file, node->show, node->ips);
1309}
1310
1311static const struct file_operations ips_debugfs_ops = {
1312 .owner = THIS_MODULE,
1313 .open = ips_debugfs_open,
1314 .read = seq_read,
1315 .llseek = seq_lseek,
1316 .release = single_release,
1317};
1318
1319static void ips_debugfs_cleanup(struct ips_driver *ips)
1320{
1321 if (ips->debug_root)
1322 debugfs_remove_recursive(ips->debug_root);
1323 return;
1324}
1325
1326static void ips_debugfs_init(struct ips_driver *ips)
1327{
1328 int i;
1329
1330 ips->debug_root = debugfs_create_dir("ips", NULL);
1331 if (!ips->debug_root) {
1332 dev_err(&ips->dev->dev,
1333 "failed to create debugfs entries: %ld\n",
1334 PTR_ERR(ips->debug_root));
1335 return;
1336 }
1337
1338 for (i = 0; i < ARRAY_SIZE(ips_debug_files); i++) {
1339 struct dentry *ent;
1340 struct ips_debugfs_node *node = &ips_debug_files[i];
1341
1342 node->ips = ips;
1343 ent = debugfs_create_file(node->name, S_IFREG | S_IRUGO,
1344 ips->debug_root, node,
1345 &ips_debugfs_ops);
1346 if (!ent) {
1347 dev_err(&ips->dev->dev,
1348 "failed to create debug file: %ld\n",
1349 PTR_ERR(ent));
1350 goto err_cleanup;
1351 }
1352 }
1353
1354 return;
1355
1356err_cleanup:
1357 ips_debugfs_cleanup(ips);
1358 return;
1359}
1360#endif /* CONFIG_DEBUG_FS */
1361
1362/**
1363 * ips_detect_cpu - detect whether CPU supports IPS
1364 *
1365 * Walk our list and see if we're on a supported CPU. If we find one,
1366 * return the limits for it.
1367 */
1368static struct ips_mcp_limits *ips_detect_cpu(struct ips_driver *ips)
1369{
1370 u64 turbo_power, misc_en;
1371 struct ips_mcp_limits *limits = NULL;
1372 u16 tdp;
1373
1374 if (!(boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 37)) {
1375 dev_info(&ips->dev->dev, "Non-IPS CPU detected.\n");
1376 goto out;
1377 }
1378
1379 rdmsrl(IA32_MISC_ENABLE, misc_en);
1380 /*
1381 * If the turbo enable bit isn't set, we shouldn't try to enable/disable
1382 * turbo manually or we'll get an illegal MSR access, even though
1383 * turbo will still be available.
1384 */
1385 if (misc_en & IA32_MISC_TURBO_EN)
1386 ips->turbo_toggle_allowed = true;
1387 else
1388 ips->turbo_toggle_allowed = false;
1389
1390 if (strstr(boot_cpu_data.x86_model_id, "CPU M"))
1391 limits = &ips_sv_limits;
1392 else if (strstr(boot_cpu_data.x86_model_id, "CPU L"))
1393 limits = &ips_lv_limits;
1394 else if (strstr(boot_cpu_data.x86_model_id, "CPU U"))
1395 limits = &ips_ulv_limits;
1396 else {
1397 dev_info(&ips->dev->dev, "No CPUID match found.\n");
1398 goto out;
1399 }
1400
1401 rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_power);
1402 tdp = turbo_power & TURBO_TDP_MASK;
1403
1404 /* Sanity check TDP against CPU */
1405 if (limits->core_power_limit != (tdp / 8) * 1000) {
1406 dev_info(&ips->dev->dev, "CPU TDP doesn't match expected value (found %d, expected %d)\n",
1407 tdp / 8, limits->core_power_limit / 1000);
1408 limits->core_power_limit = (tdp / 8) * 1000;
1409 }
1410
1411out:
1412 return limits;
1413}
1414
1415/**
1416 * ips_get_i915_syms - try to get GPU control methods from i915 driver
1417 * @ips: IPS driver
1418 *
1419 * The i915 driver exports several interfaces to allow the IPS driver to
1420 * monitor and control graphics turbo mode. If we can find them, we can
1421 * enable graphics turbo, otherwise we must disable it to avoid exceeding
1422 * thermal and power limits in the MCP.
1423 */
1424static bool ips_get_i915_syms(struct ips_driver *ips)
1425{
1426 ips->read_mch_val = symbol_get(i915_read_mch_val);
1427 if (!ips->read_mch_val)
1428 goto out_err;
1429 ips->gpu_raise = symbol_get(i915_gpu_raise);
1430 if (!ips->gpu_raise)
1431 goto out_put_mch;
1432 ips->gpu_lower = symbol_get(i915_gpu_lower);
1433 if (!ips->gpu_lower)
1434 goto out_put_raise;
1435 ips->gpu_busy = symbol_get(i915_gpu_busy);
1436 if (!ips->gpu_busy)
1437 goto out_put_lower;
1438 ips->gpu_turbo_disable = symbol_get(i915_gpu_turbo_disable);
1439 if (!ips->gpu_turbo_disable)
1440 goto out_put_busy;
1441
1442 return true;
1443
1444out_put_busy:
1445 symbol_put(i915_gpu_busy);
1446out_put_lower:
1447 symbol_put(i915_gpu_lower);
1448out_put_raise:
1449 symbol_put(i915_gpu_raise);
1450out_put_mch:
1451 symbol_put(i915_read_mch_val);
1452out_err:
1453 return false;
1454}
1455
1456static bool
1457ips_gpu_turbo_enabled(struct ips_driver *ips)
1458{
1459 if (!ips->gpu_busy && late_i915_load) {
1460 if (ips_get_i915_syms(ips)) {
1461 dev_info(&ips->dev->dev,
1462 "i915 driver attached, reenabling gpu turbo\n");
1463 ips->gpu_turbo_enabled = !(thm_readl(THM_HTS) & HTS_GTD_DIS);
1464 }
1465 }
1466
1467 return ips->gpu_turbo_enabled;
1468}
1469
1470void
1471ips_link_to_i915_driver(void)
1472{
1473 /* We can't cleanly get at the various ips_driver structs from
1474 * this caller (the i915 driver), so just set a flag saying
1475 * that it's time to try getting the symbols again.
1476 */
1477 late_i915_load = true;
1478}
1479EXPORT_SYMBOL_GPL(ips_link_to_i915_driver);
1480
1481static DEFINE_PCI_DEVICE_TABLE(ips_id_table) = {
1482 { PCI_DEVICE(PCI_VENDOR_ID_INTEL,
1483 PCI_DEVICE_ID_INTEL_THERMAL_SENSOR), },
1484 { 0, }
1485};
1486
1487MODULE_DEVICE_TABLE(pci, ips_id_table);
1488
1489static int ips_blacklist_callback(const struct dmi_system_id *id)
1490{
1491 pr_info("Blacklisted intel_ips for %s\n", id->ident);
1492 return 1;
1493}
1494
1495static const struct dmi_system_id ips_blacklist[] = {
1496 {
1497 .callback = ips_blacklist_callback,
1498 .ident = "HP ProBook",
1499 .matches = {
1500 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1501 DMI_MATCH(DMI_PRODUCT_NAME, "HP ProBook"),
1502 },
1503 },
1504 { } /* terminating entry */
1505};
1506
1507static int ips_probe(struct pci_dev *dev, const struct pci_device_id *id)
1508{
1509 u64 platform_info;
1510 struct ips_driver *ips;
1511 u32 hts;
1512 int ret = 0;
1513 u16 htshi, trc, trc_required_mask;
1514 u8 tse;
1515
1516 if (dmi_check_system(ips_blacklist))
1517 return -ENODEV;
1518
1519 ips = kzalloc(sizeof(struct ips_driver), GFP_KERNEL);
1520 if (!ips)
1521 return -ENOMEM;
1522
1523 pci_set_drvdata(dev, ips);
1524 ips->dev = dev;
1525
1526 ips->limits = ips_detect_cpu(ips);
1527 if (!ips->limits) {
1528 dev_info(&dev->dev, "IPS not supported on this CPU\n");
1529 ret = -ENXIO;
1530 goto error_free;
1531 }
1532
1533 spin_lock_init(&ips->turbo_status_lock);
1534
1535 ret = pci_enable_device(dev);
1536 if (ret) {
1537 dev_err(&dev->dev, "can't enable PCI device, aborting\n");
1538 goto error_free;
1539 }
1540
1541 if (!pci_resource_start(dev, 0)) {
1542 dev_err(&dev->dev, "TBAR not assigned, aborting\n");
1543 ret = -ENXIO;
1544 goto error_free;
1545 }
1546
1547 ret = pci_request_regions(dev, "ips thermal sensor");
1548 if (ret) {
1549 dev_err(&dev->dev, "thermal resource busy, aborting\n");
1550 goto error_free;
1551 }
1552
1553
1554 ips->regmap = ioremap(pci_resource_start(dev, 0),
1555 pci_resource_len(dev, 0));
1556 if (!ips->regmap) {
1557 dev_err(&dev->dev, "failed to map thermal regs, aborting\n");
1558 ret = -EBUSY;
1559 goto error_release;
1560 }
1561
1562 tse = thm_readb(THM_TSE);
1563 if (tse != TSE_EN) {
1564 dev_err(&dev->dev, "thermal device not enabled (0x%02x), aborting\n", tse);
1565 ret = -ENXIO;
1566 goto error_unmap;
1567 }
1568
1569 trc = thm_readw(THM_TRC);
1570 trc_required_mask = TRC_CORE1_EN | TRC_CORE_PWR | TRC_MCH_EN;
1571 if ((trc & trc_required_mask) != trc_required_mask) {
1572 dev_err(&dev->dev, "thermal reporting for required devices not enabled, aborting\n");
1573 ret = -ENXIO;
1574 goto error_unmap;
1575 }
1576
1577 if (trc & TRC_CORE2_EN)
1578 ips->second_cpu = true;
1579
1580 update_turbo_limits(ips);
1581 dev_dbg(&dev->dev, "max cpu power clamp: %dW\n",
1582 ips->mcp_power_limit / 10);
1583 dev_dbg(&dev->dev, "max core power clamp: %dW\n",
1584 ips->core_power_limit / 10);
1585 /* BIOS may update limits at runtime */
1586 if (thm_readl(THM_PSC) & PSP_PBRT)
1587 ips->poll_turbo_status = true;
1588
1589 if (!ips_get_i915_syms(ips)) {
1590 dev_info(&dev->dev, "failed to get i915 symbols, graphics turbo disabled until i915 loads\n");
1591 ips->gpu_turbo_enabled = false;
1592 } else {
1593 dev_dbg(&dev->dev, "graphics turbo enabled\n");
1594 ips->gpu_turbo_enabled = true;
1595 }
1596
1597 /*
1598 * Check PLATFORM_INFO MSR to make sure this chip is
1599 * turbo capable.
1600 */
1601 rdmsrl(PLATFORM_INFO, platform_info);
1602 if (!(platform_info & PLATFORM_TDP)) {
1603 dev_err(&dev->dev, "platform indicates TDP override unavailable, aborting\n");
1604 ret = -ENODEV;
1605 goto error_unmap;
1606 }
1607
1608 /*
1609 * IRQ handler for ME interaction
1610 * Note: don't use MSI here as the PCH has bugs.
1611 */
1612 pci_disable_msi(dev);
1613 ret = request_irq(dev->irq, ips_irq_handler, IRQF_SHARED, "ips",
1614 ips);
1615 if (ret) {
1616 dev_err(&dev->dev, "request irq failed, aborting\n");
1617 goto error_unmap;
1618 }
1619
1620 /* Enable aux, hot & critical interrupts */
1621 thm_writeb(THM_TSPIEN, TSPIEN_AUX2_LOHI | TSPIEN_CRIT_LOHI |
1622 TSPIEN_HOT_LOHI | TSPIEN_AUX_LOHI);
1623 thm_writeb(THM_TEN, TEN_UPDATE_EN);
1624
1625 /* Collect adjustment values */
1626 ips->cta_val = thm_readw(THM_CTA);
1627 ips->pta_val = thm_readw(THM_PTA);
1628 ips->mgta_val = thm_readw(THM_MGTA);
1629
1630 /* Save turbo limits & ratios */
1631 rdmsrl(TURBO_POWER_CURRENT_LIMIT, ips->orig_turbo_limit);
1632
1633 ips_disable_cpu_turbo(ips);
1634 ips->cpu_turbo_enabled = false;
1635
1636 /* Create thermal adjust thread */
1637 ips->adjust = kthread_create(ips_adjust, ips, "ips-adjust");
1638 if (IS_ERR(ips->adjust)) {
1639 dev_err(&dev->dev,
1640 "failed to create thermal adjust thread, aborting\n");
1641 ret = -ENOMEM;
1642 goto error_free_irq;
1643
1644 }
1645
1646 /*
1647 * Set up the work queue and monitor thread. The monitor thread
1648 * will wake up ips_adjust thread.
1649 */
1650 ips->monitor = kthread_run(ips_monitor, ips, "ips-monitor");
1651 if (IS_ERR(ips->monitor)) {
1652 dev_err(&dev->dev,
1653 "failed to create thermal monitor thread, aborting\n");
1654 ret = -ENOMEM;
1655 goto error_thread_cleanup;
1656 }
1657
1658 hts = (ips->core_power_limit << HTS_PCPL_SHIFT) |
1659 (ips->mcp_temp_limit << HTS_PTL_SHIFT) | HTS_NVV;
1660 htshi = HTS2_PRST_RUNNING << HTS2_PRST_SHIFT;
1661
1662 thm_writew(THM_HTSHI, htshi);
1663 thm_writel(THM_HTS, hts);
1664
1665 ips_debugfs_init(ips);
1666
1667 dev_info(&dev->dev, "IPS driver initialized, MCP temp limit %d\n",
1668 ips->mcp_temp_limit);
1669 return ret;
1670
1671error_thread_cleanup:
1672 kthread_stop(ips->adjust);
1673error_free_irq:
1674 free_irq(ips->dev->irq, ips);
1675error_unmap:
1676 iounmap(ips->regmap);
1677error_release:
1678 pci_release_regions(dev);
1679error_free:
1680 kfree(ips);
1681 return ret;
1682}
1683
1684static void ips_remove(struct pci_dev *dev)
1685{
1686 struct ips_driver *ips = pci_get_drvdata(dev);
1687 u64 turbo_override;
1688
1689 if (!ips)
1690 return;
1691
1692 ips_debugfs_cleanup(ips);
1693
1694 /* Release i915 driver */
1695 if (ips->read_mch_val)
1696 symbol_put(i915_read_mch_val);
1697 if (ips->gpu_raise)
1698 symbol_put(i915_gpu_raise);
1699 if (ips->gpu_lower)
1700 symbol_put(i915_gpu_lower);
1701 if (ips->gpu_busy)
1702 symbol_put(i915_gpu_busy);
1703 if (ips->gpu_turbo_disable)
1704 symbol_put(i915_gpu_turbo_disable);
1705
1706 rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override);
1707 turbo_override &= ~(TURBO_TDC_OVR_EN | TURBO_TDP_OVR_EN);
1708 wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override);
1709 wrmsrl(TURBO_POWER_CURRENT_LIMIT, ips->orig_turbo_limit);
1710
1711 free_irq(ips->dev->irq, ips);
1712 if (ips->adjust)
1713 kthread_stop(ips->adjust);
1714 if (ips->monitor)
1715 kthread_stop(ips->monitor);
1716 iounmap(ips->regmap);
1717 pci_release_regions(dev);
1718 kfree(ips);
1719 dev_dbg(&dev->dev, "IPS driver removed\n");
1720}
1721
1722static void ips_shutdown(struct pci_dev *dev)
1723{
1724}
1725
1726static struct pci_driver ips_pci_driver = {
1727 .name = "intel ips",
1728 .id_table = ips_id_table,
1729 .probe = ips_probe,
1730 .remove = ips_remove,
1731 .shutdown = ips_shutdown,
1732};
1733
1734module_pci_driver(ips_pci_driver);
1735
1736MODULE_LICENSE("GPL");
1737MODULE_AUTHOR("Jesse Barnes <jbarnes@virtuousgeek.org>");
1738MODULE_DESCRIPTION("Intelligent Power Sharing Driver");