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1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
32#include <linux/vmalloc.h>
33
34#include "../wifi.h"
35#include "../core.h"
36#include "../pci.h"
37#include "reg.h"
38#include "def.h"
39#include "phy.h"
40#include "dm.h"
41#include "fw.h"
42#include "hw.h"
43#include "sw.h"
44#include "trx.h"
45#include "led.h"
46
47static void rtl92s_init_aspm_vars(struct ieee80211_hw *hw)
48{
49 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
50
51 /*close ASPM for AMD defaultly */
52 rtlpci->const_amdpci_aspm = 0;
53
54 /*
55 * ASPM PS mode.
56 * 0 - Disable ASPM,
57 * 1 - Enable ASPM without Clock Req,
58 * 2 - Enable ASPM with Clock Req,
59 * 3 - Alwyas Enable ASPM with Clock Req,
60 * 4 - Always Enable ASPM without Clock Req.
61 * set defult to RTL8192CE:3 RTL8192E:2
62 * */
63 rtlpci->const_pci_aspm = 2;
64
65 /*Setting for PCI-E device */
66 rtlpci->const_devicepci_aspm_setting = 0x03;
67
68 /*Setting for PCI-E bridge */
69 rtlpci->const_hostpci_aspm_setting = 0x02;
70
71 /*
72 * In Hw/Sw Radio Off situation.
73 * 0 - Default,
74 * 1 - From ASPM setting without low Mac Pwr,
75 * 2 - From ASPM setting with low Mac Pwr,
76 * 3 - Bus D3
77 * set default to RTL8192CE:0 RTL8192SE:2
78 */
79 rtlpci->const_hwsw_rfoff_d3 = 2;
80
81 /*
82 * This setting works for those device with
83 * backdoor ASPM setting such as EPHY setting.
84 * 0 - Not support ASPM,
85 * 1 - Support ASPM,
86 * 2 - According to chipset.
87 */
88 rtlpci->const_support_pciaspm = 2;
89}
90
91static int rtl92s_init_sw_vars(struct ieee80211_hw *hw)
92{
93 struct rtl_priv *rtlpriv = rtl_priv(hw);
94 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
95 const struct firmware *firmware;
96 struct rt_firmware *pfirmware = NULL;
97 int err = 0;
98 u16 earlyrxthreshold = 7;
99
100 rtlpriv->dm.dm_initialgain_enable = 1;
101 rtlpriv->dm.dm_flag = 0;
102 rtlpriv->dm.disable_framebursting = 0;
103 rtlpriv->dm.thermalvalue = 0;
104 rtlpriv->dm.useramask = true;
105
106 /* compatible 5G band 91se just 2.4G band & smsp */
107 rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
108 rtlpriv->rtlhal.bandset = BAND_ON_2_4G;
109 rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;
110
111 rtlpci->transmit_config = 0;
112
113 rtlpci->receive_config =
114 RCR_APPFCS |
115 RCR_APWRMGT |
116 /*RCR_ADD3 |*/
117 RCR_AMF |
118 RCR_ADF |
119 RCR_APP_MIC |
120 RCR_APP_ICV |
121 RCR_AICV |
122 /* Accept ICV error, CRC32 Error */
123 RCR_ACRC32 |
124 RCR_AB |
125 /* Accept Broadcast, Multicast */
126 RCR_AM |
127 /* Accept Physical match */
128 RCR_APM |
129 /* Accept Destination Address packets */
130 /*RCR_AAP |*/
131 RCR_APP_PHYST_STAFF |
132 /* Accept PHY status */
133 RCR_APP_PHYST_RXFF |
134 (earlyrxthreshold << RCR_FIFO_OFFSET);
135
136 rtlpci->irq_mask[0] = (u32)
137 (IMR_ROK |
138 IMR_VODOK |
139 IMR_VIDOK |
140 IMR_BEDOK |
141 IMR_BKDOK |
142 IMR_HCCADOK |
143 IMR_MGNTDOK |
144 IMR_COMDOK |
145 IMR_HIGHDOK |
146 IMR_BDOK |
147 IMR_RXCMDOK |
148 /*IMR_TIMEOUT0 |*/
149 IMR_RDU |
150 IMR_RXFOVW |
151 IMR_BCNINT
152 /*| IMR_TXFOVW*/
153 /*| IMR_TBDOK |
154 IMR_TBDER*/);
155
156 rtlpci->irq_mask[1] = (u32) 0;
157
158 rtlpci->shortretry_limit = 0x30;
159 rtlpci->longretry_limit = 0x30;
160
161 rtlpci->first_init = true;
162
163 /* for LPS & IPS */
164 rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
165 rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
166 rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
167 rtlpriv->psc.reg_fwctrl_lps = 3;
168 rtlpriv->psc.reg_max_lps_awakeintvl = 5;
169 /* for ASPM, you can close aspm through
170 * set const_support_pciaspm = 0 */
171 rtl92s_init_aspm_vars(hw);
172
173 if (rtlpriv->psc.reg_fwctrl_lps == 1)
174 rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
175 else if (rtlpriv->psc.reg_fwctrl_lps == 2)
176 rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
177 else if (rtlpriv->psc.reg_fwctrl_lps == 3)
178 rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
179
180 /* for firmware buf */
181 rtlpriv->rtlhal.pfirmware = vzalloc(sizeof(struct rt_firmware));
182 if (!rtlpriv->rtlhal.pfirmware) {
183 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
184 ("Can't alloc buffer for fw.\n"));
185 return 1;
186 }
187
188 pr_info("Driver for Realtek RTL8192SE/RTL8191SE\n"
189 "Loading firmware %s\n", rtlpriv->cfg->fw_name);
190 /* request fw */
191 err = request_firmware(&firmware, rtlpriv->cfg->fw_name,
192 rtlpriv->io.dev);
193 if (err) {
194 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
195 ("Failed to request firmware!\n"));
196 return 1;
197 }
198 if (firmware->size > sizeof(struct rt_firmware)) {
199 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
200 ("Firmware is too big!\n"));
201 release_firmware(firmware);
202 return 1;
203 }
204
205 pfirmware = (struct rt_firmware *)rtlpriv->rtlhal.pfirmware;
206 memcpy(pfirmware->sz_fw_tmpbuffer, firmware->data, firmware->size);
207 pfirmware->sz_fw_tmpbufferlen = firmware->size;
208 release_firmware(firmware);
209
210 return err;
211}
212
213static void rtl92s_deinit_sw_vars(struct ieee80211_hw *hw)
214{
215 struct rtl_priv *rtlpriv = rtl_priv(hw);
216
217 if (rtlpriv->rtlhal.pfirmware) {
218 vfree(rtlpriv->rtlhal.pfirmware);
219 rtlpriv->rtlhal.pfirmware = NULL;
220 }
221}
222
223static struct rtl_hal_ops rtl8192se_hal_ops = {
224 .init_sw_vars = rtl92s_init_sw_vars,
225 .deinit_sw_vars = rtl92s_deinit_sw_vars,
226 .read_eeprom_info = rtl92se_read_eeprom_info,
227 .interrupt_recognized = rtl92se_interrupt_recognized,
228 .hw_init = rtl92se_hw_init,
229 .hw_disable = rtl92se_card_disable,
230 .hw_suspend = rtl92se_suspend,
231 .hw_resume = rtl92se_resume,
232 .enable_interrupt = rtl92se_enable_interrupt,
233 .disable_interrupt = rtl92se_disable_interrupt,
234 .set_network_type = rtl92se_set_network_type,
235 .set_chk_bssid = rtl92se_set_check_bssid,
236 .set_qos = rtl92se_set_qos,
237 .set_bcn_reg = rtl92se_set_beacon_related_registers,
238 .set_bcn_intv = rtl92se_set_beacon_interval,
239 .update_interrupt_mask = rtl92se_update_interrupt_mask,
240 .get_hw_reg = rtl92se_get_hw_reg,
241 .set_hw_reg = rtl92se_set_hw_reg,
242 .update_rate_tbl = rtl92se_update_hal_rate_tbl,
243 .fill_tx_desc = rtl92se_tx_fill_desc,
244 .fill_tx_cmddesc = rtl92se_tx_fill_cmddesc,
245 .query_rx_desc = rtl92se_rx_query_desc,
246 .set_channel_access = rtl92se_update_channel_access_setting,
247 .radio_onoff_checking = rtl92se_gpio_radio_on_off_checking,
248 .set_bw_mode = rtl92s_phy_set_bw_mode,
249 .switch_channel = rtl92s_phy_sw_chnl,
250 .dm_watchdog = rtl92s_dm_watchdog,
251 .scan_operation_backup = rtl92s_phy_scan_operation_backup,
252 .set_rf_power_state = rtl92s_phy_set_rf_power_state,
253 .led_control = rtl92se_led_control,
254 .set_desc = rtl92se_set_desc,
255 .get_desc = rtl92se_get_desc,
256 .tx_polling = rtl92se_tx_polling,
257 .enable_hw_sec = rtl92se_enable_hw_security_config,
258 .set_key = rtl92se_set_key,
259 .init_sw_leds = rtl92se_init_sw_leds,
260 .get_bbreg = rtl92s_phy_query_bb_reg,
261 .set_bbreg = rtl92s_phy_set_bb_reg,
262 .get_rfreg = rtl92s_phy_query_rf_reg,
263 .set_rfreg = rtl92s_phy_set_rf_reg,
264};
265
266static struct rtl_mod_params rtl92se_mod_params = {
267 .sw_crypto = false,
268 .inactiveps = true,
269 .swctrl_lps = true,
270 .fwctrl_lps = false,
271};
272
273/* Because memory R/W bursting will cause system hang/crash
274 * for 92se, so we don't read back after every write action */
275static struct rtl_hal_cfg rtl92se_hal_cfg = {
276 .bar_id = 1,
277 .write_readback = false,
278 .name = "rtl92s_pci",
279 .fw_name = "rtlwifi/rtl8192sefw.bin",
280 .ops = &rtl8192se_hal_ops,
281 .mod_params = &rtl92se_mod_params,
282
283 .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
284 .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
285 .maps[SYS_CLK] = SYS_CLKR,
286 .maps[MAC_RCR_AM] = RCR_AM,
287 .maps[MAC_RCR_AB] = RCR_AB,
288 .maps[MAC_RCR_ACRC32] = RCR_ACRC32,
289 .maps[MAC_RCR_ACF] = RCR_ACF,
290 .maps[MAC_RCR_AAP] = RCR_AAP,
291
292 .maps[EFUSE_TEST] = REG_EFUSE_TEST,
293 .maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
294 .maps[EFUSE_CLK] = REG_EFUSE_CLK,
295 .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
296 .maps[EFUSE_PWC_EV12V] = 0, /* nouse for 8192se */
297 .maps[EFUSE_FEN_ELDR] = 0, /* nouse for 8192se */
298 .maps[EFUSE_LOADER_CLK_EN] = 0,/* nouse for 8192se */
299 .maps[EFUSE_ANA8M] = EFUSE_ANA8M,
300 .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE_92S,
301 .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
302 .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
303
304 .maps[RWCAM] = REG_RWCAM,
305 .maps[WCAMI] = REG_WCAMI,
306 .maps[RCAMO] = REG_RCAMO,
307 .maps[CAMDBG] = REG_CAMDBG,
308 .maps[SECR] = REG_SECR,
309 .maps[SEC_CAM_NONE] = CAM_NONE,
310 .maps[SEC_CAM_WEP40] = CAM_WEP40,
311 .maps[SEC_CAM_TKIP] = CAM_TKIP,
312 .maps[SEC_CAM_AES] = CAM_AES,
313 .maps[SEC_CAM_WEP104] = CAM_WEP104,
314
315 .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
316 .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
317 .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
318 .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
319 .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
320 .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
321 .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8,
322 .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
323 .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
324 .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
325 .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
326 .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
327 .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
328 .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
329 .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,
330 .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,
331
332 .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
333 .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
334 .maps[RTL_IMR_BcnInt] = IMR_BCNINT,
335 .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
336 .maps[RTL_IMR_RDU] = IMR_RDU,
337 .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
338 .maps[RTL_IMR_BDOK] = IMR_BDOK,
339 .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
340 .maps[RTL_IMR_TBDER] = IMR_TBDER,
341 .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
342 .maps[RTL_IMR_COMDOK] = IMR_COMDOK,
343 .maps[RTL_IMR_TBDOK] = IMR_TBDOK,
344 .maps[RTL_IMR_BKDOK] = IMR_BKDOK,
345 .maps[RTL_IMR_BEDOK] = IMR_BEDOK,
346 .maps[RTL_IMR_VIDOK] = IMR_VIDOK,
347 .maps[RTL_IMR_VODOK] = IMR_VODOK,
348 .maps[RTL_IMR_ROK] = IMR_ROK,
349 .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNINT | IMR_TBDOK | IMR_TBDER),
350
351 .maps[RTL_RC_CCK_RATE1M] = DESC92S_RATE1M,
352 .maps[RTL_RC_CCK_RATE2M] = DESC92S_RATE2M,
353 .maps[RTL_RC_CCK_RATE5_5M] = DESC92S_RATE5_5M,
354 .maps[RTL_RC_CCK_RATE11M] = DESC92S_RATE11M,
355 .maps[RTL_RC_OFDM_RATE6M] = DESC92S_RATE6M,
356 .maps[RTL_RC_OFDM_RATE9M] = DESC92S_RATE9M,
357 .maps[RTL_RC_OFDM_RATE12M] = DESC92S_RATE12M,
358 .maps[RTL_RC_OFDM_RATE18M] = DESC92S_RATE18M,
359 .maps[RTL_RC_OFDM_RATE24M] = DESC92S_RATE24M,
360 .maps[RTL_RC_OFDM_RATE36M] = DESC92S_RATE36M,
361 .maps[RTL_RC_OFDM_RATE48M] = DESC92S_RATE48M,
362 .maps[RTL_RC_OFDM_RATE54M] = DESC92S_RATE54M,
363
364 .maps[RTL_RC_HT_RATEMCS7] = DESC92S_RATEMCS7,
365 .maps[RTL_RC_HT_RATEMCS15] = DESC92S_RATEMCS15,
366};
367
368static struct pci_device_id rtl92se_pci_ids[] __devinitdata = {
369 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8192, rtl92se_hal_cfg)},
370 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8171, rtl92se_hal_cfg)},
371 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8172, rtl92se_hal_cfg)},
372 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8173, rtl92se_hal_cfg)},
373 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8174, rtl92se_hal_cfg)},
374 {},
375};
376
377MODULE_DEVICE_TABLE(pci, rtl92se_pci_ids);
378
379MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>");
380MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
381MODULE_LICENSE("GPL");
382MODULE_DESCRIPTION("Realtek 8192S/8191S 802.11n PCI wireless");
383MODULE_FIRMWARE("rtlwifi/rtl8192sefw.bin");
384
385module_param_named(swenc, rtl92se_mod_params.sw_crypto, bool, 0444);
386module_param_named(ips, rtl92se_mod_params.inactiveps, bool, 0444);
387module_param_named(swlps, rtl92se_mod_params.swctrl_lps, bool, 0444);
388module_param_named(fwlps, rtl92se_mod_params.fwctrl_lps, bool, 0444);
389MODULE_PARM_DESC(swenc, "using hardware crypto (default 0 [hardware])\n");
390MODULE_PARM_DESC(ips, "using no link power save (default 1 is open)\n");
391MODULE_PARM_DESC(swlps, "using linked sw control power save (default 1 is "
392 "open)\n");
393
394
395static struct pci_driver rtl92se_driver = {
396 .name = KBUILD_MODNAME,
397 .id_table = rtl92se_pci_ids,
398 .probe = rtl_pci_probe,
399 .remove = rtl_pci_disconnect,
400
401#ifdef CONFIG_PM
402 .suspend = rtl_pci_suspend,
403 .resume = rtl_pci_resume,
404#endif
405
406};
407
408static int __init rtl92se_module_init(void)
409{
410 int ret = 0;
411
412 ret = pci_register_driver(&rtl92se_driver);
413 if (ret)
414 RT_ASSERT(false, (": No device found\n"));
415
416 return ret;
417}
418
419static void __exit rtl92se_module_exit(void)
420{
421 pci_unregister_driver(&rtl92se_driver);
422}
423
424module_init(rtl92se_module_init);
425module_exit(rtl92se_module_exit);
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2012 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "../core.h"
32#include "../base.h"
33#include "../pci.h"
34#include "reg.h"
35#include "def.h"
36#include "phy.h"
37#include "dm.h"
38#include "fw.h"
39#include "hw.h"
40#include "sw.h"
41#include "trx.h"
42#include "led.h"
43
44#include <linux/module.h>
45
46static void rtl92s_init_aspm_vars(struct ieee80211_hw *hw)
47{
48 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
49
50 /*close ASPM for AMD defaultly */
51 rtlpci->const_amdpci_aspm = 0;
52
53 /* ASPM PS mode.
54 * 0 - Disable ASPM,
55 * 1 - Enable ASPM without Clock Req,
56 * 2 - Enable ASPM with Clock Req,
57 * 3 - Alwyas Enable ASPM with Clock Req,
58 * 4 - Always Enable ASPM without Clock Req.
59 * set defult to RTL8192CE:3 RTL8192E:2
60 * */
61 rtlpci->const_pci_aspm = 2;
62
63 /*Setting for PCI-E device */
64 rtlpci->const_devicepci_aspm_setting = 0x03;
65
66 /*Setting for PCI-E bridge */
67 rtlpci->const_hostpci_aspm_setting = 0x02;
68
69 /* In Hw/Sw Radio Off situation.
70 * 0 - Default,
71 * 1 - From ASPM setting without low Mac Pwr,
72 * 2 - From ASPM setting with low Mac Pwr,
73 * 3 - Bus D3
74 * set default to RTL8192CE:0 RTL8192SE:2
75 */
76 rtlpci->const_hwsw_rfoff_d3 = 2;
77
78 /* This setting works for those device with
79 * backdoor ASPM setting such as EPHY setting.
80 * 0 - Not support ASPM,
81 * 1 - Support ASPM,
82 * 2 - According to chipset.
83 */
84 rtlpci->const_support_pciaspm = 2;
85}
86
87static void rtl92se_fw_cb(const struct firmware *firmware, void *context)
88{
89 struct ieee80211_hw *hw = context;
90 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
91 struct rtl_priv *rtlpriv = rtl_priv(hw);
92 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
93 struct rt_firmware *pfirmware = NULL;
94 int err;
95
96 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
97 "Firmware callback routine entered!\n");
98 complete(&rtlpriv->firmware_loading_complete);
99 if (!firmware) {
100 pr_err("Firmware %s not available\n", rtlpriv->cfg->fw_name);
101 rtlpriv->max_fw_size = 0;
102 return;
103 }
104 if (firmware->size > rtlpriv->max_fw_size) {
105 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
106 "Firmware is too big!\n");
107 rtlpriv->max_fw_size = 0;
108 release_firmware(firmware);
109 return;
110 }
111 pfirmware = (struct rt_firmware *)rtlpriv->rtlhal.pfirmware;
112 memcpy(pfirmware->sz_fw_tmpbuffer, firmware->data, firmware->size);
113 pfirmware->sz_fw_tmpbufferlen = firmware->size;
114 release_firmware(firmware);
115
116 err = ieee80211_register_hw(hw);
117 if (err) {
118 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
119 "Can't register mac80211 hw\n");
120 return;
121 } else {
122 rtlpriv->mac80211.mac80211_registered = 1;
123 }
124 rtlpci->irq_alloc = 1;
125 set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
126
127 /*init rfkill */
128 rtl_init_rfkill(hw);
129}
130
131static int rtl92s_init_sw_vars(struct ieee80211_hw *hw)
132{
133 struct rtl_priv *rtlpriv = rtl_priv(hw);
134 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
135 int err = 0;
136 u16 earlyrxthreshold = 7;
137
138 rtlpriv->dm.dm_initialgain_enable = true;
139 rtlpriv->dm.dm_flag = 0;
140 rtlpriv->dm.disable_framebursting = false;
141 rtlpriv->dm.thermalvalue = 0;
142 rtlpriv->dm.useramask = true;
143
144 /* compatible 5G band 91se just 2.4G band & smsp */
145 rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
146 rtlpriv->rtlhal.bandset = BAND_ON_2_4G;
147 rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;
148
149 rtlpci->transmit_config = 0;
150
151 rtlpci->receive_config =
152 RCR_APPFCS |
153 RCR_APWRMGT |
154 /*RCR_ADD3 |*/
155 RCR_AMF |
156 RCR_ADF |
157 RCR_APP_MIC |
158 RCR_APP_ICV |
159 RCR_AICV |
160 /* Accept ICV error, CRC32 Error */
161 RCR_ACRC32 |
162 RCR_AB |
163 /* Accept Broadcast, Multicast */
164 RCR_AM |
165 /* Accept Physical match */
166 RCR_APM |
167 /* Accept Destination Address packets */
168 /*RCR_AAP |*/
169 RCR_APP_PHYST_STAFF |
170 /* Accept PHY status */
171 RCR_APP_PHYST_RXFF |
172 (earlyrxthreshold << RCR_FIFO_OFFSET);
173
174 rtlpci->irq_mask[0] = (u32)
175 (IMR_ROK |
176 IMR_VODOK |
177 IMR_VIDOK |
178 IMR_BEDOK |
179 IMR_BKDOK |
180 IMR_HCCADOK |
181 IMR_MGNTDOK |
182 IMR_COMDOK |
183 IMR_HIGHDOK |
184 IMR_BDOK |
185 IMR_RXCMDOK |
186 /*IMR_TIMEOUT0 |*/
187 IMR_RDU |
188 IMR_RXFOVW |
189 IMR_BCNINT
190 /*| IMR_TXFOVW*/
191 /*| IMR_TBDOK |
192 IMR_TBDER*/);
193
194 rtlpci->irq_mask[1] = (u32) 0;
195
196 rtlpci->shortretry_limit = 0x30;
197 rtlpci->longretry_limit = 0x30;
198
199 rtlpci->first_init = true;
200
201 /* for debug level */
202 rtlpriv->dbg.global_debuglevel = rtlpriv->cfg->mod_params->debug;
203 /* for LPS & IPS */
204 rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
205 rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
206 rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
207 if (!rtlpriv->psc.inactiveps)
208 pr_info("Power Save off (module option)\n");
209 if (!rtlpriv->psc.fwctrl_lps)
210 pr_info("FW Power Save off (module option)\n");
211 rtlpriv->psc.reg_fwctrl_lps = 3;
212 rtlpriv->psc.reg_max_lps_awakeintvl = 5;
213 /* for ASPM, you can close aspm through
214 * set const_support_pciaspm = 0 */
215 rtl92s_init_aspm_vars(hw);
216
217 if (rtlpriv->psc.reg_fwctrl_lps == 1)
218 rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
219 else if (rtlpriv->psc.reg_fwctrl_lps == 2)
220 rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
221 else if (rtlpriv->psc.reg_fwctrl_lps == 3)
222 rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
223
224 /* for firmware buf */
225 rtlpriv->rtlhal.pfirmware = vzalloc(sizeof(struct rt_firmware));
226 if (!rtlpriv->rtlhal.pfirmware)
227 return 1;
228
229 rtlpriv->max_fw_size = RTL8190_MAX_RAW_FIRMWARE_CODE_SIZE;
230
231 pr_info("Driver for Realtek RTL8192SE/RTL8191SE\n"
232 "Loading firmware %s\n", rtlpriv->cfg->fw_name);
233 /* request fw */
234 err = request_firmware_nowait(THIS_MODULE, 1, rtlpriv->cfg->fw_name,
235 rtlpriv->io.dev, GFP_KERNEL, hw,
236 rtl92se_fw_cb);
237 if (err) {
238 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
239 "Failed to request firmware!\n");
240 return 1;
241 }
242
243 return err;
244}
245
246static void rtl92s_deinit_sw_vars(struct ieee80211_hw *hw)
247{
248 struct rtl_priv *rtlpriv = rtl_priv(hw);
249
250 if (rtlpriv->rtlhal.pfirmware) {
251 vfree(rtlpriv->rtlhal.pfirmware);
252 rtlpriv->rtlhal.pfirmware = NULL;
253 }
254}
255
256static struct rtl_hal_ops rtl8192se_hal_ops = {
257 .init_sw_vars = rtl92s_init_sw_vars,
258 .deinit_sw_vars = rtl92s_deinit_sw_vars,
259 .read_eeprom_info = rtl92se_read_eeprom_info,
260 .interrupt_recognized = rtl92se_interrupt_recognized,
261 .hw_init = rtl92se_hw_init,
262 .hw_disable = rtl92se_card_disable,
263 .hw_suspend = rtl92se_suspend,
264 .hw_resume = rtl92se_resume,
265 .enable_interrupt = rtl92se_enable_interrupt,
266 .disable_interrupt = rtl92se_disable_interrupt,
267 .set_network_type = rtl92se_set_network_type,
268 .set_chk_bssid = rtl92se_set_check_bssid,
269 .set_qos = rtl92se_set_qos,
270 .set_bcn_reg = rtl92se_set_beacon_related_registers,
271 .set_bcn_intv = rtl92se_set_beacon_interval,
272 .update_interrupt_mask = rtl92se_update_interrupt_mask,
273 .get_hw_reg = rtl92se_get_hw_reg,
274 .set_hw_reg = rtl92se_set_hw_reg,
275 .update_rate_tbl = rtl92se_update_hal_rate_tbl,
276 .fill_tx_desc = rtl92se_tx_fill_desc,
277 .fill_tx_cmddesc = rtl92se_tx_fill_cmddesc,
278 .query_rx_desc = rtl92se_rx_query_desc,
279 .set_channel_access = rtl92se_update_channel_access_setting,
280 .radio_onoff_checking = rtl92se_gpio_radio_on_off_checking,
281 .set_bw_mode = rtl92s_phy_set_bw_mode,
282 .switch_channel = rtl92s_phy_sw_chnl,
283 .dm_watchdog = rtl92s_dm_watchdog,
284 .scan_operation_backup = rtl92s_phy_scan_operation_backup,
285 .set_rf_power_state = rtl92s_phy_set_rf_power_state,
286 .led_control = rtl92se_led_control,
287 .set_desc = rtl92se_set_desc,
288 .get_desc = rtl92se_get_desc,
289 .tx_polling = rtl92se_tx_polling,
290 .enable_hw_sec = rtl92se_enable_hw_security_config,
291 .set_key = rtl92se_set_key,
292 .init_sw_leds = rtl92se_init_sw_leds,
293 .allow_all_destaddr = rtl92se_allow_all_destaddr,
294 .get_bbreg = rtl92s_phy_query_bb_reg,
295 .set_bbreg = rtl92s_phy_set_bb_reg,
296 .get_rfreg = rtl92s_phy_query_rf_reg,
297 .set_rfreg = rtl92s_phy_set_rf_reg,
298};
299
300static struct rtl_mod_params rtl92se_mod_params = {
301 .sw_crypto = false,
302 .inactiveps = true,
303 .swctrl_lps = true,
304 .fwctrl_lps = false,
305 .debug = DBG_EMERG,
306};
307
308/* Because memory R/W bursting will cause system hang/crash
309 * for 92se, so we don't read back after every write action */
310static struct rtl_hal_cfg rtl92se_hal_cfg = {
311 .bar_id = 1,
312 .write_readback = false,
313 .name = "rtl92s_pci",
314 .fw_name = "rtlwifi/rtl8192sefw.bin",
315 .ops = &rtl8192se_hal_ops,
316 .mod_params = &rtl92se_mod_params,
317
318 .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
319 .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
320 .maps[SYS_CLK] = SYS_CLKR,
321 .maps[MAC_RCR_AM] = RCR_AM,
322 .maps[MAC_RCR_AB] = RCR_AB,
323 .maps[MAC_RCR_ACRC32] = RCR_ACRC32,
324 .maps[MAC_RCR_ACF] = RCR_ACF,
325 .maps[MAC_RCR_AAP] = RCR_AAP,
326
327 .maps[EFUSE_TEST] = REG_EFUSE_TEST,
328 .maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
329 .maps[EFUSE_CLK] = REG_EFUSE_CLK,
330 .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
331 .maps[EFUSE_PWC_EV12V] = 0, /* nouse for 8192se */
332 .maps[EFUSE_FEN_ELDR] = 0, /* nouse for 8192se */
333 .maps[EFUSE_LOADER_CLK_EN] = 0,/* nouse for 8192se */
334 .maps[EFUSE_ANA8M] = EFUSE_ANA8M,
335 .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE_92S,
336 .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
337 .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
338 .maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES,
339
340 .maps[RWCAM] = REG_RWCAM,
341 .maps[WCAMI] = REG_WCAMI,
342 .maps[RCAMO] = REG_RCAMO,
343 .maps[CAMDBG] = REG_CAMDBG,
344 .maps[SECR] = REG_SECR,
345 .maps[SEC_CAM_NONE] = CAM_NONE,
346 .maps[SEC_CAM_WEP40] = CAM_WEP40,
347 .maps[SEC_CAM_TKIP] = CAM_TKIP,
348 .maps[SEC_CAM_AES] = CAM_AES,
349 .maps[SEC_CAM_WEP104] = CAM_WEP104,
350
351 .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
352 .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
353 .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
354 .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
355 .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
356 .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
357 .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8,
358 .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
359 .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
360 .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
361 .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
362 .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
363 .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
364 .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
365 .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,
366 .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,
367
368 .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
369 .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
370 .maps[RTL_IMR_BCNINT] = IMR_BCNINT,
371 .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
372 .maps[RTL_IMR_RDU] = IMR_RDU,
373 .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
374 .maps[RTL_IMR_BDOK] = IMR_BDOK,
375 .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
376 .maps[RTL_IMR_TBDER] = IMR_TBDER,
377 .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
378 .maps[RTL_IMR_COMDOK] = IMR_COMDOK,
379 .maps[RTL_IMR_TBDOK] = IMR_TBDOK,
380 .maps[RTL_IMR_BKDOK] = IMR_BKDOK,
381 .maps[RTL_IMR_BEDOK] = IMR_BEDOK,
382 .maps[RTL_IMR_VIDOK] = IMR_VIDOK,
383 .maps[RTL_IMR_VODOK] = IMR_VODOK,
384 .maps[RTL_IMR_ROK] = IMR_ROK,
385 .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNINT | IMR_TBDOK | IMR_TBDER),
386
387 .maps[RTL_RC_CCK_RATE1M] = DESC92_RATE1M,
388 .maps[RTL_RC_CCK_RATE2M] = DESC92_RATE2M,
389 .maps[RTL_RC_CCK_RATE5_5M] = DESC92_RATE5_5M,
390 .maps[RTL_RC_CCK_RATE11M] = DESC92_RATE11M,
391 .maps[RTL_RC_OFDM_RATE6M] = DESC92_RATE6M,
392 .maps[RTL_RC_OFDM_RATE9M] = DESC92_RATE9M,
393 .maps[RTL_RC_OFDM_RATE12M] = DESC92_RATE12M,
394 .maps[RTL_RC_OFDM_RATE18M] = DESC92_RATE18M,
395 .maps[RTL_RC_OFDM_RATE24M] = DESC92_RATE24M,
396 .maps[RTL_RC_OFDM_RATE36M] = DESC92_RATE36M,
397 .maps[RTL_RC_OFDM_RATE48M] = DESC92_RATE48M,
398 .maps[RTL_RC_OFDM_RATE54M] = DESC92_RATE54M,
399
400 .maps[RTL_RC_HT_RATEMCS7] = DESC92_RATEMCS7,
401 .maps[RTL_RC_HT_RATEMCS15] = DESC92_RATEMCS15,
402};
403
404static struct pci_device_id rtl92se_pci_ids[] = {
405 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8192, rtl92se_hal_cfg)},
406 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8171, rtl92se_hal_cfg)},
407 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8172, rtl92se_hal_cfg)},
408 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8173, rtl92se_hal_cfg)},
409 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8174, rtl92se_hal_cfg)},
410 {},
411};
412
413MODULE_DEVICE_TABLE(pci, rtl92se_pci_ids);
414
415MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>");
416MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
417MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>");
418MODULE_LICENSE("GPL");
419MODULE_DESCRIPTION("Realtek 8192S/8191S 802.11n PCI wireless");
420MODULE_FIRMWARE("rtlwifi/rtl8192sefw.bin");
421
422module_param_named(swenc, rtl92se_mod_params.sw_crypto, bool, 0444);
423module_param_named(debug, rtl92se_mod_params.debug, int, 0444);
424module_param_named(ips, rtl92se_mod_params.inactiveps, bool, 0444);
425module_param_named(swlps, rtl92se_mod_params.swctrl_lps, bool, 0444);
426module_param_named(fwlps, rtl92se_mod_params.fwctrl_lps, bool, 0444);
427MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
428MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
429MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n");
430MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n");
431MODULE_PARM_DESC(debug, "Set debug level (0-5) (default 0)");
432
433static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);
434
435static struct pci_driver rtl92se_driver = {
436 .name = KBUILD_MODNAME,
437 .id_table = rtl92se_pci_ids,
438 .probe = rtl_pci_probe,
439 .remove = rtl_pci_disconnect,
440 .driver.pm = &rtlwifi_pm_ops,
441};
442
443module_pci_driver(rtl92se_driver);