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1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
32#include "../wifi.h"
33#include "../efuse.h"
34#include "../base.h"
35#include "../cam.h"
36#include "../ps.h"
37#include "../usb.h"
38#include "reg.h"
39#include "def.h"
40#include "phy.h"
41#include "mac.h"
42#include "dm.h"
43#include "hw.h"
44#include "../rtl8192ce/hw.h"
45#include "trx.h"
46#include "led.h"
47#include "table.h"
48
49static void _rtl92cu_phy_param_tab_init(struct ieee80211_hw *hw)
50{
51 struct rtl_priv *rtlpriv = rtl_priv(hw);
52 struct rtl_phy *rtlphy = &(rtlpriv->phy);
53 struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv);
54
55 rtlphy->hwparam_tables[MAC_REG].length = RTL8192CUMAC_2T_ARRAYLENGTH;
56 rtlphy->hwparam_tables[MAC_REG].pdata = RTL8192CUMAC_2T_ARRAY;
57 if (IS_HIGHT_PA(rtlefuse->board_type)) {
58 rtlphy->hwparam_tables[PHY_REG_PG].length =
59 RTL8192CUPHY_REG_Array_PG_HPLength;
60 rtlphy->hwparam_tables[PHY_REG_PG].pdata =
61 RTL8192CUPHY_REG_Array_PG_HP;
62 } else {
63 rtlphy->hwparam_tables[PHY_REG_PG].length =
64 RTL8192CUPHY_REG_ARRAY_PGLENGTH;
65 rtlphy->hwparam_tables[PHY_REG_PG].pdata =
66 RTL8192CUPHY_REG_ARRAY_PG;
67 }
68 /* 2T */
69 rtlphy->hwparam_tables[PHY_REG_2T].length =
70 RTL8192CUPHY_REG_2TARRAY_LENGTH;
71 rtlphy->hwparam_tables[PHY_REG_2T].pdata =
72 RTL8192CUPHY_REG_2TARRAY;
73 rtlphy->hwparam_tables[RADIOA_2T].length =
74 RTL8192CURADIOA_2TARRAYLENGTH;
75 rtlphy->hwparam_tables[RADIOA_2T].pdata =
76 RTL8192CURADIOA_2TARRAY;
77 rtlphy->hwparam_tables[RADIOB_2T].length =
78 RTL8192CURADIOB_2TARRAYLENGTH;
79 rtlphy->hwparam_tables[RADIOB_2T].pdata =
80 RTL8192CU_RADIOB_2TARRAY;
81 rtlphy->hwparam_tables[AGCTAB_2T].length =
82 RTL8192CUAGCTAB_2TARRAYLENGTH;
83 rtlphy->hwparam_tables[AGCTAB_2T].pdata =
84 RTL8192CUAGCTAB_2TARRAY;
85 /* 1T */
86 if (IS_HIGHT_PA(rtlefuse->board_type)) {
87 rtlphy->hwparam_tables[PHY_REG_1T].length =
88 RTL8192CUPHY_REG_1T_HPArrayLength;
89 rtlphy->hwparam_tables[PHY_REG_1T].pdata =
90 RTL8192CUPHY_REG_1T_HPArray;
91 rtlphy->hwparam_tables[RADIOA_1T].length =
92 RTL8192CURadioA_1T_HPArrayLength;
93 rtlphy->hwparam_tables[RADIOA_1T].pdata =
94 RTL8192CURadioA_1T_HPArray;
95 rtlphy->hwparam_tables[RADIOB_1T].length =
96 RTL8192CURADIOB_1TARRAYLENGTH;
97 rtlphy->hwparam_tables[RADIOB_1T].pdata =
98 RTL8192CU_RADIOB_1TARRAY;
99 rtlphy->hwparam_tables[AGCTAB_1T].length =
100 RTL8192CUAGCTAB_1T_HPArrayLength;
101 rtlphy->hwparam_tables[AGCTAB_1T].pdata =
102 Rtl8192CUAGCTAB_1T_HPArray;
103 } else {
104 rtlphy->hwparam_tables[PHY_REG_1T].length =
105 RTL8192CUPHY_REG_1TARRAY_LENGTH;
106 rtlphy->hwparam_tables[PHY_REG_1T].pdata =
107 RTL8192CUPHY_REG_1TARRAY;
108 rtlphy->hwparam_tables[RADIOA_1T].length =
109 RTL8192CURADIOA_1TARRAYLENGTH;
110 rtlphy->hwparam_tables[RADIOA_1T].pdata =
111 RTL8192CU_RADIOA_1TARRAY;
112 rtlphy->hwparam_tables[RADIOB_1T].length =
113 RTL8192CURADIOB_1TARRAYLENGTH;
114 rtlphy->hwparam_tables[RADIOB_1T].pdata =
115 RTL8192CU_RADIOB_1TARRAY;
116 rtlphy->hwparam_tables[AGCTAB_1T].length =
117 RTL8192CUAGCTAB_1TARRAYLENGTH;
118 rtlphy->hwparam_tables[AGCTAB_1T].pdata =
119 RTL8192CUAGCTAB_1TARRAY;
120 }
121}
122
123static void _rtl92cu_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
124 bool autoload_fail,
125 u8 *hwinfo)
126{
127 struct rtl_priv *rtlpriv = rtl_priv(hw);
128 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
129 u8 rf_path, index, tempval;
130 u16 i;
131
132 for (rf_path = 0; rf_path < 2; rf_path++) {
133 for (i = 0; i < 3; i++) {
134 if (!autoload_fail) {
135 rtlefuse->
136 eeprom_chnlarea_txpwr_cck[rf_path][i] =
137 hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i];
138 rtlefuse->
139 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
140 hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 +
141 i];
142 } else {
143 rtlefuse->
144 eeprom_chnlarea_txpwr_cck[rf_path][i] =
145 EEPROM_DEFAULT_TXPOWERLEVEL;
146 rtlefuse->
147 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
148 EEPROM_DEFAULT_TXPOWERLEVEL;
149 }
150 }
151 }
152 for (i = 0; i < 3; i++) {
153 if (!autoload_fail)
154 tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i];
155 else
156 tempval = EEPROM_DEFAULT_HT40_2SDIFF;
157 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif[RF90_PATH_A][i] =
158 (tempval & 0xf);
159 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif[RF90_PATH_B][i] =
160 ((tempval & 0xf0) >> 4);
161 }
162 for (rf_path = 0; rf_path < 2; rf_path++)
163 for (i = 0; i < 3; i++)
164 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
165 ("RF(%d) EEPROM CCK Area(%d) = 0x%x\n", rf_path,
166 i, rtlefuse->
167 eeprom_chnlarea_txpwr_cck[rf_path][i]));
168 for (rf_path = 0; rf_path < 2; rf_path++)
169 for (i = 0; i < 3; i++)
170 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
171 ("RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
172 rf_path, i,
173 rtlefuse->
174 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]));
175 for (rf_path = 0; rf_path < 2; rf_path++)
176 for (i = 0; i < 3; i++)
177 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
178 ("RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
179 rf_path, i,
180 rtlefuse->
181 eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path]
182 [i]));
183 for (rf_path = 0; rf_path < 2; rf_path++) {
184 for (i = 0; i < 14; i++) {
185 index = _rtl92c_get_chnl_group((u8) i);
186 rtlefuse->txpwrlevel_cck[rf_path][i] =
187 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][index];
188 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
189 rtlefuse->
190 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index];
191 if ((rtlefuse->
192 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index] -
193 rtlefuse->
194 eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path][index])
195 > 0) {
196 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
197 rtlefuse->
198 eeprom_chnlarea_txpwr_ht40_1s[rf_path]
199 [index] - rtlefuse->
200 eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path]
201 [index];
202 } else {
203 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0;
204 }
205 }
206 for (i = 0; i < 14; i++) {
207 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
208 ("RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = "
209 "[0x%x / 0x%x / 0x%x]\n", rf_path, i,
210 rtlefuse->txpwrlevel_cck[rf_path][i],
211 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
212 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]));
213 }
214 }
215 for (i = 0; i < 3; i++) {
216 if (!autoload_fail) {
217 rtlefuse->eeprom_pwrlimit_ht40[i] =
218 hwinfo[EEPROM_TXPWR_GROUP + i];
219 rtlefuse->eeprom_pwrlimit_ht20[i] =
220 hwinfo[EEPROM_TXPWR_GROUP + 3 + i];
221 } else {
222 rtlefuse->eeprom_pwrlimit_ht40[i] = 0;
223 rtlefuse->eeprom_pwrlimit_ht20[i] = 0;
224 }
225 }
226 for (rf_path = 0; rf_path < 2; rf_path++) {
227 for (i = 0; i < 14; i++) {
228 index = _rtl92c_get_chnl_group((u8) i);
229 if (rf_path == RF90_PATH_A) {
230 rtlefuse->pwrgroup_ht20[rf_path][i] =
231 (rtlefuse->eeprom_pwrlimit_ht20[index]
232 & 0xf);
233 rtlefuse->pwrgroup_ht40[rf_path][i] =
234 (rtlefuse->eeprom_pwrlimit_ht40[index]
235 & 0xf);
236 } else if (rf_path == RF90_PATH_B) {
237 rtlefuse->pwrgroup_ht20[rf_path][i] =
238 ((rtlefuse->eeprom_pwrlimit_ht20[index]
239 & 0xf0) >> 4);
240 rtlefuse->pwrgroup_ht40[rf_path][i] =
241 ((rtlefuse->eeprom_pwrlimit_ht40[index]
242 & 0xf0) >> 4);
243 }
244 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
245 ("RF-%d pwrgroup_ht20[%d] = 0x%x\n",
246 rf_path, i,
247 rtlefuse->pwrgroup_ht20[rf_path][i]));
248 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
249 ("RF-%d pwrgroup_ht40[%d] = 0x%x\n",
250 rf_path, i,
251 rtlefuse->pwrgroup_ht40[rf_path][i]));
252 }
253 }
254 for (i = 0; i < 14; i++) {
255 index = _rtl92c_get_chnl_group((u8) i);
256 if (!autoload_fail)
257 tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index];
258 else
259 tempval = EEPROM_DEFAULT_HT20_DIFF;
260 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
261 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
262 ((tempval >> 4) & 0xF);
263 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3))
264 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0;
265 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3))
266 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0;
267 index = _rtl92c_get_chnl_group((u8) i);
268 if (!autoload_fail)
269 tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index];
270 else
271 tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
272 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF);
273 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
274 ((tempval >> 4) & 0xF);
275 }
276 rtlefuse->legacy_ht_txpowerdiff =
277 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7];
278 for (i = 0; i < 14; i++)
279 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
280 ("RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", i,
281 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]));
282 for (i = 0; i < 14; i++)
283 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
284 ("RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", i,
285 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]));
286 for (i = 0; i < 14; i++)
287 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
288 ("RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", i,
289 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]));
290 for (i = 0; i < 14; i++)
291 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
292 ("RF-B Legacy to HT40 Diff[%d] = 0x%x\n", i,
293 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]));
294 if (!autoload_fail)
295 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7);
296 else
297 rtlefuse->eeprom_regulatory = 0;
298 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
299 ("eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory));
300 if (!autoload_fail) {
301 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A];
302 rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B];
303 } else {
304 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI;
305 rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI;
306 }
307 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
308 ("TSSI_A = 0x%x, TSSI_B = 0x%x\n",
309 rtlefuse->eeprom_tssi[RF90_PATH_A],
310 rtlefuse->eeprom_tssi[RF90_PATH_B]));
311 if (!autoload_fail)
312 tempval = hwinfo[EEPROM_THERMAL_METER];
313 else
314 tempval = EEPROM_DEFAULT_THERMALMETER;
315 rtlefuse->eeprom_thermalmeter = (tempval & 0x1f);
316 if (rtlefuse->eeprom_thermalmeter < 0x06 ||
317 rtlefuse->eeprom_thermalmeter > 0x1c)
318 rtlefuse->eeprom_thermalmeter = 0x12;
319 if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail)
320 rtlefuse->apk_thermalmeterignore = true;
321 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
322 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
323 ("thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter));
324}
325
326static void _rtl92cu_read_board_type(struct ieee80211_hw *hw, u8 *contents)
327{
328 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
329 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
330 u8 boardType;
331
332 if (IS_NORMAL_CHIP(rtlhal->version)) {
333 boardType = ((contents[EEPROM_RF_OPT1]) &
334 BOARD_TYPE_NORMAL_MASK) >> 5; /*bit[7:5]*/
335 } else {
336 boardType = contents[EEPROM_RF_OPT4];
337 boardType &= BOARD_TYPE_TEST_MASK;
338 }
339 rtlefuse->board_type = boardType;
340 if (IS_HIGHT_PA(rtlefuse->board_type))
341 rtlefuse->external_pa = 1;
342 pr_info("Board Type %x\n", rtlefuse->board_type);
343
344#ifdef CONFIG_ANTENNA_DIVERSITY
345 /* Antenna Diversity setting. */
346 if (registry_par->antdiv_cfg == 2) /* 2: From Efuse */
347 rtl_efuse->antenna_cfg = (contents[EEPROM_RF_OPT1]&0x18)>>3;
348 else
349 rtl_efuse->antenna_cfg = registry_par->antdiv_cfg; /* 0:OFF, */
350
351 pr_info("Antenna Config %x\n", rtl_efuse->antenna_cfg);
352#endif
353}
354
355#ifdef CONFIG_BT_COEXIST
356static void _update_bt_param(_adapter *padapter)
357{
358 struct btcoexist_priv *pbtpriv = &(padapter->halpriv.bt_coexist);
359 struct registry_priv *registry_par = &padapter->registrypriv;
360 if (2 != registry_par->bt_iso) {
361 /* 0:Low, 1:High, 2:From Efuse */
362 pbtpriv->BT_Ant_isolation = registry_par->bt_iso;
363 }
364 if (registry_par->bt_sco == 1) {
365 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter, 4.Busy,
366 * 5.OtherBusy */
367 pbtpriv->BT_Service = BT_OtherAction;
368 } else if (registry_par->bt_sco == 2) {
369 pbtpriv->BT_Service = BT_SCO;
370 } else if (registry_par->bt_sco == 4) {
371 pbtpriv->BT_Service = BT_Busy;
372 } else if (registry_par->bt_sco == 5) {
373 pbtpriv->BT_Service = BT_OtherBusy;
374 } else {
375 pbtpriv->BT_Service = BT_Idle;
376 }
377 pbtpriv->BT_Ampdu = registry_par->bt_ampdu;
378 pbtpriv->bCOBT = _TRUE;
379 pbtpriv->BtEdcaUL = 0;
380 pbtpriv->BtEdcaDL = 0;
381 pbtpriv->BtRssiState = 0xff;
382 pbtpriv->bInitSet = _FALSE;
383 pbtpriv->bBTBusyTraffic = _FALSE;
384 pbtpriv->bBTTrafficModeSet = _FALSE;
385 pbtpriv->bBTNonTrafficModeSet = _FALSE;
386 pbtpriv->CurrentState = 0;
387 pbtpriv->PreviousState = 0;
388 pr_info("BT Coexistance = %s\n",
389 (pbtpriv->BT_Coexist == _TRUE) ? "enable" : "disable");
390 if (pbtpriv->BT_Coexist) {
391 if (pbtpriv->BT_Ant_Num == Ant_x2)
392 pr_info("BlueTooth BT_Ant_Num = Antx2\n");
393 else if (pbtpriv->BT_Ant_Num == Ant_x1)
394 pr_info("BlueTooth BT_Ant_Num = Antx1\n");
395 switch (pbtpriv->BT_CoexistType) {
396 case BT_2Wire:
397 pr_info("BlueTooth BT_CoexistType = BT_2Wire\n");
398 break;
399 case BT_ISSC_3Wire:
400 pr_info("BlueTooth BT_CoexistType = BT_ISSC_3Wire\n");
401 break;
402 case BT_Accel:
403 pr_info("BlueTooth BT_CoexistType = BT_Accel\n");
404 break;
405 case BT_CSR_BC4:
406 pr_info("BlueTooth BT_CoexistType = BT_CSR_BC4\n");
407 break;
408 case BT_CSR_BC8:
409 pr_info("BlueTooth BT_CoexistType = BT_CSR_BC8\n");
410 break;
411 case BT_RTL8756:
412 pr_info("BlueTooth BT_CoexistType = BT_RTL8756\n");
413 break;
414 default:
415 pr_info("BlueTooth BT_CoexistType = Unknown\n");
416 break;
417 }
418 pr_info("BlueTooth BT_Ant_isolation = %d\n",
419 pbtpriv->BT_Ant_isolation);
420 switch (pbtpriv->BT_Service) {
421 case BT_OtherAction:
422 pr_info("BlueTooth BT_Service = BT_OtherAction\n");
423 break;
424 case BT_SCO:
425 pr_info("BlueTooth BT_Service = BT_SCO\n");
426 break;
427 case BT_Busy:
428 pr_info("BlueTooth BT_Service = BT_Busy\n");
429 break;
430 case BT_OtherBusy:
431 pr_info("BlueTooth BT_Service = BT_OtherBusy\n");
432 break;
433 default:
434 pr_info("BlueTooth BT_Service = BT_Idle\n");
435 break;
436 }
437 pr_info("BT_RadioSharedType = 0x%x\n",
438 pbtpriv->BT_RadioSharedType);
439 }
440}
441
442#define GET_BT_COEXIST(priv) (&priv->bt_coexist)
443
444static void _rtl92cu_read_bluetooth_coexistInfo(struct ieee80211_hw *hw,
445 u8 *contents,
446 bool bautoloadfailed);
447{
448 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
449 bool isNormal = IS_NORMAL_CHIP(pHalData->VersionID);
450 struct btcoexist_priv *pbtpriv = &pHalData->bt_coexist;
451 u8 rf_opt4;
452
453 _rtw_memset(pbtpriv, 0, sizeof(struct btcoexist_priv));
454 if (AutoloadFail) {
455 pbtpriv->BT_Coexist = _FALSE;
456 pbtpriv->BT_CoexistType = BT_2Wire;
457 pbtpriv->BT_Ant_Num = Ant_x2;
458 pbtpriv->BT_Ant_isolation = 0;
459 pbtpriv->BT_RadioSharedType = BT_Radio_Shared;
460 return;
461 }
462 if (isNormal) {
463 if (pHalData->BoardType == BOARD_USB_COMBO)
464 pbtpriv->BT_Coexist = _TRUE;
465 else
466 pbtpriv->BT_Coexist = ((PROMContent[EEPROM_RF_OPT3] &
467 0x20) >> 5); /* bit[5] */
468 rf_opt4 = PROMContent[EEPROM_RF_OPT4];
469 pbtpriv->BT_CoexistType = ((rf_opt4&0xe)>>1); /* bit [3:1] */
470 pbtpriv->BT_Ant_Num = (rf_opt4&0x1); /* bit [0] */
471 pbtpriv->BT_Ant_isolation = ((rf_opt4&0x10)>>4); /* bit [4] */
472 pbtpriv->BT_RadioSharedType = ((rf_opt4&0x20)>>5); /* bit [5] */
473 } else {
474 pbtpriv->BT_Coexist = (PROMContent[EEPROM_RF_OPT4] >> 4) ?
475 _TRUE : _FALSE;
476 }
477 _update_bt_param(Adapter);
478}
479#endif
480
481static void _rtl92cu_read_adapter_info(struct ieee80211_hw *hw)
482{
483 struct rtl_priv *rtlpriv = rtl_priv(hw);
484 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
485 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
486 u16 i, usvalue;
487 u8 hwinfo[HWSET_MAX_SIZE] = {0};
488 u16 eeprom_id;
489
490 if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
491 rtl_efuse_shadow_map_update(hw);
492 memcpy((void *)hwinfo,
493 (void *)&rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
494 HWSET_MAX_SIZE);
495 } else if (rtlefuse->epromtype == EEPROM_93C46) {
496 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
497 ("RTL819X Not boot from eeprom, check it !!"));
498 }
499 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_LOUD, ("MAP\n"),
500 hwinfo, HWSET_MAX_SIZE);
501 eeprom_id = *((u16 *)&hwinfo[0]);
502 if (eeprom_id != RTL8190_EEPROM_ID) {
503 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
504 ("EEPROM ID(%#x) is invalid!!\n", eeprom_id));
505 rtlefuse->autoload_failflag = true;
506 } else {
507 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Autoload OK\n"));
508 rtlefuse->autoload_failflag = false;
509 }
510 if (rtlefuse->autoload_failflag)
511 return;
512 for (i = 0; i < 6; i += 2) {
513 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
514 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
515 }
516 pr_info("MAC address: %pM\n", rtlefuse->dev_addr);
517 _rtl92cu_read_txpower_info_from_hwpg(hw,
518 rtlefuse->autoload_failflag, hwinfo);
519 rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
520 rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID];
521 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
522 (" VID = 0x%02x PID = 0x%02x\n",
523 rtlefuse->eeprom_vid, rtlefuse->eeprom_did));
524 rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
525 rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
526 rtlefuse->txpwr_fromeprom = true;
527 rtlefuse->eeprom_oemid = *(u8 *)&hwinfo[EEPROM_CUSTOMER_ID];
528 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
529 ("EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid));
530 if (rtlhal->oem_id == RT_CID_DEFAULT) {
531 switch (rtlefuse->eeprom_oemid) {
532 case EEPROM_CID_DEFAULT:
533 if (rtlefuse->eeprom_did == 0x8176) {
534 if ((rtlefuse->eeprom_svid == 0x103C &&
535 rtlefuse->eeprom_smid == 0x1629))
536 rtlhal->oem_id = RT_CID_819x_HP;
537 else
538 rtlhal->oem_id = RT_CID_DEFAULT;
539 } else {
540 rtlhal->oem_id = RT_CID_DEFAULT;
541 }
542 break;
543 case EEPROM_CID_TOSHIBA:
544 rtlhal->oem_id = RT_CID_TOSHIBA;
545 break;
546 case EEPROM_CID_QMI:
547 rtlhal->oem_id = RT_CID_819x_QMI;
548 break;
549 case EEPROM_CID_WHQL:
550 default:
551 rtlhal->oem_id = RT_CID_DEFAULT;
552 break;
553 }
554 }
555 _rtl92cu_read_board_type(hw, hwinfo);
556#ifdef CONFIG_BT_COEXIST
557 _rtl92cu_read_bluetooth_coexistInfo(hw, hwinfo,
558 rtlefuse->autoload_failflag);
559#endif
560}
561
562static void _rtl92cu_hal_customized_behavior(struct ieee80211_hw *hw)
563{
564 struct rtl_priv *rtlpriv = rtl_priv(hw);
565 struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw);
566 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
567
568 switch (rtlhal->oem_id) {
569 case RT_CID_819x_HP:
570 usb_priv->ledctl.led_opendrain = true;
571 break;
572 case RT_CID_819x_Lenovo:
573 case RT_CID_DEFAULT:
574 case RT_CID_TOSHIBA:
575 case RT_CID_CCX:
576 case RT_CID_819x_Acer:
577 case RT_CID_WHQL:
578 default:
579 break;
580 }
581 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
582 ("RT Customized ID: 0x%02X\n", rtlhal->oem_id));
583}
584
585void rtl92cu_read_eeprom_info(struct ieee80211_hw *hw)
586{
587
588 struct rtl_priv *rtlpriv = rtl_priv(hw);
589 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
590 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
591 u8 tmp_u1b;
592
593 if (!IS_NORMAL_CHIP(rtlhal->version))
594 return;
595 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
596 rtlefuse->epromtype = (tmp_u1b & BOOT_FROM_EEPROM) ?
597 EEPROM_93C46 : EEPROM_BOOT_EFUSE;
598 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("Boot from %s\n",
599 (tmp_u1b & BOOT_FROM_EEPROM) ? "EERROM" : "EFUSE"));
600 rtlefuse->autoload_failflag = (tmp_u1b & EEPROM_EN) ? false : true;
601 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Autoload %s\n",
602 (tmp_u1b & EEPROM_EN) ? "OK!!" : "ERR!!"));
603 _rtl92cu_read_adapter_info(hw);
604 _rtl92cu_hal_customized_behavior(hw);
605 return;
606}
607
608static int _rtl92cu_init_power_on(struct ieee80211_hw *hw)
609{
610 struct rtl_priv *rtlpriv = rtl_priv(hw);
611 int status = 0;
612 u16 value16;
613 u8 value8;
614 /* polling autoload done. */
615 u32 pollingCount = 0;
616
617 do {
618 if (rtl_read_byte(rtlpriv, REG_APS_FSMCO) & PFM_ALDN) {
619 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
620 ("Autoload Done!\n"));
621 break;
622 }
623 if (pollingCount++ > 100) {
624 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
625 ("Failed to polling REG_APS_FSMCO[PFM_ALDN]"
626 " done!\n"));
627 return -ENODEV;
628 }
629 } while (true);
630 /* 0. RSV_CTRL 0x1C[7:0] = 0 unlock ISO/CLK/Power control register */
631 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0);
632 /* Power on when re-enter from IPS/Radio off/card disable */
633 /* enable SPS into PWM mode */
634 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
635 udelay(100);
636 value8 = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL);
637 if (0 == (value8 & LDV12_EN)) {
638 value8 |= LDV12_EN;
639 rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, value8);
640 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
641 (" power-on :REG_LDOV12D_CTRL Reg0x21:0x%02x.\n",
642 value8));
643 udelay(100);
644 value8 = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL);
645 value8 &= ~ISO_MD2PP;
646 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, value8);
647 }
648 /* auto enable WLAN */
649 pollingCount = 0;
650 value16 = rtl_read_word(rtlpriv, REG_APS_FSMCO);
651 value16 |= APFM_ONMAC;
652 rtl_write_word(rtlpriv, REG_APS_FSMCO, value16);
653 do {
654 if (!(rtl_read_word(rtlpriv, REG_APS_FSMCO) & APFM_ONMAC)) {
655 pr_info("MAC auto ON okay!\n");
656 break;
657 }
658 if (pollingCount++ > 100) {
659 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
660 ("Failed to polling REG_APS_FSMCO[APFM_ONMAC]"
661 " done!\n"));
662 return -ENODEV;
663 }
664 } while (true);
665 /* Enable Radio ,GPIO ,and LED function */
666 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x0812);
667 /* release RF digital isolation */
668 value16 = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL);
669 value16 &= ~ISO_DIOR;
670 rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, value16);
671 /* Reconsider when to do this operation after asking HWSD. */
672 pollingCount = 0;
673 rtl_write_byte(rtlpriv, REG_APSD_CTRL, (rtl_read_byte(rtlpriv,
674 REG_APSD_CTRL) & ~BIT(6)));
675 do {
676 pollingCount++;
677 } while ((pollingCount < 200) &&
678 (rtl_read_byte(rtlpriv, REG_APSD_CTRL) & BIT(7)));
679 /* Enable MAC DMA/WMAC/SCHEDULE/SEC block */
680 value16 = rtl_read_word(rtlpriv, REG_CR);
681 value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN |
682 PROTOCOL_EN | SCHEDULE_EN | MACTXEN | MACRXEN | ENSEC);
683 rtl_write_word(rtlpriv, REG_CR, value16);
684 return status;
685}
686
687static void _rtl92cu_init_queue_reserved_page(struct ieee80211_hw *hw,
688 bool wmm_enable,
689 u8 out_ep_num,
690 u8 queue_sel)
691{
692 struct rtl_priv *rtlpriv = rtl_priv(hw);
693 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
694 bool isChipN = IS_NORMAL_CHIP(rtlhal->version);
695 u32 outEPNum = (u32)out_ep_num;
696 u32 numHQ = 0;
697 u32 numLQ = 0;
698 u32 numNQ = 0;
699 u32 numPubQ;
700 u32 value32;
701 u8 value8;
702 u32 txQPageNum, txQPageUnit, txQRemainPage;
703
704 if (!wmm_enable) {
705 numPubQ = (isChipN) ? CHIP_B_PAGE_NUM_PUBQ :
706 CHIP_A_PAGE_NUM_PUBQ;
707 txQPageNum = TX_TOTAL_PAGE_NUMBER - numPubQ;
708
709 txQPageUnit = txQPageNum/outEPNum;
710 txQRemainPage = txQPageNum % outEPNum;
711 if (queue_sel & TX_SELE_HQ)
712 numHQ = txQPageUnit;
713 if (queue_sel & TX_SELE_LQ)
714 numLQ = txQPageUnit;
715 /* HIGH priority queue always present in the configuration of
716 * 2 out-ep. Remainder pages have assigned to High queue */
717 if ((outEPNum > 1) && (txQRemainPage))
718 numHQ += txQRemainPage;
719 /* NOTE: This step done before writting REG_RQPN. */
720 if (isChipN) {
721 if (queue_sel & TX_SELE_NQ)
722 numNQ = txQPageUnit;
723 value8 = (u8)_NPQ(numNQ);
724 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8);
725 }
726 } else {
727 /* for WMM ,number of out-ep must more than or equal to 2! */
728 numPubQ = isChipN ? WMM_CHIP_B_PAGE_NUM_PUBQ :
729 WMM_CHIP_A_PAGE_NUM_PUBQ;
730 if (queue_sel & TX_SELE_HQ) {
731 numHQ = isChipN ? WMM_CHIP_B_PAGE_NUM_HPQ :
732 WMM_CHIP_A_PAGE_NUM_HPQ;
733 }
734 if (queue_sel & TX_SELE_LQ) {
735 numLQ = isChipN ? WMM_CHIP_B_PAGE_NUM_LPQ :
736 WMM_CHIP_A_PAGE_NUM_LPQ;
737 }
738 /* NOTE: This step done before writting REG_RQPN. */
739 if (isChipN) {
740 if (queue_sel & TX_SELE_NQ)
741 numNQ = WMM_CHIP_B_PAGE_NUM_NPQ;
742 value8 = (u8)_NPQ(numNQ);
743 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8);
744 }
745 }
746 /* TX DMA */
747 value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
748 rtl_write_dword(rtlpriv, REG_RQPN, value32);
749}
750
751static void _rtl92c_init_trx_buffer(struct ieee80211_hw *hw, bool wmm_enable)
752{
753 struct rtl_priv *rtlpriv = rtl_priv(hw);
754 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
755 u8 txpktbuf_bndy;
756 u8 value8;
757
758 if (!wmm_enable)
759 txpktbuf_bndy = TX_PAGE_BOUNDARY;
760 else /* for WMM */
761 txpktbuf_bndy = (IS_NORMAL_CHIP(rtlhal->version))
762 ? WMM_CHIP_B_TX_PAGE_BOUNDARY
763 : WMM_CHIP_A_TX_PAGE_BOUNDARY;
764 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
765 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
766 rtl_write_byte(rtlpriv, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy);
767 rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy);
768 rtl_write_byte(rtlpriv, REG_TDECTRL+1, txpktbuf_bndy);
769 rtl_write_word(rtlpriv, (REG_TRXFF_BNDY + 2), 0x27FF);
770 value8 = _PSRX(RX_PAGE_SIZE_REG_VALUE) | _PSTX(PBP_128);
771 rtl_write_byte(rtlpriv, REG_PBP, value8);
772}
773
774static void _rtl92c_init_chipN_reg_priority(struct ieee80211_hw *hw, u16 beQ,
775 u16 bkQ, u16 viQ, u16 voQ,
776 u16 mgtQ, u16 hiQ)
777{
778 struct rtl_priv *rtlpriv = rtl_priv(hw);
779 u16 value16 = (rtl_read_word(rtlpriv, REG_TRXDMA_CTRL) & 0x7);
780
781 value16 |= _TXDMA_BEQ_MAP(beQ) | _TXDMA_BKQ_MAP(bkQ) |
782 _TXDMA_VIQ_MAP(viQ) | _TXDMA_VOQ_MAP(voQ) |
783 _TXDMA_MGQ_MAP(mgtQ) | _TXDMA_HIQ_MAP(hiQ);
784 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, value16);
785}
786
787static void _rtl92cu_init_chipN_one_out_ep_priority(struct ieee80211_hw *hw,
788 bool wmm_enable,
789 u8 queue_sel)
790{
791 u16 uninitialized_var(value);
792
793 switch (queue_sel) {
794 case TX_SELE_HQ:
795 value = QUEUE_HIGH;
796 break;
797 case TX_SELE_LQ:
798 value = QUEUE_LOW;
799 break;
800 case TX_SELE_NQ:
801 value = QUEUE_NORMAL;
802 break;
803 default:
804 WARN_ON(1); /* Shall not reach here! */
805 break;
806 }
807 _rtl92c_init_chipN_reg_priority(hw, value, value, value, value,
808 value, value);
809 pr_info("Tx queue select: 0x%02x\n", queue_sel);
810}
811
812static void _rtl92cu_init_chipN_two_out_ep_priority(struct ieee80211_hw *hw,
813 bool wmm_enable,
814 u8 queue_sel)
815{
816 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
817 u16 uninitialized_var(valueHi);
818 u16 uninitialized_var(valueLow);
819
820 switch (queue_sel) {
821 case (TX_SELE_HQ | TX_SELE_LQ):
822 valueHi = QUEUE_HIGH;
823 valueLow = QUEUE_LOW;
824 break;
825 case (TX_SELE_NQ | TX_SELE_LQ):
826 valueHi = QUEUE_NORMAL;
827 valueLow = QUEUE_LOW;
828 break;
829 case (TX_SELE_HQ | TX_SELE_NQ):
830 valueHi = QUEUE_HIGH;
831 valueLow = QUEUE_NORMAL;
832 break;
833 default:
834 WARN_ON(1);
835 break;
836 }
837 if (!wmm_enable) {
838 beQ = valueLow;
839 bkQ = valueLow;
840 viQ = valueHi;
841 voQ = valueHi;
842 mgtQ = valueHi;
843 hiQ = valueHi;
844 } else {/* for WMM ,CONFIG_OUT_EP_WIFI_MODE */
845 beQ = valueHi;
846 bkQ = valueLow;
847 viQ = valueLow;
848 voQ = valueHi;
849 mgtQ = valueHi;
850 hiQ = valueHi;
851 }
852 _rtl92c_init_chipN_reg_priority(hw, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
853 pr_info("Tx queue select: 0x%02x\n", queue_sel);
854}
855
856static void _rtl92cu_init_chipN_three_out_ep_priority(struct ieee80211_hw *hw,
857 bool wmm_enable,
858 u8 queue_sel)
859{
860 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
861 struct rtl_priv *rtlpriv = rtl_priv(hw);
862
863 if (!wmm_enable) { /* typical setting */
864 beQ = QUEUE_LOW;
865 bkQ = QUEUE_LOW;
866 viQ = QUEUE_NORMAL;
867 voQ = QUEUE_HIGH;
868 mgtQ = QUEUE_HIGH;
869 hiQ = QUEUE_HIGH;
870 } else { /* for WMM */
871 beQ = QUEUE_LOW;
872 bkQ = QUEUE_NORMAL;
873 viQ = QUEUE_NORMAL;
874 voQ = QUEUE_HIGH;
875 mgtQ = QUEUE_HIGH;
876 hiQ = QUEUE_HIGH;
877 }
878 _rtl92c_init_chipN_reg_priority(hw, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
879 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
880 ("Tx queue select :0x%02x..\n", queue_sel));
881}
882
883static void _rtl92cu_init_chipN_queue_priority(struct ieee80211_hw *hw,
884 bool wmm_enable,
885 u8 out_ep_num,
886 u8 queue_sel)
887{
888 switch (out_ep_num) {
889 case 1:
890 _rtl92cu_init_chipN_one_out_ep_priority(hw, wmm_enable,
891 queue_sel);
892 break;
893 case 2:
894 _rtl92cu_init_chipN_two_out_ep_priority(hw, wmm_enable,
895 queue_sel);
896 break;
897 case 3:
898 _rtl92cu_init_chipN_three_out_ep_priority(hw, wmm_enable,
899 queue_sel);
900 break;
901 default:
902 WARN_ON(1); /* Shall not reach here! */
903 break;
904 }
905}
906
907static void _rtl92cu_init_chipT_queue_priority(struct ieee80211_hw *hw,
908 bool wmm_enable,
909 u8 out_ep_num,
910 u8 queue_sel)
911{
912 u8 hq_sele = 0;
913 struct rtl_priv *rtlpriv = rtl_priv(hw);
914
915 switch (out_ep_num) {
916 case 2: /* (TX_SELE_HQ|TX_SELE_LQ) */
917 if (!wmm_enable) /* typical setting */
918 hq_sele = HQSEL_VOQ | HQSEL_VIQ | HQSEL_MGTQ |
919 HQSEL_HIQ;
920 else /* for WMM */
921 hq_sele = HQSEL_VOQ | HQSEL_BEQ | HQSEL_MGTQ |
922 HQSEL_HIQ;
923 break;
924 case 1:
925 if (TX_SELE_LQ == queue_sel) {
926 /* map all endpoint to Low queue */
927 hq_sele = 0;
928 } else if (TX_SELE_HQ == queue_sel) {
929 /* map all endpoint to High queue */
930 hq_sele = HQSEL_VOQ | HQSEL_VIQ | HQSEL_BEQ |
931 HQSEL_BKQ | HQSEL_MGTQ | HQSEL_HIQ;
932 }
933 break;
934 default:
935 WARN_ON(1); /* Shall not reach here! */
936 break;
937 }
938 rtl_write_byte(rtlpriv, (REG_TRXDMA_CTRL+1), hq_sele);
939 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
940 ("Tx queue select :0x%02x..\n", hq_sele));
941}
942
943static void _rtl92cu_init_queue_priority(struct ieee80211_hw *hw,
944 bool wmm_enable,
945 u8 out_ep_num,
946 u8 queue_sel)
947{
948 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
949 if (IS_NORMAL_CHIP(rtlhal->version))
950 _rtl92cu_init_chipN_queue_priority(hw, wmm_enable, out_ep_num,
951 queue_sel);
952 else
953 _rtl92cu_init_chipT_queue_priority(hw, wmm_enable, out_ep_num,
954 queue_sel);
955}
956
957static void _rtl92cu_init_usb_aggregation(struct ieee80211_hw *hw)
958{
959}
960
961static void _rtl92cu_init_wmac_setting(struct ieee80211_hw *hw)
962{
963 u16 value16;
964
965 struct rtl_priv *rtlpriv = rtl_priv(hw);
966 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
967
968 mac->rx_conf = (RCR_APM | RCR_AM | RCR_ADF | RCR_AB | RCR_APPFCS |
969 RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL |
970 RCR_APP_MIC | RCR_APP_PHYSTS | RCR_ACRC32);
971 rtl_write_dword(rtlpriv, REG_RCR, mac->rx_conf);
972 /* Accept all multicast address */
973 rtl_write_dword(rtlpriv, REG_MAR, 0xFFFFFFFF);
974 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xFFFFFFFF);
975 /* Accept all management frames */
976 value16 = 0xFFFF;
977 rtl92c_set_mgt_filter(hw, value16);
978 /* Reject all control frame - default value is 0 */
979 rtl92c_set_ctrl_filter(hw, 0x0);
980 /* Accept all data frames */
981 value16 = 0xFFFF;
982 rtl92c_set_data_filter(hw, value16);
983}
984
985static int _rtl92cu_init_mac(struct ieee80211_hw *hw)
986{
987 struct rtl_priv *rtlpriv = rtl_priv(hw);
988 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
989 struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw);
990 struct rtl_usb *rtlusb = rtl_usbdev(usb_priv);
991 int err = 0;
992 u32 boundary = 0;
993 u8 wmm_enable = false; /* TODO */
994 u8 out_ep_nums = rtlusb->out_ep_nums;
995 u8 queue_sel = rtlusb->out_queue_sel;
996 err = _rtl92cu_init_power_on(hw);
997
998 if (err) {
999 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1000 ("Failed to init power on!\n"));
1001 return err;
1002 }
1003 if (!wmm_enable) {
1004 boundary = TX_PAGE_BOUNDARY;
1005 } else { /* for WMM */
1006 boundary = (IS_NORMAL_CHIP(rtlhal->version))
1007 ? WMM_CHIP_B_TX_PAGE_BOUNDARY
1008 : WMM_CHIP_A_TX_PAGE_BOUNDARY;
1009 }
1010 if (false == rtl92c_init_llt_table(hw, boundary)) {
1011 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1012 ("Failed to init LLT Table!\n"));
1013 return -EINVAL;
1014 }
1015 _rtl92cu_init_queue_reserved_page(hw, wmm_enable, out_ep_nums,
1016 queue_sel);
1017 _rtl92c_init_trx_buffer(hw, wmm_enable);
1018 _rtl92cu_init_queue_priority(hw, wmm_enable, out_ep_nums,
1019 queue_sel);
1020 /* Get Rx PHY status in order to report RSSI and others. */
1021 rtl92c_init_driver_info_size(hw, RTL92C_DRIVER_INFO_SIZE);
1022 rtl92c_init_interrupt(hw);
1023 rtl92c_init_network_type(hw);
1024 _rtl92cu_init_wmac_setting(hw);
1025 rtl92c_init_adaptive_ctrl(hw);
1026 rtl92c_init_edca(hw);
1027 rtl92c_init_rate_fallback(hw);
1028 rtl92c_init_retry_function(hw);
1029 _rtl92cu_init_usb_aggregation(hw);
1030 rtlpriv->cfg->ops->set_bw_mode(hw, NL80211_CHAN_HT20);
1031 rtl92c_set_min_space(hw, IS_92C_SERIAL(rtlhal->version));
1032 rtl92c_init_beacon_parameters(hw, rtlhal->version);
1033 rtl92c_init_ampdu_aggregation(hw);
1034 rtl92c_init_beacon_max_error(hw, true);
1035 return err;
1036}
1037
1038void rtl92cu_enable_hw_security_config(struct ieee80211_hw *hw)
1039{
1040 struct rtl_priv *rtlpriv = rtl_priv(hw);
1041 u8 sec_reg_value = 0x0;
1042 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1043
1044 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1045 ("PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1046 rtlpriv->sec.pairwise_enc_algorithm,
1047 rtlpriv->sec.group_enc_algorithm));
1048 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
1049 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1050 ("not open sw encryption\n"));
1051 return;
1052 }
1053 sec_reg_value = SCR_TxEncEnable | SCR_RxDecEnable;
1054 if (rtlpriv->sec.use_defaultkey) {
1055 sec_reg_value |= SCR_TxUseDK;
1056 sec_reg_value |= SCR_RxUseDK;
1057 }
1058 if (IS_NORMAL_CHIP(rtlhal->version))
1059 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
1060 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
1061 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
1062 ("The SECR-value %x\n", sec_reg_value));
1063 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
1064}
1065
1066static void _rtl92cu_hw_configure(struct ieee80211_hw *hw)
1067{
1068 struct rtl_priv *rtlpriv = rtl_priv(hw);
1069 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1070
1071 /* To Fix MAC loopback mode fail. */
1072 rtl_write_byte(rtlpriv, REG_LDOHCI12_CTRL, 0x0f);
1073 rtl_write_byte(rtlpriv, 0x15, 0xe9);
1074 /* HW SEQ CTRL */
1075 /* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */
1076 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
1077 /* fixed USB interface interference issue */
1078 rtl_write_byte(rtlpriv, 0xfe40, 0xe0);
1079 rtl_write_byte(rtlpriv, 0xfe41, 0x8d);
1080 rtl_write_byte(rtlpriv, 0xfe42, 0x80);
1081 rtlusb->reg_bcn_ctrl_val = 0x18;
1082 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlusb->reg_bcn_ctrl_val);
1083}
1084
1085static void _InitPABias(struct ieee80211_hw *hw)
1086{
1087 struct rtl_priv *rtlpriv = rtl_priv(hw);
1088 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1089 u8 pa_setting;
1090
1091 /* FIXED PA current issue */
1092 pa_setting = efuse_read_1byte(hw, 0x1FA);
1093 if (!(pa_setting & BIT(0))) {
1094 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x0F406);
1095 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x4F406);
1096 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x8F406);
1097 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0xCF406);
1098 }
1099 if (!(pa_setting & BIT(1)) && IS_NORMAL_CHIP(rtlhal->version) &&
1100 IS_92C_SERIAL(rtlhal->version)) {
1101 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x0F406);
1102 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x4F406);
1103 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x8F406);
1104 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0xCF406);
1105 }
1106 if (!(pa_setting & BIT(4))) {
1107 pa_setting = rtl_read_byte(rtlpriv, 0x16);
1108 pa_setting &= 0x0F;
1109 rtl_write_byte(rtlpriv, 0x16, pa_setting | 0x90);
1110 }
1111}
1112
1113static void _InitAntenna_Selection(struct ieee80211_hw *hw)
1114{
1115#ifdef CONFIG_ANTENNA_DIVERSITY
1116 struct rtl_priv *rtlpriv = rtl_priv(hw);
1117 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1118 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1119
1120 if (pHalData->AntDivCfg == 0)
1121 return;
1122
1123 if (rtlphy->rf_type == RF_1T1R) {
1124 rtl_write_dword(rtlpriv, REG_LEDCFG0,
1125 rtl_read_dword(rtlpriv,
1126 REG_LEDCFG0)|BIT(23));
1127 rtl_set_bbreg(hw, rFPGA0_XAB_RFPARAMETER, BIT(13), 0x01);
1128 if (rtl_get_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300) ==
1129 Antenna_A)
1130 pHalData->CurAntenna = Antenna_A;
1131 else
1132 pHalData->CurAntenna = Antenna_B;
1133 }
1134#endif
1135}
1136
1137static void _dump_registers(struct ieee80211_hw *hw)
1138{
1139}
1140
1141static void _update_mac_setting(struct ieee80211_hw *hw)
1142{
1143 struct rtl_priv *rtlpriv = rtl_priv(hw);
1144 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1145
1146 mac->rx_conf = rtl_read_dword(rtlpriv, REG_RCR);
1147 mac->rx_mgt_filter = rtl_read_word(rtlpriv, REG_RXFLTMAP0);
1148 mac->rx_ctrl_filter = rtl_read_word(rtlpriv, REG_RXFLTMAP1);
1149 mac->rx_data_filter = rtl_read_word(rtlpriv, REG_RXFLTMAP2);
1150}
1151
1152int rtl92cu_hw_init(struct ieee80211_hw *hw)
1153{
1154 struct rtl_priv *rtlpriv = rtl_priv(hw);
1155 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1156 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1157 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1158 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1159 int err = 0;
1160 static bool iqk_initialized;
1161
1162 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CU;
1163 err = _rtl92cu_init_mac(hw);
1164 if (err) {
1165 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("init mac failed!\n"));
1166 return err;
1167 }
1168 err = rtl92c_download_fw(hw);
1169 if (err) {
1170 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1171 ("Failed to download FW. Init HW without FW now..\n"));
1172 err = 1;
1173 rtlhal->fw_ready = false;
1174 return err;
1175 } else {
1176 rtlhal->fw_ready = true;
1177 }
1178 rtlhal->last_hmeboxnum = 0; /* h2c */
1179 _rtl92cu_phy_param_tab_init(hw);
1180 rtl92cu_phy_mac_config(hw);
1181 rtl92cu_phy_bb_config(hw);
1182 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
1183 rtl92c_phy_rf_config(hw);
1184 if (IS_VENDOR_UMC_A_CUT(rtlhal->version) &&
1185 !IS_92C_SERIAL(rtlhal->version)) {
1186 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255);
1187 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00);
1188 }
1189 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
1190 RF_CHNLBW, RFREG_OFFSET_MASK);
1191 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
1192 RF_CHNLBW, RFREG_OFFSET_MASK);
1193 rtl92cu_bb_block_on(hw);
1194 rtl_cam_reset_all_entry(hw);
1195 rtl92cu_enable_hw_security_config(hw);
1196 ppsc->rfpwr_state = ERFON;
1197 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1198 if (ppsc->rfpwr_state == ERFON) {
1199 rtl92c_phy_set_rfpath_switch(hw, 1);
1200 if (iqk_initialized) {
1201 rtl92c_phy_iq_calibrate(hw, false);
1202 } else {
1203 rtl92c_phy_iq_calibrate(hw, false);
1204 iqk_initialized = true;
1205 }
1206 rtl92c_dm_check_txpower_tracking(hw);
1207 rtl92c_phy_lc_calibrate(hw);
1208 }
1209 _rtl92cu_hw_configure(hw);
1210 _InitPABias(hw);
1211 _InitAntenna_Selection(hw);
1212 _update_mac_setting(hw);
1213 rtl92c_dm_init(hw);
1214 _dump_registers(hw);
1215 return err;
1216}
1217
1218static void _DisableRFAFEAndResetBB(struct ieee80211_hw *hw)
1219{
1220 struct rtl_priv *rtlpriv = rtl_priv(hw);
1221/**************************************
1222a. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue
1223b. RF path 0 offset 0x00 = 0x00 disable RF
1224c. APSD_CTRL 0x600[7:0] = 0x40
1225d. SYS_FUNC_EN 0x02[7:0] = 0x16 reset BB state machine
1226e. SYS_FUNC_EN 0x02[7:0] = 0x14 reset BB state machine
1227***************************************/
1228 u8 eRFPath = 0, value8 = 0;
1229 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1230 rtl_set_rfreg(hw, (enum radio_path)eRFPath, 0x0, MASKBYTE0, 0x0);
1231
1232 value8 |= APSDOFF;
1233 rtl_write_byte(rtlpriv, REG_APSD_CTRL, value8); /*0x40*/
1234 value8 = 0;
1235 value8 |= (FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTn);
1236 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value8);/*0x16*/
1237 value8 &= (~FEN_BB_GLB_RSTn);
1238 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value8); /*0x14*/
1239}
1240
1241static void _ResetDigitalProcedure1(struct ieee80211_hw *hw, bool bWithoutHWSM)
1242{
1243 struct rtl_priv *rtlpriv = rtl_priv(hw);
1244 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1245
1246 if (rtlhal->fw_version <= 0x20) {
1247 /*****************************
1248 f. MCUFWDL 0x80[7:0]=0 reset MCU ready status
1249 g. SYS_FUNC_EN 0x02[10]= 0 reset MCU reg, (8051 reset)
1250 h. SYS_FUNC_EN 0x02[15-12]= 5 reset MAC reg, DCORE
1251 i. SYS_FUNC_EN 0x02[10]= 1 enable MCU reg, (8051 enable)
1252 ******************************/
1253 u16 valu16 = 0;
1254
1255 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1256 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1257 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 &
1258 (~FEN_CPUEN))); /* reset MCU ,8051 */
1259 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN)&0x0FFF;
1260 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 |
1261 (FEN_HWPDN|FEN_ELDR))); /* reset MAC */
1262 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1263 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 |
1264 FEN_CPUEN)); /* enable MCU ,8051 */
1265 } else {
1266 u8 retry_cnts = 0;
1267
1268 /* IF fw in RAM code, do reset */
1269 if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(1)) {
1270 /* reset MCU ready status */
1271 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1272 if (rtlhal->fw_ready) {
1273 /* 8051 reset by self */
1274 rtl_write_byte(rtlpriv, REG_HMETFR+3, 0x20);
1275 while ((retry_cnts++ < 100) &&
1276 (FEN_CPUEN & rtl_read_word(rtlpriv,
1277 REG_SYS_FUNC_EN))) {
1278 udelay(50);
1279 }
1280 if (retry_cnts >= 100) {
1281 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1282 ("#####=> 8051 reset failed!.."
1283 ".......................\n"););
1284 /* if 8051 reset fail, reset MAC. */
1285 rtl_write_byte(rtlpriv,
1286 REG_SYS_FUNC_EN + 1,
1287 0x50);
1288 udelay(100);
1289 }
1290 }
1291 }
1292 /* Reset MAC and Enable 8051 */
1293 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x54);
1294 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1295 }
1296 if (bWithoutHWSM) {
1297 /*****************************
1298 Without HW auto state machine
1299 g.SYS_CLKR 0x08[15:0] = 0x30A3 disable MAC clock
1300 h.AFE_PLL_CTRL 0x28[7:0] = 0x80 disable AFE PLL
1301 i.AFE_XTAL_CTRL 0x24[15:0] = 0x880F gated AFE DIG_CLOCK
1302 j.SYS_ISu_CTRL 0x00[7:0] = 0xF9 isolated digital to PON
1303 ******************************/
1304 rtl_write_word(rtlpriv, REG_SYS_CLKR, 0x70A3);
1305 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80);
1306 rtl_write_word(rtlpriv, REG_AFE_XTAL_CTRL, 0x880F);
1307 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xF9);
1308 }
1309}
1310
1311static void _ResetDigitalProcedure2(struct ieee80211_hw *hw)
1312{
1313 struct rtl_priv *rtlpriv = rtl_priv(hw);
1314/*****************************
1315k. SYS_FUNC_EN 0x03[7:0] = 0x44 disable ELDR runction
1316l. SYS_CLKR 0x08[15:0] = 0x3083 disable ELDR clock
1317m. SYS_ISO_CTRL 0x01[7:0] = 0x83 isolated ELDR to PON
1318******************************/
1319 rtl_write_word(rtlpriv, REG_SYS_CLKR, 0x70A3);
1320 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL+1, 0x82);
1321}
1322
1323static void _DisableGPIO(struct ieee80211_hw *hw)
1324{
1325 struct rtl_priv *rtlpriv = rtl_priv(hw);
1326/***************************************
1327j. GPIO_PIN_CTRL 0x44[31:0]=0x000
1328k. Value = GPIO_PIN_CTRL[7:0]
1329l. GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); write ext PIN level
1330m. GPIO_MUXCFG 0x42 [15:0] = 0x0780
1331n. LEDCFG 0x4C[15:0] = 0x8080
1332***************************************/
1333 u8 value8;
1334 u16 value16;
1335 u32 value32;
1336
1337 /* 1. Disable GPIO[7:0] */
1338 rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL+2, 0x0000);
1339 value32 = rtl_read_dword(rtlpriv, REG_GPIO_PIN_CTRL) & 0xFFFF00FF;
1340 value8 = (u8) (value32&0x000000FF);
1341 value32 |= ((value8<<8) | 0x00FF0000);
1342 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, value32);
1343 /* 2. Disable GPIO[10:8] */
1344 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG+3, 0x00);
1345 value16 = rtl_read_word(rtlpriv, REG_GPIO_MUXCFG+2) & 0xFF0F;
1346 value8 = (u8) (value16&0x000F);
1347 value16 |= ((value8<<4) | 0x0780);
1348 rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL+2, value16);
1349 /* 3. Disable LED0 & 1 */
1350 rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080);
1351}
1352
1353static void _DisableAnalog(struct ieee80211_hw *hw, bool bWithoutHWSM)
1354{
1355 struct rtl_priv *rtlpriv = rtl_priv(hw);
1356 u16 value16 = 0;
1357 u8 value8 = 0;
1358
1359 if (bWithoutHWSM) {
1360 /*****************************
1361 n. LDOA15_CTRL 0x20[7:0] = 0x04 disable A15 power
1362 o. LDOV12D_CTRL 0x21[7:0] = 0x54 disable digital core power
1363 r. When driver call disable, the ASIC will turn off remaining
1364 clock automatically
1365 ******************************/
1366 rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x04);
1367 value8 = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL);
1368 value8 &= (~LDV12_EN);
1369 rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, value8);
1370 }
1371
1372/*****************************
1373h. SPS0_CTRL 0x11[7:0] = 0x23 enter PFM mode
1374i. APS_FSMCO 0x04[15:0] = 0x4802 set USB suspend
1375******************************/
1376 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);
1377 value16 |= (APDM_HOST | AFSM_HSUS | PFM_ALDN);
1378 rtl_write_word(rtlpriv, REG_APS_FSMCO, (u16)value16);
1379 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0E);
1380}
1381
1382static void _CardDisableHWSM(struct ieee80211_hw *hw)
1383{
1384 /* ==== RF Off Sequence ==== */
1385 _DisableRFAFEAndResetBB(hw);
1386 /* ==== Reset digital sequence ====== */
1387 _ResetDigitalProcedure1(hw, false);
1388 /* ==== Pull GPIO PIN to balance level and LED control ====== */
1389 _DisableGPIO(hw);
1390 /* ==== Disable analog sequence === */
1391 _DisableAnalog(hw, false);
1392}
1393
1394static void _CardDisableWithoutHWSM(struct ieee80211_hw *hw)
1395{
1396 /*==== RF Off Sequence ==== */
1397 _DisableRFAFEAndResetBB(hw);
1398 /* ==== Reset digital sequence ====== */
1399 _ResetDigitalProcedure1(hw, true);
1400 /* ==== Pull GPIO PIN to balance level and LED control ====== */
1401 _DisableGPIO(hw);
1402 /* ==== Reset digital sequence ====== */
1403 _ResetDigitalProcedure2(hw);
1404 /* ==== Disable analog sequence === */
1405 _DisableAnalog(hw, true);
1406}
1407
1408static void _rtl92cu_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
1409 u8 set_bits, u8 clear_bits)
1410{
1411 struct rtl_priv *rtlpriv = rtl_priv(hw);
1412 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1413
1414 rtlusb->reg_bcn_ctrl_val |= set_bits;
1415 rtlusb->reg_bcn_ctrl_val &= ~clear_bits;
1416 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlusb->reg_bcn_ctrl_val);
1417}
1418
1419static void _rtl92cu_stop_tx_beacon(struct ieee80211_hw *hw)
1420{
1421 struct rtl_priv *rtlpriv = rtl_priv(hw);
1422 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1423 u8 tmp1byte = 0;
1424 if (IS_NORMAL_CHIP(rtlhal->version)) {
1425 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
1426 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
1427 tmp1byte & (~BIT(6)));
1428 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
1429 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
1430 tmp1byte &= ~(BIT(0));
1431 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
1432 } else {
1433 rtl_write_byte(rtlpriv, REG_TXPAUSE,
1434 rtl_read_byte(rtlpriv, REG_TXPAUSE) | BIT(6));
1435 }
1436}
1437
1438static void _rtl92cu_resume_tx_beacon(struct ieee80211_hw *hw)
1439{
1440 struct rtl_priv *rtlpriv = rtl_priv(hw);
1441 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1442 u8 tmp1byte = 0;
1443
1444 if (IS_NORMAL_CHIP(rtlhal->version)) {
1445 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
1446 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
1447 tmp1byte | BIT(6));
1448 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
1449 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
1450 tmp1byte |= BIT(0);
1451 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
1452 } else {
1453 rtl_write_byte(rtlpriv, REG_TXPAUSE,
1454 rtl_read_byte(rtlpriv, REG_TXPAUSE) & (~BIT(6)));
1455 }
1456}
1457
1458static void _rtl92cu_enable_bcn_sub_func(struct ieee80211_hw *hw)
1459{
1460 struct rtl_priv *rtlpriv = rtl_priv(hw);
1461 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1462
1463 if (IS_NORMAL_CHIP(rtlhal->version))
1464 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(1));
1465 else
1466 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4));
1467}
1468
1469static void _rtl92cu_disable_bcn_sub_func(struct ieee80211_hw *hw)
1470{
1471 struct rtl_priv *rtlpriv = rtl_priv(hw);
1472 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1473
1474 if (IS_NORMAL_CHIP(rtlhal->version))
1475 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(1), 0);
1476 else
1477 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
1478}
1479
1480static int _rtl92cu_set_media_status(struct ieee80211_hw *hw,
1481 enum nl80211_iftype type)
1482{
1483 struct rtl_priv *rtlpriv = rtl_priv(hw);
1484 u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1485 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1486
1487 bt_msr &= 0xfc;
1488 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xFF);
1489 if (type == NL80211_IFTYPE_UNSPECIFIED || type ==
1490 NL80211_IFTYPE_STATION) {
1491 _rtl92cu_stop_tx_beacon(hw);
1492 _rtl92cu_enable_bcn_sub_func(hw);
1493 } else if (type == NL80211_IFTYPE_ADHOC || type == NL80211_IFTYPE_AP) {
1494 _rtl92cu_resume_tx_beacon(hw);
1495 _rtl92cu_disable_bcn_sub_func(hw);
1496 } else {
1497 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, ("Set HW_VAR_MEDIA_"
1498 "STATUS:No such media status(%x).\n", type));
1499 }
1500 switch (type) {
1501 case NL80211_IFTYPE_UNSPECIFIED:
1502 bt_msr |= MSR_NOLINK;
1503 ledaction = LED_CTL_LINK;
1504 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1505 ("Set Network type to NO LINK!\n"));
1506 break;
1507 case NL80211_IFTYPE_ADHOC:
1508 bt_msr |= MSR_ADHOC;
1509 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1510 ("Set Network type to Ad Hoc!\n"));
1511 break;
1512 case NL80211_IFTYPE_STATION:
1513 bt_msr |= MSR_INFRA;
1514 ledaction = LED_CTL_LINK;
1515 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1516 ("Set Network type to STA!\n"));
1517 break;
1518 case NL80211_IFTYPE_AP:
1519 bt_msr |= MSR_AP;
1520 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1521 ("Set Network type to AP!\n"));
1522 break;
1523 default:
1524 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1525 ("Network type %d not support!\n", type));
1526 goto error_out;
1527 }
1528 rtl_write_byte(rtlpriv, (MSR), bt_msr);
1529 rtlpriv->cfg->ops->led_control(hw, ledaction);
1530 if ((bt_msr & 0xfc) == MSR_AP)
1531 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1532 else
1533 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1534 return 0;
1535error_out:
1536 return 1;
1537}
1538
1539void rtl92cu_card_disable(struct ieee80211_hw *hw)
1540{
1541 struct rtl_priv *rtlpriv = rtl_priv(hw);
1542 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1543 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1544 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1545 enum nl80211_iftype opmode;
1546
1547 mac->link_state = MAC80211_NOLINK;
1548 opmode = NL80211_IFTYPE_UNSPECIFIED;
1549 _rtl92cu_set_media_status(hw, opmode);
1550 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1551 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1552 if (rtlusb->disableHWSM)
1553 _CardDisableHWSM(hw);
1554 else
1555 _CardDisableWithoutHWSM(hw);
1556}
1557
1558void rtl92cu_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1559{
1560 /* dummy routine needed for callback from rtl_op_configure_filter() */
1561}
1562
1563/*========================================================================== */
1564
1565static void _rtl92cu_set_check_bssid(struct ieee80211_hw *hw,
1566 enum nl80211_iftype type)
1567{
1568 struct rtl_priv *rtlpriv = rtl_priv(hw);
1569 u32 reg_rcr = rtl_read_dword(rtlpriv, REG_RCR);
1570 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1571 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1572 u8 filterout_non_associated_bssid = false;
1573
1574 switch (type) {
1575 case NL80211_IFTYPE_ADHOC:
1576 case NL80211_IFTYPE_STATION:
1577 filterout_non_associated_bssid = true;
1578 break;
1579 case NL80211_IFTYPE_UNSPECIFIED:
1580 case NL80211_IFTYPE_AP:
1581 default:
1582 break;
1583 }
1584 if (filterout_non_associated_bssid) {
1585 if (IS_NORMAL_CHIP(rtlhal->version)) {
1586 switch (rtlphy->current_io_type) {
1587 case IO_CMD_RESUME_DM_BY_SCAN:
1588 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1589 rtlpriv->cfg->ops->set_hw_reg(hw,
1590 HW_VAR_RCR, (u8 *)(®_rcr));
1591 /* enable update TSF */
1592 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4));
1593 break;
1594 case IO_CMD_PAUSE_DM_BY_SCAN:
1595 reg_rcr &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1596 rtlpriv->cfg->ops->set_hw_reg(hw,
1597 HW_VAR_RCR, (u8 *)(®_rcr));
1598 /* disable update TSF */
1599 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
1600 break;
1601 }
1602 } else {
1603 reg_rcr |= (RCR_CBSSID);
1604 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1605 (u8 *)(®_rcr));
1606 _rtl92cu_set_bcn_ctrl_reg(hw, 0, (BIT(4)|BIT(5)));
1607 }
1608 } else if (filterout_non_associated_bssid == false) {
1609 if (IS_NORMAL_CHIP(rtlhal->version)) {
1610 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1611 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1612 (u8 *)(®_rcr));
1613 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
1614 } else {
1615 reg_rcr &= (~RCR_CBSSID);
1616 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1617 (u8 *)(®_rcr));
1618 _rtl92cu_set_bcn_ctrl_reg(hw, (BIT(4)|BIT(5)), 0);
1619 }
1620 }
1621}
1622
1623int rtl92cu_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1624{
1625 if (_rtl92cu_set_media_status(hw, type))
1626 return -EOPNOTSUPP;
1627 _rtl92cu_set_check_bssid(hw, type);
1628 return 0;
1629}
1630
1631static void _InitBeaconParameters(struct ieee80211_hw *hw)
1632{
1633 struct rtl_priv *rtlpriv = rtl_priv(hw);
1634 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1635
1636 rtl_write_word(rtlpriv, REG_BCN_CTRL, 0x1010);
1637
1638 /* TODO: Remove these magic number */
1639 rtl_write_word(rtlpriv, REG_TBTT_PROHIBIT, 0x6404);
1640 rtl_write_byte(rtlpriv, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME);
1641 rtl_write_byte(rtlpriv, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME);
1642 /* Change beacon AIFS to the largest number
1643 * beacause test chip does not contension before sending beacon. */
1644 if (IS_NORMAL_CHIP(rtlhal->version))
1645 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660F);
1646 else
1647 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x66FF);
1648}
1649
1650static void _beacon_function_enable(struct ieee80211_hw *hw, bool Enable,
1651 bool Linked)
1652{
1653 struct rtl_priv *rtlpriv = rtl_priv(hw);
1654
1655 _rtl92cu_set_bcn_ctrl_reg(hw, (BIT(4) | BIT(3) | BIT(1)), 0x00);
1656 rtl_write_byte(rtlpriv, REG_RD_CTRL+1, 0x6F);
1657}
1658
1659void rtl92cu_set_beacon_related_registers(struct ieee80211_hw *hw)
1660{
1661
1662 struct rtl_priv *rtlpriv = rtl_priv(hw);
1663 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1664 u16 bcn_interval, atim_window;
1665 u32 value32;
1666
1667 bcn_interval = mac->beacon_interval;
1668 atim_window = 2; /*FIX MERGE */
1669 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1670 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1671 _InitBeaconParameters(hw);
1672 rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
1673 /*
1674 * Force beacon frame transmission even after receiving beacon frame
1675 * from other ad hoc STA
1676 *
1677 *
1678 * Reset TSF Timer to zero, added by Roger. 2008.06.24
1679 */
1680 value32 = rtl_read_dword(rtlpriv, REG_TCR);
1681 value32 &= ~TSFRST;
1682 rtl_write_dword(rtlpriv, REG_TCR, value32);
1683 value32 |= TSFRST;
1684 rtl_write_dword(rtlpriv, REG_TCR, value32);
1685 RT_TRACE(rtlpriv, COMP_INIT|COMP_BEACON, DBG_LOUD,
1686 ("SetBeaconRelatedRegisters8192CUsb(): Set TCR(%x)\n",
1687 value32));
1688 /* TODO: Modify later (Find the right parameters)
1689 * NOTE: Fix test chip's bug (about contention windows's randomness) */
1690 if ((mac->opmode == NL80211_IFTYPE_ADHOC) ||
1691 (mac->opmode == NL80211_IFTYPE_AP)) {
1692 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x50);
1693 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x50);
1694 }
1695 _beacon_function_enable(hw, true, true);
1696}
1697
1698void rtl92cu_set_beacon_interval(struct ieee80211_hw *hw)
1699{
1700 struct rtl_priv *rtlpriv = rtl_priv(hw);
1701 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1702 u16 bcn_interval = mac->beacon_interval;
1703
1704 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1705 ("beacon_interval:%d\n", bcn_interval));
1706 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1707}
1708
1709void rtl92cu_update_interrupt_mask(struct ieee80211_hw *hw,
1710 u32 add_msr, u32 rm_msr)
1711{
1712}
1713
1714void rtl92cu_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
1715{
1716 struct rtl_priv *rtlpriv = rtl_priv(hw);
1717 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1718 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1719
1720 switch (variable) {
1721 case HW_VAR_RCR:
1722 *((u32 *)(val)) = mac->rx_conf;
1723 break;
1724 case HW_VAR_RF_STATE:
1725 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
1726 break;
1727 case HW_VAR_FWLPS_RF_ON:{
1728 enum rf_pwrstate rfState;
1729 u32 val_rcr;
1730
1731 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,
1732 (u8 *)(&rfState));
1733 if (rfState == ERFOFF) {
1734 *((bool *) (val)) = true;
1735 } else {
1736 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
1737 val_rcr &= 0x00070000;
1738 if (val_rcr)
1739 *((bool *) (val)) = false;
1740 else
1741 *((bool *) (val)) = true;
1742 }
1743 break;
1744 }
1745 case HW_VAR_FW_PSMODE_STATUS:
1746 *((bool *) (val)) = ppsc->fw_current_inpsmode;
1747 break;
1748 case HW_VAR_CORRECT_TSF:{
1749 u64 tsf;
1750 u32 *ptsf_low = (u32 *)&tsf;
1751 u32 *ptsf_high = ((u32 *)&tsf) + 1;
1752
1753 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
1754 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
1755 *((u64 *)(val)) = tsf;
1756 break;
1757 }
1758 case HW_VAR_MGT_FILTER:
1759 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP0);
1760 break;
1761 case HW_VAR_CTRL_FILTER:
1762 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP1);
1763 break;
1764 case HW_VAR_DATA_FILTER:
1765 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP2);
1766 break;
1767 default:
1768 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1769 ("switch case not process\n"));
1770 break;
1771 }
1772}
1773
1774void rtl92cu_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
1775{
1776 struct rtl_priv *rtlpriv = rtl_priv(hw);
1777 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1778 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1779 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1780 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1781 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1782 enum wireless_mode wirelessmode = mac->mode;
1783 u8 idx = 0;
1784
1785 switch (variable) {
1786 case HW_VAR_ETHER_ADDR:{
1787 for (idx = 0; idx < ETH_ALEN; idx++) {
1788 rtl_write_byte(rtlpriv, (REG_MACID + idx),
1789 val[idx]);
1790 }
1791 break;
1792 }
1793 case HW_VAR_BASIC_RATE:{
1794 u16 rate_cfg = ((u16 *) val)[0];
1795 u8 rate_index = 0;
1796
1797 rate_cfg &= 0x15f;
1798 /* TODO */
1799 /* if (mac->current_network.vender == HT_IOT_PEER_CISCO
1800 * && ((rate_cfg & 0x150) == 0)) {
1801 * rate_cfg |= 0x010;
1802 * } */
1803 rate_cfg |= 0x01;
1804 rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
1805 rtl_write_byte(rtlpriv, REG_RRSR + 1,
1806 (rate_cfg >> 8) & 0xff);
1807 while (rate_cfg > 0x1) {
1808 rate_cfg >>= 1;
1809 rate_index++;
1810 }
1811 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
1812 rate_index);
1813 break;
1814 }
1815 case HW_VAR_BSSID:{
1816 for (idx = 0; idx < ETH_ALEN; idx++) {
1817 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
1818 val[idx]);
1819 }
1820 break;
1821 }
1822 case HW_VAR_SIFS:{
1823 rtl_write_byte(rtlpriv, REG_SIFS_CCK + 1, val[0]);
1824 rtl_write_byte(rtlpriv, REG_SIFS_OFDM + 1, val[1]);
1825 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
1826 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
1827 rtl_write_byte(rtlpriv, REG_R2T_SIFS+1, val[0]);
1828 rtl_write_byte(rtlpriv, REG_T2T_SIFS+1, val[0]);
1829 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1830 ("HW_VAR_SIFS\n"));
1831 break;
1832 }
1833 case HW_VAR_SLOT_TIME:{
1834 u8 e_aci;
1835 u8 QOS_MODE = 1;
1836
1837 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
1838 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1839 ("HW_VAR_SLOT_TIME %x\n", val[0]));
1840 if (QOS_MODE) {
1841 for (e_aci = 0; e_aci < AC_MAX; e_aci++)
1842 rtlpriv->cfg->ops->set_hw_reg(hw,
1843 HW_VAR_AC_PARAM,
1844 (u8 *)(&e_aci));
1845 } else {
1846 u8 sifstime = 0;
1847 u8 u1bAIFS;
1848
1849 if (IS_WIRELESS_MODE_A(wirelessmode) ||
1850 IS_WIRELESS_MODE_N_24G(wirelessmode) ||
1851 IS_WIRELESS_MODE_N_5G(wirelessmode))
1852 sifstime = 16;
1853 else
1854 sifstime = 10;
1855 u1bAIFS = sifstime + (2 * val[0]);
1856 rtl_write_byte(rtlpriv, REG_EDCA_VO_PARAM,
1857 u1bAIFS);
1858 rtl_write_byte(rtlpriv, REG_EDCA_VI_PARAM,
1859 u1bAIFS);
1860 rtl_write_byte(rtlpriv, REG_EDCA_BE_PARAM,
1861 u1bAIFS);
1862 rtl_write_byte(rtlpriv, REG_EDCA_BK_PARAM,
1863 u1bAIFS);
1864 }
1865 break;
1866 }
1867 case HW_VAR_ACK_PREAMBLE:{
1868 u8 reg_tmp;
1869 u8 short_preamble = (bool) (*(u8 *) val);
1870 reg_tmp = 0;
1871 if (short_preamble)
1872 reg_tmp |= 0x80;
1873 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
1874 break;
1875 }
1876 case HW_VAR_AMPDU_MIN_SPACE:{
1877 u8 min_spacing_to_set;
1878 u8 sec_min_space;
1879
1880 min_spacing_to_set = *((u8 *) val);
1881 if (min_spacing_to_set <= 7) {
1882 switch (rtlpriv->sec.pairwise_enc_algorithm) {
1883 case NO_ENCRYPTION:
1884 case AESCCMP_ENCRYPTION:
1885 sec_min_space = 0;
1886 break;
1887 case WEP40_ENCRYPTION:
1888 case WEP104_ENCRYPTION:
1889 case TKIP_ENCRYPTION:
1890 sec_min_space = 6;
1891 break;
1892 default:
1893 sec_min_space = 7;
1894 break;
1895 }
1896 if (min_spacing_to_set < sec_min_space)
1897 min_spacing_to_set = sec_min_space;
1898 mac->min_space_cfg = ((mac->min_space_cfg &
1899 0xf8) |
1900 min_spacing_to_set);
1901 *val = min_spacing_to_set;
1902 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1903 ("Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
1904 mac->min_space_cfg));
1905 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
1906 mac->min_space_cfg);
1907 }
1908 break;
1909 }
1910 case HW_VAR_SHORTGI_DENSITY:{
1911 u8 density_to_set;
1912
1913 density_to_set = *((u8 *) val);
1914 density_to_set &= 0x1f;
1915 mac->min_space_cfg &= 0x07;
1916 mac->min_space_cfg |= (density_to_set << 3);
1917 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1918 ("Set HW_VAR_SHORTGI_DENSITY: %#x\n",
1919 mac->min_space_cfg));
1920 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
1921 mac->min_space_cfg);
1922 break;
1923 }
1924 case HW_VAR_AMPDU_FACTOR:{
1925 u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9};
1926 u8 factor_toset;
1927 u8 *p_regtoset = NULL;
1928 u8 index = 0;
1929
1930 p_regtoset = regtoset_normal;
1931 factor_toset = *((u8 *) val);
1932 if (factor_toset <= 3) {
1933 factor_toset = (1 << (factor_toset + 2));
1934 if (factor_toset > 0xf)
1935 factor_toset = 0xf;
1936 for (index = 0; index < 4; index++) {
1937 if ((p_regtoset[index] & 0xf0) >
1938 (factor_toset << 4))
1939 p_regtoset[index] =
1940 (p_regtoset[index] & 0x0f)
1941 | (factor_toset << 4);
1942 if ((p_regtoset[index] & 0x0f) >
1943 factor_toset)
1944 p_regtoset[index] =
1945 (p_regtoset[index] & 0xf0)
1946 | (factor_toset);
1947 rtl_write_byte(rtlpriv,
1948 (REG_AGGLEN_LMT + index),
1949 p_regtoset[index]);
1950 }
1951 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1952 ("Set HW_VAR_AMPDU_FACTOR: %#x\n",
1953 factor_toset));
1954 }
1955 break;
1956 }
1957 case HW_VAR_AC_PARAM:{
1958 u8 e_aci = *((u8 *) val);
1959 u32 u4b_ac_param;
1960 u16 cw_min = le16_to_cpu(mac->ac[e_aci].cw_min);
1961 u16 cw_max = le16_to_cpu(mac->ac[e_aci].cw_max);
1962 u16 tx_op = le16_to_cpu(mac->ac[e_aci].tx_op);
1963
1964 u4b_ac_param = (u32) mac->ac[e_aci].aifs;
1965 u4b_ac_param |= (u32) ((cw_min & 0xF) <<
1966 AC_PARAM_ECW_MIN_OFFSET);
1967 u4b_ac_param |= (u32) ((cw_max & 0xF) <<
1968 AC_PARAM_ECW_MAX_OFFSET);
1969 u4b_ac_param |= (u32) tx_op << AC_PARAM_TXOP_OFFSET;
1970 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1971 ("queue:%x, ac_param:%x\n", e_aci,
1972 u4b_ac_param));
1973 switch (e_aci) {
1974 case AC1_BK:
1975 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM,
1976 u4b_ac_param);
1977 break;
1978 case AC0_BE:
1979 rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM,
1980 u4b_ac_param);
1981 break;
1982 case AC2_VI:
1983 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM,
1984 u4b_ac_param);
1985 break;
1986 case AC3_VO:
1987 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM,
1988 u4b_ac_param);
1989 break;
1990 default:
1991 RT_ASSERT(false, ("SetHwReg8185(): invalid"
1992 " aci: %d !\n", e_aci));
1993 break;
1994 }
1995 if (rtlusb->acm_method != eAcmWay2_SW)
1996 rtlpriv->cfg->ops->set_hw_reg(hw,
1997 HW_VAR_ACM_CTRL, (u8 *)(&e_aci));
1998 break;
1999 }
2000 case HW_VAR_ACM_CTRL:{
2001 u8 e_aci = *((u8 *) val);
2002 union aci_aifsn *p_aci_aifsn = (union aci_aifsn *)
2003 (&(mac->ac[0].aifs));
2004 u8 acm = p_aci_aifsn->f.acm;
2005 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
2006
2007 acm_ctrl =
2008 acm_ctrl | ((rtlusb->acm_method == 2) ? 0x0 : 0x1);
2009 if (acm) {
2010 switch (e_aci) {
2011 case AC0_BE:
2012 acm_ctrl |= AcmHw_BeqEn;
2013 break;
2014 case AC2_VI:
2015 acm_ctrl |= AcmHw_ViqEn;
2016 break;
2017 case AC3_VO:
2018 acm_ctrl |= AcmHw_VoqEn;
2019 break;
2020 default:
2021 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2022 ("HW_VAR_ACM_CTRL acm set "
2023 "failed: eACI is %d\n", acm));
2024 break;
2025 }
2026 } else {
2027 switch (e_aci) {
2028 case AC0_BE:
2029 acm_ctrl &= (~AcmHw_BeqEn);
2030 break;
2031 case AC2_VI:
2032 acm_ctrl &= (~AcmHw_ViqEn);
2033 break;
2034 case AC3_VO:
2035 acm_ctrl &= (~AcmHw_BeqEn);
2036 break;
2037 default:
2038 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2039 ("switch case not process\n"));
2040 break;
2041 }
2042 }
2043 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
2044 ("SetHwReg8190pci(): [HW_VAR_ACM_CTRL] "
2045 "Write 0x%X\n", acm_ctrl));
2046 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
2047 break;
2048 }
2049 case HW_VAR_RCR:{
2050 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
2051 mac->rx_conf = ((u32 *) (val))[0];
2052 RT_TRACE(rtlpriv, COMP_RECV, DBG_DMESG,
2053 ("### Set RCR(0x%08x) ###\n", mac->rx_conf));
2054 break;
2055 }
2056 case HW_VAR_RETRY_LIMIT:{
2057 u8 retry_limit = ((u8 *) (val))[0];
2058
2059 rtl_write_word(rtlpriv, REG_RL,
2060 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
2061 retry_limit << RETRY_LIMIT_LONG_SHIFT);
2062 RT_TRACE(rtlpriv, COMP_MLME, DBG_DMESG, ("Set HW_VAR_R"
2063 "ETRY_LIMIT(0x%08x)\n", retry_limit));
2064 break;
2065 }
2066 case HW_VAR_DUAL_TSF_RST:
2067 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
2068 break;
2069 case HW_VAR_EFUSE_BYTES:
2070 rtlefuse->efuse_usedbytes = *((u16 *) val);
2071 break;
2072 case HW_VAR_EFUSE_USAGE:
2073 rtlefuse->efuse_usedpercentage = *((u8 *) val);
2074 break;
2075 case HW_VAR_IO_CMD:
2076 rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val));
2077 break;
2078 case HW_VAR_WPA_CONFIG:
2079 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *) val));
2080 break;
2081 case HW_VAR_SET_RPWM:{
2082 u8 rpwm_val = rtl_read_byte(rtlpriv, REG_USB_HRPWM);
2083
2084 if (rpwm_val & BIT(7))
2085 rtl_write_byte(rtlpriv, REG_USB_HRPWM,
2086 (*(u8 *)val));
2087 else
2088 rtl_write_byte(rtlpriv, REG_USB_HRPWM,
2089 ((*(u8 *)val) | BIT(7)));
2090 break;
2091 }
2092 case HW_VAR_H2C_FW_PWRMODE:{
2093 u8 psmode = (*(u8 *) val);
2094
2095 if ((psmode != FW_PS_ACTIVE_MODE) &&
2096 (!IS_92C_SERIAL(rtlhal->version)))
2097 rtl92c_dm_rf_saving(hw, true);
2098 rtl92c_set_fw_pwrmode_cmd(hw, (*(u8 *) val));
2099 break;
2100 }
2101 case HW_VAR_FW_PSMODE_STATUS:
2102 ppsc->fw_current_inpsmode = *((bool *) val);
2103 break;
2104 case HW_VAR_H2C_FW_JOINBSSRPT:{
2105 u8 mstatus = (*(u8 *) val);
2106 u8 tmp_reg422;
2107 bool recover = false;
2108
2109 if (mstatus == RT_MEDIA_CONNECT) {
2110 rtlpriv->cfg->ops->set_hw_reg(hw,
2111 HW_VAR_AID, NULL);
2112 rtl_write_byte(rtlpriv, REG_CR + 1, 0x03);
2113 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3));
2114 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
2115 tmp_reg422 = rtl_read_byte(rtlpriv,
2116 REG_FWHW_TXQ_CTRL + 2);
2117 if (tmp_reg422 & BIT(6))
2118 recover = true;
2119 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
2120 tmp_reg422 & (~BIT(6)));
2121 rtl92c_set_fw_rsvdpagepkt(hw, 0);
2122 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0);
2123 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4));
2124 if (recover)
2125 rtl_write_byte(rtlpriv,
2126 REG_FWHW_TXQ_CTRL + 2,
2127 tmp_reg422 | BIT(6));
2128 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
2129 }
2130 rtl92c_set_fw_joinbss_report_cmd(hw, (*(u8 *) val));
2131 break;
2132 }
2133 case HW_VAR_AID:{
2134 u16 u2btmp;
2135
2136 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
2137 u2btmp &= 0xC000;
2138 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT,
2139 (u2btmp | mac->assoc_id));
2140 break;
2141 }
2142 case HW_VAR_CORRECT_TSF:{
2143 u8 btype_ibss = ((u8 *) (val))[0];
2144
2145 if (btype_ibss)
2146 _rtl92cu_stop_tx_beacon(hw);
2147 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3));
2148 rtl_write_dword(rtlpriv, REG_TSFTR, (u32)(mac->tsf &
2149 0xffffffff));
2150 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
2151 (u32)((mac->tsf >> 32) & 0xffffffff));
2152 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0);
2153 if (btype_ibss)
2154 _rtl92cu_resume_tx_beacon(hw);
2155 break;
2156 }
2157 case HW_VAR_MGT_FILTER:
2158 rtl_write_word(rtlpriv, REG_RXFLTMAP0, *(u16 *)val);
2159 break;
2160 case HW_VAR_CTRL_FILTER:
2161 rtl_write_word(rtlpriv, REG_RXFLTMAP1, *(u16 *)val);
2162 break;
2163 case HW_VAR_DATA_FILTER:
2164 rtl_write_word(rtlpriv, REG_RXFLTMAP2, *(u16 *)val);
2165 break;
2166 default:
2167 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("switch case "
2168 "not process\n"));
2169 break;
2170 }
2171}
2172
2173void rtl92cu_update_hal_rate_table(struct ieee80211_hw *hw,
2174 struct ieee80211_sta *sta,
2175 u8 rssi_level)
2176{
2177 struct rtl_priv *rtlpriv = rtl_priv(hw);
2178 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2179 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2180 u32 ratr_value = (u32) mac->basic_rates;
2181 u8 *mcsrate = mac->mcs;
2182 u8 ratr_index = 0;
2183 u8 nmode = mac->ht_enable;
2184 u8 mimo_ps = 1;
2185 u16 shortgi_rate = 0;
2186 u32 tmp_ratr_value = 0;
2187 u8 curtxbw_40mhz = mac->bw_40;
2188 u8 curshortgi_40mhz = mac->sgi_40;
2189 u8 curshortgi_20mhz = mac->sgi_20;
2190 enum wireless_mode wirelessmode = mac->mode;
2191
2192 ratr_value |= ((*(u16 *) (mcsrate))) << 12;
2193 switch (wirelessmode) {
2194 case WIRELESS_MODE_B:
2195 if (ratr_value & 0x0000000c)
2196 ratr_value &= 0x0000000d;
2197 else
2198 ratr_value &= 0x0000000f;
2199 break;
2200 case WIRELESS_MODE_G:
2201 ratr_value &= 0x00000FF5;
2202 break;
2203 case WIRELESS_MODE_N_24G:
2204 case WIRELESS_MODE_N_5G:
2205 nmode = 1;
2206 if (mimo_ps == 0) {
2207 ratr_value &= 0x0007F005;
2208 } else {
2209 u32 ratr_mask;
2210
2211 if (get_rf_type(rtlphy) == RF_1T2R ||
2212 get_rf_type(rtlphy) == RF_1T1R)
2213 ratr_mask = 0x000ff005;
2214 else
2215 ratr_mask = 0x0f0ff005;
2216 if (curtxbw_40mhz)
2217 ratr_mask |= 0x00000010;
2218 ratr_value &= ratr_mask;
2219 }
2220 break;
2221 default:
2222 if (rtlphy->rf_type == RF_1T2R)
2223 ratr_value &= 0x000ff0ff;
2224 else
2225 ratr_value &= 0x0f0ff0ff;
2226 break;
2227 }
2228 ratr_value &= 0x0FFFFFFF;
2229 if (nmode && ((curtxbw_40mhz && curshortgi_40mhz) ||
2230 (!curtxbw_40mhz && curshortgi_20mhz))) {
2231 ratr_value |= 0x10000000;
2232 tmp_ratr_value = (ratr_value >> 12);
2233 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2234 if ((1 << shortgi_rate) & tmp_ratr_value)
2235 break;
2236 }
2237 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2238 (shortgi_rate << 4) | (shortgi_rate);
2239 }
2240 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
2241 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, ("%x\n", rtl_read_dword(rtlpriv,
2242 REG_ARFR0)));
2243}
2244
2245void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw, u8 rssi_level)
2246{
2247 struct rtl_priv *rtlpriv = rtl_priv(hw);
2248 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2249 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2250 u32 ratr_bitmap = (u32) mac->basic_rates;
2251 u8 *p_mcsrate = mac->mcs;
2252 u8 ratr_index = 0;
2253 u8 curtxbw_40mhz = mac->bw_40;
2254 u8 curshortgi_40mhz = mac->sgi_40;
2255 u8 curshortgi_20mhz = mac->sgi_20;
2256 enum wireless_mode wirelessmode = mac->mode;
2257 bool shortgi = false;
2258 u8 rate_mask[5];
2259 u8 macid = 0;
2260 u8 mimops = 1;
2261
2262 ratr_bitmap |= (p_mcsrate[1] << 20) | (p_mcsrate[0] << 12);
2263 switch (wirelessmode) {
2264 case WIRELESS_MODE_B:
2265 ratr_index = RATR_INX_WIRELESS_B;
2266 if (ratr_bitmap & 0x0000000c)
2267 ratr_bitmap &= 0x0000000d;
2268 else
2269 ratr_bitmap &= 0x0000000f;
2270 break;
2271 case WIRELESS_MODE_G:
2272 ratr_index = RATR_INX_WIRELESS_GB;
2273 if (rssi_level == 1)
2274 ratr_bitmap &= 0x00000f00;
2275 else if (rssi_level == 2)
2276 ratr_bitmap &= 0x00000ff0;
2277 else
2278 ratr_bitmap &= 0x00000ff5;
2279 break;
2280 case WIRELESS_MODE_A:
2281 ratr_index = RATR_INX_WIRELESS_A;
2282 ratr_bitmap &= 0x00000ff0;
2283 break;
2284 case WIRELESS_MODE_N_24G:
2285 case WIRELESS_MODE_N_5G:
2286 ratr_index = RATR_INX_WIRELESS_NGB;
2287 if (mimops == 0) {
2288 if (rssi_level == 1)
2289 ratr_bitmap &= 0x00070000;
2290 else if (rssi_level == 2)
2291 ratr_bitmap &= 0x0007f000;
2292 else
2293 ratr_bitmap &= 0x0007f005;
2294 } else {
2295 if (rtlphy->rf_type == RF_1T2R ||
2296 rtlphy->rf_type == RF_1T1R) {
2297 if (curtxbw_40mhz) {
2298 if (rssi_level == 1)
2299 ratr_bitmap &= 0x000f0000;
2300 else if (rssi_level == 2)
2301 ratr_bitmap &= 0x000ff000;
2302 else
2303 ratr_bitmap &= 0x000ff015;
2304 } else {
2305 if (rssi_level == 1)
2306 ratr_bitmap &= 0x000f0000;
2307 else if (rssi_level == 2)
2308 ratr_bitmap &= 0x000ff000;
2309 else
2310 ratr_bitmap &= 0x000ff005;
2311 }
2312 } else {
2313 if (curtxbw_40mhz) {
2314 if (rssi_level == 1)
2315 ratr_bitmap &= 0x0f0f0000;
2316 else if (rssi_level == 2)
2317 ratr_bitmap &= 0x0f0ff000;
2318 else
2319 ratr_bitmap &= 0x0f0ff015;
2320 } else {
2321 if (rssi_level == 1)
2322 ratr_bitmap &= 0x0f0f0000;
2323 else if (rssi_level == 2)
2324 ratr_bitmap &= 0x0f0ff000;
2325 else
2326 ratr_bitmap &= 0x0f0ff005;
2327 }
2328 }
2329 }
2330 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2331 (!curtxbw_40mhz && curshortgi_20mhz)) {
2332 if (macid == 0)
2333 shortgi = true;
2334 else if (macid == 1)
2335 shortgi = false;
2336 }
2337 break;
2338 default:
2339 ratr_index = RATR_INX_WIRELESS_NGB;
2340 if (rtlphy->rf_type == RF_1T2R)
2341 ratr_bitmap &= 0x000ff0ff;
2342 else
2343 ratr_bitmap &= 0x0f0ff0ff;
2344 break;
2345 }
2346 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, ("ratr_bitmap :%x\n",
2347 ratr_bitmap));
2348 *(u32 *)&rate_mask = ((ratr_bitmap & 0x0fffffff) |
2349 ratr_index << 28);
2350 rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
2351 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, ("Rate_index:%x, "
2352 "ratr_val:%x, %x:%x:%x:%x:%x\n",
2353 ratr_index, ratr_bitmap,
2354 rate_mask[0], rate_mask[1],
2355 rate_mask[2], rate_mask[3],
2356 rate_mask[4]));
2357 rtl92c_fill_h2c_cmd(hw, H2C_RA_MASK, 5, rate_mask);
2358}
2359
2360void rtl92cu_update_channel_access_setting(struct ieee80211_hw *hw)
2361{
2362 struct rtl_priv *rtlpriv = rtl_priv(hw);
2363 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2364 u16 sifs_timer;
2365
2366 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2367 (u8 *)&mac->slot_time);
2368 if (!mac->ht_enable)
2369 sifs_timer = 0x0a0a;
2370 else
2371 sifs_timer = 0x0e0e;
2372 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2373}
2374
2375bool rtl92cu_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 * valid)
2376{
2377 struct rtl_priv *rtlpriv = rtl_priv(hw);
2378 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2379 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2380 enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
2381 u8 u1tmp = 0;
2382 bool actuallyset = false;
2383 unsigned long flag = 0;
2384 /* to do - usb autosuspend */
2385 u8 usb_autosuspend = 0;
2386
2387 if (ppsc->swrf_processing)
2388 return false;
2389 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2390 if (ppsc->rfchange_inprogress) {
2391 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2392 return false;
2393 } else {
2394 ppsc->rfchange_inprogress = true;
2395 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2396 }
2397 cur_rfstate = ppsc->rfpwr_state;
2398 if (usb_autosuspend) {
2399 /* to do................... */
2400 } else {
2401 if (ppsc->pwrdown_mode) {
2402 u1tmp = rtl_read_byte(rtlpriv, REG_HSISR);
2403 e_rfpowerstate_toset = (u1tmp & BIT(7)) ?
2404 ERFOFF : ERFON;
2405 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
2406 ("pwrdown, 0x5c(BIT7)=%02x\n", u1tmp));
2407 } else {
2408 rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG,
2409 rtl_read_byte(rtlpriv,
2410 REG_MAC_PINMUX_CFG) & ~(BIT(3)));
2411 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
2412 e_rfpowerstate_toset = (u1tmp & BIT(3)) ?
2413 ERFON : ERFOFF;
2414 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
2415 ("GPIO_IN=%02x\n", u1tmp));
2416 }
2417 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, ("N-SS RF =%x\n",
2418 e_rfpowerstate_toset));
2419 }
2420 if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
2421 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, ("GPIOChangeRF - HW "
2422 "Radio ON, RF ON\n"));
2423 ppsc->hwradiooff = false;
2424 actuallyset = true;
2425 } else if ((!ppsc->hwradiooff) && (e_rfpowerstate_toset ==
2426 ERFOFF)) {
2427 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, ("GPIOChangeRF - HW"
2428 " Radio OFF\n"));
2429 ppsc->hwradiooff = true;
2430 actuallyset = true;
2431 } else {
2432 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD ,
2433 ("pHalData->bHwRadioOff and eRfPowerStateToSet do not"
2434 " match: pHalData->bHwRadioOff %x, eRfPowerStateToSet "
2435 "%x\n", ppsc->hwradiooff, e_rfpowerstate_toset));
2436 }
2437 if (actuallyset) {
2438 ppsc->hwradiooff = 1;
2439 if (e_rfpowerstate_toset == ERFON) {
2440 if ((ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) &&
2441 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM))
2442 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2443 else if ((ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3)
2444 && RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3))
2445 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2446 }
2447 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2448 ppsc->rfchange_inprogress = false;
2449 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2450 /* For power down module, we need to enable register block
2451 * contrl reg at 0x1c. Then enable power down control bit
2452 * of register 0x04 BIT4 and BIT15 as 1.
2453 */
2454 if (ppsc->pwrdown_mode && e_rfpowerstate_toset == ERFOFF) {
2455 /* Enable register area 0x0-0xc. */
2456 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0);
2457 if (IS_HARDWARE_TYPE_8723U(rtlhal)) {
2458 /*
2459 * We should configure HW PDn source for WiFi
2460 * ONLY, and then our HW will be set in
2461 * power-down mode if PDn source from all
2462 * functions are configured.
2463 */
2464 u1tmp = rtl_read_byte(rtlpriv,
2465 REG_MULTI_FUNC_CTRL);
2466 rtl_write_byte(rtlpriv, REG_MULTI_FUNC_CTRL,
2467 (u1tmp|WL_HWPDN_EN));
2468 } else {
2469 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x8812);
2470 }
2471 }
2472 if (e_rfpowerstate_toset == ERFOFF) {
2473 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM)
2474 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2475 else if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3)
2476 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2477 }
2478 } else if (e_rfpowerstate_toset == ERFOFF || cur_rfstate == ERFOFF) {
2479 /* Enter D3 or ASPM after GPIO had been done. */
2480 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM)
2481 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2482 else if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3)
2483 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2484 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2485 ppsc->rfchange_inprogress = false;
2486 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2487 } else {
2488 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2489 ppsc->rfchange_inprogress = false;
2490 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2491 }
2492 *valid = 1;
2493 return !ppsc->hwradiooff;
2494}
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2012 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "../efuse.h"
32#include "../base.h"
33#include "../cam.h"
34#include "../ps.h"
35#include "../usb.h"
36#include "reg.h"
37#include "def.h"
38#include "phy.h"
39#include "mac.h"
40#include "dm.h"
41#include "hw.h"
42#include "../rtl8192ce/hw.h"
43#include "trx.h"
44#include "led.h"
45#include "table.h"
46
47static void _rtl92cu_phy_param_tab_init(struct ieee80211_hw *hw)
48{
49 struct rtl_priv *rtlpriv = rtl_priv(hw);
50 struct rtl_phy *rtlphy = &(rtlpriv->phy);
51 struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv);
52
53 rtlphy->hwparam_tables[MAC_REG].length = RTL8192CUMAC_2T_ARRAYLENGTH;
54 rtlphy->hwparam_tables[MAC_REG].pdata = RTL8192CUMAC_2T_ARRAY;
55 if (IS_HIGHT_PA(rtlefuse->board_type)) {
56 rtlphy->hwparam_tables[PHY_REG_PG].length =
57 RTL8192CUPHY_REG_Array_PG_HPLength;
58 rtlphy->hwparam_tables[PHY_REG_PG].pdata =
59 RTL8192CUPHY_REG_Array_PG_HP;
60 } else {
61 rtlphy->hwparam_tables[PHY_REG_PG].length =
62 RTL8192CUPHY_REG_ARRAY_PGLENGTH;
63 rtlphy->hwparam_tables[PHY_REG_PG].pdata =
64 RTL8192CUPHY_REG_ARRAY_PG;
65 }
66 /* 2T */
67 rtlphy->hwparam_tables[PHY_REG_2T].length =
68 RTL8192CUPHY_REG_2TARRAY_LENGTH;
69 rtlphy->hwparam_tables[PHY_REG_2T].pdata =
70 RTL8192CUPHY_REG_2TARRAY;
71 rtlphy->hwparam_tables[RADIOA_2T].length =
72 RTL8192CURADIOA_2TARRAYLENGTH;
73 rtlphy->hwparam_tables[RADIOA_2T].pdata =
74 RTL8192CURADIOA_2TARRAY;
75 rtlphy->hwparam_tables[RADIOB_2T].length =
76 RTL8192CURADIOB_2TARRAYLENGTH;
77 rtlphy->hwparam_tables[RADIOB_2T].pdata =
78 RTL8192CU_RADIOB_2TARRAY;
79 rtlphy->hwparam_tables[AGCTAB_2T].length =
80 RTL8192CUAGCTAB_2TARRAYLENGTH;
81 rtlphy->hwparam_tables[AGCTAB_2T].pdata =
82 RTL8192CUAGCTAB_2TARRAY;
83 /* 1T */
84 if (IS_HIGHT_PA(rtlefuse->board_type)) {
85 rtlphy->hwparam_tables[PHY_REG_1T].length =
86 RTL8192CUPHY_REG_1T_HPArrayLength;
87 rtlphy->hwparam_tables[PHY_REG_1T].pdata =
88 RTL8192CUPHY_REG_1T_HPArray;
89 rtlphy->hwparam_tables[RADIOA_1T].length =
90 RTL8192CURadioA_1T_HPArrayLength;
91 rtlphy->hwparam_tables[RADIOA_1T].pdata =
92 RTL8192CURadioA_1T_HPArray;
93 rtlphy->hwparam_tables[RADIOB_1T].length =
94 RTL8192CURADIOB_1TARRAYLENGTH;
95 rtlphy->hwparam_tables[RADIOB_1T].pdata =
96 RTL8192CU_RADIOB_1TARRAY;
97 rtlphy->hwparam_tables[AGCTAB_1T].length =
98 RTL8192CUAGCTAB_1T_HPArrayLength;
99 rtlphy->hwparam_tables[AGCTAB_1T].pdata =
100 Rtl8192CUAGCTAB_1T_HPArray;
101 } else {
102 rtlphy->hwparam_tables[PHY_REG_1T].length =
103 RTL8192CUPHY_REG_1TARRAY_LENGTH;
104 rtlphy->hwparam_tables[PHY_REG_1T].pdata =
105 RTL8192CUPHY_REG_1TARRAY;
106 rtlphy->hwparam_tables[RADIOA_1T].length =
107 RTL8192CURADIOA_1TARRAYLENGTH;
108 rtlphy->hwparam_tables[RADIOA_1T].pdata =
109 RTL8192CU_RADIOA_1TARRAY;
110 rtlphy->hwparam_tables[RADIOB_1T].length =
111 RTL8192CURADIOB_1TARRAYLENGTH;
112 rtlphy->hwparam_tables[RADIOB_1T].pdata =
113 RTL8192CU_RADIOB_1TARRAY;
114 rtlphy->hwparam_tables[AGCTAB_1T].length =
115 RTL8192CUAGCTAB_1TARRAYLENGTH;
116 rtlphy->hwparam_tables[AGCTAB_1T].pdata =
117 RTL8192CUAGCTAB_1TARRAY;
118 }
119}
120
121static void _rtl92cu_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
122 bool autoload_fail,
123 u8 *hwinfo)
124{
125 struct rtl_priv *rtlpriv = rtl_priv(hw);
126 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
127 u8 rf_path, index, tempval;
128 u16 i;
129
130 for (rf_path = 0; rf_path < 2; rf_path++) {
131 for (i = 0; i < 3; i++) {
132 if (!autoload_fail) {
133 rtlefuse->
134 eeprom_chnlarea_txpwr_cck[rf_path][i] =
135 hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i];
136 rtlefuse->
137 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
138 hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 +
139 i];
140 } else {
141 rtlefuse->
142 eeprom_chnlarea_txpwr_cck[rf_path][i] =
143 EEPROM_DEFAULT_TXPOWERLEVEL;
144 rtlefuse->
145 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
146 EEPROM_DEFAULT_TXPOWERLEVEL;
147 }
148 }
149 }
150 for (i = 0; i < 3; i++) {
151 if (!autoload_fail)
152 tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i];
153 else
154 tempval = EEPROM_DEFAULT_HT40_2SDIFF;
155 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_A][i] =
156 (tempval & 0xf);
157 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_B][i] =
158 ((tempval & 0xf0) >> 4);
159 }
160 for (rf_path = 0; rf_path < 2; rf_path++)
161 for (i = 0; i < 3; i++)
162 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
163 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n",
164 rf_path, i,
165 rtlefuse->
166 eeprom_chnlarea_txpwr_cck[rf_path][i]);
167 for (rf_path = 0; rf_path < 2; rf_path++)
168 for (i = 0; i < 3; i++)
169 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
170 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
171 rf_path, i,
172 rtlefuse->
173 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]);
174 for (rf_path = 0; rf_path < 2; rf_path++)
175 for (i = 0; i < 3; i++)
176 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
177 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
178 rf_path, i,
179 rtlefuse->
180 eprom_chnl_txpwr_ht40_2sdf[rf_path][i]);
181 for (rf_path = 0; rf_path < 2; rf_path++) {
182 for (i = 0; i < 14; i++) {
183 index = _rtl92c_get_chnl_group((u8) i);
184 rtlefuse->txpwrlevel_cck[rf_path][i] =
185 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][index];
186 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
187 rtlefuse->
188 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index];
189 if ((rtlefuse->
190 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index] -
191 rtlefuse->
192 eprom_chnl_txpwr_ht40_2sdf[rf_path][index])
193 > 0) {
194 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
195 rtlefuse->
196 eeprom_chnlarea_txpwr_ht40_1s[rf_path]
197 [index] - rtlefuse->
198 eprom_chnl_txpwr_ht40_2sdf[rf_path]
199 [index];
200 } else {
201 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0;
202 }
203 }
204 for (i = 0; i < 14; i++) {
205 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
206 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n", rf_path, i,
207 rtlefuse->txpwrlevel_cck[rf_path][i],
208 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
209 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]);
210 }
211 }
212 for (i = 0; i < 3; i++) {
213 if (!autoload_fail) {
214 rtlefuse->eeprom_pwrlimit_ht40[i] =
215 hwinfo[EEPROM_TXPWR_GROUP + i];
216 rtlefuse->eeprom_pwrlimit_ht20[i] =
217 hwinfo[EEPROM_TXPWR_GROUP + 3 + i];
218 } else {
219 rtlefuse->eeprom_pwrlimit_ht40[i] = 0;
220 rtlefuse->eeprom_pwrlimit_ht20[i] = 0;
221 }
222 }
223 for (rf_path = 0; rf_path < 2; rf_path++) {
224 for (i = 0; i < 14; i++) {
225 index = _rtl92c_get_chnl_group((u8) i);
226 if (rf_path == RF90_PATH_A) {
227 rtlefuse->pwrgroup_ht20[rf_path][i] =
228 (rtlefuse->eeprom_pwrlimit_ht20[index]
229 & 0xf);
230 rtlefuse->pwrgroup_ht40[rf_path][i] =
231 (rtlefuse->eeprom_pwrlimit_ht40[index]
232 & 0xf);
233 } else if (rf_path == RF90_PATH_B) {
234 rtlefuse->pwrgroup_ht20[rf_path][i] =
235 ((rtlefuse->eeprom_pwrlimit_ht20[index]
236 & 0xf0) >> 4);
237 rtlefuse->pwrgroup_ht40[rf_path][i] =
238 ((rtlefuse->eeprom_pwrlimit_ht40[index]
239 & 0xf0) >> 4);
240 }
241 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
242 "RF-%d pwrgroup_ht20[%d] = 0x%x\n",
243 rf_path, i,
244 rtlefuse->pwrgroup_ht20[rf_path][i]);
245 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
246 "RF-%d pwrgroup_ht40[%d] = 0x%x\n",
247 rf_path, i,
248 rtlefuse->pwrgroup_ht40[rf_path][i]);
249 }
250 }
251 for (i = 0; i < 14; i++) {
252 index = _rtl92c_get_chnl_group((u8) i);
253 if (!autoload_fail)
254 tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index];
255 else
256 tempval = EEPROM_DEFAULT_HT20_DIFF;
257 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
258 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
259 ((tempval >> 4) & 0xF);
260 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3))
261 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0;
262 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3))
263 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0;
264 index = _rtl92c_get_chnl_group((u8) i);
265 if (!autoload_fail)
266 tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index];
267 else
268 tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
269 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF);
270 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
271 ((tempval >> 4) & 0xF);
272 }
273 rtlefuse->legacy_ht_txpowerdiff =
274 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7];
275 for (i = 0; i < 14; i++)
276 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
277 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n",
278 i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]);
279 for (i = 0; i < 14; i++)
280 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
281 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n",
282 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]);
283 for (i = 0; i < 14; i++)
284 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
285 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n",
286 i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]);
287 for (i = 0; i < 14; i++)
288 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
289 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n",
290 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]);
291 if (!autoload_fail)
292 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7);
293 else
294 rtlefuse->eeprom_regulatory = 0;
295 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
296 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
297 if (!autoload_fail) {
298 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A];
299 rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B];
300 } else {
301 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI;
302 rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI;
303 }
304 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
305 "TSSI_A = 0x%x, TSSI_B = 0x%x\n",
306 rtlefuse->eeprom_tssi[RF90_PATH_A],
307 rtlefuse->eeprom_tssi[RF90_PATH_B]);
308 if (!autoload_fail)
309 tempval = hwinfo[EEPROM_THERMAL_METER];
310 else
311 tempval = EEPROM_DEFAULT_THERMALMETER;
312 rtlefuse->eeprom_thermalmeter = (tempval & 0x1f);
313 if (rtlefuse->eeprom_thermalmeter < 0x06 ||
314 rtlefuse->eeprom_thermalmeter > 0x1c)
315 rtlefuse->eeprom_thermalmeter = 0x12;
316 if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail)
317 rtlefuse->apk_thermalmeterignore = true;
318 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
319 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
320 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
321}
322
323static void _rtl92cu_read_board_type(struct ieee80211_hw *hw, u8 *contents)
324{
325 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
326 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
327 u8 boardType;
328
329 if (IS_NORMAL_CHIP(rtlhal->version)) {
330 boardType = ((contents[EEPROM_RF_OPT1]) &
331 BOARD_TYPE_NORMAL_MASK) >> 5; /*bit[7:5]*/
332 } else {
333 boardType = contents[EEPROM_RF_OPT4];
334 boardType &= BOARD_TYPE_TEST_MASK;
335 }
336 rtlefuse->board_type = boardType;
337 if (IS_HIGHT_PA(rtlefuse->board_type))
338 rtlefuse->external_pa = 1;
339 pr_info("Board Type %x\n", rtlefuse->board_type);
340}
341
342static void _rtl92cu_read_adapter_info(struct ieee80211_hw *hw)
343{
344 struct rtl_priv *rtlpriv = rtl_priv(hw);
345 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
346 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
347 u16 i, usvalue;
348 u8 hwinfo[HWSET_MAX_SIZE] = {0};
349 u16 eeprom_id;
350
351 if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
352 rtl_efuse_shadow_map_update(hw);
353 memcpy((void *)hwinfo,
354 (void *)&rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
355 HWSET_MAX_SIZE);
356 } else if (rtlefuse->epromtype == EEPROM_93C46) {
357 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
358 "RTL819X Not boot from eeprom, check it !!\n");
359 }
360 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_LOUD, "MAP",
361 hwinfo, HWSET_MAX_SIZE);
362 eeprom_id = le16_to_cpu(*((__le16 *)&hwinfo[0]));
363 if (eeprom_id != RTL8190_EEPROM_ID) {
364 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
365 "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
366 rtlefuse->autoload_failflag = true;
367 } else {
368 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
369 rtlefuse->autoload_failflag = false;
370 }
371 if (rtlefuse->autoload_failflag)
372 return;
373 for (i = 0; i < 6; i += 2) {
374 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
375 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
376 }
377 pr_info("MAC address: %pM\n", rtlefuse->dev_addr);
378 _rtl92cu_read_txpower_info_from_hwpg(hw,
379 rtlefuse->autoload_failflag, hwinfo);
380 rtlefuse->eeprom_vid = le16_to_cpu(*(__le16 *)&hwinfo[EEPROM_VID]);
381 rtlefuse->eeprom_did = le16_to_cpu(*(__le16 *)&hwinfo[EEPROM_DID]);
382 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, " VID = 0x%02x PID = 0x%02x\n",
383 rtlefuse->eeprom_vid, rtlefuse->eeprom_did);
384 rtlefuse->eeprom_channelplan = hwinfo[EEPROM_CHANNELPLAN];
385 rtlefuse->eeprom_version =
386 le16_to_cpu(*(__le16 *)&hwinfo[EEPROM_VERSION]);
387 rtlefuse->txpwr_fromeprom = true;
388 rtlefuse->eeprom_oemid = hwinfo[EEPROM_CUSTOMER_ID];
389 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "EEPROM Customer ID: 0x%2x\n",
390 rtlefuse->eeprom_oemid);
391 if (rtlhal->oem_id == RT_CID_DEFAULT) {
392 switch (rtlefuse->eeprom_oemid) {
393 case EEPROM_CID_DEFAULT:
394 if (rtlefuse->eeprom_did == 0x8176) {
395 if ((rtlefuse->eeprom_svid == 0x103C &&
396 rtlefuse->eeprom_smid == 0x1629))
397 rtlhal->oem_id = RT_CID_819X_HP;
398 else
399 rtlhal->oem_id = RT_CID_DEFAULT;
400 } else {
401 rtlhal->oem_id = RT_CID_DEFAULT;
402 }
403 break;
404 case EEPROM_CID_TOSHIBA:
405 rtlhal->oem_id = RT_CID_TOSHIBA;
406 break;
407 case EEPROM_CID_QMI:
408 rtlhal->oem_id = RT_CID_819X_QMI;
409 break;
410 case EEPROM_CID_WHQL:
411 default:
412 rtlhal->oem_id = RT_CID_DEFAULT;
413 break;
414 }
415 }
416 _rtl92cu_read_board_type(hw, hwinfo);
417}
418
419static void _rtl92cu_hal_customized_behavior(struct ieee80211_hw *hw)
420{
421 struct rtl_priv *rtlpriv = rtl_priv(hw);
422 struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw);
423 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
424
425 switch (rtlhal->oem_id) {
426 case RT_CID_819X_HP:
427 usb_priv->ledctl.led_opendrain = true;
428 break;
429 case RT_CID_819X_LENOVO:
430 case RT_CID_DEFAULT:
431 case RT_CID_TOSHIBA:
432 case RT_CID_CCX:
433 case RT_CID_819X_ACER:
434 case RT_CID_WHQL:
435 default:
436 break;
437 }
438 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "RT Customized ID: 0x%02X\n",
439 rtlhal->oem_id);
440}
441
442void rtl92cu_read_eeprom_info(struct ieee80211_hw *hw)
443{
444
445 struct rtl_priv *rtlpriv = rtl_priv(hw);
446 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
447 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
448 u8 tmp_u1b;
449
450 if (!IS_NORMAL_CHIP(rtlhal->version))
451 return;
452 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
453 rtlefuse->epromtype = (tmp_u1b & BOOT_FROM_EEPROM) ?
454 EEPROM_93C46 : EEPROM_BOOT_EFUSE;
455 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from %s\n",
456 tmp_u1b & BOOT_FROM_EEPROM ? "EERROM" : "EFUSE");
457 rtlefuse->autoload_failflag = (tmp_u1b & EEPROM_EN) ? false : true;
458 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload %s\n",
459 tmp_u1b & EEPROM_EN ? "OK!!" : "ERR!!");
460 _rtl92cu_read_adapter_info(hw);
461 _rtl92cu_hal_customized_behavior(hw);
462 return;
463}
464
465static int _rtl92cu_init_power_on(struct ieee80211_hw *hw)
466{
467 struct rtl_priv *rtlpriv = rtl_priv(hw);
468 int status = 0;
469 u16 value16;
470 u8 value8;
471 /* polling autoload done. */
472 u32 pollingCount = 0;
473
474 do {
475 if (rtl_read_byte(rtlpriv, REG_APS_FSMCO) & PFM_ALDN) {
476 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
477 "Autoload Done!\n");
478 break;
479 }
480 if (pollingCount++ > 100) {
481 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
482 "Failed to polling REG_APS_FSMCO[PFM_ALDN] done!\n");
483 return -ENODEV;
484 }
485 } while (true);
486 /* 0. RSV_CTRL 0x1C[7:0] = 0 unlock ISO/CLK/Power control register */
487 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0);
488 /* Power on when re-enter from IPS/Radio off/card disable */
489 /* enable SPS into PWM mode */
490 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
491 udelay(100);
492 value8 = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL);
493 if (0 == (value8 & LDV12_EN)) {
494 value8 |= LDV12_EN;
495 rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, value8);
496 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
497 " power-on :REG_LDOV12D_CTRL Reg0x21:0x%02x\n",
498 value8);
499 udelay(100);
500 value8 = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL);
501 value8 &= ~ISO_MD2PP;
502 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, value8);
503 }
504 /* auto enable WLAN */
505 pollingCount = 0;
506 value16 = rtl_read_word(rtlpriv, REG_APS_FSMCO);
507 value16 |= APFM_ONMAC;
508 rtl_write_word(rtlpriv, REG_APS_FSMCO, value16);
509 do {
510 if (!(rtl_read_word(rtlpriv, REG_APS_FSMCO) & APFM_ONMAC)) {
511 pr_info("MAC auto ON okay!\n");
512 break;
513 }
514 if (pollingCount++ > 100) {
515 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
516 "Failed to polling REG_APS_FSMCO[APFM_ONMAC] done!\n");
517 return -ENODEV;
518 }
519 } while (true);
520 /* Enable Radio ,GPIO ,and LED function */
521 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x0812);
522 /* release RF digital isolation */
523 value16 = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL);
524 value16 &= ~ISO_DIOR;
525 rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, value16);
526 /* Reconsider when to do this operation after asking HWSD. */
527 pollingCount = 0;
528 rtl_write_byte(rtlpriv, REG_APSD_CTRL, (rtl_read_byte(rtlpriv,
529 REG_APSD_CTRL) & ~BIT(6)));
530 do {
531 pollingCount++;
532 } while ((pollingCount < 200) &&
533 (rtl_read_byte(rtlpriv, REG_APSD_CTRL) & BIT(7)));
534 /* Enable MAC DMA/WMAC/SCHEDULE/SEC block */
535 value16 = rtl_read_word(rtlpriv, REG_CR);
536 value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN |
537 PROTOCOL_EN | SCHEDULE_EN | MACTXEN | MACRXEN | ENSEC);
538 rtl_write_word(rtlpriv, REG_CR, value16);
539 return status;
540}
541
542static void _rtl92cu_init_queue_reserved_page(struct ieee80211_hw *hw,
543 bool wmm_enable,
544 u8 out_ep_num,
545 u8 queue_sel)
546{
547 struct rtl_priv *rtlpriv = rtl_priv(hw);
548 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
549 bool isChipN = IS_NORMAL_CHIP(rtlhal->version);
550 u32 outEPNum = (u32)out_ep_num;
551 u32 numHQ = 0;
552 u32 numLQ = 0;
553 u32 numNQ = 0;
554 u32 numPubQ;
555 u32 value32;
556 u8 value8;
557 u32 txQPageNum, txQPageUnit, txQRemainPage;
558
559 if (!wmm_enable) {
560 numPubQ = (isChipN) ? CHIP_B_PAGE_NUM_PUBQ :
561 CHIP_A_PAGE_NUM_PUBQ;
562 txQPageNum = TX_TOTAL_PAGE_NUMBER - numPubQ;
563
564 txQPageUnit = txQPageNum/outEPNum;
565 txQRemainPage = txQPageNum % outEPNum;
566 if (queue_sel & TX_SELE_HQ)
567 numHQ = txQPageUnit;
568 if (queue_sel & TX_SELE_LQ)
569 numLQ = txQPageUnit;
570 /* HIGH priority queue always present in the configuration of
571 * 2 out-ep. Remainder pages have assigned to High queue */
572 if ((outEPNum > 1) && (txQRemainPage))
573 numHQ += txQRemainPage;
574 /* NOTE: This step done before writting REG_RQPN. */
575 if (isChipN) {
576 if (queue_sel & TX_SELE_NQ)
577 numNQ = txQPageUnit;
578 value8 = (u8)_NPQ(numNQ);
579 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8);
580 }
581 } else {
582 /* for WMM ,number of out-ep must more than or equal to 2! */
583 numPubQ = isChipN ? WMM_CHIP_B_PAGE_NUM_PUBQ :
584 WMM_CHIP_A_PAGE_NUM_PUBQ;
585 if (queue_sel & TX_SELE_HQ) {
586 numHQ = isChipN ? WMM_CHIP_B_PAGE_NUM_HPQ :
587 WMM_CHIP_A_PAGE_NUM_HPQ;
588 }
589 if (queue_sel & TX_SELE_LQ) {
590 numLQ = isChipN ? WMM_CHIP_B_PAGE_NUM_LPQ :
591 WMM_CHIP_A_PAGE_NUM_LPQ;
592 }
593 /* NOTE: This step done before writting REG_RQPN. */
594 if (isChipN) {
595 if (queue_sel & TX_SELE_NQ)
596 numNQ = WMM_CHIP_B_PAGE_NUM_NPQ;
597 value8 = (u8)_NPQ(numNQ);
598 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8);
599 }
600 }
601 /* TX DMA */
602 value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
603 rtl_write_dword(rtlpriv, REG_RQPN, value32);
604}
605
606static void _rtl92c_init_trx_buffer(struct ieee80211_hw *hw, bool wmm_enable)
607{
608 struct rtl_priv *rtlpriv = rtl_priv(hw);
609 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
610 u8 txpktbuf_bndy;
611 u8 value8;
612
613 if (!wmm_enable)
614 txpktbuf_bndy = TX_PAGE_BOUNDARY;
615 else /* for WMM */
616 txpktbuf_bndy = (IS_NORMAL_CHIP(rtlhal->version))
617 ? WMM_CHIP_B_TX_PAGE_BOUNDARY
618 : WMM_CHIP_A_TX_PAGE_BOUNDARY;
619 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
620 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
621 rtl_write_byte(rtlpriv, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy);
622 rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy);
623 rtl_write_byte(rtlpriv, REG_TDECTRL+1, txpktbuf_bndy);
624 rtl_write_word(rtlpriv, (REG_TRXFF_BNDY + 2), 0x27FF);
625 value8 = _PSRX(RX_PAGE_SIZE_REG_VALUE) | _PSTX(PBP_128);
626 rtl_write_byte(rtlpriv, REG_PBP, value8);
627}
628
629static void _rtl92c_init_chipN_reg_priority(struct ieee80211_hw *hw, u16 beQ,
630 u16 bkQ, u16 viQ, u16 voQ,
631 u16 mgtQ, u16 hiQ)
632{
633 struct rtl_priv *rtlpriv = rtl_priv(hw);
634 u16 value16 = (rtl_read_word(rtlpriv, REG_TRXDMA_CTRL) & 0x7);
635
636 value16 |= _TXDMA_BEQ_MAP(beQ) | _TXDMA_BKQ_MAP(bkQ) |
637 _TXDMA_VIQ_MAP(viQ) | _TXDMA_VOQ_MAP(voQ) |
638 _TXDMA_MGQ_MAP(mgtQ) | _TXDMA_HIQ_MAP(hiQ);
639 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, value16);
640}
641
642static void _rtl92cu_init_chipN_one_out_ep_priority(struct ieee80211_hw *hw,
643 bool wmm_enable,
644 u8 queue_sel)
645{
646 u16 uninitialized_var(value);
647
648 switch (queue_sel) {
649 case TX_SELE_HQ:
650 value = QUEUE_HIGH;
651 break;
652 case TX_SELE_LQ:
653 value = QUEUE_LOW;
654 break;
655 case TX_SELE_NQ:
656 value = QUEUE_NORMAL;
657 break;
658 default:
659 WARN_ON(1); /* Shall not reach here! */
660 break;
661 }
662 _rtl92c_init_chipN_reg_priority(hw, value, value, value, value,
663 value, value);
664 pr_info("Tx queue select: 0x%02x\n", queue_sel);
665}
666
667static void _rtl92cu_init_chipN_two_out_ep_priority(struct ieee80211_hw *hw,
668 bool wmm_enable,
669 u8 queue_sel)
670{
671 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
672 u16 uninitialized_var(valueHi);
673 u16 uninitialized_var(valueLow);
674
675 switch (queue_sel) {
676 case (TX_SELE_HQ | TX_SELE_LQ):
677 valueHi = QUEUE_HIGH;
678 valueLow = QUEUE_LOW;
679 break;
680 case (TX_SELE_NQ | TX_SELE_LQ):
681 valueHi = QUEUE_NORMAL;
682 valueLow = QUEUE_LOW;
683 break;
684 case (TX_SELE_HQ | TX_SELE_NQ):
685 valueHi = QUEUE_HIGH;
686 valueLow = QUEUE_NORMAL;
687 break;
688 default:
689 WARN_ON(1);
690 break;
691 }
692 if (!wmm_enable) {
693 beQ = valueLow;
694 bkQ = valueLow;
695 viQ = valueHi;
696 voQ = valueHi;
697 mgtQ = valueHi;
698 hiQ = valueHi;
699 } else {/* for WMM ,CONFIG_OUT_EP_WIFI_MODE */
700 beQ = valueHi;
701 bkQ = valueLow;
702 viQ = valueLow;
703 voQ = valueHi;
704 mgtQ = valueHi;
705 hiQ = valueHi;
706 }
707 _rtl92c_init_chipN_reg_priority(hw, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
708 pr_info("Tx queue select: 0x%02x\n", queue_sel);
709}
710
711static void _rtl92cu_init_chipN_three_out_ep_priority(struct ieee80211_hw *hw,
712 bool wmm_enable,
713 u8 queue_sel)
714{
715 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
716 struct rtl_priv *rtlpriv = rtl_priv(hw);
717
718 if (!wmm_enable) { /* typical setting */
719 beQ = QUEUE_LOW;
720 bkQ = QUEUE_LOW;
721 viQ = QUEUE_NORMAL;
722 voQ = QUEUE_HIGH;
723 mgtQ = QUEUE_HIGH;
724 hiQ = QUEUE_HIGH;
725 } else { /* for WMM */
726 beQ = QUEUE_LOW;
727 bkQ = QUEUE_NORMAL;
728 viQ = QUEUE_NORMAL;
729 voQ = QUEUE_HIGH;
730 mgtQ = QUEUE_HIGH;
731 hiQ = QUEUE_HIGH;
732 }
733 _rtl92c_init_chipN_reg_priority(hw, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
734 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, "Tx queue select :0x%02x..\n",
735 queue_sel);
736}
737
738static void _rtl92cu_init_chipN_queue_priority(struct ieee80211_hw *hw,
739 bool wmm_enable,
740 u8 out_ep_num,
741 u8 queue_sel)
742{
743 switch (out_ep_num) {
744 case 1:
745 _rtl92cu_init_chipN_one_out_ep_priority(hw, wmm_enable,
746 queue_sel);
747 break;
748 case 2:
749 _rtl92cu_init_chipN_two_out_ep_priority(hw, wmm_enable,
750 queue_sel);
751 break;
752 case 3:
753 _rtl92cu_init_chipN_three_out_ep_priority(hw, wmm_enable,
754 queue_sel);
755 break;
756 default:
757 WARN_ON(1); /* Shall not reach here! */
758 break;
759 }
760}
761
762static void _rtl92cu_init_chipT_queue_priority(struct ieee80211_hw *hw,
763 bool wmm_enable,
764 u8 out_ep_num,
765 u8 queue_sel)
766{
767 u8 hq_sele = 0;
768 struct rtl_priv *rtlpriv = rtl_priv(hw);
769
770 switch (out_ep_num) {
771 case 2: /* (TX_SELE_HQ|TX_SELE_LQ) */
772 if (!wmm_enable) /* typical setting */
773 hq_sele = HQSEL_VOQ | HQSEL_VIQ | HQSEL_MGTQ |
774 HQSEL_HIQ;
775 else /* for WMM */
776 hq_sele = HQSEL_VOQ | HQSEL_BEQ | HQSEL_MGTQ |
777 HQSEL_HIQ;
778 break;
779 case 1:
780 if (TX_SELE_LQ == queue_sel) {
781 /* map all endpoint to Low queue */
782 hq_sele = 0;
783 } else if (TX_SELE_HQ == queue_sel) {
784 /* map all endpoint to High queue */
785 hq_sele = HQSEL_VOQ | HQSEL_VIQ | HQSEL_BEQ |
786 HQSEL_BKQ | HQSEL_MGTQ | HQSEL_HIQ;
787 }
788 break;
789 default:
790 WARN_ON(1); /* Shall not reach here! */
791 break;
792 }
793 rtl_write_byte(rtlpriv, (REG_TRXDMA_CTRL+1), hq_sele);
794 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, "Tx queue select :0x%02x..\n",
795 hq_sele);
796}
797
798static void _rtl92cu_init_queue_priority(struct ieee80211_hw *hw,
799 bool wmm_enable,
800 u8 out_ep_num,
801 u8 queue_sel)
802{
803 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
804 if (IS_NORMAL_CHIP(rtlhal->version))
805 _rtl92cu_init_chipN_queue_priority(hw, wmm_enable, out_ep_num,
806 queue_sel);
807 else
808 _rtl92cu_init_chipT_queue_priority(hw, wmm_enable, out_ep_num,
809 queue_sel);
810}
811
812static void _rtl92cu_init_usb_aggregation(struct ieee80211_hw *hw)
813{
814}
815
816static void _rtl92cu_init_wmac_setting(struct ieee80211_hw *hw)
817{
818 u16 value16;
819
820 struct rtl_priv *rtlpriv = rtl_priv(hw);
821 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
822
823 mac->rx_conf = (RCR_APM | RCR_AM | RCR_ADF | RCR_AB | RCR_APPFCS |
824 RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL |
825 RCR_APP_MIC | RCR_APP_PHYSTS | RCR_ACRC32);
826 rtl_write_dword(rtlpriv, REG_RCR, mac->rx_conf);
827 /* Accept all multicast address */
828 rtl_write_dword(rtlpriv, REG_MAR, 0xFFFFFFFF);
829 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xFFFFFFFF);
830 /* Accept all management frames */
831 value16 = 0xFFFF;
832 rtl92c_set_mgt_filter(hw, value16);
833 /* Reject all control frame - default value is 0 */
834 rtl92c_set_ctrl_filter(hw, 0x0);
835 /* Accept all data frames */
836 value16 = 0xFFFF;
837 rtl92c_set_data_filter(hw, value16);
838}
839
840static int _rtl92cu_init_mac(struct ieee80211_hw *hw)
841{
842 struct rtl_priv *rtlpriv = rtl_priv(hw);
843 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
844 struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw);
845 struct rtl_usb *rtlusb = rtl_usbdev(usb_priv);
846 int err = 0;
847 u32 boundary = 0;
848 u8 wmm_enable = false; /* TODO */
849 u8 out_ep_nums = rtlusb->out_ep_nums;
850 u8 queue_sel = rtlusb->out_queue_sel;
851 err = _rtl92cu_init_power_on(hw);
852
853 if (err) {
854 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
855 "Failed to init power on!\n");
856 return err;
857 }
858 if (!wmm_enable) {
859 boundary = TX_PAGE_BOUNDARY;
860 } else { /* for WMM */
861 boundary = (IS_NORMAL_CHIP(rtlhal->version))
862 ? WMM_CHIP_B_TX_PAGE_BOUNDARY
863 : WMM_CHIP_A_TX_PAGE_BOUNDARY;
864 }
865 if (false == rtl92c_init_llt_table(hw, boundary)) {
866 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
867 "Failed to init LLT Table!\n");
868 return -EINVAL;
869 }
870 _rtl92cu_init_queue_reserved_page(hw, wmm_enable, out_ep_nums,
871 queue_sel);
872 _rtl92c_init_trx_buffer(hw, wmm_enable);
873 _rtl92cu_init_queue_priority(hw, wmm_enable, out_ep_nums,
874 queue_sel);
875 /* Get Rx PHY status in order to report RSSI and others. */
876 rtl92c_init_driver_info_size(hw, RTL92C_DRIVER_INFO_SIZE);
877 rtl92c_init_interrupt(hw);
878 rtl92c_init_network_type(hw);
879 _rtl92cu_init_wmac_setting(hw);
880 rtl92c_init_adaptive_ctrl(hw);
881 rtl92c_init_edca(hw);
882 rtl92c_init_rate_fallback(hw);
883 rtl92c_init_retry_function(hw);
884 _rtl92cu_init_usb_aggregation(hw);
885 rtlpriv->cfg->ops->set_bw_mode(hw, NL80211_CHAN_HT20);
886 rtl92c_set_min_space(hw, IS_92C_SERIAL(rtlhal->version));
887 rtl92c_init_beacon_parameters(hw, rtlhal->version);
888 rtl92c_init_ampdu_aggregation(hw);
889 rtl92c_init_beacon_max_error(hw, true);
890 return err;
891}
892
893void rtl92cu_enable_hw_security_config(struct ieee80211_hw *hw)
894{
895 struct rtl_priv *rtlpriv = rtl_priv(hw);
896 u8 sec_reg_value = 0x0;
897 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
898
899 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
900 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
901 rtlpriv->sec.pairwise_enc_algorithm,
902 rtlpriv->sec.group_enc_algorithm);
903 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
904 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
905 "not open sw encryption\n");
906 return;
907 }
908 sec_reg_value = SCR_TxEncEnable | SCR_RxDecEnable;
909 if (rtlpriv->sec.use_defaultkey) {
910 sec_reg_value |= SCR_TxUseDK;
911 sec_reg_value |= SCR_RxUseDK;
912 }
913 if (IS_NORMAL_CHIP(rtlhal->version))
914 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
915 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
916 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, "The SECR-value %x\n",
917 sec_reg_value);
918 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
919}
920
921static void _rtl92cu_hw_configure(struct ieee80211_hw *hw)
922{
923 struct rtl_priv *rtlpriv = rtl_priv(hw);
924 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
925
926 /* To Fix MAC loopback mode fail. */
927 rtl_write_byte(rtlpriv, REG_LDOHCI12_CTRL, 0x0f);
928 rtl_write_byte(rtlpriv, 0x15, 0xe9);
929 /* HW SEQ CTRL */
930 /* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */
931 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
932 /* fixed USB interface interference issue */
933 rtl_write_byte(rtlpriv, 0xfe40, 0xe0);
934 rtl_write_byte(rtlpriv, 0xfe41, 0x8d);
935 rtl_write_byte(rtlpriv, 0xfe42, 0x80);
936 rtlusb->reg_bcn_ctrl_val = 0x18;
937 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlusb->reg_bcn_ctrl_val);
938}
939
940static void _InitPABias(struct ieee80211_hw *hw)
941{
942 struct rtl_priv *rtlpriv = rtl_priv(hw);
943 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
944 u8 pa_setting;
945
946 /* FIXED PA current issue */
947 pa_setting = efuse_read_1byte(hw, 0x1FA);
948 if (!(pa_setting & BIT(0))) {
949 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x0F406);
950 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x4F406);
951 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x8F406);
952 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0xCF406);
953 }
954 if (!(pa_setting & BIT(1)) && IS_NORMAL_CHIP(rtlhal->version) &&
955 IS_92C_SERIAL(rtlhal->version)) {
956 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x0F406);
957 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x4F406);
958 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x8F406);
959 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0xCF406);
960 }
961 if (!(pa_setting & BIT(4))) {
962 pa_setting = rtl_read_byte(rtlpriv, 0x16);
963 pa_setting &= 0x0F;
964 rtl_write_byte(rtlpriv, 0x16, pa_setting | 0x90);
965 }
966}
967
968static void _update_mac_setting(struct ieee80211_hw *hw)
969{
970 struct rtl_priv *rtlpriv = rtl_priv(hw);
971 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
972
973 mac->rx_conf = rtl_read_dword(rtlpriv, REG_RCR);
974 mac->rx_mgt_filter = rtl_read_word(rtlpriv, REG_RXFLTMAP0);
975 mac->rx_ctrl_filter = rtl_read_word(rtlpriv, REG_RXFLTMAP1);
976 mac->rx_data_filter = rtl_read_word(rtlpriv, REG_RXFLTMAP2);
977}
978
979int rtl92cu_hw_init(struct ieee80211_hw *hw)
980{
981 struct rtl_priv *rtlpriv = rtl_priv(hw);
982 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
983 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
984 struct rtl_phy *rtlphy = &(rtlpriv->phy);
985 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
986 int err = 0;
987 static bool iqk_initialized;
988 unsigned long flags;
989
990 /* As this function can take a very long time (up to 350 ms)
991 * and can be called with irqs disabled, reenable the irqs
992 * to let the other devices continue being serviced.
993 *
994 * It is safe doing so since our own interrupts will only be enabled
995 * in a subsequent step.
996 */
997 local_save_flags(flags);
998 local_irq_enable();
999
1000 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CU;
1001 err = _rtl92cu_init_mac(hw);
1002 if (err) {
1003 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "init mac failed!\n");
1004 goto exit;
1005 }
1006 err = rtl92c_download_fw(hw);
1007 if (err) {
1008 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1009 "Failed to download FW. Init HW without FW now..\n");
1010 err = 1;
1011 goto exit;
1012 }
1013 rtlhal->last_hmeboxnum = 0; /* h2c */
1014 _rtl92cu_phy_param_tab_init(hw);
1015 rtl92cu_phy_mac_config(hw);
1016 rtl92cu_phy_bb_config(hw);
1017 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
1018 rtl92c_phy_rf_config(hw);
1019 if (IS_VENDOR_UMC_A_CUT(rtlhal->version) &&
1020 !IS_92C_SERIAL(rtlhal->version)) {
1021 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255);
1022 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00);
1023 }
1024 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
1025 RF_CHNLBW, RFREG_OFFSET_MASK);
1026 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
1027 RF_CHNLBW, RFREG_OFFSET_MASK);
1028 rtl92cu_bb_block_on(hw);
1029 rtl_cam_reset_all_entry(hw);
1030 rtl92cu_enable_hw_security_config(hw);
1031 ppsc->rfpwr_state = ERFON;
1032 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1033 if (ppsc->rfpwr_state == ERFON) {
1034 rtl92c_phy_set_rfpath_switch(hw, 1);
1035 if (iqk_initialized) {
1036 rtl92c_phy_iq_calibrate(hw, true);
1037 } else {
1038 rtl92c_phy_iq_calibrate(hw, false);
1039 iqk_initialized = true;
1040 }
1041 rtl92c_dm_check_txpower_tracking(hw);
1042 rtl92c_phy_lc_calibrate(hw);
1043 }
1044 _rtl92cu_hw_configure(hw);
1045 _InitPABias(hw);
1046 _update_mac_setting(hw);
1047 rtl92c_dm_init(hw);
1048exit:
1049 local_irq_restore(flags);
1050 return err;
1051}
1052
1053static void _DisableRFAFEAndResetBB(struct ieee80211_hw *hw)
1054{
1055 struct rtl_priv *rtlpriv = rtl_priv(hw);
1056/**************************************
1057a. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue
1058b. RF path 0 offset 0x00 = 0x00 disable RF
1059c. APSD_CTRL 0x600[7:0] = 0x40
1060d. SYS_FUNC_EN 0x02[7:0] = 0x16 reset BB state machine
1061e. SYS_FUNC_EN 0x02[7:0] = 0x14 reset BB state machine
1062***************************************/
1063 u8 eRFPath = 0, value8 = 0;
1064 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1065 rtl_set_rfreg(hw, (enum radio_path)eRFPath, 0x0, MASKBYTE0, 0x0);
1066
1067 value8 |= APSDOFF;
1068 rtl_write_byte(rtlpriv, REG_APSD_CTRL, value8); /*0x40*/
1069 value8 = 0;
1070 value8 |= (FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTn);
1071 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value8);/*0x16*/
1072 value8 &= (~FEN_BB_GLB_RSTn);
1073 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value8); /*0x14*/
1074}
1075
1076static void _ResetDigitalProcedure1(struct ieee80211_hw *hw, bool bWithoutHWSM)
1077{
1078 struct rtl_priv *rtlpriv = rtl_priv(hw);
1079 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1080
1081 if (rtlhal->fw_version <= 0x20) {
1082 /*****************************
1083 f. MCUFWDL 0x80[7:0]=0 reset MCU ready status
1084 g. SYS_FUNC_EN 0x02[10]= 0 reset MCU reg, (8051 reset)
1085 h. SYS_FUNC_EN 0x02[15-12]= 5 reset MAC reg, DCORE
1086 i. SYS_FUNC_EN 0x02[10]= 1 enable MCU reg, (8051 enable)
1087 ******************************/
1088 u16 valu16 = 0;
1089
1090 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1091 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1092 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 &
1093 (~FEN_CPUEN))); /* reset MCU ,8051 */
1094 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN)&0x0FFF;
1095 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 |
1096 (FEN_HWPDN|FEN_ELDR))); /* reset MAC */
1097 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1098 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 |
1099 FEN_CPUEN)); /* enable MCU ,8051 */
1100 } else {
1101 u8 retry_cnts = 0;
1102
1103 /* IF fw in RAM code, do reset */
1104 if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(1)) {
1105 /* reset MCU ready status */
1106 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1107 /* 8051 reset by self */
1108 rtl_write_byte(rtlpriv, REG_HMETFR+3, 0x20);
1109 while ((retry_cnts++ < 100) &&
1110 (FEN_CPUEN & rtl_read_word(rtlpriv,
1111 REG_SYS_FUNC_EN))) {
1112 udelay(50);
1113 }
1114 if (retry_cnts >= 100) {
1115 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1116 "#####=> 8051 reset failed!.........................\n");
1117 /* if 8051 reset fail, reset MAC. */
1118 rtl_write_byte(rtlpriv,
1119 REG_SYS_FUNC_EN + 1,
1120 0x50);
1121 udelay(100);
1122 }
1123 }
1124 /* Reset MAC and Enable 8051 */
1125 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x54);
1126 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1127 }
1128 if (bWithoutHWSM) {
1129 /*****************************
1130 Without HW auto state machine
1131 g.SYS_CLKR 0x08[15:0] = 0x30A3 disable MAC clock
1132 h.AFE_PLL_CTRL 0x28[7:0] = 0x80 disable AFE PLL
1133 i.AFE_XTAL_CTRL 0x24[15:0] = 0x880F gated AFE DIG_CLOCK
1134 j.SYS_ISu_CTRL 0x00[7:0] = 0xF9 isolated digital to PON
1135 ******************************/
1136 rtl_write_word(rtlpriv, REG_SYS_CLKR, 0x70A3);
1137 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80);
1138 rtl_write_word(rtlpriv, REG_AFE_XTAL_CTRL, 0x880F);
1139 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xF9);
1140 }
1141}
1142
1143static void _ResetDigitalProcedure2(struct ieee80211_hw *hw)
1144{
1145 struct rtl_priv *rtlpriv = rtl_priv(hw);
1146/*****************************
1147k. SYS_FUNC_EN 0x03[7:0] = 0x44 disable ELDR runction
1148l. SYS_CLKR 0x08[15:0] = 0x3083 disable ELDR clock
1149m. SYS_ISO_CTRL 0x01[7:0] = 0x83 isolated ELDR to PON
1150******************************/
1151 rtl_write_word(rtlpriv, REG_SYS_CLKR, 0x70A3);
1152 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL+1, 0x82);
1153}
1154
1155static void _DisableGPIO(struct ieee80211_hw *hw)
1156{
1157 struct rtl_priv *rtlpriv = rtl_priv(hw);
1158/***************************************
1159j. GPIO_PIN_CTRL 0x44[31:0]=0x000
1160k. Value = GPIO_PIN_CTRL[7:0]
1161l. GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); write ext PIN level
1162m. GPIO_MUXCFG 0x42 [15:0] = 0x0780
1163n. LEDCFG 0x4C[15:0] = 0x8080
1164***************************************/
1165 u8 value8;
1166 u16 value16;
1167 u32 value32;
1168
1169 /* 1. Disable GPIO[7:0] */
1170 rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL+2, 0x0000);
1171 value32 = rtl_read_dword(rtlpriv, REG_GPIO_PIN_CTRL) & 0xFFFF00FF;
1172 value8 = (u8) (value32&0x000000FF);
1173 value32 |= ((value8<<8) | 0x00FF0000);
1174 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, value32);
1175 /* 2. Disable GPIO[10:8] */
1176 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG+3, 0x00);
1177 value16 = rtl_read_word(rtlpriv, REG_GPIO_MUXCFG+2) & 0xFF0F;
1178 value8 = (u8) (value16&0x000F);
1179 value16 |= ((value8<<4) | 0x0780);
1180 rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL+2, value16);
1181 /* 3. Disable LED0 & 1 */
1182 rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080);
1183}
1184
1185static void _DisableAnalog(struct ieee80211_hw *hw, bool bWithoutHWSM)
1186{
1187 struct rtl_priv *rtlpriv = rtl_priv(hw);
1188 u16 value16 = 0;
1189 u8 value8 = 0;
1190
1191 if (bWithoutHWSM) {
1192 /*****************************
1193 n. LDOA15_CTRL 0x20[7:0] = 0x04 disable A15 power
1194 o. LDOV12D_CTRL 0x21[7:0] = 0x54 disable digital core power
1195 r. When driver call disable, the ASIC will turn off remaining
1196 clock automatically
1197 ******************************/
1198 rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x04);
1199 value8 = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL);
1200 value8 &= (~LDV12_EN);
1201 rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, value8);
1202 }
1203
1204/*****************************
1205h. SPS0_CTRL 0x11[7:0] = 0x23 enter PFM mode
1206i. APS_FSMCO 0x04[15:0] = 0x4802 set USB suspend
1207******************************/
1208 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);
1209 value16 |= (APDM_HOST | AFSM_HSUS | PFM_ALDN);
1210 rtl_write_word(rtlpriv, REG_APS_FSMCO, (u16)value16);
1211 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0E);
1212}
1213
1214static void _CardDisableHWSM(struct ieee80211_hw *hw)
1215{
1216 /* ==== RF Off Sequence ==== */
1217 _DisableRFAFEAndResetBB(hw);
1218 /* ==== Reset digital sequence ====== */
1219 _ResetDigitalProcedure1(hw, false);
1220 /* ==== Pull GPIO PIN to balance level and LED control ====== */
1221 _DisableGPIO(hw);
1222 /* ==== Disable analog sequence === */
1223 _DisableAnalog(hw, false);
1224}
1225
1226static void _CardDisableWithoutHWSM(struct ieee80211_hw *hw)
1227{
1228 /*==== RF Off Sequence ==== */
1229 _DisableRFAFEAndResetBB(hw);
1230 /* ==== Reset digital sequence ====== */
1231 _ResetDigitalProcedure1(hw, true);
1232 /* ==== Pull GPIO PIN to balance level and LED control ====== */
1233 _DisableGPIO(hw);
1234 /* ==== Reset digital sequence ====== */
1235 _ResetDigitalProcedure2(hw);
1236 /* ==== Disable analog sequence === */
1237 _DisableAnalog(hw, true);
1238}
1239
1240static void _rtl92cu_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
1241 u8 set_bits, u8 clear_bits)
1242{
1243 struct rtl_priv *rtlpriv = rtl_priv(hw);
1244 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1245
1246 rtlusb->reg_bcn_ctrl_val |= set_bits;
1247 rtlusb->reg_bcn_ctrl_val &= ~clear_bits;
1248 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlusb->reg_bcn_ctrl_val);
1249}
1250
1251static void _rtl92cu_stop_tx_beacon(struct ieee80211_hw *hw)
1252{
1253 struct rtl_priv *rtlpriv = rtl_priv(hw);
1254 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1255 u8 tmp1byte = 0;
1256 if (IS_NORMAL_CHIP(rtlhal->version)) {
1257 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
1258 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
1259 tmp1byte & (~BIT(6)));
1260 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
1261 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
1262 tmp1byte &= ~(BIT(0));
1263 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
1264 } else {
1265 rtl_write_byte(rtlpriv, REG_TXPAUSE,
1266 rtl_read_byte(rtlpriv, REG_TXPAUSE) | BIT(6));
1267 }
1268}
1269
1270static void _rtl92cu_resume_tx_beacon(struct ieee80211_hw *hw)
1271{
1272 struct rtl_priv *rtlpriv = rtl_priv(hw);
1273 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1274 u8 tmp1byte = 0;
1275
1276 if (IS_NORMAL_CHIP(rtlhal->version)) {
1277 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
1278 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
1279 tmp1byte | BIT(6));
1280 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
1281 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
1282 tmp1byte |= BIT(0);
1283 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
1284 } else {
1285 rtl_write_byte(rtlpriv, REG_TXPAUSE,
1286 rtl_read_byte(rtlpriv, REG_TXPAUSE) & (~BIT(6)));
1287 }
1288}
1289
1290static void _rtl92cu_enable_bcn_sub_func(struct ieee80211_hw *hw)
1291{
1292 struct rtl_priv *rtlpriv = rtl_priv(hw);
1293 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1294
1295 if (IS_NORMAL_CHIP(rtlhal->version))
1296 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(1));
1297 else
1298 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4));
1299}
1300
1301static void _rtl92cu_disable_bcn_sub_func(struct ieee80211_hw *hw)
1302{
1303 struct rtl_priv *rtlpriv = rtl_priv(hw);
1304 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1305
1306 if (IS_NORMAL_CHIP(rtlhal->version))
1307 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(1), 0);
1308 else
1309 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
1310}
1311
1312static int _rtl92cu_set_media_status(struct ieee80211_hw *hw,
1313 enum nl80211_iftype type)
1314{
1315 struct rtl_priv *rtlpriv = rtl_priv(hw);
1316 u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1317 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1318
1319 bt_msr &= 0xfc;
1320 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xFF);
1321 if (type == NL80211_IFTYPE_UNSPECIFIED || type ==
1322 NL80211_IFTYPE_STATION) {
1323 _rtl92cu_stop_tx_beacon(hw);
1324 _rtl92cu_enable_bcn_sub_func(hw);
1325 } else if (type == NL80211_IFTYPE_ADHOC || type == NL80211_IFTYPE_AP) {
1326 _rtl92cu_resume_tx_beacon(hw);
1327 _rtl92cu_disable_bcn_sub_func(hw);
1328 } else {
1329 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1330 "Set HW_VAR_MEDIA_STATUS:No such media status(%x)\n",
1331 type);
1332 }
1333 switch (type) {
1334 case NL80211_IFTYPE_UNSPECIFIED:
1335 bt_msr |= MSR_NOLINK;
1336 ledaction = LED_CTL_LINK;
1337 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1338 "Set Network type to NO LINK!\n");
1339 break;
1340 case NL80211_IFTYPE_ADHOC:
1341 bt_msr |= MSR_ADHOC;
1342 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1343 "Set Network type to Ad Hoc!\n");
1344 break;
1345 case NL80211_IFTYPE_STATION:
1346 bt_msr |= MSR_INFRA;
1347 ledaction = LED_CTL_LINK;
1348 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1349 "Set Network type to STA!\n");
1350 break;
1351 case NL80211_IFTYPE_AP:
1352 bt_msr |= MSR_AP;
1353 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1354 "Set Network type to AP!\n");
1355 break;
1356 default:
1357 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1358 "Network type %d not supported!\n", type);
1359 goto error_out;
1360 }
1361 rtl_write_byte(rtlpriv, (MSR), bt_msr);
1362 rtlpriv->cfg->ops->led_control(hw, ledaction);
1363 if ((bt_msr & 0xfc) == MSR_AP)
1364 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1365 else
1366 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1367 return 0;
1368error_out:
1369 return 1;
1370}
1371
1372void rtl92cu_card_disable(struct ieee80211_hw *hw)
1373{
1374 struct rtl_priv *rtlpriv = rtl_priv(hw);
1375 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1376 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1377 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1378 enum nl80211_iftype opmode;
1379
1380 mac->link_state = MAC80211_NOLINK;
1381 opmode = NL80211_IFTYPE_UNSPECIFIED;
1382 _rtl92cu_set_media_status(hw, opmode);
1383 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1384 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1385 if (rtlusb->disableHWSM)
1386 _CardDisableHWSM(hw);
1387 else
1388 _CardDisableWithoutHWSM(hw);
1389}
1390
1391void rtl92cu_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1392{
1393 struct rtl_priv *rtlpriv = rtl_priv(hw);
1394 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1395 u32 reg_rcr;
1396
1397 if (rtlpriv->psc.rfpwr_state != ERFON)
1398 return;
1399
1400 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr));
1401
1402 if (check_bssid) {
1403 u8 tmp;
1404 if (IS_NORMAL_CHIP(rtlhal->version)) {
1405 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1406 tmp = BIT(4);
1407 } else {
1408 reg_rcr |= RCR_CBSSID;
1409 tmp = BIT(4) | BIT(5);
1410 }
1411 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1412 (u8 *) (®_rcr));
1413 _rtl92cu_set_bcn_ctrl_reg(hw, 0, tmp);
1414 } else {
1415 u8 tmp;
1416 if (IS_NORMAL_CHIP(rtlhal->version)) {
1417 reg_rcr &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1418 tmp = BIT(4);
1419 } else {
1420 reg_rcr &= ~RCR_CBSSID;
1421 tmp = BIT(4) | BIT(5);
1422 }
1423 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1424 rtlpriv->cfg->ops->set_hw_reg(hw,
1425 HW_VAR_RCR, (u8 *) (®_rcr));
1426 _rtl92cu_set_bcn_ctrl_reg(hw, tmp, 0);
1427 }
1428}
1429
1430/*========================================================================== */
1431
1432int rtl92cu_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1433{
1434 struct rtl_priv *rtlpriv = rtl_priv(hw);
1435
1436 if (_rtl92cu_set_media_status(hw, type))
1437 return -EOPNOTSUPP;
1438
1439 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1440 if (type != NL80211_IFTYPE_AP)
1441 rtl92cu_set_check_bssid(hw, true);
1442 } else {
1443 rtl92cu_set_check_bssid(hw, false);
1444 }
1445
1446 return 0;
1447}
1448
1449static void _InitBeaconParameters(struct ieee80211_hw *hw)
1450{
1451 struct rtl_priv *rtlpriv = rtl_priv(hw);
1452 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1453
1454 rtl_write_word(rtlpriv, REG_BCN_CTRL, 0x1010);
1455
1456 /* TODO: Remove these magic number */
1457 rtl_write_word(rtlpriv, REG_TBTT_PROHIBIT, 0x6404);
1458 rtl_write_byte(rtlpriv, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME);
1459 rtl_write_byte(rtlpriv, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME);
1460 /* Change beacon AIFS to the largest number
1461 * beacause test chip does not contension before sending beacon. */
1462 if (IS_NORMAL_CHIP(rtlhal->version))
1463 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660F);
1464 else
1465 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x66FF);
1466}
1467
1468static void _beacon_function_enable(struct ieee80211_hw *hw, bool Enable,
1469 bool Linked)
1470{
1471 struct rtl_priv *rtlpriv = rtl_priv(hw);
1472
1473 _rtl92cu_set_bcn_ctrl_reg(hw, (BIT(4) | BIT(3) | BIT(1)), 0x00);
1474 rtl_write_byte(rtlpriv, REG_RD_CTRL+1, 0x6F);
1475}
1476
1477void rtl92cu_set_beacon_related_registers(struct ieee80211_hw *hw)
1478{
1479
1480 struct rtl_priv *rtlpriv = rtl_priv(hw);
1481 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1482 u16 bcn_interval, atim_window;
1483 u32 value32;
1484
1485 bcn_interval = mac->beacon_interval;
1486 atim_window = 2; /*FIX MERGE */
1487 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1488 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1489 _InitBeaconParameters(hw);
1490 rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
1491 /*
1492 * Force beacon frame transmission even after receiving beacon frame
1493 * from other ad hoc STA
1494 *
1495 *
1496 * Reset TSF Timer to zero, added by Roger. 2008.06.24
1497 */
1498 value32 = rtl_read_dword(rtlpriv, REG_TCR);
1499 value32 &= ~TSFRST;
1500 rtl_write_dword(rtlpriv, REG_TCR, value32);
1501 value32 |= TSFRST;
1502 rtl_write_dword(rtlpriv, REG_TCR, value32);
1503 RT_TRACE(rtlpriv, COMP_INIT|COMP_BEACON, DBG_LOUD,
1504 "SetBeaconRelatedRegisters8192CUsb(): Set TCR(%x)\n",
1505 value32);
1506 /* TODO: Modify later (Find the right parameters)
1507 * NOTE: Fix test chip's bug (about contention windows's randomness) */
1508 if ((mac->opmode == NL80211_IFTYPE_ADHOC) ||
1509 (mac->opmode == NL80211_IFTYPE_AP)) {
1510 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x50);
1511 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x50);
1512 }
1513 _beacon_function_enable(hw, true, true);
1514}
1515
1516void rtl92cu_set_beacon_interval(struct ieee80211_hw *hw)
1517{
1518 struct rtl_priv *rtlpriv = rtl_priv(hw);
1519 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1520 u16 bcn_interval = mac->beacon_interval;
1521
1522 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG, "beacon_interval:%d\n",
1523 bcn_interval);
1524 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1525}
1526
1527void rtl92cu_update_interrupt_mask(struct ieee80211_hw *hw,
1528 u32 add_msr, u32 rm_msr)
1529{
1530}
1531
1532void rtl92cu_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
1533{
1534 struct rtl_priv *rtlpriv = rtl_priv(hw);
1535 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1536 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1537
1538 switch (variable) {
1539 case HW_VAR_RCR:
1540 *((u32 *)(val)) = mac->rx_conf;
1541 break;
1542 case HW_VAR_RF_STATE:
1543 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
1544 break;
1545 case HW_VAR_FWLPS_RF_ON:{
1546 enum rf_pwrstate rfState;
1547 u32 val_rcr;
1548
1549 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,
1550 (u8 *)(&rfState));
1551 if (rfState == ERFOFF) {
1552 *((bool *) (val)) = true;
1553 } else {
1554 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
1555 val_rcr &= 0x00070000;
1556 if (val_rcr)
1557 *((bool *) (val)) = false;
1558 else
1559 *((bool *) (val)) = true;
1560 }
1561 break;
1562 }
1563 case HW_VAR_FW_PSMODE_STATUS:
1564 *((bool *) (val)) = ppsc->fw_current_inpsmode;
1565 break;
1566 case HW_VAR_CORRECT_TSF:{
1567 u64 tsf;
1568 u32 *ptsf_low = (u32 *)&tsf;
1569 u32 *ptsf_high = ((u32 *)&tsf) + 1;
1570
1571 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
1572 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
1573 *((u64 *)(val)) = tsf;
1574 break;
1575 }
1576 case HW_VAR_MGT_FILTER:
1577 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP0);
1578 break;
1579 case HW_VAR_CTRL_FILTER:
1580 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP1);
1581 break;
1582 case HW_VAR_DATA_FILTER:
1583 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP2);
1584 break;
1585 default:
1586 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1587 "switch case not processed\n");
1588 break;
1589 }
1590}
1591
1592void rtl92cu_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
1593{
1594 struct rtl_priv *rtlpriv = rtl_priv(hw);
1595 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1596 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1597 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1598 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1599 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1600 enum wireless_mode wirelessmode = mac->mode;
1601 u8 idx = 0;
1602
1603 switch (variable) {
1604 case HW_VAR_ETHER_ADDR:{
1605 for (idx = 0; idx < ETH_ALEN; idx++) {
1606 rtl_write_byte(rtlpriv, (REG_MACID + idx),
1607 val[idx]);
1608 }
1609 break;
1610 }
1611 case HW_VAR_BASIC_RATE:{
1612 u16 rate_cfg = ((u16 *) val)[0];
1613 u8 rate_index = 0;
1614
1615 rate_cfg &= 0x15f;
1616 /* TODO */
1617 /* if (mac->current_network.vender == HT_IOT_PEER_CISCO
1618 * && ((rate_cfg & 0x150) == 0)) {
1619 * rate_cfg |= 0x010;
1620 * } */
1621 rate_cfg |= 0x01;
1622 rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
1623 rtl_write_byte(rtlpriv, REG_RRSR + 1,
1624 (rate_cfg >> 8) & 0xff);
1625 while (rate_cfg > 0x1) {
1626 rate_cfg >>= 1;
1627 rate_index++;
1628 }
1629 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
1630 rate_index);
1631 break;
1632 }
1633 case HW_VAR_BSSID:{
1634 for (idx = 0; idx < ETH_ALEN; idx++) {
1635 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
1636 val[idx]);
1637 }
1638 break;
1639 }
1640 case HW_VAR_SIFS:{
1641 rtl_write_byte(rtlpriv, REG_SIFS_CCK + 1, val[0]);
1642 rtl_write_byte(rtlpriv, REG_SIFS_OFDM + 1, val[1]);
1643 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
1644 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
1645 rtl_write_byte(rtlpriv, REG_R2T_SIFS+1, val[0]);
1646 rtl_write_byte(rtlpriv, REG_T2T_SIFS+1, val[0]);
1647 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, "HW_VAR_SIFS\n");
1648 break;
1649 }
1650 case HW_VAR_SLOT_TIME:{
1651 u8 e_aci;
1652 u8 QOS_MODE = 1;
1653
1654 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
1655 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1656 "HW_VAR_SLOT_TIME %x\n", val[0]);
1657 if (QOS_MODE) {
1658 for (e_aci = 0; e_aci < AC_MAX; e_aci++)
1659 rtlpriv->cfg->ops->set_hw_reg(hw,
1660 HW_VAR_AC_PARAM,
1661 &e_aci);
1662 } else {
1663 u8 sifstime = 0;
1664 u8 u1bAIFS;
1665
1666 if (IS_WIRELESS_MODE_A(wirelessmode) ||
1667 IS_WIRELESS_MODE_N_24G(wirelessmode) ||
1668 IS_WIRELESS_MODE_N_5G(wirelessmode))
1669 sifstime = 16;
1670 else
1671 sifstime = 10;
1672 u1bAIFS = sifstime + (2 * val[0]);
1673 rtl_write_byte(rtlpriv, REG_EDCA_VO_PARAM,
1674 u1bAIFS);
1675 rtl_write_byte(rtlpriv, REG_EDCA_VI_PARAM,
1676 u1bAIFS);
1677 rtl_write_byte(rtlpriv, REG_EDCA_BE_PARAM,
1678 u1bAIFS);
1679 rtl_write_byte(rtlpriv, REG_EDCA_BK_PARAM,
1680 u1bAIFS);
1681 }
1682 break;
1683 }
1684 case HW_VAR_ACK_PREAMBLE:{
1685 u8 reg_tmp;
1686 u8 short_preamble = (bool)*val;
1687 reg_tmp = 0;
1688 if (short_preamble)
1689 reg_tmp |= 0x80;
1690 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
1691 break;
1692 }
1693 case HW_VAR_AMPDU_MIN_SPACE:{
1694 u8 min_spacing_to_set;
1695 u8 sec_min_space;
1696
1697 min_spacing_to_set = *val;
1698 if (min_spacing_to_set <= 7) {
1699 switch (rtlpriv->sec.pairwise_enc_algorithm) {
1700 case NO_ENCRYPTION:
1701 case AESCCMP_ENCRYPTION:
1702 sec_min_space = 0;
1703 break;
1704 case WEP40_ENCRYPTION:
1705 case WEP104_ENCRYPTION:
1706 case TKIP_ENCRYPTION:
1707 sec_min_space = 6;
1708 break;
1709 default:
1710 sec_min_space = 7;
1711 break;
1712 }
1713 if (min_spacing_to_set < sec_min_space)
1714 min_spacing_to_set = sec_min_space;
1715 mac->min_space_cfg = ((mac->min_space_cfg &
1716 0xf8) |
1717 min_spacing_to_set);
1718 *val = min_spacing_to_set;
1719 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1720 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
1721 mac->min_space_cfg);
1722 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
1723 mac->min_space_cfg);
1724 }
1725 break;
1726 }
1727 case HW_VAR_SHORTGI_DENSITY:{
1728 u8 density_to_set;
1729
1730 density_to_set = *val;
1731 density_to_set &= 0x1f;
1732 mac->min_space_cfg &= 0x07;
1733 mac->min_space_cfg |= (density_to_set << 3);
1734 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1735 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
1736 mac->min_space_cfg);
1737 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
1738 mac->min_space_cfg);
1739 break;
1740 }
1741 case HW_VAR_AMPDU_FACTOR:{
1742 u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9};
1743 u8 factor_toset;
1744 u8 *p_regtoset = NULL;
1745 u8 index = 0;
1746
1747 p_regtoset = regtoset_normal;
1748 factor_toset = *val;
1749 if (factor_toset <= 3) {
1750 factor_toset = (1 << (factor_toset + 2));
1751 if (factor_toset > 0xf)
1752 factor_toset = 0xf;
1753 for (index = 0; index < 4; index++) {
1754 if ((p_regtoset[index] & 0xf0) >
1755 (factor_toset << 4))
1756 p_regtoset[index] =
1757 (p_regtoset[index] & 0x0f)
1758 | (factor_toset << 4);
1759 if ((p_regtoset[index] & 0x0f) >
1760 factor_toset)
1761 p_regtoset[index] =
1762 (p_regtoset[index] & 0xf0)
1763 | (factor_toset);
1764 rtl_write_byte(rtlpriv,
1765 (REG_AGGLEN_LMT + index),
1766 p_regtoset[index]);
1767 }
1768 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1769 "Set HW_VAR_AMPDU_FACTOR: %#x\n",
1770 factor_toset);
1771 }
1772 break;
1773 }
1774 case HW_VAR_AC_PARAM:{
1775 u8 e_aci = *val;
1776 u32 u4b_ac_param;
1777 u16 cw_min = le16_to_cpu(mac->ac[e_aci].cw_min);
1778 u16 cw_max = le16_to_cpu(mac->ac[e_aci].cw_max);
1779 u16 tx_op = le16_to_cpu(mac->ac[e_aci].tx_op);
1780
1781 u4b_ac_param = (u32) mac->ac[e_aci].aifs;
1782 u4b_ac_param |= (u32) ((cw_min & 0xF) <<
1783 AC_PARAM_ECW_MIN_OFFSET);
1784 u4b_ac_param |= (u32) ((cw_max & 0xF) <<
1785 AC_PARAM_ECW_MAX_OFFSET);
1786 u4b_ac_param |= (u32) tx_op << AC_PARAM_TXOP_OFFSET;
1787 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1788 "queue:%x, ac_param:%x\n",
1789 e_aci, u4b_ac_param);
1790 switch (e_aci) {
1791 case AC1_BK:
1792 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM,
1793 u4b_ac_param);
1794 break;
1795 case AC0_BE:
1796 rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM,
1797 u4b_ac_param);
1798 break;
1799 case AC2_VI:
1800 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM,
1801 u4b_ac_param);
1802 break;
1803 case AC3_VO:
1804 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM,
1805 u4b_ac_param);
1806 break;
1807 default:
1808 RT_ASSERT(false,
1809 "SetHwReg8185(): invalid aci: %d !\n",
1810 e_aci);
1811 break;
1812 }
1813 if (rtlusb->acm_method != EACMWAY2_SW)
1814 rtlpriv->cfg->ops->set_hw_reg(hw,
1815 HW_VAR_ACM_CTRL, &e_aci);
1816 break;
1817 }
1818 case HW_VAR_ACM_CTRL:{
1819 u8 e_aci = *val;
1820 union aci_aifsn *p_aci_aifsn = (union aci_aifsn *)
1821 (&(mac->ac[0].aifs));
1822 u8 acm = p_aci_aifsn->f.acm;
1823 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
1824
1825 acm_ctrl =
1826 acm_ctrl | ((rtlusb->acm_method == 2) ? 0x0 : 0x1);
1827 if (acm) {
1828 switch (e_aci) {
1829 case AC0_BE:
1830 acm_ctrl |= AcmHw_BeqEn;
1831 break;
1832 case AC2_VI:
1833 acm_ctrl |= AcmHw_ViqEn;
1834 break;
1835 case AC3_VO:
1836 acm_ctrl |= AcmHw_VoqEn;
1837 break;
1838 default:
1839 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1840 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
1841 acm);
1842 break;
1843 }
1844 } else {
1845 switch (e_aci) {
1846 case AC0_BE:
1847 acm_ctrl &= (~AcmHw_BeqEn);
1848 break;
1849 case AC2_VI:
1850 acm_ctrl &= (~AcmHw_ViqEn);
1851 break;
1852 case AC3_VO:
1853 acm_ctrl &= (~AcmHw_BeqEn);
1854 break;
1855 default:
1856 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1857 "switch case not processed\n");
1858 break;
1859 }
1860 }
1861 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
1862 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
1863 acm_ctrl);
1864 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
1865 break;
1866 }
1867 case HW_VAR_RCR:{
1868 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
1869 mac->rx_conf = ((u32 *) (val))[0];
1870 RT_TRACE(rtlpriv, COMP_RECV, DBG_DMESG,
1871 "### Set RCR(0x%08x) ###\n", mac->rx_conf);
1872 break;
1873 }
1874 case HW_VAR_RETRY_LIMIT:{
1875 u8 retry_limit = val[0];
1876
1877 rtl_write_word(rtlpriv, REG_RL,
1878 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
1879 retry_limit << RETRY_LIMIT_LONG_SHIFT);
1880 RT_TRACE(rtlpriv, COMP_MLME, DBG_DMESG,
1881 "Set HW_VAR_RETRY_LIMIT(0x%08x)\n",
1882 retry_limit);
1883 break;
1884 }
1885 case HW_VAR_DUAL_TSF_RST:
1886 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
1887 break;
1888 case HW_VAR_EFUSE_BYTES:
1889 rtlefuse->efuse_usedbytes = *((u16 *) val);
1890 break;
1891 case HW_VAR_EFUSE_USAGE:
1892 rtlefuse->efuse_usedpercentage = *val;
1893 break;
1894 case HW_VAR_IO_CMD:
1895 rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val));
1896 break;
1897 case HW_VAR_WPA_CONFIG:
1898 rtl_write_byte(rtlpriv, REG_SECCFG, *val);
1899 break;
1900 case HW_VAR_SET_RPWM:{
1901 u8 rpwm_val = rtl_read_byte(rtlpriv, REG_USB_HRPWM);
1902
1903 if (rpwm_val & BIT(7))
1904 rtl_write_byte(rtlpriv, REG_USB_HRPWM, *val);
1905 else
1906 rtl_write_byte(rtlpriv, REG_USB_HRPWM,
1907 *val | BIT(7));
1908 break;
1909 }
1910 case HW_VAR_H2C_FW_PWRMODE:{
1911 u8 psmode = *val;
1912
1913 if ((psmode != FW_PS_ACTIVE_MODE) &&
1914 (!IS_92C_SERIAL(rtlhal->version)))
1915 rtl92c_dm_rf_saving(hw, true);
1916 rtl92c_set_fw_pwrmode_cmd(hw, (*val));
1917 break;
1918 }
1919 case HW_VAR_FW_PSMODE_STATUS:
1920 ppsc->fw_current_inpsmode = *((bool *) val);
1921 break;
1922 case HW_VAR_H2C_FW_JOINBSSRPT:{
1923 u8 mstatus = *val;
1924 u8 tmp_reg422;
1925 bool recover = false;
1926
1927 if (mstatus == RT_MEDIA_CONNECT) {
1928 rtlpriv->cfg->ops->set_hw_reg(hw,
1929 HW_VAR_AID, NULL);
1930 rtl_write_byte(rtlpriv, REG_CR + 1, 0x03);
1931 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3));
1932 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
1933 tmp_reg422 = rtl_read_byte(rtlpriv,
1934 REG_FWHW_TXQ_CTRL + 2);
1935 if (tmp_reg422 & BIT(6))
1936 recover = true;
1937 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
1938 tmp_reg422 & (~BIT(6)));
1939 rtl92c_set_fw_rsvdpagepkt(hw, 0);
1940 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0);
1941 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4));
1942 if (recover)
1943 rtl_write_byte(rtlpriv,
1944 REG_FWHW_TXQ_CTRL + 2,
1945 tmp_reg422 | BIT(6));
1946 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
1947 }
1948 rtl92c_set_fw_joinbss_report_cmd(hw, (*val));
1949 break;
1950 }
1951 case HW_VAR_AID:{
1952 u16 u2btmp;
1953
1954 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
1955 u2btmp &= 0xC000;
1956 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT,
1957 (u2btmp | mac->assoc_id));
1958 break;
1959 }
1960 case HW_VAR_CORRECT_TSF:{
1961 u8 btype_ibss = val[0];
1962
1963 if (btype_ibss)
1964 _rtl92cu_stop_tx_beacon(hw);
1965 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3));
1966 rtl_write_dword(rtlpriv, REG_TSFTR, (u32)(mac->tsf &
1967 0xffffffff));
1968 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
1969 (u32)((mac->tsf >> 32) & 0xffffffff));
1970 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0);
1971 if (btype_ibss)
1972 _rtl92cu_resume_tx_beacon(hw);
1973 break;
1974 }
1975 case HW_VAR_MGT_FILTER:
1976 rtl_write_word(rtlpriv, REG_RXFLTMAP0, *(u16 *)val);
1977 break;
1978 case HW_VAR_CTRL_FILTER:
1979 rtl_write_word(rtlpriv, REG_RXFLTMAP1, *(u16 *)val);
1980 break;
1981 case HW_VAR_DATA_FILTER:
1982 rtl_write_word(rtlpriv, REG_RXFLTMAP2, *(u16 *)val);
1983 break;
1984 default:
1985 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1986 "switch case not processed\n");
1987 break;
1988 }
1989}
1990
1991static void rtl92cu_update_hal_rate_table(struct ieee80211_hw *hw,
1992 struct ieee80211_sta *sta)
1993{
1994 struct rtl_priv *rtlpriv = rtl_priv(hw);
1995 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1996 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1997 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1998 u32 ratr_value;
1999 u8 ratr_index = 0;
2000 u8 nmode = mac->ht_enable;
2001 u8 mimo_ps = IEEE80211_SMPS_OFF;
2002 u16 shortgi_rate;
2003 u32 tmp_ratr_value;
2004 u8 curtxbw_40mhz = mac->bw_40;
2005 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2006 1 : 0;
2007 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2008 1 : 0;
2009 enum wireless_mode wirelessmode = mac->mode;
2010
2011 if (rtlhal->current_bandtype == BAND_ON_5G)
2012 ratr_value = sta->supp_rates[1] << 4;
2013 else
2014 ratr_value = sta->supp_rates[0];
2015 if (mac->opmode == NL80211_IFTYPE_ADHOC)
2016 ratr_value = 0xfff;
2017
2018 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2019 sta->ht_cap.mcs.rx_mask[0] << 12);
2020 switch (wirelessmode) {
2021 case WIRELESS_MODE_B:
2022 if (ratr_value & 0x0000000c)
2023 ratr_value &= 0x0000000d;
2024 else
2025 ratr_value &= 0x0000000f;
2026 break;
2027 case WIRELESS_MODE_G:
2028 ratr_value &= 0x00000FF5;
2029 break;
2030 case WIRELESS_MODE_N_24G:
2031 case WIRELESS_MODE_N_5G:
2032 nmode = 1;
2033 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2034 ratr_value &= 0x0007F005;
2035 } else {
2036 u32 ratr_mask;
2037
2038 if (get_rf_type(rtlphy) == RF_1T2R ||
2039 get_rf_type(rtlphy) == RF_1T1R)
2040 ratr_mask = 0x000ff005;
2041 else
2042 ratr_mask = 0x0f0ff005;
2043
2044 ratr_value &= ratr_mask;
2045 }
2046 break;
2047 default:
2048 if (rtlphy->rf_type == RF_1T2R)
2049 ratr_value &= 0x000ff0ff;
2050 else
2051 ratr_value &= 0x0f0ff0ff;
2052
2053 break;
2054 }
2055
2056 ratr_value &= 0x0FFFFFFF;
2057
2058 if (nmode && ((curtxbw_40mhz &&
2059 curshortgi_40mhz) || (!curtxbw_40mhz &&
2060 curshortgi_20mhz))) {
2061
2062 ratr_value |= 0x10000000;
2063 tmp_ratr_value = (ratr_value >> 12);
2064
2065 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2066 if ((1 << shortgi_rate) & tmp_ratr_value)
2067 break;
2068 }
2069
2070 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2071 (shortgi_rate << 4) | (shortgi_rate);
2072 }
2073
2074 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
2075
2076 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n",
2077 rtl_read_dword(rtlpriv, REG_ARFR0));
2078}
2079
2080static void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw,
2081 struct ieee80211_sta *sta,
2082 u8 rssi_level)
2083{
2084 struct rtl_priv *rtlpriv = rtl_priv(hw);
2085 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2086 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2087 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2088 struct rtl_sta_info *sta_entry = NULL;
2089 u32 ratr_bitmap;
2090 u8 ratr_index;
2091 u8 curtxbw_40mhz = (sta->bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0;
2092 u8 curshortgi_40mhz = curtxbw_40mhz &&
2093 (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2094 1 : 0;
2095 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2096 1 : 0;
2097 enum wireless_mode wirelessmode = 0;
2098 bool shortgi = false;
2099 u8 rate_mask[5];
2100 u8 macid = 0;
2101 u8 mimo_ps = IEEE80211_SMPS_OFF;
2102
2103 sta_entry = (struct rtl_sta_info *) sta->drv_priv;
2104 wirelessmode = sta_entry->wireless_mode;
2105 if (mac->opmode == NL80211_IFTYPE_STATION ||
2106 mac->opmode == NL80211_IFTYPE_MESH_POINT)
2107 curtxbw_40mhz = mac->bw_40;
2108 else if (mac->opmode == NL80211_IFTYPE_AP ||
2109 mac->opmode == NL80211_IFTYPE_ADHOC)
2110 macid = sta->aid + 1;
2111
2112 if (rtlhal->current_bandtype == BAND_ON_5G)
2113 ratr_bitmap = sta->supp_rates[1] << 4;
2114 else
2115 ratr_bitmap = sta->supp_rates[0];
2116 if (mac->opmode == NL80211_IFTYPE_ADHOC)
2117 ratr_bitmap = 0xfff;
2118 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2119 sta->ht_cap.mcs.rx_mask[0] << 12);
2120 switch (wirelessmode) {
2121 case WIRELESS_MODE_B:
2122 ratr_index = RATR_INX_WIRELESS_B;
2123 if (ratr_bitmap & 0x0000000c)
2124 ratr_bitmap &= 0x0000000d;
2125 else
2126 ratr_bitmap &= 0x0000000f;
2127 break;
2128 case WIRELESS_MODE_G:
2129 ratr_index = RATR_INX_WIRELESS_GB;
2130
2131 if (rssi_level == 1)
2132 ratr_bitmap &= 0x00000f00;
2133 else if (rssi_level == 2)
2134 ratr_bitmap &= 0x00000ff0;
2135 else
2136 ratr_bitmap &= 0x00000ff5;
2137 break;
2138 case WIRELESS_MODE_A:
2139 ratr_index = RATR_INX_WIRELESS_A;
2140 ratr_bitmap &= 0x00000ff0;
2141 break;
2142 case WIRELESS_MODE_N_24G:
2143 case WIRELESS_MODE_N_5G:
2144 ratr_index = RATR_INX_WIRELESS_NGB;
2145
2146 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2147 if (rssi_level == 1)
2148 ratr_bitmap &= 0x00070000;
2149 else if (rssi_level == 2)
2150 ratr_bitmap &= 0x0007f000;
2151 else
2152 ratr_bitmap &= 0x0007f005;
2153 } else {
2154 if (rtlphy->rf_type == RF_1T2R ||
2155 rtlphy->rf_type == RF_1T1R) {
2156 if (curtxbw_40mhz) {
2157 if (rssi_level == 1)
2158 ratr_bitmap &= 0x000f0000;
2159 else if (rssi_level == 2)
2160 ratr_bitmap &= 0x000ff000;
2161 else
2162 ratr_bitmap &= 0x000ff015;
2163 } else {
2164 if (rssi_level == 1)
2165 ratr_bitmap &= 0x000f0000;
2166 else if (rssi_level == 2)
2167 ratr_bitmap &= 0x000ff000;
2168 else
2169 ratr_bitmap &= 0x000ff005;
2170 }
2171 } else {
2172 if (curtxbw_40mhz) {
2173 if (rssi_level == 1)
2174 ratr_bitmap &= 0x0f0f0000;
2175 else if (rssi_level == 2)
2176 ratr_bitmap &= 0x0f0ff000;
2177 else
2178 ratr_bitmap &= 0x0f0ff015;
2179 } else {
2180 if (rssi_level == 1)
2181 ratr_bitmap &= 0x0f0f0000;
2182 else if (rssi_level == 2)
2183 ratr_bitmap &= 0x0f0ff000;
2184 else
2185 ratr_bitmap &= 0x0f0ff005;
2186 }
2187 }
2188 }
2189
2190 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2191 (!curtxbw_40mhz && curshortgi_20mhz)) {
2192
2193 if (macid == 0)
2194 shortgi = true;
2195 else if (macid == 1)
2196 shortgi = false;
2197 }
2198 break;
2199 default:
2200 ratr_index = RATR_INX_WIRELESS_NGB;
2201
2202 if (rtlphy->rf_type == RF_1T2R)
2203 ratr_bitmap &= 0x000ff0ff;
2204 else
2205 ratr_bitmap &= 0x0f0ff0ff;
2206 break;
2207 }
2208 sta_entry->ratr_index = ratr_index;
2209
2210 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2211 "ratr_bitmap :%x\n", ratr_bitmap);
2212 *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
2213 (ratr_index << 28);
2214 rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
2215 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2216 "Rate_index:%x, ratr_val:%x, %5phC\n",
2217 ratr_index, ratr_bitmap, rate_mask);
2218 memcpy(rtlpriv->rate_mask, rate_mask, 5);
2219 /* rtl92c_fill_h2c_cmd() does USB I/O and will result in a
2220 * "scheduled while atomic" if called directly */
2221 schedule_work(&rtlpriv->works.fill_h2c_cmd);
2222
2223 if (macid != 0)
2224 sta_entry->ratr_index = ratr_index;
2225}
2226
2227void rtl92cu_update_hal_rate_tbl(struct ieee80211_hw *hw,
2228 struct ieee80211_sta *sta,
2229 u8 rssi_level)
2230{
2231 struct rtl_priv *rtlpriv = rtl_priv(hw);
2232
2233 if (rtlpriv->dm.useramask)
2234 rtl92cu_update_hal_rate_mask(hw, sta, rssi_level);
2235 else
2236 rtl92cu_update_hal_rate_table(hw, sta);
2237}
2238
2239void rtl92cu_update_channel_access_setting(struct ieee80211_hw *hw)
2240{
2241 struct rtl_priv *rtlpriv = rtl_priv(hw);
2242 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2243 u16 sifs_timer;
2244
2245 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2246 &mac->slot_time);
2247 if (!mac->ht_enable)
2248 sifs_timer = 0x0a0a;
2249 else
2250 sifs_timer = 0x0e0e;
2251 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2252}
2253
2254bool rtl92cu_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 * valid)
2255{
2256 struct rtl_priv *rtlpriv = rtl_priv(hw);
2257 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2258 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2259 enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
2260 u8 u1tmp = 0;
2261 bool actuallyset = false;
2262 unsigned long flag = 0;
2263 /* to do - usb autosuspend */
2264 u8 usb_autosuspend = 0;
2265
2266 if (ppsc->swrf_processing)
2267 return false;
2268 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2269 if (ppsc->rfchange_inprogress) {
2270 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2271 return false;
2272 } else {
2273 ppsc->rfchange_inprogress = true;
2274 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2275 }
2276 cur_rfstate = ppsc->rfpwr_state;
2277 if (usb_autosuspend) {
2278 /* to do................... */
2279 } else {
2280 if (ppsc->pwrdown_mode) {
2281 u1tmp = rtl_read_byte(rtlpriv, REG_HSISR);
2282 e_rfpowerstate_toset = (u1tmp & BIT(7)) ?
2283 ERFOFF : ERFON;
2284 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
2285 "pwrdown, 0x5c(BIT7)=%02x\n", u1tmp);
2286 } else {
2287 rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG,
2288 rtl_read_byte(rtlpriv,
2289 REG_MAC_PINMUX_CFG) & ~(BIT(3)));
2290 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
2291 e_rfpowerstate_toset = (u1tmp & BIT(3)) ?
2292 ERFON : ERFOFF;
2293 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
2294 "GPIO_IN=%02x\n", u1tmp);
2295 }
2296 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "N-SS RF =%x\n",
2297 e_rfpowerstate_toset);
2298 }
2299 if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
2300 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
2301 "GPIOChangeRF - HW Radio ON, RF ON\n");
2302 ppsc->hwradiooff = false;
2303 actuallyset = true;
2304 } else if ((!ppsc->hwradiooff) && (e_rfpowerstate_toset ==
2305 ERFOFF)) {
2306 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
2307 "GPIOChangeRF - HW Radio OFF\n");
2308 ppsc->hwradiooff = true;
2309 actuallyset = true;
2310 } else {
2311 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
2312 "pHalData->bHwRadioOff and eRfPowerStateToSet do not match: pHalData->bHwRadioOff %x, eRfPowerStateToSet %x\n",
2313 ppsc->hwradiooff, e_rfpowerstate_toset);
2314 }
2315 if (actuallyset) {
2316 ppsc->hwradiooff = true;
2317 if (e_rfpowerstate_toset == ERFON) {
2318 if ((ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) &&
2319 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM))
2320 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2321 else if ((ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3)
2322 && RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3))
2323 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2324 }
2325 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2326 ppsc->rfchange_inprogress = false;
2327 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2328 /* For power down module, we need to enable register block
2329 * contrl reg at 0x1c. Then enable power down control bit
2330 * of register 0x04 BIT4 and BIT15 as 1.
2331 */
2332 if (ppsc->pwrdown_mode && e_rfpowerstate_toset == ERFOFF) {
2333 /* Enable register area 0x0-0xc. */
2334 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0);
2335 if (IS_HARDWARE_TYPE_8723U(rtlhal)) {
2336 /*
2337 * We should configure HW PDn source for WiFi
2338 * ONLY, and then our HW will be set in
2339 * power-down mode if PDn source from all
2340 * functions are configured.
2341 */
2342 u1tmp = rtl_read_byte(rtlpriv,
2343 REG_MULTI_FUNC_CTRL);
2344 rtl_write_byte(rtlpriv, REG_MULTI_FUNC_CTRL,
2345 (u1tmp|WL_HWPDN_EN));
2346 } else {
2347 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x8812);
2348 }
2349 }
2350 if (e_rfpowerstate_toset == ERFOFF) {
2351 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM)
2352 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2353 else if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3)
2354 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2355 }
2356 } else if (e_rfpowerstate_toset == ERFOFF || cur_rfstate == ERFOFF) {
2357 /* Enter D3 or ASPM after GPIO had been done. */
2358 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM)
2359 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2360 else if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3)
2361 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2362 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2363 ppsc->rfchange_inprogress = false;
2364 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2365 } else {
2366 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2367 ppsc->rfchange_inprogress = false;
2368 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2369 }
2370 *valid = 1;
2371 return !ppsc->hwradiooff;
2372}