Loading...
Note: File does not exist in v3.1.
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2013 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "../pci.h"
32#include "../core.h"
33#include "../ps.h"
34#include "reg.h"
35#include "def.h"
36#include "phy.h"
37#include "rf.h"
38#include "dm.h"
39#include "table.h"
40
41static void set_baseband_phy_config(struct ieee80211_hw *hw);
42static void set_baseband_agc_config(struct ieee80211_hw *hw);
43static void store_pwrindex_offset(struct ieee80211_hw *hw,
44 u32 regaddr, u32 bitmask,
45 u32 data);
46static bool check_cond(struct ieee80211_hw *hw, const u32 condition);
47
48static u32 rf_serial_read(struct ieee80211_hw *hw,
49 enum radio_path rfpath, u32 offset)
50{
51 struct rtl_priv *rtlpriv = rtl_priv(hw);
52 struct rtl_phy *rtlphy = &(rtlpriv->phy);
53 struct bb_reg_def *phreg = &rtlphy->phyreg_def[rfpath];
54 u32 newoffset;
55 u32 tmplong, tmplong2;
56 u8 rfpi_enable = 0;
57 u32 ret;
58 int jj = RF90_PATH_A;
59 int kk = RF90_PATH_B;
60
61 offset &= 0xff;
62 newoffset = offset;
63 if (RT_CANNOT_IO(hw)) {
64 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "return all one\n");
65 return 0xFFFFFFFF;
66 }
67 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
68 if (rfpath == jj)
69 tmplong2 = tmplong;
70 else
71 tmplong2 = rtl_get_bbreg(hw, phreg->rfhssi_para2, MASKDWORD);
72 tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) |
73 (newoffset << 23) | BLSSIREADEDGE;
74 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
75 tmplong & (~BLSSIREADEDGE));
76 mdelay(1);
77 rtl_set_bbreg(hw, phreg->rfhssi_para2, MASKDWORD, tmplong2);
78 mdelay(2);
79 if (rfpath == jj)
80 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
81 BIT(8));
82 else if (rfpath == kk)
83 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
84 BIT(8));
85 if (rfpi_enable)
86 ret = rtl_get_bbreg(hw, phreg->rf_rbpi, BLSSIREADBACKDATA);
87 else
88 ret = rtl_get_bbreg(hw, phreg->rf_rb, BLSSIREADBACKDATA);
89 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x]= 0x%x\n",
90 rfpath, phreg->rf_rb, ret);
91 return ret;
92}
93
94static void rf_serial_write(struct ieee80211_hw *hw,
95 enum radio_path rfpath, u32 offset,
96 u32 data)
97{
98 u32 data_and_addr;
99 u32 newoffset;
100 struct rtl_priv *rtlpriv = rtl_priv(hw);
101 struct rtl_phy *rtlphy = &(rtlpriv->phy);
102 struct bb_reg_def *phreg = &rtlphy->phyreg_def[rfpath];
103
104 if (RT_CANNOT_IO(hw)) {
105 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "stop\n");
106 return;
107 }
108 offset &= 0xff;
109 newoffset = offset;
110 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
111 rtl_set_bbreg(hw, phreg->rf3wire_offset, MASKDWORD, data_and_addr);
112 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]= 0x%x\n",
113 rfpath, phreg->rf3wire_offset, data_and_addr);
114}
115
116static u32 cal_bit_shift(u32 bitmask)
117{
118 u32 i;
119
120 for (i = 0; i <= 31; i++) {
121 if (((bitmask >> i) & 0x1) == 1)
122 break;
123 }
124 return i;
125}
126
127static bool config_bb_with_header(struct ieee80211_hw *hw,
128 u8 configtype)
129{
130 if (configtype == BASEBAND_CONFIG_PHY_REG)
131 set_baseband_phy_config(hw);
132 else if (configtype == BASEBAND_CONFIG_AGC_TAB)
133 set_baseband_agc_config(hw);
134 return true;
135}
136
137static bool config_bb_with_pgheader(struct ieee80211_hw *hw,
138 u8 configtype)
139{
140 struct rtl_priv *rtlpriv = rtl_priv(hw);
141 int i;
142 u32 *table_pg;
143 u16 tbl_page_len;
144 u32 v1 = 0, v2 = 0;
145
146 tbl_page_len = RTL8188EEPHY_REG_ARRAY_PGLEN;
147 table_pg = RTL8188EEPHY_REG_ARRAY_PG;
148
149 if (configtype == BASEBAND_CONFIG_PHY_REG) {
150 for (i = 0; i < tbl_page_len; i = i + 3) {
151 v1 = table_pg[i];
152 v2 = table_pg[i + 1];
153
154 if (v1 < 0xcdcdcdcd) {
155 rtl_addr_delay(table_pg[i]);
156
157 store_pwrindex_offset(hw, table_pg[i],
158 table_pg[i + 1],
159 table_pg[i + 2]);
160 continue;
161 } else {
162 if (!check_cond(hw, table_pg[i])) {
163 /*don't need the hw_body*/
164 i += 2; /* skip the pair of expression*/
165 v1 = table_pg[i];
166 v2 = table_pg[i + 1];
167 while (v2 != 0xDEAD) {
168 i += 3;
169 v1 = table_pg[i];
170 v2 = table_pg[i + 1];
171 }
172 }
173 }
174 }
175 } else {
176 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
177 "configtype != BaseBand_Config_PHY_REG\n");
178 }
179 return true;
180}
181
182static bool config_parafile(struct ieee80211_hw *hw)
183{
184 struct rtl_priv *rtlpriv = rtl_priv(hw);
185 struct rtl_phy *rtlphy = &(rtlpriv->phy);
186 struct rtl_efuse *fuse = rtl_efuse(rtl_priv(hw));
187 bool rtstatus;
188
189 rtstatus = config_bb_with_header(hw, BASEBAND_CONFIG_PHY_REG);
190 if (rtstatus != true) {
191 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Write BB Reg Fail!!");
192 return false;
193 }
194
195 if (fuse->autoload_failflag == false) {
196 rtlphy->pwrgroup_cnt = 0;
197 rtstatus = config_bb_with_pgheader(hw, BASEBAND_CONFIG_PHY_REG);
198 }
199 if (rtstatus != true) {
200 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "BB_PG Reg Fail!!");
201 return false;
202 }
203 rtstatus = config_bb_with_header(hw, BASEBAND_CONFIG_AGC_TAB);
204 if (rtstatus != true) {
205 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "AGC Table Fail\n");
206 return false;
207 }
208 rtlphy->cck_high_power = (bool) (rtl_get_bbreg(hw,
209 RFPGA0_XA_HSSIPARAMETER2, 0x200));
210
211 return true;
212}
213
214static void rtl88e_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw)
215{
216 struct rtl_priv *rtlpriv = rtl_priv(hw);
217 struct rtl_phy *rtlphy = &(rtlpriv->phy);
218 int jj = RF90_PATH_A;
219 int kk = RF90_PATH_B;
220
221 rtlphy->phyreg_def[jj].rfintfs = RFPGA0_XAB_RFINTERFACESW;
222 rtlphy->phyreg_def[kk].rfintfs = RFPGA0_XAB_RFINTERFACESW;
223 rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
224 rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
225
226 rtlphy->phyreg_def[jj].rfintfi = RFPGA0_XAB_RFINTERFACERB;
227 rtlphy->phyreg_def[kk].rfintfi = RFPGA0_XAB_RFINTERFACERB;
228 rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;
229 rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;
230
231 rtlphy->phyreg_def[jj].rfintfo = RFPGA0_XA_RFINTERFACEOE;
232 rtlphy->phyreg_def[kk].rfintfo = RFPGA0_XB_RFINTERFACEOE;
233
234 rtlphy->phyreg_def[jj].rfintfe = RFPGA0_XA_RFINTERFACEOE;
235 rtlphy->phyreg_def[kk].rfintfe = RFPGA0_XB_RFINTERFACEOE;
236
237 rtlphy->phyreg_def[jj].rf3wire_offset = RFPGA0_XA_LSSIPARAMETER;
238 rtlphy->phyreg_def[kk].rf3wire_offset = RFPGA0_XB_LSSIPARAMETER;
239
240 rtlphy->phyreg_def[jj].rflssi_select = rFPGA0_XAB_RFPARAMETER;
241 rtlphy->phyreg_def[kk].rflssi_select = rFPGA0_XAB_RFPARAMETER;
242 rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = rFPGA0_XCD_RFPARAMETER;
243 rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = rFPGA0_XCD_RFPARAMETER;
244
245 rtlphy->phyreg_def[jj].rftxgain_stage = RFPGA0_TXGAINSTAGE;
246 rtlphy->phyreg_def[kk].rftxgain_stage = RFPGA0_TXGAINSTAGE;
247 rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;
248 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;
249
250 rtlphy->phyreg_def[jj].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;
251 rtlphy->phyreg_def[kk].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;
252
253 rtlphy->phyreg_def[jj].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
254 rtlphy->phyreg_def[kk].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
255
256 rtlphy->phyreg_def[jj].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
257 rtlphy->phyreg_def[kk].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
258 rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
259 rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
260
261 rtlphy->phyreg_def[jj].rfagc_control1 = ROFDM0_XAAGCCORE1;
262 rtlphy->phyreg_def[kk].rfagc_control1 = ROFDM0_XBAGCCORE1;
263 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;
264 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;
265
266 rtlphy->phyreg_def[jj].rfagc_control2 = ROFDM0_XAAGCCORE2;
267 rtlphy->phyreg_def[kk].rfagc_control2 = ROFDM0_XBAGCCORE2;
268 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;
269 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;
270
271 rtlphy->phyreg_def[jj].rfrxiq_imbal = ROFDM0_XARXIQIMBAL;
272 rtlphy->phyreg_def[kk].rfrxiq_imbal = ROFDM0_XBRXIQIMBAL;
273 rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBAL;
274 rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBAL;
275
276 rtlphy->phyreg_def[jj].rfrx_afe = ROFDM0_XARXAFE;
277 rtlphy->phyreg_def[kk].rfrx_afe = ROFDM0_XBRXAFE;
278 rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
279 rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
280
281 rtlphy->phyreg_def[jj].rftxiq_imbal = ROFDM0_XATXIQIMBAL;
282 rtlphy->phyreg_def[kk].rftxiq_imbal = ROFDM0_XBTXIQIMBAL;
283 rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBAL;
284 rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBAL;
285
286 rtlphy->phyreg_def[jj].rftx_afe = ROFDM0_XATXAFE;
287 rtlphy->phyreg_def[kk].rftx_afe = ROFDM0_XBTXAFE;
288
289 rtlphy->phyreg_def[jj].rf_rb = RFPGA0_XA_LSSIREADBACK;
290 rtlphy->phyreg_def[kk].rf_rb = RFPGA0_XB_LSSIREADBACK;
291
292 rtlphy->phyreg_def[jj].rf_rbpi = TRANSCEIVEA_HSPI_READBACK;
293 rtlphy->phyreg_def[kk].rf_rbpi = TRANSCEIVEB_HSPI_READBACK;
294}
295
296static bool rtl88e_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
297 u32 cmdtableidx, u32 cmdtablesz,
298 enum swchnlcmd_id cmdid,
299 u32 para1, u32 para2, u32 msdelay)
300{
301 struct swchnlcmd *pcmd;
302
303 if (cmdtable == NULL) {
304 RT_ASSERT(false, "cmdtable cannot be NULL.\n");
305 return false;
306 }
307
308 if (cmdtableidx >= cmdtablesz)
309 return false;
310
311 pcmd = cmdtable + cmdtableidx;
312 pcmd->cmdid = cmdid;
313 pcmd->para1 = para1;
314 pcmd->para2 = para2;
315 pcmd->msdelay = msdelay;
316 return true;
317}
318
319static bool chnl_step_by_step(struct ieee80211_hw *hw,
320 u8 channel, u8 *stage, u8 *step,
321 u32 *delay)
322{
323 struct rtl_priv *rtlpriv = rtl_priv(hw);
324 struct rtl_phy *rtlphy = &(rtlpriv->phy);
325 struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
326 u32 precommoncmdcnt;
327 struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
328 u32 postcommoncmdcnt;
329 struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
330 u32 rfdependcmdcnt;
331 struct swchnlcmd *currentcmd = NULL;
332 u8 rfpath;
333 u8 num_total_rfpath = rtlphy->num_total_rfpath;
334
335 precommoncmdcnt = 0;
336 rtl88e_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
337 MAX_PRECMD_CNT,
338 CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0);
339 rtl88e_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
340 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
341
342 postcommoncmdcnt = 0;
343
344 rtl88e_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
345 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
346
347 rfdependcmdcnt = 0;
348
349 RT_ASSERT((channel >= 1 && channel <= 14),
350 "illegal channel for Zebra: %d\n", channel);
351
352 rtl88e_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
353 MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG,
354 RF_CHNLBW, channel, 10);
355
356 rtl88e_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
357 MAX_RFDEPENDCMD_CNT, CMDID_END, 0, 0,
358 0);
359
360 do {
361 switch (*stage) {
362 case 0:
363 currentcmd = &precommoncmd[*step];
364 break;
365 case 1:
366 currentcmd = &rfdependcmd[*step];
367 break;
368 case 2:
369 currentcmd = &postcommoncmd[*step];
370 break;
371 }
372
373 if (currentcmd->cmdid == CMDID_END) {
374 if ((*stage) == 2) {
375 return true;
376 } else {
377 (*stage)++;
378 (*step) = 0;
379 continue;
380 }
381 }
382
383 switch (currentcmd->cmdid) {
384 case CMDID_SET_TXPOWEROWER_LEVEL:
385 rtl88e_phy_set_txpower_level(hw, channel);
386 break;
387 case CMDID_WRITEPORT_ULONG:
388 rtl_write_dword(rtlpriv, currentcmd->para1,
389 currentcmd->para2);
390 break;
391 case CMDID_WRITEPORT_USHORT:
392 rtl_write_word(rtlpriv, currentcmd->para1,
393 (u16) currentcmd->para2);
394 break;
395 case CMDID_WRITEPORT_UCHAR:
396 rtl_write_byte(rtlpriv, currentcmd->para1,
397 (u8) currentcmd->para2);
398 break;
399 case CMDID_RF_WRITEREG:
400 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
401 rtlphy->rfreg_chnlval[rfpath] =
402 ((rtlphy->rfreg_chnlval[rfpath] &
403 0xfffffc00) | currentcmd->para2);
404
405 rtl_set_rfreg(hw, (enum radio_path)rfpath,
406 currentcmd->para1,
407 RFREG_OFFSET_MASK,
408 rtlphy->rfreg_chnlval[rfpath]);
409 }
410 break;
411 default:
412 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
413 "switch case not processed\n");
414 break;
415 }
416
417 break;
418 } while (true);
419
420 (*delay) = currentcmd->msdelay;
421 (*step)++;
422 return false;
423}
424
425static long rtl88e_pwr_idx_dbm(struct ieee80211_hw *hw,
426 enum wireless_mode wirelessmode,
427 u8 txpwridx)
428{
429 long offset;
430 long pwrout_dbm;
431
432 switch (wirelessmode) {
433 case WIRELESS_MODE_B:
434 offset = -7;
435 break;
436 case WIRELESS_MODE_G:
437 case WIRELESS_MODE_N_24G:
438 offset = -8;
439 break;
440 default:
441 offset = -8;
442 break;
443 }
444 pwrout_dbm = txpwridx / 2 + offset;
445 return pwrout_dbm;
446}
447
448static void rtl88e_phy_set_io(struct ieee80211_hw *hw)
449{
450 struct rtl_priv *rtlpriv = rtl_priv(hw);
451 struct rtl_phy *rtlphy = &(rtlpriv->phy);
452 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
453
454 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
455 "--->Cmd(%#x), set_io_inprogress(%d)\n",
456 rtlphy->current_io_type, rtlphy->set_io_inprogress);
457 switch (rtlphy->current_io_type) {
458 case IO_CMD_RESUME_DM_BY_SCAN:
459 dm_digtable->cur_igvalue = rtlphy->initgain_backup.xaagccore1;
460 /*rtl92c_dm_write_dig(hw);*/
461 rtl88e_phy_set_txpower_level(hw, rtlphy->current_channel);
462 rtl_set_bbreg(hw, RCCK0_CCA, 0xff0000, 0x83);
463 break;
464 case IO_CMD_PAUSE_DM_BY_SCAN:
465 rtlphy->initgain_backup.xaagccore1 = dm_digtable->cur_igvalue;
466 dm_digtable->cur_igvalue = 0x17;
467 rtl_set_bbreg(hw, RCCK0_CCA, 0xff0000, 0x40);
468 break;
469 default:
470 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
471 "switch case not processed\n");
472 break;
473 }
474 rtlphy->set_io_inprogress = false;
475 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
476 "(%#x)\n", rtlphy->current_io_type);
477}
478
479u32 rtl88e_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
480{
481 struct rtl_priv *rtlpriv = rtl_priv(hw);
482 u32 returnvalue, originalvalue, bitshift;
483
484 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
485 "regaddr(%#x), bitmask(%#x)\n", regaddr, bitmask);
486 originalvalue = rtl_read_dword(rtlpriv, regaddr);
487 bitshift = cal_bit_shift(bitmask);
488 returnvalue = (originalvalue & bitmask) >> bitshift;
489
490 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
491 "BBR MASK = 0x%x Addr[0x%x]= 0x%x\n", bitmask,
492 regaddr, originalvalue);
493
494 return returnvalue;
495}
496
497void rtl88e_phy_set_bb_reg(struct ieee80211_hw *hw,
498 u32 regaddr, u32 bitmask, u32 data)
499{
500 struct rtl_priv *rtlpriv = rtl_priv(hw);
501 u32 originalvalue, bitshift;
502
503 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
504 "regaddr(%#x), bitmask(%#x),data(%#x)\n",
505 regaddr, bitmask, data);
506
507 if (bitmask != MASKDWORD) {
508 originalvalue = rtl_read_dword(rtlpriv, regaddr);
509 bitshift = cal_bit_shift(bitmask);
510 data = ((originalvalue & (~bitmask)) | (data << bitshift));
511 }
512
513 rtl_write_dword(rtlpriv, regaddr, data);
514
515 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
516 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
517 regaddr, bitmask, data);
518}
519
520u32 rtl88e_phy_query_rf_reg(struct ieee80211_hw *hw,
521 enum radio_path rfpath, u32 regaddr, u32 bitmask)
522{
523 struct rtl_priv *rtlpriv = rtl_priv(hw);
524 u32 original_value, readback_value, bitshift;
525 unsigned long flags;
526
527 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
528 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
529 regaddr, rfpath, bitmask);
530
531 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
532
533
534 original_value = rf_serial_read(hw, rfpath, regaddr);
535 bitshift = cal_bit_shift(bitmask);
536 readback_value = (original_value & bitmask) >> bitshift;
537
538 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
539
540 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
541 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
542 regaddr, rfpath, bitmask, original_value);
543
544 return readback_value;
545}
546
547void rtl88e_phy_set_rf_reg(struct ieee80211_hw *hw,
548 enum radio_path rfpath,
549 u32 regaddr, u32 bitmask, u32 data)
550{
551 struct rtl_priv *rtlpriv = rtl_priv(hw);
552 u32 original_value, bitshift;
553 unsigned long flags;
554
555 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
556 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
557 regaddr, bitmask, data, rfpath);
558
559 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
560
561 if (bitmask != RFREG_OFFSET_MASK) {
562 original_value = rf_serial_read(hw, rfpath, regaddr);
563 bitshift = cal_bit_shift(bitmask);
564 data = ((original_value & (~bitmask)) |
565 (data << bitshift));
566 }
567
568 rf_serial_write(hw, rfpath, regaddr, data);
569
570
571 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
572
573 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
574 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
575 regaddr, bitmask, data, rfpath);
576}
577
578static bool config_mac_with_header(struct ieee80211_hw *hw)
579{
580 struct rtl_priv *rtlpriv = rtl_priv(hw);
581 u32 i;
582 u32 arraylength;
583 u32 *ptrarray;
584
585 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Read Rtl8188EMACPHY_Array\n");
586 arraylength = RTL8188EEMAC_1T_ARRAYLEN;
587 ptrarray = RTL8188EEMAC_1T_ARRAY;
588 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
589 "Img:RTL8188EEMAC_1T_ARRAY LEN %d\n", arraylength);
590 for (i = 0; i < arraylength; i = i + 2)
591 rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]);
592 return true;
593}
594
595bool rtl88e_phy_mac_config(struct ieee80211_hw *hw)
596{
597 struct rtl_priv *rtlpriv = rtl_priv(hw);
598 bool rtstatus = config_mac_with_header(hw);
599
600 rtl_write_byte(rtlpriv, 0x04CA, 0x0B);
601 return rtstatus;
602}
603
604bool rtl88e_phy_bb_config(struct ieee80211_hw *hw)
605{
606 bool rtstatus = true;
607 struct rtl_priv *rtlpriv = rtl_priv(hw);
608 u16 regval;
609 u8 reg_hwparafile = 1;
610 u32 tmp;
611 rtl88e_phy_init_bb_rf_register_definition(hw);
612 regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
613 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN,
614 regval | BIT(13) | BIT(0) | BIT(1));
615
616 rtl_write_byte(rtlpriv, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
617 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN,
618 FEN_PPLL | FEN_PCIEA | FEN_DIO_PCIE |
619 FEN_BB_GLB_RSTN | FEN_BBRSTB);
620 tmp = rtl_read_dword(rtlpriv, 0x4c);
621 rtl_write_dword(rtlpriv, 0x4c, tmp | BIT(23));
622 if (reg_hwparafile == 1)
623 rtstatus = config_parafile(hw);
624 return rtstatus;
625}
626
627bool rtl88e_phy_rf_config(struct ieee80211_hw *hw)
628{
629 return rtl88e_phy_rf6052_config(hw);
630}
631
632static bool check_cond(struct ieee80211_hw *hw,
633 const u32 condition)
634{
635 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
636 struct rtl_efuse *fuse = rtl_efuse(rtl_priv(hw));
637 u32 _board = fuse->board_type; /*need efuse define*/
638 u32 _interface = rtlhal->interface;
639 u32 _platform = 0x08;/*SupportPlatform */
640 u32 cond = condition;
641
642 if (condition == 0xCDCDCDCD)
643 return true;
644
645 cond = condition & 0xFF;
646 if ((_board & cond) == 0 && cond != 0x1F)
647 return false;
648
649 cond = condition & 0xFF00;
650 cond = cond >> 8;
651 if ((_interface & cond) == 0 && cond != 0x07)
652 return false;
653
654 cond = condition & 0xFF0000;
655 cond = cond >> 16;
656 if ((_platform & cond) == 0 && cond != 0x0F)
657 return false;
658 return true;
659}
660
661static void _rtl8188e_config_rf_reg(struct ieee80211_hw *hw,
662 u32 addr, u32 data, enum radio_path rfpath,
663 u32 regaddr)
664{
665 rtl_rfreg_delay(hw, rfpath, regaddr,
666 RFREG_OFFSET_MASK,
667 data);
668}
669
670static void rtl88_config_s(struct ieee80211_hw *hw,
671 u32 addr, u32 data)
672{
673 u32 content = 0x1000; /*RF Content: radio_a_txt*/
674 u32 maskforphyset = (u32)(content & 0xE000);
675
676 _rtl8188e_config_rf_reg(hw, addr, data, RF90_PATH_A,
677 addr | maskforphyset);
678}
679
680#define NEXT_PAIR(v1, v2, i) \
681 do { \
682 i += 2; v1 = array_table[i]; \
683 v2 = array_table[i + 1]; \
684 } while (0)
685
686static void set_baseband_agc_config(struct ieee80211_hw *hw)
687{
688 int i;
689 u32 *array_table;
690 u16 arraylen;
691 struct rtl_priv *rtlpriv = rtl_priv(hw);
692 u32 v1 = 0, v2 = 0;
693
694 arraylen = RTL8188EEAGCTAB_1TARRAYLEN;
695 array_table = RTL8188EEAGCTAB_1TARRAY;
696
697 for (i = 0; i < arraylen; i += 2) {
698 v1 = array_table[i];
699 v2 = array_table[i + 1];
700 if (v1 < 0xCDCDCDCD) {
701 rtl_set_bbreg(hw, array_table[i], MASKDWORD,
702 array_table[i + 1]);
703 udelay(1);
704 continue;
705 } else {/*This line is the start line of branch.*/
706 if (!check_cond(hw, array_table[i])) {
707 /*Discard the following (offset, data) pairs*/
708 NEXT_PAIR(v1, v2, i);
709 while (v2 != 0xDEAD && v2 != 0xCDEF &&
710 v2 != 0xCDCD && i < arraylen - 2) {
711 NEXT_PAIR(v1, v2, i);
712 }
713 i -= 2; /* compensate for loop's += 2*/
714 } else {
715 /* Configure matched pairs and skip to end */
716 NEXT_PAIR(v1, v2, i);
717 while (v2 != 0xDEAD && v2 != 0xCDEF &&
718 v2 != 0xCDCD && i < arraylen - 2) {
719 rtl_set_bbreg(hw, array_table[i],
720 MASKDWORD,
721 array_table[i + 1]);
722 udelay(1);
723 NEXT_PAIR(v1, v2, i);
724 }
725
726 while (v2 != 0xDEAD && i < arraylen - 2)
727 NEXT_PAIR(v1, v2, i);
728 }
729 }
730 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
731 "The agctab_array_table[0] is %x Rtl818EEPHY_REGArray[1] is %x\n",
732 array_table[i],
733 array_table[i + 1]);
734 }
735}
736
737static void set_baseband_phy_config(struct ieee80211_hw *hw)
738{
739 int i;
740 u32 *array_table;
741 u16 arraylen;
742 u32 v1 = 0, v2 = 0;
743
744 arraylen = RTL8188EEPHY_REG_1TARRAYLEN;
745 array_table = RTL8188EEPHY_REG_1TARRAY;
746
747 for (i = 0; i < arraylen; i += 2) {
748 v1 = array_table[i];
749 v2 = array_table[i + 1];
750 if (v1 < 0xcdcdcdcd) {
751 rtl_bb_delay(hw, v1, v2);
752 } else {/*This line is the start line of branch.*/
753 if (!check_cond(hw, array_table[i])) {
754 /*Discard the following (offset, data) pairs*/
755 NEXT_PAIR(v1, v2, i);
756 while (v2 != 0xDEAD &&
757 v2 != 0xCDEF &&
758 v2 != 0xCDCD && i < arraylen - 2)
759 NEXT_PAIR(v1, v2, i);
760 i -= 2; /* prevent from for-loop += 2*/
761 } else {
762 /* Configure matched pairs and skip to end */
763 NEXT_PAIR(v1, v2, i);
764 while (v2 != 0xDEAD &&
765 v2 != 0xCDEF &&
766 v2 != 0xCDCD && i < arraylen - 2) {
767 rtl_bb_delay(hw, v1, v2);
768 NEXT_PAIR(v1, v2, i);
769 }
770
771 while (v2 != 0xDEAD && i < arraylen - 2)
772 NEXT_PAIR(v1, v2, i);
773 }
774 }
775 }
776}
777
778static void store_pwrindex_offset(struct ieee80211_hw *hw,
779 u32 regaddr, u32 bitmask,
780 u32 data)
781{
782 struct rtl_priv *rtlpriv = rtl_priv(hw);
783 struct rtl_phy *rtlphy = &(rtlpriv->phy);
784
785 if (regaddr == RTXAGC_A_RATE18_06) {
786 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][0] = data;
787 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
788 "MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x\n",
789 rtlphy->pwrgroup_cnt,
790 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][0]);
791 }
792 if (regaddr == RTXAGC_A_RATE54_24) {
793 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][1] = data;
794 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
795 "MCSTxPowerLevelOriginalOffset[%d][1] = 0x%x\n",
796 rtlphy->pwrgroup_cnt,
797 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][1]);
798 }
799 if (regaddr == RTXAGC_A_CCK1_MCS32) {
800 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][6] = data;
801 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
802 "MCSTxPowerLevelOriginalOffset[%d][6] = 0x%x\n",
803 rtlphy->pwrgroup_cnt,
804 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][6]);
805 }
806 if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00) {
807 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][7] = data;
808 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
809 "MCSTxPowerLevelOriginalOffset[%d][7] = 0x%x\n",
810 rtlphy->pwrgroup_cnt,
811 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][7]);
812 }
813 if (regaddr == RTXAGC_A_MCS03_MCS00) {
814 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][2] = data;
815 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
816 "MCSTxPowerLevelOriginalOffset[%d][2] = 0x%x\n",
817 rtlphy->pwrgroup_cnt,
818 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][2]);
819 }
820 if (regaddr == RTXAGC_A_MCS07_MCS04) {
821 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][3] = data;
822 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
823 "MCSTxPowerLevelOriginalOffset[%d][3] = 0x%x\n",
824 rtlphy->pwrgroup_cnt,
825 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][3]);
826 }
827 if (regaddr == RTXAGC_A_MCS11_MCS08) {
828 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][4] = data;
829 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
830 "MCSTxPowerLevelOriginalOffset[%d][4] = 0x%x\n",
831 rtlphy->pwrgroup_cnt,
832 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][4]);
833 }
834 if (regaddr == RTXAGC_A_MCS15_MCS12) {
835 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][5] = data;
836 if (get_rf_type(rtlphy) == RF_1T1R)
837 rtlphy->pwrgroup_cnt++;
838 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
839 "MCSTxPowerLevelOriginalOffset[%d][5] = 0x%x\n",
840 rtlphy->pwrgroup_cnt,
841 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][5]);
842 }
843 if (regaddr == RTXAGC_B_RATE18_06) {
844 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][8] = data;
845 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
846 "MCSTxPowerLevelOriginalOffset[%d][8] = 0x%x\n",
847 rtlphy->pwrgroup_cnt,
848 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][8]);
849 }
850 if (regaddr == RTXAGC_B_RATE54_24) {
851 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][9] = data;
852 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
853 "MCSTxPowerLevelOriginalOffset[%d][9] = 0x%x\n",
854 rtlphy->pwrgroup_cnt,
855 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][9]);
856 }
857 if (regaddr == RTXAGC_B_CCK1_55_MCS32) {
858 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][14] = data;
859 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
860 "MCSTxPowerLevelOriginalOffset[%d][14] = 0x%x\n",
861 rtlphy->pwrgroup_cnt,
862 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][14]);
863 }
864 if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff) {
865 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][15] = data;
866 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
867 "MCSTxPowerLevelOriginalOffset[%d][15] = 0x%x\n",
868 rtlphy->pwrgroup_cnt,
869 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][15]);
870 }
871 if (regaddr == RTXAGC_B_MCS03_MCS00) {
872 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][10] = data;
873 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
874 "MCSTxPowerLevelOriginalOffset[%d][10] = 0x%x\n",
875 rtlphy->pwrgroup_cnt,
876 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][10]);
877 }
878 if (regaddr == RTXAGC_B_MCS07_MCS04) {
879 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][11] = data;
880 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
881 "MCSTxPowerLevelOriginalOffset[%d][11] = 0x%x\n",
882 rtlphy->pwrgroup_cnt,
883 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][11]);
884 }
885 if (regaddr == RTXAGC_B_MCS11_MCS08) {
886 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][12] = data;
887 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
888 "MCSTxPowerLevelOriginalOffset[%d][12] = 0x%x\n",
889 rtlphy->pwrgroup_cnt,
890 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][12]);
891 }
892 if (regaddr == RTXAGC_B_MCS15_MCS12) {
893 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][13] = data;
894 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
895 "MCSTxPowerLevelOriginalOffset[%d][13] = 0x%x\n",
896 rtlphy->pwrgroup_cnt,
897 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][13]);
898 if (get_rf_type(rtlphy) != RF_1T1R)
899 rtlphy->pwrgroup_cnt++;
900 }
901}
902
903#define READ_NEXT_RF_PAIR(v1, v2, i) \
904 do { \
905 i += 2; v1 = a_table[i]; \
906 v2 = a_table[i + 1]; \
907 } while (0)
908
909bool rtl88e_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
910 enum radio_path rfpath)
911{
912 int i;
913 u32 *a_table;
914 u16 a_len;
915 struct rtl_priv *rtlpriv = rtl_priv(hw);
916 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
917 u32 v1 = 0, v2 = 0;
918
919 a_len = RTL8188EE_RADIOA_1TARRAYLEN;
920 a_table = RTL8188EE_RADIOA_1TARRAY;
921 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
922 "Radio_A:RTL8188EE_RADIOA_1TARRAY %d\n", a_len);
923 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Radio No %x\n", rfpath);
924 switch (rfpath) {
925 case RF90_PATH_A:
926 for (i = 0; i < a_len; i = i + 2) {
927 v1 = a_table[i];
928 v2 = a_table[i + 1];
929 if (v1 < 0xcdcdcdcd) {
930 rtl88_config_s(hw, v1, v2);
931 } else {/*This line is the start line of branch.*/
932 if (!check_cond(hw, a_table[i])) {
933 /* Discard the following (offset, data)
934 * pairs
935 */
936 READ_NEXT_RF_PAIR(v1, v2, i);
937 while (v2 != 0xDEAD && v2 != 0xCDEF &&
938 v2 != 0xCDCD && i < a_len - 2)
939 READ_NEXT_RF_PAIR(v1, v2, i);
940 i -= 2; /* prevent from for-loop += 2*/
941 } else {
942 /* Configure matched pairs and skip to
943 * end of if-else.
944 */
945 READ_NEXT_RF_PAIR(v1, v2, i);
946 while (v2 != 0xDEAD && v2 != 0xCDEF &&
947 v2 != 0xCDCD && i < a_len - 2) {
948 rtl88_config_s(hw, v1, v2);
949 READ_NEXT_RF_PAIR(v1, v2, i);
950 }
951
952 while (v2 != 0xDEAD && i < a_len - 2)
953 READ_NEXT_RF_PAIR(v1, v2, i);
954 }
955 }
956 }
957
958 if (rtlhal->oem_id == RT_CID_819X_HP)
959 rtl88_config_s(hw, 0x52, 0x7E4BD);
960
961 break;
962
963 case RF90_PATH_B:
964 case RF90_PATH_C:
965 case RF90_PATH_D:
966 default:
967 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
968 "switch case not processed\n");
969 break;
970 }
971 return true;
972}
973
974void rtl88e_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
975{
976 struct rtl_priv *rtlpriv = rtl_priv(hw);
977 struct rtl_phy *rtlphy = &(rtlpriv->phy);
978
979 rtlphy->default_initialgain[0] = rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1,
980 MASKBYTE0);
981 rtlphy->default_initialgain[1] = rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1,
982 MASKBYTE0);
983 rtlphy->default_initialgain[2] = rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1,
984 MASKBYTE0);
985 rtlphy->default_initialgain[3] = rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1,
986 MASKBYTE0);
987
988 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
989 "Default initial gain (c50 = 0x%x, c58 = 0x%x, c60 = 0x%x, c68 = 0x%x\n",
990 rtlphy->default_initialgain[0],
991 rtlphy->default_initialgain[1],
992 rtlphy->default_initialgain[2],
993 rtlphy->default_initialgain[3]);
994
995 rtlphy->framesync = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3,
996 MASKBYTE0);
997 rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2,
998 MASKDWORD);
999
1000 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1001 "Default framesync (0x%x) = 0x%x\n",
1002 ROFDM0_RXDETECTOR3, rtlphy->framesync);
1003}
1004
1005void rtl88e_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel)
1006{
1007 struct rtl_priv *rtlpriv = rtl_priv(hw);
1008 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1009 u8 level;
1010 long dbm;
1011
1012 level = rtlphy->cur_cck_txpwridx;
1013 dbm = rtl88e_pwr_idx_dbm(hw, WIRELESS_MODE_B, level);
1014 level = rtlphy->cur_ofdm24g_txpwridx;
1015 if (rtl88e_pwr_idx_dbm(hw, WIRELESS_MODE_G, level) > dbm)
1016 dbm = rtl88e_pwr_idx_dbm(hw, WIRELESS_MODE_G, level);
1017 level = rtlphy->cur_ofdm24g_txpwridx;
1018 if (rtl88e_pwr_idx_dbm(hw, WIRELESS_MODE_N_24G, level) > dbm)
1019 dbm = rtl88e_pwr_idx_dbm(hw, WIRELESS_MODE_N_24G, level);
1020 *powerlevel = dbm;
1021}
1022
1023static void _rtl88e_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
1024 u8 *cckpower, u8 *ofdm, u8 *bw20_pwr,
1025 u8 *bw40_pwr)
1026{
1027 struct rtl_efuse *fuse = rtl_efuse(rtl_priv(hw));
1028 u8 i = (channel - 1);
1029 u8 rf_path = 0;
1030 int jj = RF90_PATH_A;
1031 int kk = RF90_PATH_B;
1032
1033 for (rf_path = 0; rf_path < 2; rf_path++) {
1034 if (rf_path == jj) {
1035 cckpower[jj] = fuse->txpwrlevel_cck[jj][i];
1036 if (fuse->txpwr_ht20diff[jj][i] > 0x0f) /*-8~7 */
1037 bw20_pwr[jj] = fuse->txpwrlevel_ht40_1s[jj][i] -
1038 (~(fuse->txpwr_ht20diff[jj][i]) + 1);
1039 else
1040 bw20_pwr[jj] = fuse->txpwrlevel_ht40_1s[jj][i] +
1041 fuse->txpwr_ht20diff[jj][i];
1042 if (fuse->txpwr_legacyhtdiff[jj][i] > 0xf)
1043 ofdm[jj] = fuse->txpwrlevel_ht40_1s[jj][i] -
1044 (~(fuse->txpwr_legacyhtdiff[jj][i])+1);
1045 else
1046 ofdm[jj] = fuse->txpwrlevel_ht40_1s[jj][i] +
1047 fuse->txpwr_legacyhtdiff[jj][i];
1048 bw40_pwr[jj] = fuse->txpwrlevel_ht40_1s[jj][i];
1049
1050 } else if (rf_path == kk) {
1051 cckpower[kk] = fuse->txpwrlevel_cck[kk][i];
1052 bw20_pwr[kk] = fuse->txpwrlevel_ht40_1s[kk][i] +
1053 fuse->txpwr_ht20diff[kk][i];
1054 ofdm[kk] = fuse->txpwrlevel_ht40_1s[kk][i] +
1055 fuse->txpwr_legacyhtdiff[kk][i];
1056 bw40_pwr[kk] = fuse->txpwrlevel_ht40_1s[kk][i];
1057 }
1058 }
1059}
1060
1061static void _rtl88e_ccxpower_index_check(struct ieee80211_hw *hw,
1062 u8 channel, u8 *cckpower,
1063 u8 *ofdm, u8 *bw20_pwr,
1064 u8 *bw40_pwr)
1065{
1066 struct rtl_priv *rtlpriv = rtl_priv(hw);
1067 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1068
1069 rtlphy->cur_cck_txpwridx = cckpower[0];
1070 rtlphy->cur_ofdm24g_txpwridx = ofdm[0];
1071 rtlphy->cur_bw20_txpwridx = bw20_pwr[0];
1072 rtlphy->cur_bw40_txpwridx = bw40_pwr[0];
1073}
1074
1075void rtl88e_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel)
1076{
1077 struct rtl_efuse *fuse = rtl_efuse(rtl_priv(hw));
1078 u8 cckpower[MAX_TX_COUNT] = {0}, ofdm[MAX_TX_COUNT] = {0};
1079 u8 bw20_pwr[MAX_TX_COUNT] = {0}, bw40_pwr[MAX_TX_COUNT] = {0};
1080
1081 if (fuse->txpwr_fromeprom == false)
1082 return;
1083 _rtl88e_get_txpower_index(hw, channel, &cckpower[0], &ofdm[0],
1084 &bw20_pwr[0], &bw40_pwr[0]);
1085 _rtl88e_ccxpower_index_check(hw, channel, &cckpower[0], &ofdm[0],
1086 &bw20_pwr[0], &bw40_pwr[0]);
1087 rtl88e_phy_rf6052_set_cck_txpower(hw, &cckpower[0]);
1088 rtl88e_phy_rf6052_set_ofdm_txpower(hw, &ofdm[0], &bw20_pwr[0],
1089 &bw40_pwr[0], channel);
1090}
1091
1092void rtl88e_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
1093{
1094 struct rtl_priv *rtlpriv = rtl_priv(hw);
1095 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1096 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1097 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1098 u8 reg_bw_opmode;
1099 u8 reg_prsr_rsc;
1100
1101 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
1102 "Switch to %s bandwidth\n",
1103 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
1104 "20MHz" : "40MHz");
1105
1106 if (is_hal_stop(rtlhal)) {
1107 rtlphy->set_bwmode_inprogress = false;
1108 return;
1109 }
1110
1111 reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
1112 reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);
1113
1114 switch (rtlphy->current_chan_bw) {
1115 case HT_CHANNEL_WIDTH_20:
1116 reg_bw_opmode |= BW_OPMODE_20MHZ;
1117 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
1118 break;
1119 case HT_CHANNEL_WIDTH_20_40:
1120 reg_bw_opmode &= ~BW_OPMODE_20MHZ;
1121 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
1122 reg_prsr_rsc =
1123 (reg_prsr_rsc & 0x90) | (mac->cur_40_prime_sc << 5);
1124 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
1125 break;
1126 default:
1127 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1128 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
1129 break;
1130 }
1131
1132 switch (rtlphy->current_chan_bw) {
1133 case HT_CHANNEL_WIDTH_20:
1134 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
1135 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
1136 /* rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);*/
1137 break;
1138 case HT_CHANNEL_WIDTH_20_40:
1139 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
1140 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
1141
1142 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
1143 (mac->cur_40_prime_sc >> 1));
1144 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
1145 /*rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0);*/
1146
1147 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
1148 (mac->cur_40_prime_sc ==
1149 HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
1150 break;
1151 default:
1152 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1153 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
1154 break;
1155 }
1156 rtl88e_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
1157 rtlphy->set_bwmode_inprogress = false;
1158 RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD, "\n");
1159}
1160
1161void rtl88e_phy_set_bw_mode(struct ieee80211_hw *hw,
1162 enum nl80211_channel_type ch_type)
1163{
1164 struct rtl_priv *rtlpriv = rtl_priv(hw);
1165 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1166 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1167 u8 tmp_bw = rtlphy->current_chan_bw;
1168
1169 if (rtlphy->set_bwmode_inprogress)
1170 return;
1171 rtlphy->set_bwmode_inprogress = true;
1172 if ((!is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
1173 rtl88e_phy_set_bw_mode_callback(hw);
1174 } else {
1175 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1176 "FALSE driver sleep or unload\n");
1177 rtlphy->set_bwmode_inprogress = false;
1178 rtlphy->current_chan_bw = tmp_bw;
1179 }
1180}
1181
1182void rtl88e_phy_sw_chnl_callback(struct ieee80211_hw *hw)
1183{
1184 struct rtl_priv *rtlpriv = rtl_priv(hw);
1185 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1186 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1187 u32 delay;
1188
1189 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
1190 "switch to channel%d\n", rtlphy->current_channel);
1191 if (is_hal_stop(rtlhal))
1192 return;
1193 do {
1194 if (!rtlphy->sw_chnl_inprogress)
1195 break;
1196 if (!chnl_step_by_step(hw, rtlphy->current_channel,
1197 &rtlphy->sw_chnl_stage,
1198 &rtlphy->sw_chnl_step, &delay)) {
1199 if (delay > 0)
1200 mdelay(delay);
1201 else
1202 continue;
1203 } else {
1204 rtlphy->sw_chnl_inprogress = false;
1205 }
1206 break;
1207 } while (true);
1208 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "\n");
1209}
1210
1211u8 rtl88e_phy_sw_chnl(struct ieee80211_hw *hw)
1212{
1213 struct rtl_priv *rtlpriv = rtl_priv(hw);
1214 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1215 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1216
1217 if (rtlphy->sw_chnl_inprogress)
1218 return 0;
1219 if (rtlphy->set_bwmode_inprogress)
1220 return 0;
1221 RT_ASSERT((rtlphy->current_channel <= 14),
1222 "WIRELESS_MODE_G but channel>14");
1223 rtlphy->sw_chnl_inprogress = true;
1224 rtlphy->sw_chnl_stage = 0;
1225 rtlphy->sw_chnl_step = 0;
1226 if (!(is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
1227 rtl88e_phy_sw_chnl_callback(hw);
1228 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
1229 "sw_chnl_inprogress false schdule workitem current channel %d\n",
1230 rtlphy->current_channel);
1231 rtlphy->sw_chnl_inprogress = false;
1232 } else {
1233 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
1234 "sw_chnl_inprogress false driver sleep or unload\n");
1235 rtlphy->sw_chnl_inprogress = false;
1236 }
1237 return 1;
1238}
1239
1240static u8 _rtl88e_phy_path_a_iqk(struct ieee80211_hw *hw, bool config_pathb)
1241{
1242 u32 reg_eac, reg_e94, reg_e9c;
1243 u8 result = 0x00;
1244
1245 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1c);
1246 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x30008c1c);
1247 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x8214032a);
1248 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x28160000);
1249
1250 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911);
1251 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000);
1252 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
1253
1254 mdelay(IQK_DELAY_TIME);
1255
1256 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1257 reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);
1258 reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);
1259
1260 if (!(reg_eac & BIT(28)) &&
1261 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
1262 (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
1263 result |= 0x01;
1264 return result;
1265}
1266
1267static u8 _rtl88e_phy_path_b_iqk(struct ieee80211_hw *hw)
1268{
1269 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
1270 u8 result = 0x00;
1271
1272 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002);
1273 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000);
1274 mdelay(IQK_DELAY_TIME);
1275 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1276 reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);
1277 reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);
1278 reg_ec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD);
1279 reg_ecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD);
1280
1281 if (!(reg_eac & BIT(31)) &&
1282 (((reg_eb4 & 0x03FF0000) >> 16) != 0x142) &&
1283 (((reg_ebc & 0x03FF0000) >> 16) != 0x42))
1284 result |= 0x01;
1285 else
1286 return result;
1287 if (!(reg_eac & BIT(30)) &&
1288 (((reg_ec4 & 0x03FF0000) >> 16) != 0x132) &&
1289 (((reg_ecc & 0x03FF0000) >> 16) != 0x36))
1290 result |= 0x02;
1291 return result;
1292}
1293
1294static u8 _rtl88e_phy_path_a_rx_iqk(struct ieee80211_hw *hw, bool config_pathb)
1295{
1296 u32 reg_eac, reg_e94, reg_e9c, reg_ea4, u32temp;
1297 u8 result = 0x00;
1298 int jj = RF90_PATH_A;
1299
1300 /*Get TXIMR Setting*/
1301 /*Modify RX IQK mode table*/
1302 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
1303 rtl_set_rfreg(hw, jj, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0);
1304 rtl_set_rfreg(hw, jj, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000);
1305 rtl_set_rfreg(hw, jj, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f);
1306 rtl_set_rfreg(hw, jj, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf117b);
1307 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
1308
1309 /*IQK Setting*/
1310 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00);
1311 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x81004800);
1312
1313 /*path a IQK setting*/
1314 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x10008c1c);
1315 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x30008c1c);
1316 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160804);
1317 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28160000);
1318
1319 /*LO calibration Setting*/
1320 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911);
1321 /*one shot, path A LOK & iqk*/
1322 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);
1323 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);
1324
1325 mdelay(IQK_DELAY_TIME);
1326
1327 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);
1328 reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD);
1329 reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD);
1330
1331
1332 if (!(reg_eac & BIT(28)) &&
1333 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
1334 (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
1335 result |= 0x01;
1336 else
1337 return result;
1338
1339 u32temp = 0x80007C00 | (reg_e94&0x3FF0000) |
1340 ((reg_e9c&0x3FF0000) >> 16);
1341 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32temp);
1342 /*RX IQK*/
1343 /*Modify RX IQK mode table*/
1344 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
1345 rtl_set_rfreg(hw, jj, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0);
1346 rtl_set_rfreg(hw, jj, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000);
1347 rtl_set_rfreg(hw, jj, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f);
1348 rtl_set_rfreg(hw, jj, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf7ffa);
1349 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
1350
1351 /*IQK Setting*/
1352 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);
1353
1354 /*path a IQK setting*/
1355 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x30008c1c);
1356 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x10008c1c);
1357 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160c05);
1358 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28160c05);
1359
1360 /*LO calibration Setting*/
1361 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911);
1362 /*one shot, path A LOK & iqk*/
1363 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);
1364 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);
1365
1366 mdelay(IQK_DELAY_TIME);
1367
1368 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);
1369 reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD);
1370 reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD);
1371 reg_ea4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, MASKDWORD);
1372
1373 if (!(reg_eac & BIT(27)) &&
1374 (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) &&
1375 (((reg_eac & 0x03FF0000) >> 16) != 0x36))
1376 result |= 0x02;
1377 return result;
1378}
1379
1380static void fill_iqk(struct ieee80211_hw *hw, bool iqk_ok, long result[][8],
1381 u8 final, bool btxonly)
1382{
1383 u32 oldval_0, x, tx0_a, reg;
1384 long y, tx0_c;
1385
1386 if (final == 0xFF) {
1387 return;
1388 } else if (iqk_ok) {
1389 oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBAL,
1390 MASKDWORD) >> 22) & 0x3FF;
1391 x = result[final][0];
1392 if ((x & 0x00000200) != 0)
1393 x = x | 0xFFFFFC00;
1394 tx0_a = (x * oldval_0) >> 8;
1395 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBAL, 0x3FF, tx0_a);
1396 rtl_set_bbreg(hw, ROFDM0_ECCATHRES, BIT(31),
1397 ((x * oldval_0 >> 7) & 0x1));
1398 y = result[final][1];
1399 if ((y & 0x00000200) != 0)
1400 y |= 0xFFFFFC00;
1401 tx0_c = (y * oldval_0) >> 8;
1402 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000,
1403 ((tx0_c & 0x3C0) >> 6));
1404 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBAL, 0x003F0000,
1405 (tx0_c & 0x3F));
1406 rtl_set_bbreg(hw, ROFDM0_ECCATHRES, BIT(29),
1407 ((y * oldval_0 >> 7) & 0x1));
1408 if (btxonly)
1409 return;
1410 reg = result[final][2];
1411 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBAL, 0x3FF, reg);
1412 reg = result[final][3] & 0x3F;
1413 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBAL, 0xFC00, reg);
1414 reg = (result[final][3] >> 6) & 0xF;
1415 rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg);
1416 }
1417}
1418
1419static void save_adda_reg(struct ieee80211_hw *hw,
1420 const u32 *addareg, u32 *backup,
1421 u32 registernum)
1422{
1423 u32 i;
1424
1425 for (i = 0; i < registernum; i++)
1426 backup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD);
1427}
1428
1429static void save_mac_reg(struct ieee80211_hw *hw, const u32 *macreg,
1430 u32 *macbackup)
1431{
1432 struct rtl_priv *rtlpriv = rtl_priv(hw);
1433 u32 i;
1434
1435 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1436 macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]);
1437 macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]);
1438}
1439
1440static void reload_adda(struct ieee80211_hw *hw, const u32 *addareg,
1441 u32 *backup, u32 reg_num)
1442{
1443 u32 i;
1444
1445 for (i = 0; i < reg_num; i++)
1446 rtl_set_bbreg(hw, addareg[i], MASKDWORD, backup[i]);
1447}
1448
1449static void reload_mac(struct ieee80211_hw *hw, const u32 *macreg,
1450 u32 *macbackup)
1451{
1452 struct rtl_priv *rtlpriv = rtl_priv(hw);
1453 u32 i;
1454
1455 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1456 rtl_write_byte(rtlpriv, macreg[i], (u8) macbackup[i]);
1457 rtl_write_dword(rtlpriv, macreg[i], macbackup[i]);
1458}
1459
1460static void _rtl88e_phy_path_adda_on(struct ieee80211_hw *hw,
1461 const u32 *addareg, bool is_patha_on,
1462 bool is2t)
1463{
1464 u32 pathon;
1465 u32 i;
1466
1467 pathon = is_patha_on ? 0x04db25a4 : 0x0b1b25a4;
1468 if (false == is2t) {
1469 pathon = 0x0bdb25a0;
1470 rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0b1b25a0);
1471 } else {
1472 rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathon);
1473 }
1474
1475 for (i = 1; i < IQK_ADDA_REG_NUM; i++)
1476 rtl_set_bbreg(hw, addareg[i], MASKDWORD, pathon);
1477}
1478
1479static void _rtl88e_phy_mac_setting_calibration(struct ieee80211_hw *hw,
1480 const u32 *macreg,
1481 u32 *macbackup)
1482{
1483 struct rtl_priv *rtlpriv = rtl_priv(hw);
1484 u32 i = 0;
1485
1486 rtl_write_byte(rtlpriv, macreg[i], 0x3F);
1487
1488 for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++)
1489 rtl_write_byte(rtlpriv, macreg[i],
1490 (u8) (macbackup[i] & (~BIT(3))));
1491 rtl_write_byte(rtlpriv, macreg[i], (u8) (macbackup[i] & (~BIT(5))));
1492}
1493
1494static void _rtl88e_phy_path_a_standby(struct ieee80211_hw *hw)
1495{
1496 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0);
1497 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000);
1498 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1499}
1500
1501static void _rtl88e_phy_pi_mode_switch(struct ieee80211_hw *hw, bool pi_mode)
1502{
1503 u32 mode;
1504
1505 mode = pi_mode ? 0x01000100 : 0x01000000;
1506 rtl_set_bbreg(hw, 0x820, MASKDWORD, mode);
1507 rtl_set_bbreg(hw, 0x828, MASKDWORD, mode);
1508}
1509
1510static bool sim_comp(struct ieee80211_hw *hw, long result[][8], u8 c1, u8 c2)
1511{
1512 u32 i, j, diff, bitmap, bound;
1513 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1514
1515 u8 final[2] = {0xFF, 0xFF};
1516 bool bresult = true, is2t = IS_92C_SERIAL(rtlhal->version);
1517
1518 if (is2t)
1519 bound = 8;
1520 else
1521 bound = 4;
1522
1523 bitmap = 0;
1524
1525 for (i = 0; i < bound; i++) {
1526 diff = (result[c1][i] > result[c2][i]) ?
1527 (result[c1][i] - result[c2][i]) :
1528 (result[c2][i] - result[c1][i]);
1529
1530 if (diff > MAX_TOLERANCE) {
1531 if ((i == 2 || i == 6) && !bitmap) {
1532 if (result[c1][i] + result[c1][i + 1] == 0)
1533 final[(i / 4)] = c2;
1534 else if (result[c2][i] + result[c2][i + 1] == 0)
1535 final[(i / 4)] = c1;
1536 else
1537 bitmap = bitmap | (1 << i);
1538 } else {
1539 bitmap = bitmap | (1 << i);
1540 }
1541 }
1542 }
1543
1544 if (bitmap == 0) {
1545 for (i = 0; i < (bound / 4); i++) {
1546 if (final[i] != 0xFF) {
1547 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
1548 result[3][j] = result[final[i]][j];
1549 bresult = false;
1550 }
1551 }
1552 return bresult;
1553 } else if (!(bitmap & 0x0F)) {
1554 for (i = 0; i < 4; i++)
1555 result[3][i] = result[c1][i];
1556 return false;
1557 } else if (!(bitmap & 0xF0) && is2t) {
1558 for (i = 4; i < 8; i++)
1559 result[3][i] = result[c1][i];
1560 return false;
1561 } else {
1562 return false;
1563 }
1564}
1565
1566static void _rtl88e_phy_iq_calibrate(struct ieee80211_hw *hw,
1567 long result[][8], u8 t, bool is2t)
1568{
1569 struct rtl_priv *rtlpriv = rtl_priv(hw);
1570 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1571 u32 i;
1572 u8 patha_ok, pathb_ok;
1573 const u32 adda_reg[IQK_ADDA_REG_NUM] = {
1574 0x85c, 0xe6c, 0xe70, 0xe74,
1575 0xe78, 0xe7c, 0xe80, 0xe84,
1576 0xe88, 0xe8c, 0xed0, 0xed4,
1577 0xed8, 0xedc, 0xee0, 0xeec
1578 };
1579 const u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
1580 0x522, 0x550, 0x551, 0x040
1581 };
1582 const u32 iqk_bb_reg[IQK_BB_REG_NUM] = {
1583 ROFDM0_TRXPATHENABLE, ROFDM0_TRMUXPAR, RFPGA0_XCD_RFINTERFACESW,
1584 0xb68, 0xb6c, 0x870, 0x860, 0x864, 0x800
1585 };
1586 const u32 retrycount = 2;
1587
1588 if (t == 0) {
1589 save_adda_reg(hw, adda_reg, rtlphy->adda_backup, 16);
1590 save_mac_reg(hw, iqk_mac_reg, rtlphy->iqk_mac_backup);
1591 save_adda_reg(hw, iqk_bb_reg, rtlphy->iqk_bb_backup,
1592 IQK_BB_REG_NUM);
1593 }
1594 _rtl88e_phy_path_adda_on(hw, adda_reg, true, is2t);
1595 if (t == 0) {
1596 rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw,
1597 RFPGA0_XA_HSSIPARAMETER1, BIT(8));
1598 }
1599
1600 if (!rtlphy->rfpi_enable)
1601 _rtl88e_phy_pi_mode_switch(hw, true);
1602 /*BB Setting*/
1603 rtl_set_bbreg(hw, 0x800, BIT(24), 0x00);
1604 rtl_set_bbreg(hw, 0xc04, MASKDWORD, 0x03a05600);
1605 rtl_set_bbreg(hw, 0xc08, MASKDWORD, 0x000800e4);
1606 rtl_set_bbreg(hw, 0x874, MASKDWORD, 0x22204000);
1607
1608 rtl_set_bbreg(hw, 0x870, BIT(10), 0x01);
1609 rtl_set_bbreg(hw, 0x870, BIT(26), 0x01);
1610 rtl_set_bbreg(hw, 0x860, BIT(10), 0x00);
1611 rtl_set_bbreg(hw, 0x864, BIT(10), 0x00);
1612
1613 if (is2t) {
1614 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000);
1615 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00010000);
1616 }
1617 _rtl88e_phy_mac_setting_calibration(hw, iqk_mac_reg,
1618 rtlphy->iqk_mac_backup);
1619 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000);
1620 if (is2t)
1621 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000);
1622
1623 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1624 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00);
1625 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x81004800);
1626 for (i = 0; i < retrycount; i++) {
1627 patha_ok = _rtl88e_phy_path_a_iqk(hw, is2t);
1628 if (patha_ok == 0x01) {
1629 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1630 "Path A Tx IQK Success!!\n");
1631 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
1632 0x3FF0000) >> 16;
1633 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
1634 0x3FF0000) >> 16;
1635 break;
1636 }
1637 }
1638
1639 for (i = 0; i < retrycount; i++) {
1640 patha_ok = _rtl88e_phy_path_a_rx_iqk(hw, is2t);
1641 if (patha_ok == 0x03) {
1642 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1643 "Path A Rx IQK Success!!\n");
1644 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) &
1645 0x3FF0000) >> 16;
1646 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) &
1647 0x3FF0000) >> 16;
1648 break;
1649 } else {
1650 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1651 "Path a RX iqk fail!!!\n");
1652 }
1653 }
1654
1655 if (0 == patha_ok) {
1656 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1657 "Path A IQK Success!!\n");
1658 }
1659 if (is2t) {
1660 _rtl88e_phy_path_a_standby(hw);
1661 _rtl88e_phy_path_adda_on(hw, adda_reg, false, is2t);
1662 for (i = 0; i < retrycount; i++) {
1663 pathb_ok = _rtl88e_phy_path_b_iqk(hw);
1664 if (pathb_ok == 0x03) {
1665 result[t][4] = (rtl_get_bbreg(hw,
1666 0xeb4, MASKDWORD) &
1667 0x3FF0000) >> 16;
1668 result[t][5] =
1669 (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
1670 0x3FF0000) >> 16;
1671 result[t][6] =
1672 (rtl_get_bbreg(hw, 0xec4, MASKDWORD) &
1673 0x3FF0000) >> 16;
1674 result[t][7] =
1675 (rtl_get_bbreg(hw, 0xecc, MASKDWORD) &
1676 0x3FF0000) >> 16;
1677 break;
1678 } else if (i == (retrycount - 1) && pathb_ok == 0x01) {
1679 result[t][4] = (rtl_get_bbreg(hw,
1680 0xeb4, MASKDWORD) &
1681 0x3FF0000) >> 16;
1682 }
1683 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
1684 0x3FF0000) >> 16;
1685 }
1686 }
1687
1688 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0);
1689
1690 if (t != 0) {
1691 if (!rtlphy->rfpi_enable)
1692 _rtl88e_phy_pi_mode_switch(hw, false);
1693 reload_adda(hw, adda_reg, rtlphy->adda_backup, 16);
1694 reload_mac(hw, iqk_mac_reg, rtlphy->iqk_mac_backup);
1695 reload_adda(hw, iqk_bb_reg, rtlphy->iqk_bb_backup,
1696 IQK_BB_REG_NUM);
1697
1698 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00032ed3);
1699 if (is2t)
1700 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00032ed3);
1701 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x01008c00);
1702 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x01008c00);
1703 }
1704 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "88ee IQK Finish!!\n");
1705}
1706
1707static void _rtl88e_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
1708{
1709 u8 tmpreg;
1710 u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal;
1711 struct rtl_priv *rtlpriv = rtl_priv(hw);
1712 int jj = RF90_PATH_A;
1713 int kk = RF90_PATH_B;
1714
1715 tmpreg = rtl_read_byte(rtlpriv, 0xd03);
1716
1717 if ((tmpreg & 0x70) != 0)
1718 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
1719 else
1720 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1721
1722 if ((tmpreg & 0x70) != 0) {
1723 rf_a_mode = rtl_get_rfreg(hw, jj, 0x00, MASK12BITS);
1724
1725 if (is2t)
1726 rf_b_mode = rtl_get_rfreg(hw, kk, 0x00,
1727 MASK12BITS);
1728
1729 rtl_set_rfreg(hw, jj, 0x00, MASK12BITS,
1730 (rf_a_mode & 0x8FFFF) | 0x10000);
1731
1732 if (is2t)
1733 rtl_set_rfreg(hw, kk, 0x00, MASK12BITS,
1734 (rf_b_mode & 0x8FFFF) | 0x10000);
1735 }
1736 lc_cal = rtl_get_rfreg(hw, jj, 0x18, MASK12BITS);
1737
1738 rtl_set_rfreg(hw, jj, 0x18, MASK12BITS, lc_cal | 0x08000);
1739
1740 mdelay(100);
1741
1742 if ((tmpreg & 0x70) != 0) {
1743 rtl_write_byte(rtlpriv, 0xd03, tmpreg);
1744 rtl_set_rfreg(hw, jj, 0x00, MASK12BITS, rf_a_mode);
1745
1746 if (is2t)
1747 rtl_set_rfreg(hw, kk, 0x00, MASK12BITS,
1748 rf_b_mode);
1749 } else {
1750 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
1751 }
1752 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "\n");
1753}
1754
1755static void rfpath_switch(struct ieee80211_hw *hw,
1756 bool bmain, bool is2t)
1757{
1758 struct rtl_priv *rtlpriv = rtl_priv(hw);
1759 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1760 struct rtl_efuse *fuse = rtl_efuse(rtl_priv(hw));
1761 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "\n");
1762
1763 if (is_hal_stop(rtlhal)) {
1764 u8 u1btmp;
1765 u1btmp = rtl_read_byte(rtlpriv, REG_LEDCFG0);
1766 rtl_write_byte(rtlpriv, REG_LEDCFG0, u1btmp | BIT(7));
1767 rtl_set_bbreg(hw, rFPGA0_XAB_RFPARAMETER, BIT(13), 0x01);
1768 }
1769 if (is2t) {
1770 if (bmain)
1771 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
1772 BIT(5) | BIT(6), 0x1);
1773 else
1774 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
1775 BIT(5) | BIT(6), 0x2);
1776 } else {
1777 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BIT(8) | BIT(9), 0);
1778 rtl_set_bbreg(hw, 0x914, MASKLWORD, 0x0201);
1779
1780 /* We use the RF definition of MAIN and AUX, left antenna and
1781 * right antenna repectively.
1782 * Default output at AUX.
1783 */
1784 if (bmain) {
1785 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(14) |
1786 BIT(13) | BIT(12), 0);
1787 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BIT(5) |
1788 BIT(4) | BIT(3), 0);
1789 if (fuse->antenna_div_type == CGCS_RX_HW_ANTDIV)
1790 rtl_set_bbreg(hw, RCONFIG_RAM64X16, BIT(31), 0);
1791 } else {
1792 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(14) |
1793 BIT(13) | BIT(12), 1);
1794 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BIT(5) |
1795 BIT(4) | BIT(3), 1);
1796 if (fuse->antenna_div_type == CGCS_RX_HW_ANTDIV)
1797 rtl_set_bbreg(hw, RCONFIG_RAM64X16, BIT(31), 1);
1798 }
1799 }
1800}
1801
1802#undef IQK_ADDA_REG_NUM
1803#undef IQK_DELAY_TIME
1804
1805void rtl88e_phy_iq_calibrate(struct ieee80211_hw *hw, bool recovery)
1806{
1807 struct rtl_priv *rtlpriv = rtl_priv(hw);
1808 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1809 long result[4][8];
1810 u8 i, final;
1811 bool patha_ok;
1812 long reg_e94, reg_e9c, reg_ea4, reg_eb4, reg_ebc, reg_tmp = 0;
1813 bool is12simular, is13simular, is23simular;
1814 u32 iqk_bb_reg[9] = {
1815 ROFDM0_XARXIQIMBAL,
1816 ROFDM0_XBRXIQIMBAL,
1817 ROFDM0_ECCATHRES,
1818 ROFDM0_AGCRSSITABLE,
1819 ROFDM0_XATXIQIMBAL,
1820 ROFDM0_XBTXIQIMBAL,
1821 ROFDM0_XCTXAFE,
1822 ROFDM0_XDTXAFE,
1823 ROFDM0_RXIQEXTANTA
1824 };
1825
1826 if (recovery) {
1827 reload_adda(hw, iqk_bb_reg, rtlphy->iqk_bb_backup, 9);
1828 return;
1829 }
1830
1831 memset(result, 0, 32 * sizeof(long));
1832 final = 0xff;
1833 patha_ok = false;
1834 is12simular = false;
1835 is23simular = false;
1836 is13simular = false;
1837 for (i = 0; i < 3; i++) {
1838 if (get_rf_type(rtlphy) == RF_2T2R)
1839 _rtl88e_phy_iq_calibrate(hw, result, i, true);
1840 else
1841 _rtl88e_phy_iq_calibrate(hw, result, i, false);
1842 if (i == 1) {
1843 is12simular = sim_comp(hw, result, 0, 1);
1844 if (is12simular) {
1845 final = 0;
1846 break;
1847 }
1848 }
1849 if (i == 2) {
1850 is13simular = sim_comp(hw, result, 0, 2);
1851 if (is13simular) {
1852 final = 0;
1853 break;
1854 }
1855 is23simular = sim_comp(hw, result, 1, 2);
1856 if (is23simular) {
1857 final = 1;
1858 } else {
1859 for (i = 0; i < 8; i++)
1860 reg_tmp += result[3][i];
1861
1862 if (reg_tmp != 0)
1863 final = 3;
1864 else
1865 final = 0xFF;
1866 }
1867 }
1868 }
1869 for (i = 0; i < 4; i++) {
1870 reg_e94 = result[i][0];
1871 reg_e9c = result[i][1];
1872 reg_ea4 = result[i][2];
1873 reg_eb4 = result[i][4];
1874 reg_ebc = result[i][5];
1875 }
1876 if (final != 0xff) {
1877 reg_e94 = result[final][0];
1878 rtlphy->reg_e94 = reg_e94;
1879 reg_e9c = result[final][1];
1880 rtlphy->reg_e9c = reg_e9c;
1881 reg_ea4 = result[final][2];
1882 reg_eb4 = result[final][4];
1883 rtlphy->reg_eb4 = reg_eb4;
1884 reg_ebc = result[final][5];
1885 rtlphy->reg_ebc = reg_ebc;
1886 patha_ok = true;
1887 } else {
1888 rtlphy->reg_e94 = 0x100;
1889 rtlphy->reg_eb4 = 0x100;
1890 rtlphy->reg_ebc = 0x0;
1891 rtlphy->reg_e9c = 0x0;
1892 }
1893 if (reg_e94 != 0) /*&&(reg_ea4 != 0) */
1894 fill_iqk(hw, patha_ok, result, final, (reg_ea4 == 0));
1895 if (final != 0xFF) {
1896 for (i = 0; i < IQK_MATRIX_REG_NUM; i++)
1897 rtlphy->iqk_matrix[0].value[0][i] = result[final][i];
1898 rtlphy->iqk_matrix[0].iqk_done = true;
1899 }
1900 save_adda_reg(hw, iqk_bb_reg, rtlphy->iqk_bb_backup, 9);
1901}
1902
1903void rtl88e_phy_lc_calibrate(struct ieee80211_hw *hw)
1904{
1905 struct rtl_priv *rtlpriv = rtl_priv(hw);
1906 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1907 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
1908 bool start_conttx = false, singletone = false;
1909 u32 timeout = 2000, timecount = 0;
1910
1911 if (start_conttx || singletone)
1912 return;
1913
1914 while (rtlpriv->mac80211.act_scanning && timecount < timeout) {
1915 udelay(50);
1916 timecount += 50;
1917 }
1918
1919 rtlphy->lck_inprogress = true;
1920 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1921 "LCK:Start!!! currentband %x delay %d ms\n",
1922 rtlhal->current_bandtype, timecount);
1923
1924 _rtl88e_phy_lc_calibrate(hw, false);
1925
1926 rtlphy->lck_inprogress = false;
1927}
1928
1929void rtl88e_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain)
1930{
1931 rfpath_switch(hw, bmain, false);
1932}
1933
1934bool rtl88e_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
1935{
1936 struct rtl_priv *rtlpriv = rtl_priv(hw);
1937 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1938 bool postprocessing = false;
1939
1940 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1941 "-->IO Cmd(%#x), set_io_inprogress(%d)\n",
1942 iotype, rtlphy->set_io_inprogress);
1943 do {
1944 switch (iotype) {
1945 case IO_CMD_RESUME_DM_BY_SCAN:
1946 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1947 "[IO CMD] Resume DM after scan.\n");
1948 postprocessing = true;
1949 break;
1950 case IO_CMD_PAUSE_DM_BY_SCAN:
1951 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1952 "[IO CMD] Pause DM before scan.\n");
1953 postprocessing = true;
1954 break;
1955 default:
1956 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1957 "switch case not processed\n");
1958 break;
1959 }
1960 } while (false);
1961 if (postprocessing && !rtlphy->set_io_inprogress) {
1962 rtlphy->set_io_inprogress = true;
1963 rtlphy->current_io_type = iotype;
1964 } else {
1965 return false;
1966 }
1967 rtl88e_phy_set_io(hw);
1968 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, "IO Type(%#x)\n", iotype);
1969 return true;
1970}
1971
1972static void rtl88ee_phy_set_rf_on(struct ieee80211_hw *hw)
1973{
1974 struct rtl_priv *rtlpriv = rtl_priv(hw);
1975
1976 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
1977 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
1978 /*rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);*/
1979 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1980 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
1981 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
1982}
1983
1984static void _rtl88ee_phy_set_rf_sleep(struct ieee80211_hw *hw)
1985{
1986 struct rtl_priv *rtlpriv = rtl_priv(hw);
1987 int jj = RF90_PATH_A;
1988
1989 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1990 rtl_set_rfreg(hw, jj, 0x00, RFREG_OFFSET_MASK, 0x00);
1991 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1992 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
1993}
1994
1995static bool _rtl88ee_phy_set_rf_power_state(struct ieee80211_hw *hw,
1996 enum rf_pwrstate rfpwr_state)
1997{
1998 struct rtl_priv *rtlpriv = rtl_priv(hw);
1999 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2000 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2001 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2002 struct rtl8192_tx_ring *ring = NULL;
2003 bool bresult = true;
2004 u8 i, queue_id;
2005
2006 switch (rfpwr_state) {
2007 case ERFON:{
2008 if ((ppsc->rfpwr_state == ERFOFF) &&
2009 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
2010 bool rtstatus;
2011 u32 init = 0;
2012 do {
2013 init++;
2014 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2015 "IPS Set eRf nic enable\n");
2016 rtstatus = rtl_ps_enable_nic(hw);
2017 } while ((rtstatus != true) && (init < 10));
2018 RT_CLEAR_PS_LEVEL(ppsc,
2019 RT_RF_OFF_LEVL_HALT_NIC);
2020 } else {
2021 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2022 "Set ERFON sleeped:%d ms\n",
2023 jiffies_to_msecs(jiffies - ppsc->
2024 last_sleep_jiffies));
2025 ppsc->last_awake_jiffies = jiffies;
2026 rtl88ee_phy_set_rf_on(hw);
2027 }
2028 if (mac->link_state == MAC80211_LINKED)
2029 rtlpriv->cfg->ops->led_control(hw, LED_CTL_LINK);
2030 else
2031 rtlpriv->cfg->ops->led_control(hw, LED_CTL_NO_LINK);
2032 break; }
2033 case ERFOFF:{
2034 for (queue_id = 0, i = 0;
2035 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
2036 ring = &pcipriv->dev.tx_ring[queue_id];
2037 if (skb_queue_len(&ring->queue) == 0) {
2038 queue_id++;
2039 continue;
2040 } else {
2041 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2042 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
2043 (i + 1), queue_id,
2044 skb_queue_len(&ring->queue));
2045
2046 udelay(10);
2047 i++;
2048 }
2049 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
2050 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2051 "\n ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n",
2052 MAX_DOZE_WAITING_TIMES_9x,
2053 queue_id,
2054 skb_queue_len(&ring->queue));
2055 break;
2056 }
2057 }
2058 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
2059 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2060 "IPS Set eRf nic disable\n");
2061 rtl_ps_disable_nic(hw);
2062 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2063 } else {
2064 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) {
2065 rtlpriv->cfg->ops->led_control(hw,
2066 LED_CTL_NO_LINK);
2067 } else {
2068 rtlpriv->cfg->ops->led_control(hw,
2069 LED_CTL_POWER_OFF);
2070 }
2071 }
2072 break; }
2073 case ERFSLEEP:{
2074 if (ppsc->rfpwr_state == ERFOFF)
2075 break;
2076 for (queue_id = 0, i = 0;
2077 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
2078 ring = &pcipriv->dev.tx_ring[queue_id];
2079 if (skb_queue_len(&ring->queue) == 0) {
2080 queue_id++;
2081 continue;
2082 } else {
2083 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2084 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
2085 (i + 1), queue_id,
2086 skb_queue_len(&ring->queue));
2087
2088 udelay(10);
2089 i++;
2090 }
2091 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
2092 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2093 "\n ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n",
2094 MAX_DOZE_WAITING_TIMES_9x,
2095 queue_id,
2096 skb_queue_len(&ring->queue));
2097 break;
2098 }
2099 }
2100 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2101 "Set ERFSLEEP awaked:%d ms\n",
2102 jiffies_to_msecs(jiffies - ppsc->last_awake_jiffies));
2103 ppsc->last_sleep_jiffies = jiffies;
2104 _rtl88ee_phy_set_rf_sleep(hw);
2105 break; }
2106 default:
2107 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2108 "switch case not processed\n");
2109 bresult = false;
2110 break;
2111 }
2112 if (bresult)
2113 ppsc->rfpwr_state = rfpwr_state;
2114 return bresult;
2115}
2116
2117bool rtl88e_phy_set_rf_power_state(struct ieee80211_hw *hw,
2118 enum rf_pwrstate rfpwr_state)
2119{
2120 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2121 bool bresult;
2122
2123 if (rfpwr_state == ppsc->rfpwr_state)
2124 return false;
2125 bresult = _rtl88ee_phy_set_rf_power_state(hw, rfpwr_state);
2126 return bresult;
2127}