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1/******************************************************************************
2 *
3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
19 *
20 * The full GNU General Public License is included in this distribution in the
21 * file called LICENSE.
22 *
23 * Contact Information:
24 * Intel Linux Wireless <ilw@linux.intel.com>
25 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *
27 *****************************************************************************/
28
29#include "iwl-io.h"
30
31#define IWL_POLL_INTERVAL 10 /* microseconds */
32
33static inline void __iwl_set_bit(struct iwl_priv *priv, u32 reg, u32 mask)
34{
35 iwl_write32(priv, reg, iwl_read32(priv, reg) | mask);
36}
37
38static inline void __iwl_clear_bit(struct iwl_priv *priv, u32 reg, u32 mask)
39{
40 iwl_write32(priv, reg, iwl_read32(priv, reg) & ~mask);
41}
42
43void iwl_set_bit(struct iwl_priv *priv, u32 reg, u32 mask)
44{
45 unsigned long flags;
46
47 spin_lock_irqsave(&priv->reg_lock, flags);
48 __iwl_set_bit(priv, reg, mask);
49 spin_unlock_irqrestore(&priv->reg_lock, flags);
50}
51
52void iwl_clear_bit(struct iwl_priv *priv, u32 reg, u32 mask)
53{
54 unsigned long flags;
55
56 spin_lock_irqsave(&priv->reg_lock, flags);
57 __iwl_clear_bit(priv, reg, mask);
58 spin_unlock_irqrestore(&priv->reg_lock, flags);
59}
60
61int iwl_poll_bit(struct iwl_priv *priv, u32 addr,
62 u32 bits, u32 mask, int timeout)
63{
64 int t = 0;
65
66 do {
67 if ((iwl_read32(priv, addr) & mask) == (bits & mask))
68 return t;
69 udelay(IWL_POLL_INTERVAL);
70 t += IWL_POLL_INTERVAL;
71 } while (t < timeout);
72
73 return -ETIMEDOUT;
74}
75
76int iwl_grab_nic_access_silent(struct iwl_priv *priv)
77{
78 int ret;
79
80 lockdep_assert_held(&priv->reg_lock);
81
82 /* this bit wakes up the NIC */
83 __iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
84
85 /*
86 * These bits say the device is running, and should keep running for
87 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
88 * but they do not indicate that embedded SRAM is restored yet;
89 * 3945 and 4965 have volatile SRAM, and must save/restore contents
90 * to/from host DRAM when sleeping/waking for power-saving.
91 * Each direction takes approximately 1/4 millisecond; with this
92 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
93 * series of register accesses are expected (e.g. reading Event Log),
94 * to keep device from sleeping.
95 *
96 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
97 * SRAM is okay/restored. We don't check that here because this call
98 * is just for hardware register access; but GP1 MAC_SLEEP check is a
99 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
100 *
101 * 5000 series and later (including 1000 series) have non-volatile SRAM,
102 * and do not save/restore SRAM when power cycling.
103 */
104 ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
105 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
106 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
107 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
108 if (ret < 0) {
109 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
110 return -EIO;
111 }
112
113 return 0;
114}
115
116int iwl_grab_nic_access(struct iwl_priv *priv)
117{
118 int ret = iwl_grab_nic_access_silent(priv);
119 if (ret) {
120 u32 val = iwl_read32(priv, CSR_GP_CNTRL);
121 IWL_ERR(priv,
122 "MAC is in deep sleep!. CSR_GP_CNTRL = 0x%08X\n", val);
123 }
124
125 return ret;
126}
127
128void iwl_release_nic_access(struct iwl_priv *priv)
129{
130 lockdep_assert_held(&priv->reg_lock);
131 __iwl_clear_bit(priv, CSR_GP_CNTRL,
132 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
133}
134
135u32 iwl_read_direct32(struct iwl_priv *priv, u32 reg)
136{
137 u32 value;
138 unsigned long flags;
139
140 spin_lock_irqsave(&priv->reg_lock, flags);
141 iwl_grab_nic_access(priv);
142 value = iwl_read32(priv, reg);
143 iwl_release_nic_access(priv);
144 spin_unlock_irqrestore(&priv->reg_lock, flags);
145
146 return value;
147}
148
149void iwl_write_direct32(struct iwl_priv *priv, u32 reg, u32 value)
150{
151 unsigned long flags;
152
153 spin_lock_irqsave(&priv->reg_lock, flags);
154 if (!iwl_grab_nic_access(priv)) {
155 iwl_write32(priv, reg, value);
156 iwl_release_nic_access(priv);
157 }
158 spin_unlock_irqrestore(&priv->reg_lock, flags);
159}
160
161int iwl_poll_direct_bit(struct iwl_priv *priv, u32 addr, u32 mask,
162 int timeout)
163{
164 int t = 0;
165
166 do {
167 if ((iwl_read_direct32(priv, addr) & mask) == mask)
168 return t;
169 udelay(IWL_POLL_INTERVAL);
170 t += IWL_POLL_INTERVAL;
171 } while (t < timeout);
172
173 return -ETIMEDOUT;
174}
175
176static inline u32 __iwl_read_prph(struct iwl_priv *priv, u32 reg)
177{
178 iwl_write32(priv, HBUS_TARG_PRPH_RADDR, reg | (3 << 24));
179 rmb();
180 return iwl_read32(priv, HBUS_TARG_PRPH_RDAT);
181}
182
183static inline void __iwl_write_prph(struct iwl_priv *priv, u32 addr, u32 val)
184{
185 iwl_write32(priv, HBUS_TARG_PRPH_WADDR,
186 ((addr & 0x0000FFFF) | (3 << 24)));
187 wmb();
188 iwl_write32(priv, HBUS_TARG_PRPH_WDAT, val);
189}
190
191u32 iwl_read_prph(struct iwl_priv *priv, u32 reg)
192{
193 unsigned long flags;
194 u32 val;
195
196 spin_lock_irqsave(&priv->reg_lock, flags);
197 iwl_grab_nic_access(priv);
198 val = __iwl_read_prph(priv, reg);
199 iwl_release_nic_access(priv);
200 spin_unlock_irqrestore(&priv->reg_lock, flags);
201 return val;
202}
203
204void iwl_write_prph(struct iwl_priv *priv, u32 addr, u32 val)
205{
206 unsigned long flags;
207
208 spin_lock_irqsave(&priv->reg_lock, flags);
209 if (!iwl_grab_nic_access(priv)) {
210 __iwl_write_prph(priv, addr, val);
211 iwl_release_nic_access(priv);
212 }
213 spin_unlock_irqrestore(&priv->reg_lock, flags);
214}
215
216void iwl_set_bits_prph(struct iwl_priv *priv, u32 reg, u32 mask)
217{
218 unsigned long flags;
219
220 spin_lock_irqsave(&priv->reg_lock, flags);
221 iwl_grab_nic_access(priv);
222 __iwl_write_prph(priv, reg, __iwl_read_prph(priv, reg) | mask);
223 iwl_release_nic_access(priv);
224 spin_unlock_irqrestore(&priv->reg_lock, flags);
225}
226
227void iwl_set_bits_mask_prph(struct iwl_priv *priv, u32 reg,
228 u32 bits, u32 mask)
229{
230 unsigned long flags;
231
232 spin_lock_irqsave(&priv->reg_lock, flags);
233 iwl_grab_nic_access(priv);
234 __iwl_write_prph(priv, reg,
235 (__iwl_read_prph(priv, reg) & mask) | bits);
236 iwl_release_nic_access(priv);
237 spin_unlock_irqrestore(&priv->reg_lock, flags);
238}
239
240void iwl_clear_bits_prph(struct iwl_priv *priv, u32 reg, u32 mask)
241{
242 unsigned long flags;
243 u32 val;
244
245 spin_lock_irqsave(&priv->reg_lock, flags);
246 iwl_grab_nic_access(priv);
247 val = __iwl_read_prph(priv, reg);
248 __iwl_write_prph(priv, reg, (val & ~mask));
249 iwl_release_nic_access(priv);
250 spin_unlock_irqrestore(&priv->reg_lock, flags);
251}
252
253void _iwl_read_targ_mem_words(struct iwl_priv *priv, u32 addr,
254 void *buf, int words)
255{
256 unsigned long flags;
257 int offs;
258 u32 *vals = buf;
259
260 spin_lock_irqsave(&priv->reg_lock, flags);
261 iwl_grab_nic_access(priv);
262
263 iwl_write32(priv, HBUS_TARG_MEM_RADDR, addr);
264 rmb();
265
266 for (offs = 0; offs < words; offs++)
267 vals[offs] = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
268
269 iwl_release_nic_access(priv);
270 spin_unlock_irqrestore(&priv->reg_lock, flags);
271}
272
273u32 iwl_read_targ_mem(struct iwl_priv *priv, u32 addr)
274{
275 u32 value;
276
277 _iwl_read_targ_mem_words(priv, addr, &value, 1);
278
279 return value;
280}
281
282void iwl_write_targ_mem(struct iwl_priv *priv, u32 addr, u32 val)
283{
284 unsigned long flags;
285
286 spin_lock_irqsave(&priv->reg_lock, flags);
287 if (!iwl_grab_nic_access(priv)) {
288 iwl_write32(priv, HBUS_TARG_MEM_WADDR, addr);
289 wmb();
290 iwl_write32(priv, HBUS_TARG_MEM_WDAT, val);
291 iwl_release_nic_access(priv);
292 }
293 spin_unlock_irqrestore(&priv->reg_lock, flags);
294}
1/******************************************************************************
2 *
3 * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
19 *
20 * The full GNU General Public License is included in this distribution in the
21 * file called LICENSE.
22 *
23 * Contact Information:
24 * Intel Linux Wireless <ilw@linux.intel.com>
25 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *
27 *****************************************************************************/
28#include <linux/delay.h>
29#include <linux/device.h>
30#include <linux/export.h>
31
32#include "iwl-drv.h"
33#include "iwl-io.h"
34#include "iwl-csr.h"
35#include "iwl-debug.h"
36#include "iwl-fh.h"
37
38#define IWL_POLL_INTERVAL 10 /* microseconds */
39
40int iwl_poll_bit(struct iwl_trans *trans, u32 addr,
41 u32 bits, u32 mask, int timeout)
42{
43 int t = 0;
44
45 do {
46 if ((iwl_read32(trans, addr) & mask) == (bits & mask))
47 return t;
48 udelay(IWL_POLL_INTERVAL);
49 t += IWL_POLL_INTERVAL;
50 } while (t < timeout);
51
52 return -ETIMEDOUT;
53}
54IWL_EXPORT_SYMBOL(iwl_poll_bit);
55
56u32 iwl_read_direct32(struct iwl_trans *trans, u32 reg)
57{
58 u32 value = 0x5a5a5a5a;
59 unsigned long flags;
60 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
61 value = iwl_read32(trans, reg);
62 iwl_trans_release_nic_access(trans, &flags);
63 }
64
65 return value;
66}
67IWL_EXPORT_SYMBOL(iwl_read_direct32);
68
69void iwl_write_direct32(struct iwl_trans *trans, u32 reg, u32 value)
70{
71 unsigned long flags;
72
73 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
74 iwl_write32(trans, reg, value);
75 iwl_trans_release_nic_access(trans, &flags);
76 }
77}
78IWL_EXPORT_SYMBOL(iwl_write_direct32);
79
80int iwl_poll_direct_bit(struct iwl_trans *trans, u32 addr, u32 mask,
81 int timeout)
82{
83 int t = 0;
84
85 do {
86 if ((iwl_read_direct32(trans, addr) & mask) == mask)
87 return t;
88 udelay(IWL_POLL_INTERVAL);
89 t += IWL_POLL_INTERVAL;
90 } while (t < timeout);
91
92 return -ETIMEDOUT;
93}
94IWL_EXPORT_SYMBOL(iwl_poll_direct_bit);
95
96u32 __iwl_read_prph(struct iwl_trans *trans, u32 ofs)
97{
98 u32 val = iwl_trans_read_prph(trans, ofs);
99 trace_iwlwifi_dev_ioread_prph32(trans->dev, ofs, val);
100 return val;
101}
102
103void __iwl_write_prph(struct iwl_trans *trans, u32 ofs, u32 val)
104{
105 trace_iwlwifi_dev_iowrite_prph32(trans->dev, ofs, val);
106 iwl_trans_write_prph(trans, ofs, val);
107}
108
109u32 iwl_read_prph(struct iwl_trans *trans, u32 ofs)
110{
111 unsigned long flags;
112 u32 val = 0x5a5a5a5a;
113
114 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
115 val = __iwl_read_prph(trans, ofs);
116 iwl_trans_release_nic_access(trans, &flags);
117 }
118 return val;
119}
120IWL_EXPORT_SYMBOL(iwl_read_prph);
121
122void iwl_write_prph(struct iwl_trans *trans, u32 ofs, u32 val)
123{
124 unsigned long flags;
125
126 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
127 __iwl_write_prph(trans, ofs, val);
128 iwl_trans_release_nic_access(trans, &flags);
129 }
130}
131IWL_EXPORT_SYMBOL(iwl_write_prph);
132
133int iwl_poll_prph_bit(struct iwl_trans *trans, u32 addr,
134 u32 bits, u32 mask, int timeout)
135{
136 int t = 0;
137
138 do {
139 if ((iwl_read_prph(trans, addr) & mask) == (bits & mask))
140 return t;
141 udelay(IWL_POLL_INTERVAL);
142 t += IWL_POLL_INTERVAL;
143 } while (t < timeout);
144
145 return -ETIMEDOUT;
146}
147
148void iwl_set_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask)
149{
150 unsigned long flags;
151
152 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
153 __iwl_write_prph(trans, ofs,
154 __iwl_read_prph(trans, ofs) | mask);
155 iwl_trans_release_nic_access(trans, &flags);
156 }
157}
158IWL_EXPORT_SYMBOL(iwl_set_bits_prph);
159
160void iwl_set_bits_mask_prph(struct iwl_trans *trans, u32 ofs,
161 u32 bits, u32 mask)
162{
163 unsigned long flags;
164
165 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
166 __iwl_write_prph(trans, ofs,
167 (__iwl_read_prph(trans, ofs) & mask) | bits);
168 iwl_trans_release_nic_access(trans, &flags);
169 }
170}
171IWL_EXPORT_SYMBOL(iwl_set_bits_mask_prph);
172
173void iwl_clear_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask)
174{
175 unsigned long flags;
176 u32 val;
177
178 if (iwl_trans_grab_nic_access(trans, false, &flags)) {
179 val = __iwl_read_prph(trans, ofs);
180 __iwl_write_prph(trans, ofs, (val & ~mask));
181 iwl_trans_release_nic_access(trans, &flags);
182 }
183}
184IWL_EXPORT_SYMBOL(iwl_clear_bits_prph);
185
186static const char *get_fh_string(int cmd)
187{
188#define IWL_CMD(x) case x: return #x
189 switch (cmd) {
190 IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
191 IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
192 IWL_CMD(FH_RSCSR_CHNL0_WPTR);
193 IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
194 IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
195 IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
196 IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
197 IWL_CMD(FH_TSSR_TX_STATUS_REG);
198 IWL_CMD(FH_TSSR_TX_ERROR_REG);
199 default:
200 return "UNKNOWN";
201 }
202#undef IWL_CMD
203}
204
205int iwl_dump_fh(struct iwl_trans *trans, char **buf)
206{
207 int i;
208 static const u32 fh_tbl[] = {
209 FH_RSCSR_CHNL0_STTS_WPTR_REG,
210 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
211 FH_RSCSR_CHNL0_WPTR,
212 FH_MEM_RCSR_CHNL0_CONFIG_REG,
213 FH_MEM_RSSR_SHARED_CTRL_REG,
214 FH_MEM_RSSR_RX_STATUS_REG,
215 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
216 FH_TSSR_TX_STATUS_REG,
217 FH_TSSR_TX_ERROR_REG
218 };
219
220#ifdef CONFIG_IWLWIFI_DEBUGFS
221 if (buf) {
222 int pos = 0;
223 size_t bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
224
225 *buf = kmalloc(bufsz, GFP_KERNEL);
226 if (!*buf)
227 return -ENOMEM;
228
229 pos += scnprintf(*buf + pos, bufsz - pos,
230 "FH register values:\n");
231
232 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++)
233 pos += scnprintf(*buf + pos, bufsz - pos,
234 " %34s: 0X%08x\n",
235 get_fh_string(fh_tbl[i]),
236 iwl_read_direct32(trans, fh_tbl[i]));
237
238 return pos;
239 }
240#endif
241
242 IWL_ERR(trans, "FH register values:\n");
243 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++)
244 IWL_ERR(trans, " %34s: 0X%08x\n",
245 get_fh_string(fh_tbl[i]),
246 iwl_read_direct32(trans, fh_tbl[i]));
247
248 return 0;
249}