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1/*
2
3 Broadcom B43 wireless driver
4
5 DMA ringbuffer and descriptor allocation/management
6
7 Copyright (c) 2005, 2006 Michael Buesch <m@bues.ch>
8
9 Some code in this file is derived from the b44.c driver
10 Copyright (C) 2002 David S. Miller
11 Copyright (C) Pekka Pietikainen
12
13 This program is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2 of the License, or
16 (at your option) any later version.
17
18 This program is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
22
23 You should have received a copy of the GNU General Public License
24 along with this program; see the file COPYING. If not, write to
25 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
26 Boston, MA 02110-1301, USA.
27
28*/
29
30#include "b43.h"
31#include "dma.h"
32#include "main.h"
33#include "debugfs.h"
34#include "xmit.h"
35
36#include <linux/dma-mapping.h>
37#include <linux/pci.h>
38#include <linux/delay.h>
39#include <linux/skbuff.h>
40#include <linux/etherdevice.h>
41#include <linux/slab.h>
42#include <asm/div64.h>
43
44
45/* Required number of TX DMA slots per TX frame.
46 * This currently is 2, because we put the header and the ieee80211 frame
47 * into separate slots. */
48#define TX_SLOTS_PER_FRAME 2
49
50
51/* 32bit DMA ops. */
52static
53struct b43_dmadesc_generic *op32_idx2desc(struct b43_dmaring *ring,
54 int slot,
55 struct b43_dmadesc_meta **meta)
56{
57 struct b43_dmadesc32 *desc;
58
59 *meta = &(ring->meta[slot]);
60 desc = ring->descbase;
61 desc = &(desc[slot]);
62
63 return (struct b43_dmadesc_generic *)desc;
64}
65
66static void op32_fill_descriptor(struct b43_dmaring *ring,
67 struct b43_dmadesc_generic *desc,
68 dma_addr_t dmaaddr, u16 bufsize,
69 int start, int end, int irq)
70{
71 struct b43_dmadesc32 *descbase = ring->descbase;
72 int slot;
73 u32 ctl;
74 u32 addr;
75 u32 addrext;
76
77 slot = (int)(&(desc->dma32) - descbase);
78 B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
79
80 addr = (u32) (dmaaddr & ~SSB_DMA_TRANSLATION_MASK);
81 addrext = (u32) (dmaaddr & SSB_DMA_TRANSLATION_MASK)
82 >> SSB_DMA_TRANSLATION_SHIFT;
83 addr |= ring->dev->dma.translation;
84 ctl = bufsize & B43_DMA32_DCTL_BYTECNT;
85 if (slot == ring->nr_slots - 1)
86 ctl |= B43_DMA32_DCTL_DTABLEEND;
87 if (start)
88 ctl |= B43_DMA32_DCTL_FRAMESTART;
89 if (end)
90 ctl |= B43_DMA32_DCTL_FRAMEEND;
91 if (irq)
92 ctl |= B43_DMA32_DCTL_IRQ;
93 ctl |= (addrext << B43_DMA32_DCTL_ADDREXT_SHIFT)
94 & B43_DMA32_DCTL_ADDREXT_MASK;
95
96 desc->dma32.control = cpu_to_le32(ctl);
97 desc->dma32.address = cpu_to_le32(addr);
98}
99
100static void op32_poke_tx(struct b43_dmaring *ring, int slot)
101{
102 b43_dma_write(ring, B43_DMA32_TXINDEX,
103 (u32) (slot * sizeof(struct b43_dmadesc32)));
104}
105
106static void op32_tx_suspend(struct b43_dmaring *ring)
107{
108 b43_dma_write(ring, B43_DMA32_TXCTL, b43_dma_read(ring, B43_DMA32_TXCTL)
109 | B43_DMA32_TXSUSPEND);
110}
111
112static void op32_tx_resume(struct b43_dmaring *ring)
113{
114 b43_dma_write(ring, B43_DMA32_TXCTL, b43_dma_read(ring, B43_DMA32_TXCTL)
115 & ~B43_DMA32_TXSUSPEND);
116}
117
118static int op32_get_current_rxslot(struct b43_dmaring *ring)
119{
120 u32 val;
121
122 val = b43_dma_read(ring, B43_DMA32_RXSTATUS);
123 val &= B43_DMA32_RXDPTR;
124
125 return (val / sizeof(struct b43_dmadesc32));
126}
127
128static void op32_set_current_rxslot(struct b43_dmaring *ring, int slot)
129{
130 b43_dma_write(ring, B43_DMA32_RXINDEX,
131 (u32) (slot * sizeof(struct b43_dmadesc32)));
132}
133
134static const struct b43_dma_ops dma32_ops = {
135 .idx2desc = op32_idx2desc,
136 .fill_descriptor = op32_fill_descriptor,
137 .poke_tx = op32_poke_tx,
138 .tx_suspend = op32_tx_suspend,
139 .tx_resume = op32_tx_resume,
140 .get_current_rxslot = op32_get_current_rxslot,
141 .set_current_rxslot = op32_set_current_rxslot,
142};
143
144/* 64bit DMA ops. */
145static
146struct b43_dmadesc_generic *op64_idx2desc(struct b43_dmaring *ring,
147 int slot,
148 struct b43_dmadesc_meta **meta)
149{
150 struct b43_dmadesc64 *desc;
151
152 *meta = &(ring->meta[slot]);
153 desc = ring->descbase;
154 desc = &(desc[slot]);
155
156 return (struct b43_dmadesc_generic *)desc;
157}
158
159static void op64_fill_descriptor(struct b43_dmaring *ring,
160 struct b43_dmadesc_generic *desc,
161 dma_addr_t dmaaddr, u16 bufsize,
162 int start, int end, int irq)
163{
164 struct b43_dmadesc64 *descbase = ring->descbase;
165 int slot;
166 u32 ctl0 = 0, ctl1 = 0;
167 u32 addrlo, addrhi;
168 u32 addrext;
169
170 slot = (int)(&(desc->dma64) - descbase);
171 B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
172
173 addrlo = (u32) (dmaaddr & 0xFFFFFFFF);
174 addrhi = (((u64) dmaaddr >> 32) & ~SSB_DMA_TRANSLATION_MASK);
175 addrext = (((u64) dmaaddr >> 32) & SSB_DMA_TRANSLATION_MASK)
176 >> SSB_DMA_TRANSLATION_SHIFT;
177 addrhi |= ring->dev->dma.translation;
178 if (slot == ring->nr_slots - 1)
179 ctl0 |= B43_DMA64_DCTL0_DTABLEEND;
180 if (start)
181 ctl0 |= B43_DMA64_DCTL0_FRAMESTART;
182 if (end)
183 ctl0 |= B43_DMA64_DCTL0_FRAMEEND;
184 if (irq)
185 ctl0 |= B43_DMA64_DCTL0_IRQ;
186 ctl1 |= bufsize & B43_DMA64_DCTL1_BYTECNT;
187 ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT)
188 & B43_DMA64_DCTL1_ADDREXT_MASK;
189
190 desc->dma64.control0 = cpu_to_le32(ctl0);
191 desc->dma64.control1 = cpu_to_le32(ctl1);
192 desc->dma64.address_low = cpu_to_le32(addrlo);
193 desc->dma64.address_high = cpu_to_le32(addrhi);
194}
195
196static void op64_poke_tx(struct b43_dmaring *ring, int slot)
197{
198 b43_dma_write(ring, B43_DMA64_TXINDEX,
199 (u32) (slot * sizeof(struct b43_dmadesc64)));
200}
201
202static void op64_tx_suspend(struct b43_dmaring *ring)
203{
204 b43_dma_write(ring, B43_DMA64_TXCTL, b43_dma_read(ring, B43_DMA64_TXCTL)
205 | B43_DMA64_TXSUSPEND);
206}
207
208static void op64_tx_resume(struct b43_dmaring *ring)
209{
210 b43_dma_write(ring, B43_DMA64_TXCTL, b43_dma_read(ring, B43_DMA64_TXCTL)
211 & ~B43_DMA64_TXSUSPEND);
212}
213
214static int op64_get_current_rxslot(struct b43_dmaring *ring)
215{
216 u32 val;
217
218 val = b43_dma_read(ring, B43_DMA64_RXSTATUS);
219 val &= B43_DMA64_RXSTATDPTR;
220
221 return (val / sizeof(struct b43_dmadesc64));
222}
223
224static void op64_set_current_rxslot(struct b43_dmaring *ring, int slot)
225{
226 b43_dma_write(ring, B43_DMA64_RXINDEX,
227 (u32) (slot * sizeof(struct b43_dmadesc64)));
228}
229
230static const struct b43_dma_ops dma64_ops = {
231 .idx2desc = op64_idx2desc,
232 .fill_descriptor = op64_fill_descriptor,
233 .poke_tx = op64_poke_tx,
234 .tx_suspend = op64_tx_suspend,
235 .tx_resume = op64_tx_resume,
236 .get_current_rxslot = op64_get_current_rxslot,
237 .set_current_rxslot = op64_set_current_rxslot,
238};
239
240static inline int free_slots(struct b43_dmaring *ring)
241{
242 return (ring->nr_slots - ring->used_slots);
243}
244
245static inline int next_slot(struct b43_dmaring *ring, int slot)
246{
247 B43_WARN_ON(!(slot >= -1 && slot <= ring->nr_slots - 1));
248 if (slot == ring->nr_slots - 1)
249 return 0;
250 return slot + 1;
251}
252
253static inline int prev_slot(struct b43_dmaring *ring, int slot)
254{
255 B43_WARN_ON(!(slot >= 0 && slot <= ring->nr_slots - 1));
256 if (slot == 0)
257 return ring->nr_slots - 1;
258 return slot - 1;
259}
260
261#ifdef CONFIG_B43_DEBUG
262static void update_max_used_slots(struct b43_dmaring *ring,
263 int current_used_slots)
264{
265 if (current_used_slots <= ring->max_used_slots)
266 return;
267 ring->max_used_slots = current_used_slots;
268 if (b43_debug(ring->dev, B43_DBG_DMAVERBOSE)) {
269 b43dbg(ring->dev->wl,
270 "max_used_slots increased to %d on %s ring %d\n",
271 ring->max_used_slots,
272 ring->tx ? "TX" : "RX", ring->index);
273 }
274}
275#else
276static inline
277 void update_max_used_slots(struct b43_dmaring *ring, int current_used_slots)
278{
279}
280#endif /* DEBUG */
281
282/* Request a slot for usage. */
283static inline int request_slot(struct b43_dmaring *ring)
284{
285 int slot;
286
287 B43_WARN_ON(!ring->tx);
288 B43_WARN_ON(ring->stopped);
289 B43_WARN_ON(free_slots(ring) == 0);
290
291 slot = next_slot(ring, ring->current_slot);
292 ring->current_slot = slot;
293 ring->used_slots++;
294
295 update_max_used_slots(ring, ring->used_slots);
296
297 return slot;
298}
299
300static u16 b43_dmacontroller_base(enum b43_dmatype type, int controller_idx)
301{
302 static const u16 map64[] = {
303 B43_MMIO_DMA64_BASE0,
304 B43_MMIO_DMA64_BASE1,
305 B43_MMIO_DMA64_BASE2,
306 B43_MMIO_DMA64_BASE3,
307 B43_MMIO_DMA64_BASE4,
308 B43_MMIO_DMA64_BASE5,
309 };
310 static const u16 map32[] = {
311 B43_MMIO_DMA32_BASE0,
312 B43_MMIO_DMA32_BASE1,
313 B43_MMIO_DMA32_BASE2,
314 B43_MMIO_DMA32_BASE3,
315 B43_MMIO_DMA32_BASE4,
316 B43_MMIO_DMA32_BASE5,
317 };
318
319 if (type == B43_DMA_64BIT) {
320 B43_WARN_ON(!(controller_idx >= 0 &&
321 controller_idx < ARRAY_SIZE(map64)));
322 return map64[controller_idx];
323 }
324 B43_WARN_ON(!(controller_idx >= 0 &&
325 controller_idx < ARRAY_SIZE(map32)));
326 return map32[controller_idx];
327}
328
329static inline
330 dma_addr_t map_descbuffer(struct b43_dmaring *ring,
331 unsigned char *buf, size_t len, int tx)
332{
333 dma_addr_t dmaaddr;
334
335 if (tx) {
336 dmaaddr = dma_map_single(ring->dev->dev->dma_dev,
337 buf, len, DMA_TO_DEVICE);
338 } else {
339 dmaaddr = dma_map_single(ring->dev->dev->dma_dev,
340 buf, len, DMA_FROM_DEVICE);
341 }
342
343 return dmaaddr;
344}
345
346static inline
347 void unmap_descbuffer(struct b43_dmaring *ring,
348 dma_addr_t addr, size_t len, int tx)
349{
350 if (tx) {
351 dma_unmap_single(ring->dev->dev->dma_dev,
352 addr, len, DMA_TO_DEVICE);
353 } else {
354 dma_unmap_single(ring->dev->dev->dma_dev,
355 addr, len, DMA_FROM_DEVICE);
356 }
357}
358
359static inline
360 void sync_descbuffer_for_cpu(struct b43_dmaring *ring,
361 dma_addr_t addr, size_t len)
362{
363 B43_WARN_ON(ring->tx);
364 dma_sync_single_for_cpu(ring->dev->dev->dma_dev,
365 addr, len, DMA_FROM_DEVICE);
366}
367
368static inline
369 void sync_descbuffer_for_device(struct b43_dmaring *ring,
370 dma_addr_t addr, size_t len)
371{
372 B43_WARN_ON(ring->tx);
373 dma_sync_single_for_device(ring->dev->dev->dma_dev,
374 addr, len, DMA_FROM_DEVICE);
375}
376
377static inline
378 void free_descriptor_buffer(struct b43_dmaring *ring,
379 struct b43_dmadesc_meta *meta)
380{
381 if (meta->skb) {
382 dev_kfree_skb_any(meta->skb);
383 meta->skb = NULL;
384 }
385}
386
387static int alloc_ringmemory(struct b43_dmaring *ring)
388{
389 gfp_t flags = GFP_KERNEL;
390
391 /* The specs call for 4K buffers for 30- and 32-bit DMA with 4K
392 * alignment and 8K buffers for 64-bit DMA with 8K alignment. Testing
393 * has shown that 4K is sufficient for the latter as long as the buffer
394 * does not cross an 8K boundary.
395 *
396 * For unknown reasons - possibly a hardware error - the BCM4311 rev
397 * 02, which uses 64-bit DMA, needs the ring buffer in very low memory,
398 * which accounts for the GFP_DMA flag below.
399 *
400 * The flags here must match the flags in free_ringmemory below!
401 */
402 if (ring->type == B43_DMA_64BIT)
403 flags |= GFP_DMA;
404 ring->descbase = dma_alloc_coherent(ring->dev->dev->dma_dev,
405 B43_DMA_RINGMEMSIZE,
406 &(ring->dmabase), flags);
407 if (!ring->descbase) {
408 b43err(ring->dev->wl, "DMA ringmemory allocation failed\n");
409 return -ENOMEM;
410 }
411 memset(ring->descbase, 0, B43_DMA_RINGMEMSIZE);
412
413 return 0;
414}
415
416static void free_ringmemory(struct b43_dmaring *ring)
417{
418 dma_free_coherent(ring->dev->dev->dma_dev, B43_DMA_RINGMEMSIZE,
419 ring->descbase, ring->dmabase);
420}
421
422/* Reset the RX DMA channel */
423static int b43_dmacontroller_rx_reset(struct b43_wldev *dev, u16 mmio_base,
424 enum b43_dmatype type)
425{
426 int i;
427 u32 value;
428 u16 offset;
429
430 might_sleep();
431
432 offset = (type == B43_DMA_64BIT) ? B43_DMA64_RXCTL : B43_DMA32_RXCTL;
433 b43_write32(dev, mmio_base + offset, 0);
434 for (i = 0; i < 10; i++) {
435 offset = (type == B43_DMA_64BIT) ? B43_DMA64_RXSTATUS :
436 B43_DMA32_RXSTATUS;
437 value = b43_read32(dev, mmio_base + offset);
438 if (type == B43_DMA_64BIT) {
439 value &= B43_DMA64_RXSTAT;
440 if (value == B43_DMA64_RXSTAT_DISABLED) {
441 i = -1;
442 break;
443 }
444 } else {
445 value &= B43_DMA32_RXSTATE;
446 if (value == B43_DMA32_RXSTAT_DISABLED) {
447 i = -1;
448 break;
449 }
450 }
451 msleep(1);
452 }
453 if (i != -1) {
454 b43err(dev->wl, "DMA RX reset timed out\n");
455 return -ENODEV;
456 }
457
458 return 0;
459}
460
461/* Reset the TX DMA channel */
462static int b43_dmacontroller_tx_reset(struct b43_wldev *dev, u16 mmio_base,
463 enum b43_dmatype type)
464{
465 int i;
466 u32 value;
467 u16 offset;
468
469 might_sleep();
470
471 for (i = 0; i < 10; i++) {
472 offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXSTATUS :
473 B43_DMA32_TXSTATUS;
474 value = b43_read32(dev, mmio_base + offset);
475 if (type == B43_DMA_64BIT) {
476 value &= B43_DMA64_TXSTAT;
477 if (value == B43_DMA64_TXSTAT_DISABLED ||
478 value == B43_DMA64_TXSTAT_IDLEWAIT ||
479 value == B43_DMA64_TXSTAT_STOPPED)
480 break;
481 } else {
482 value &= B43_DMA32_TXSTATE;
483 if (value == B43_DMA32_TXSTAT_DISABLED ||
484 value == B43_DMA32_TXSTAT_IDLEWAIT ||
485 value == B43_DMA32_TXSTAT_STOPPED)
486 break;
487 }
488 msleep(1);
489 }
490 offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXCTL : B43_DMA32_TXCTL;
491 b43_write32(dev, mmio_base + offset, 0);
492 for (i = 0; i < 10; i++) {
493 offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXSTATUS :
494 B43_DMA32_TXSTATUS;
495 value = b43_read32(dev, mmio_base + offset);
496 if (type == B43_DMA_64BIT) {
497 value &= B43_DMA64_TXSTAT;
498 if (value == B43_DMA64_TXSTAT_DISABLED) {
499 i = -1;
500 break;
501 }
502 } else {
503 value &= B43_DMA32_TXSTATE;
504 if (value == B43_DMA32_TXSTAT_DISABLED) {
505 i = -1;
506 break;
507 }
508 }
509 msleep(1);
510 }
511 if (i != -1) {
512 b43err(dev->wl, "DMA TX reset timed out\n");
513 return -ENODEV;
514 }
515 /* ensure the reset is completed. */
516 msleep(1);
517
518 return 0;
519}
520
521/* Check if a DMA mapping address is invalid. */
522static bool b43_dma_mapping_error(struct b43_dmaring *ring,
523 dma_addr_t addr,
524 size_t buffersize, bool dma_to_device)
525{
526 if (unlikely(dma_mapping_error(ring->dev->dev->dma_dev, addr)))
527 return 1;
528
529 switch (ring->type) {
530 case B43_DMA_30BIT:
531 if ((u64)addr + buffersize > (1ULL << 30))
532 goto address_error;
533 break;
534 case B43_DMA_32BIT:
535 if ((u64)addr + buffersize > (1ULL << 32))
536 goto address_error;
537 break;
538 case B43_DMA_64BIT:
539 /* Currently we can't have addresses beyond
540 * 64bit in the kernel. */
541 break;
542 }
543
544 /* The address is OK. */
545 return 0;
546
547address_error:
548 /* We can't support this address. Unmap it again. */
549 unmap_descbuffer(ring, addr, buffersize, dma_to_device);
550
551 return 1;
552}
553
554static bool b43_rx_buffer_is_poisoned(struct b43_dmaring *ring, struct sk_buff *skb)
555{
556 unsigned char *f = skb->data + ring->frameoffset;
557
558 return ((f[0] & f[1] & f[2] & f[3] & f[4] & f[5] & f[6] & f[7]) == 0xFF);
559}
560
561static void b43_poison_rx_buffer(struct b43_dmaring *ring, struct sk_buff *skb)
562{
563 struct b43_rxhdr_fw4 *rxhdr;
564 unsigned char *frame;
565
566 /* This poisons the RX buffer to detect DMA failures. */
567
568 rxhdr = (struct b43_rxhdr_fw4 *)(skb->data);
569 rxhdr->frame_len = 0;
570
571 B43_WARN_ON(ring->rx_buffersize < ring->frameoffset + sizeof(struct b43_plcp_hdr6) + 2);
572 frame = skb->data + ring->frameoffset;
573 memset(frame, 0xFF, sizeof(struct b43_plcp_hdr6) + 2 /* padding */);
574}
575
576static int setup_rx_descbuffer(struct b43_dmaring *ring,
577 struct b43_dmadesc_generic *desc,
578 struct b43_dmadesc_meta *meta, gfp_t gfp_flags)
579{
580 dma_addr_t dmaaddr;
581 struct sk_buff *skb;
582
583 B43_WARN_ON(ring->tx);
584
585 skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
586 if (unlikely(!skb))
587 return -ENOMEM;
588 b43_poison_rx_buffer(ring, skb);
589 dmaaddr = map_descbuffer(ring, skb->data, ring->rx_buffersize, 0);
590 if (b43_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) {
591 /* ugh. try to realloc in zone_dma */
592 gfp_flags |= GFP_DMA;
593
594 dev_kfree_skb_any(skb);
595
596 skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
597 if (unlikely(!skb))
598 return -ENOMEM;
599 b43_poison_rx_buffer(ring, skb);
600 dmaaddr = map_descbuffer(ring, skb->data,
601 ring->rx_buffersize, 0);
602 if (b43_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) {
603 b43err(ring->dev->wl, "RX DMA buffer allocation failed\n");
604 dev_kfree_skb_any(skb);
605 return -EIO;
606 }
607 }
608
609 meta->skb = skb;
610 meta->dmaaddr = dmaaddr;
611 ring->ops->fill_descriptor(ring, desc, dmaaddr,
612 ring->rx_buffersize, 0, 0, 0);
613
614 return 0;
615}
616
617/* Allocate the initial descbuffers.
618 * This is used for an RX ring only.
619 */
620static int alloc_initial_descbuffers(struct b43_dmaring *ring)
621{
622 int i, err = -ENOMEM;
623 struct b43_dmadesc_generic *desc;
624 struct b43_dmadesc_meta *meta;
625
626 for (i = 0; i < ring->nr_slots; i++) {
627 desc = ring->ops->idx2desc(ring, i, &meta);
628
629 err = setup_rx_descbuffer(ring, desc, meta, GFP_KERNEL);
630 if (err) {
631 b43err(ring->dev->wl,
632 "Failed to allocate initial descbuffers\n");
633 goto err_unwind;
634 }
635 }
636 mb();
637 ring->used_slots = ring->nr_slots;
638 err = 0;
639 out:
640 return err;
641
642 err_unwind:
643 for (i--; i >= 0; i--) {
644 desc = ring->ops->idx2desc(ring, i, &meta);
645
646 unmap_descbuffer(ring, meta->dmaaddr, ring->rx_buffersize, 0);
647 dev_kfree_skb(meta->skb);
648 }
649 goto out;
650}
651
652/* Do initial setup of the DMA controller.
653 * Reset the controller, write the ring busaddress
654 * and switch the "enable" bit on.
655 */
656static int dmacontroller_setup(struct b43_dmaring *ring)
657{
658 int err = 0;
659 u32 value;
660 u32 addrext;
661 u32 trans = ring->dev->dma.translation;
662 bool parity = ring->dev->dma.parity;
663
664 if (ring->tx) {
665 if (ring->type == B43_DMA_64BIT) {
666 u64 ringbase = (u64) (ring->dmabase);
667
668 addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK)
669 >> SSB_DMA_TRANSLATION_SHIFT;
670 value = B43_DMA64_TXENABLE;
671 value |= (addrext << B43_DMA64_TXADDREXT_SHIFT)
672 & B43_DMA64_TXADDREXT_MASK;
673 if (!parity)
674 value |= B43_DMA64_TXPARITYDISABLE;
675 b43_dma_write(ring, B43_DMA64_TXCTL, value);
676 b43_dma_write(ring, B43_DMA64_TXRINGLO,
677 (ringbase & 0xFFFFFFFF));
678 b43_dma_write(ring, B43_DMA64_TXRINGHI,
679 ((ringbase >> 32) &
680 ~SSB_DMA_TRANSLATION_MASK)
681 | trans);
682 } else {
683 u32 ringbase = (u32) (ring->dmabase);
684
685 addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
686 >> SSB_DMA_TRANSLATION_SHIFT;
687 value = B43_DMA32_TXENABLE;
688 value |= (addrext << B43_DMA32_TXADDREXT_SHIFT)
689 & B43_DMA32_TXADDREXT_MASK;
690 if (!parity)
691 value |= B43_DMA32_TXPARITYDISABLE;
692 b43_dma_write(ring, B43_DMA32_TXCTL, value);
693 b43_dma_write(ring, B43_DMA32_TXRING,
694 (ringbase & ~SSB_DMA_TRANSLATION_MASK)
695 | trans);
696 }
697 } else {
698 err = alloc_initial_descbuffers(ring);
699 if (err)
700 goto out;
701 if (ring->type == B43_DMA_64BIT) {
702 u64 ringbase = (u64) (ring->dmabase);
703
704 addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK)
705 >> SSB_DMA_TRANSLATION_SHIFT;
706 value = (ring->frameoffset << B43_DMA64_RXFROFF_SHIFT);
707 value |= B43_DMA64_RXENABLE;
708 value |= (addrext << B43_DMA64_RXADDREXT_SHIFT)
709 & B43_DMA64_RXADDREXT_MASK;
710 if (!parity)
711 value |= B43_DMA64_RXPARITYDISABLE;
712 b43_dma_write(ring, B43_DMA64_RXCTL, value);
713 b43_dma_write(ring, B43_DMA64_RXRINGLO,
714 (ringbase & 0xFFFFFFFF));
715 b43_dma_write(ring, B43_DMA64_RXRINGHI,
716 ((ringbase >> 32) &
717 ~SSB_DMA_TRANSLATION_MASK)
718 | trans);
719 b43_dma_write(ring, B43_DMA64_RXINDEX, ring->nr_slots *
720 sizeof(struct b43_dmadesc64));
721 } else {
722 u32 ringbase = (u32) (ring->dmabase);
723
724 addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
725 >> SSB_DMA_TRANSLATION_SHIFT;
726 value = (ring->frameoffset << B43_DMA32_RXFROFF_SHIFT);
727 value |= B43_DMA32_RXENABLE;
728 value |= (addrext << B43_DMA32_RXADDREXT_SHIFT)
729 & B43_DMA32_RXADDREXT_MASK;
730 if (!parity)
731 value |= B43_DMA32_RXPARITYDISABLE;
732 b43_dma_write(ring, B43_DMA32_RXCTL, value);
733 b43_dma_write(ring, B43_DMA32_RXRING,
734 (ringbase & ~SSB_DMA_TRANSLATION_MASK)
735 | trans);
736 b43_dma_write(ring, B43_DMA32_RXINDEX, ring->nr_slots *
737 sizeof(struct b43_dmadesc32));
738 }
739 }
740
741out:
742 return err;
743}
744
745/* Shutdown the DMA controller. */
746static void dmacontroller_cleanup(struct b43_dmaring *ring)
747{
748 if (ring->tx) {
749 b43_dmacontroller_tx_reset(ring->dev, ring->mmio_base,
750 ring->type);
751 if (ring->type == B43_DMA_64BIT) {
752 b43_dma_write(ring, B43_DMA64_TXRINGLO, 0);
753 b43_dma_write(ring, B43_DMA64_TXRINGHI, 0);
754 } else
755 b43_dma_write(ring, B43_DMA32_TXRING, 0);
756 } else {
757 b43_dmacontroller_rx_reset(ring->dev, ring->mmio_base,
758 ring->type);
759 if (ring->type == B43_DMA_64BIT) {
760 b43_dma_write(ring, B43_DMA64_RXRINGLO, 0);
761 b43_dma_write(ring, B43_DMA64_RXRINGHI, 0);
762 } else
763 b43_dma_write(ring, B43_DMA32_RXRING, 0);
764 }
765}
766
767static void free_all_descbuffers(struct b43_dmaring *ring)
768{
769 struct b43_dmadesc_meta *meta;
770 int i;
771
772 if (!ring->used_slots)
773 return;
774 for (i = 0; i < ring->nr_slots; i++) {
775 /* get meta - ignore returned value */
776 ring->ops->idx2desc(ring, i, &meta);
777
778 if (!meta->skb || b43_dma_ptr_is_poisoned(meta->skb)) {
779 B43_WARN_ON(!ring->tx);
780 continue;
781 }
782 if (ring->tx) {
783 unmap_descbuffer(ring, meta->dmaaddr,
784 meta->skb->len, 1);
785 } else {
786 unmap_descbuffer(ring, meta->dmaaddr,
787 ring->rx_buffersize, 0);
788 }
789 free_descriptor_buffer(ring, meta);
790 }
791}
792
793static u64 supported_dma_mask(struct b43_wldev *dev)
794{
795 u32 tmp;
796 u16 mmio_base;
797
798 switch (dev->dev->bus_type) {
799#ifdef CONFIG_B43_BCMA
800 case B43_BUS_BCMA:
801 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOST);
802 if (tmp & BCMA_IOST_DMA64)
803 return DMA_BIT_MASK(64);
804 break;
805#endif
806#ifdef CONFIG_B43_SSB
807 case B43_BUS_SSB:
808 tmp = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
809 if (tmp & SSB_TMSHIGH_DMA64)
810 return DMA_BIT_MASK(64);
811 break;
812#endif
813 }
814
815 mmio_base = b43_dmacontroller_base(0, 0);
816 b43_write32(dev, mmio_base + B43_DMA32_TXCTL, B43_DMA32_TXADDREXT_MASK);
817 tmp = b43_read32(dev, mmio_base + B43_DMA32_TXCTL);
818 if (tmp & B43_DMA32_TXADDREXT_MASK)
819 return DMA_BIT_MASK(32);
820
821 return DMA_BIT_MASK(30);
822}
823
824static enum b43_dmatype dma_mask_to_engine_type(u64 dmamask)
825{
826 if (dmamask == DMA_BIT_MASK(30))
827 return B43_DMA_30BIT;
828 if (dmamask == DMA_BIT_MASK(32))
829 return B43_DMA_32BIT;
830 if (dmamask == DMA_BIT_MASK(64))
831 return B43_DMA_64BIT;
832 B43_WARN_ON(1);
833 return B43_DMA_30BIT;
834}
835
836/* Main initialization function. */
837static
838struct b43_dmaring *b43_setup_dmaring(struct b43_wldev *dev,
839 int controller_index,
840 int for_tx,
841 enum b43_dmatype type)
842{
843 struct b43_dmaring *ring;
844 int i, err;
845 dma_addr_t dma_test;
846
847 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
848 if (!ring)
849 goto out;
850
851 ring->nr_slots = B43_RXRING_SLOTS;
852 if (for_tx)
853 ring->nr_slots = B43_TXRING_SLOTS;
854
855 ring->meta = kcalloc(ring->nr_slots, sizeof(struct b43_dmadesc_meta),
856 GFP_KERNEL);
857 if (!ring->meta)
858 goto err_kfree_ring;
859 for (i = 0; i < ring->nr_slots; i++)
860 ring->meta->skb = B43_DMA_PTR_POISON;
861
862 ring->type = type;
863 ring->dev = dev;
864 ring->mmio_base = b43_dmacontroller_base(type, controller_index);
865 ring->index = controller_index;
866 if (type == B43_DMA_64BIT)
867 ring->ops = &dma64_ops;
868 else
869 ring->ops = &dma32_ops;
870 if (for_tx) {
871 ring->tx = 1;
872 ring->current_slot = -1;
873 } else {
874 if (ring->index == 0) {
875 ring->rx_buffersize = B43_DMA0_RX_BUFFERSIZE;
876 ring->frameoffset = B43_DMA0_RX_FRAMEOFFSET;
877 } else
878 B43_WARN_ON(1);
879 }
880#ifdef CONFIG_B43_DEBUG
881 ring->last_injected_overflow = jiffies;
882#endif
883
884 if (for_tx) {
885 /* Assumption: B43_TXRING_SLOTS can be divided by TX_SLOTS_PER_FRAME */
886 BUILD_BUG_ON(B43_TXRING_SLOTS % TX_SLOTS_PER_FRAME != 0);
887
888 ring->txhdr_cache = kcalloc(ring->nr_slots / TX_SLOTS_PER_FRAME,
889 b43_txhdr_size(dev),
890 GFP_KERNEL);
891 if (!ring->txhdr_cache)
892 goto err_kfree_meta;
893
894 /* test for ability to dma to txhdr_cache */
895 dma_test = dma_map_single(dev->dev->dma_dev,
896 ring->txhdr_cache,
897 b43_txhdr_size(dev),
898 DMA_TO_DEVICE);
899
900 if (b43_dma_mapping_error(ring, dma_test,
901 b43_txhdr_size(dev), 1)) {
902 /* ugh realloc */
903 kfree(ring->txhdr_cache);
904 ring->txhdr_cache = kcalloc(ring->nr_slots / TX_SLOTS_PER_FRAME,
905 b43_txhdr_size(dev),
906 GFP_KERNEL | GFP_DMA);
907 if (!ring->txhdr_cache)
908 goto err_kfree_meta;
909
910 dma_test = dma_map_single(dev->dev->dma_dev,
911 ring->txhdr_cache,
912 b43_txhdr_size(dev),
913 DMA_TO_DEVICE);
914
915 if (b43_dma_mapping_error(ring, dma_test,
916 b43_txhdr_size(dev), 1)) {
917
918 b43err(dev->wl,
919 "TXHDR DMA allocation failed\n");
920 goto err_kfree_txhdr_cache;
921 }
922 }
923
924 dma_unmap_single(dev->dev->dma_dev,
925 dma_test, b43_txhdr_size(dev),
926 DMA_TO_DEVICE);
927 }
928
929 err = alloc_ringmemory(ring);
930 if (err)
931 goto err_kfree_txhdr_cache;
932 err = dmacontroller_setup(ring);
933 if (err)
934 goto err_free_ringmemory;
935
936 out:
937 return ring;
938
939 err_free_ringmemory:
940 free_ringmemory(ring);
941 err_kfree_txhdr_cache:
942 kfree(ring->txhdr_cache);
943 err_kfree_meta:
944 kfree(ring->meta);
945 err_kfree_ring:
946 kfree(ring);
947 ring = NULL;
948 goto out;
949}
950
951#define divide(a, b) ({ \
952 typeof(a) __a = a; \
953 do_div(__a, b); \
954 __a; \
955 })
956
957#define modulo(a, b) ({ \
958 typeof(a) __a = a; \
959 do_div(__a, b); \
960 })
961
962/* Main cleanup function. */
963static void b43_destroy_dmaring(struct b43_dmaring *ring,
964 const char *ringname)
965{
966 if (!ring)
967 return;
968
969#ifdef CONFIG_B43_DEBUG
970 {
971 /* Print some statistics. */
972 u64 failed_packets = ring->nr_failed_tx_packets;
973 u64 succeed_packets = ring->nr_succeed_tx_packets;
974 u64 nr_packets = failed_packets + succeed_packets;
975 u64 permille_failed = 0, average_tries = 0;
976
977 if (nr_packets)
978 permille_failed = divide(failed_packets * 1000, nr_packets);
979 if (nr_packets)
980 average_tries = divide(ring->nr_total_packet_tries * 100, nr_packets);
981
982 b43dbg(ring->dev->wl, "DMA-%u %s: "
983 "Used slots %d/%d, Failed frames %llu/%llu = %llu.%01llu%%, "
984 "Average tries %llu.%02llu\n",
985 (unsigned int)(ring->type), ringname,
986 ring->max_used_slots,
987 ring->nr_slots,
988 (unsigned long long)failed_packets,
989 (unsigned long long)nr_packets,
990 (unsigned long long)divide(permille_failed, 10),
991 (unsigned long long)modulo(permille_failed, 10),
992 (unsigned long long)divide(average_tries, 100),
993 (unsigned long long)modulo(average_tries, 100));
994 }
995#endif /* DEBUG */
996
997 /* Device IRQs are disabled prior entering this function,
998 * so no need to take care of concurrency with rx handler stuff.
999 */
1000 dmacontroller_cleanup(ring);
1001 free_all_descbuffers(ring);
1002 free_ringmemory(ring);
1003
1004 kfree(ring->txhdr_cache);
1005 kfree(ring->meta);
1006 kfree(ring);
1007}
1008
1009#define destroy_ring(dma, ring) do { \
1010 b43_destroy_dmaring((dma)->ring, __stringify(ring)); \
1011 (dma)->ring = NULL; \
1012 } while (0)
1013
1014void b43_dma_free(struct b43_wldev *dev)
1015{
1016 struct b43_dma *dma;
1017
1018 if (b43_using_pio_transfers(dev))
1019 return;
1020 dma = &dev->dma;
1021
1022 destroy_ring(dma, rx_ring);
1023 destroy_ring(dma, tx_ring_AC_BK);
1024 destroy_ring(dma, tx_ring_AC_BE);
1025 destroy_ring(dma, tx_ring_AC_VI);
1026 destroy_ring(dma, tx_ring_AC_VO);
1027 destroy_ring(dma, tx_ring_mcast);
1028}
1029
1030static int b43_dma_set_mask(struct b43_wldev *dev, u64 mask)
1031{
1032 u64 orig_mask = mask;
1033 bool fallback = 0;
1034 int err;
1035
1036 /* Try to set the DMA mask. If it fails, try falling back to a
1037 * lower mask, as we can always also support a lower one. */
1038 while (1) {
1039 err = dma_set_mask(dev->dev->dma_dev, mask);
1040 if (!err) {
1041 err = dma_set_coherent_mask(dev->dev->dma_dev, mask);
1042 if (!err)
1043 break;
1044 }
1045 if (mask == DMA_BIT_MASK(64)) {
1046 mask = DMA_BIT_MASK(32);
1047 fallback = 1;
1048 continue;
1049 }
1050 if (mask == DMA_BIT_MASK(32)) {
1051 mask = DMA_BIT_MASK(30);
1052 fallback = 1;
1053 continue;
1054 }
1055 b43err(dev->wl, "The machine/kernel does not support "
1056 "the required %u-bit DMA mask\n",
1057 (unsigned int)dma_mask_to_engine_type(orig_mask));
1058 return -EOPNOTSUPP;
1059 }
1060 if (fallback) {
1061 b43info(dev->wl, "DMA mask fallback from %u-bit to %u-bit\n",
1062 (unsigned int)dma_mask_to_engine_type(orig_mask),
1063 (unsigned int)dma_mask_to_engine_type(mask));
1064 }
1065
1066 return 0;
1067}
1068
1069int b43_dma_init(struct b43_wldev *dev)
1070{
1071 struct b43_dma *dma = &dev->dma;
1072 int err;
1073 u64 dmamask;
1074 enum b43_dmatype type;
1075
1076 dmamask = supported_dma_mask(dev);
1077 type = dma_mask_to_engine_type(dmamask);
1078 err = b43_dma_set_mask(dev, dmamask);
1079 if (err)
1080 return err;
1081
1082 switch (dev->dev->bus_type) {
1083#ifdef CONFIG_B43_BCMA
1084 case B43_BUS_BCMA:
1085 dma->translation = bcma_core_dma_translation(dev->dev->bdev);
1086 break;
1087#endif
1088#ifdef CONFIG_B43_SSB
1089 case B43_BUS_SSB:
1090 dma->translation = ssb_dma_translation(dev->dev->sdev);
1091 break;
1092#endif
1093 }
1094
1095 dma->parity = true;
1096#ifdef CONFIG_B43_BCMA
1097 /* TODO: find out which SSB devices need disabling parity */
1098 if (dev->dev->bus_type == B43_BUS_BCMA)
1099 dma->parity = false;
1100#endif
1101
1102 err = -ENOMEM;
1103 /* setup TX DMA channels. */
1104 dma->tx_ring_AC_BK = b43_setup_dmaring(dev, 0, 1, type);
1105 if (!dma->tx_ring_AC_BK)
1106 goto out;
1107
1108 dma->tx_ring_AC_BE = b43_setup_dmaring(dev, 1, 1, type);
1109 if (!dma->tx_ring_AC_BE)
1110 goto err_destroy_bk;
1111
1112 dma->tx_ring_AC_VI = b43_setup_dmaring(dev, 2, 1, type);
1113 if (!dma->tx_ring_AC_VI)
1114 goto err_destroy_be;
1115
1116 dma->tx_ring_AC_VO = b43_setup_dmaring(dev, 3, 1, type);
1117 if (!dma->tx_ring_AC_VO)
1118 goto err_destroy_vi;
1119
1120 dma->tx_ring_mcast = b43_setup_dmaring(dev, 4, 1, type);
1121 if (!dma->tx_ring_mcast)
1122 goto err_destroy_vo;
1123
1124 /* setup RX DMA channel. */
1125 dma->rx_ring = b43_setup_dmaring(dev, 0, 0, type);
1126 if (!dma->rx_ring)
1127 goto err_destroy_mcast;
1128
1129 /* No support for the TX status DMA ring. */
1130 B43_WARN_ON(dev->dev->core_rev < 5);
1131
1132 b43dbg(dev->wl, "%u-bit DMA initialized\n",
1133 (unsigned int)type);
1134 err = 0;
1135out:
1136 return err;
1137
1138err_destroy_mcast:
1139 destroy_ring(dma, tx_ring_mcast);
1140err_destroy_vo:
1141 destroy_ring(dma, tx_ring_AC_VO);
1142err_destroy_vi:
1143 destroy_ring(dma, tx_ring_AC_VI);
1144err_destroy_be:
1145 destroy_ring(dma, tx_ring_AC_BE);
1146err_destroy_bk:
1147 destroy_ring(dma, tx_ring_AC_BK);
1148 return err;
1149}
1150
1151/* Generate a cookie for the TX header. */
1152static u16 generate_cookie(struct b43_dmaring *ring, int slot)
1153{
1154 u16 cookie;
1155
1156 /* Use the upper 4 bits of the cookie as
1157 * DMA controller ID and store the slot number
1158 * in the lower 12 bits.
1159 * Note that the cookie must never be 0, as this
1160 * is a special value used in RX path.
1161 * It can also not be 0xFFFF because that is special
1162 * for multicast frames.
1163 */
1164 cookie = (((u16)ring->index + 1) << 12);
1165 B43_WARN_ON(slot & ~0x0FFF);
1166 cookie |= (u16)slot;
1167
1168 return cookie;
1169}
1170
1171/* Inspect a cookie and find out to which controller/slot it belongs. */
1172static
1173struct b43_dmaring *parse_cookie(struct b43_wldev *dev, u16 cookie, int *slot)
1174{
1175 struct b43_dma *dma = &dev->dma;
1176 struct b43_dmaring *ring = NULL;
1177
1178 switch (cookie & 0xF000) {
1179 case 0x1000:
1180 ring = dma->tx_ring_AC_BK;
1181 break;
1182 case 0x2000:
1183 ring = dma->tx_ring_AC_BE;
1184 break;
1185 case 0x3000:
1186 ring = dma->tx_ring_AC_VI;
1187 break;
1188 case 0x4000:
1189 ring = dma->tx_ring_AC_VO;
1190 break;
1191 case 0x5000:
1192 ring = dma->tx_ring_mcast;
1193 break;
1194 }
1195 *slot = (cookie & 0x0FFF);
1196 if (unlikely(!ring || *slot < 0 || *slot >= ring->nr_slots)) {
1197 b43dbg(dev->wl, "TX-status contains "
1198 "invalid cookie: 0x%04X\n", cookie);
1199 return NULL;
1200 }
1201
1202 return ring;
1203}
1204
1205static int dma_tx_fragment(struct b43_dmaring *ring,
1206 struct sk_buff *skb)
1207{
1208 const struct b43_dma_ops *ops = ring->ops;
1209 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1210 struct b43_private_tx_info *priv_info = b43_get_priv_tx_info(info);
1211 u8 *header;
1212 int slot, old_top_slot, old_used_slots;
1213 int err;
1214 struct b43_dmadesc_generic *desc;
1215 struct b43_dmadesc_meta *meta;
1216 struct b43_dmadesc_meta *meta_hdr;
1217 u16 cookie;
1218 size_t hdrsize = b43_txhdr_size(ring->dev);
1219
1220 /* Important note: If the number of used DMA slots per TX frame
1221 * is changed here, the TX_SLOTS_PER_FRAME definition at the top of
1222 * the file has to be updated, too!
1223 */
1224
1225 old_top_slot = ring->current_slot;
1226 old_used_slots = ring->used_slots;
1227
1228 /* Get a slot for the header. */
1229 slot = request_slot(ring);
1230 desc = ops->idx2desc(ring, slot, &meta_hdr);
1231 memset(meta_hdr, 0, sizeof(*meta_hdr));
1232
1233 header = &(ring->txhdr_cache[(slot / TX_SLOTS_PER_FRAME) * hdrsize]);
1234 cookie = generate_cookie(ring, slot);
1235 err = b43_generate_txhdr(ring->dev, header,
1236 skb, info, cookie);
1237 if (unlikely(err)) {
1238 ring->current_slot = old_top_slot;
1239 ring->used_slots = old_used_slots;
1240 return err;
1241 }
1242
1243 meta_hdr->dmaaddr = map_descbuffer(ring, (unsigned char *)header,
1244 hdrsize, 1);
1245 if (b43_dma_mapping_error(ring, meta_hdr->dmaaddr, hdrsize, 1)) {
1246 ring->current_slot = old_top_slot;
1247 ring->used_slots = old_used_slots;
1248 return -EIO;
1249 }
1250 ops->fill_descriptor(ring, desc, meta_hdr->dmaaddr,
1251 hdrsize, 1, 0, 0);
1252
1253 /* Get a slot for the payload. */
1254 slot = request_slot(ring);
1255 desc = ops->idx2desc(ring, slot, &meta);
1256 memset(meta, 0, sizeof(*meta));
1257
1258 meta->skb = skb;
1259 meta->is_last_fragment = 1;
1260 priv_info->bouncebuffer = NULL;
1261
1262 meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
1263 /* create a bounce buffer in zone_dma on mapping failure. */
1264 if (b43_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) {
1265 priv_info->bouncebuffer = kmemdup(skb->data, skb->len,
1266 GFP_ATOMIC | GFP_DMA);
1267 if (!priv_info->bouncebuffer) {
1268 ring->current_slot = old_top_slot;
1269 ring->used_slots = old_used_slots;
1270 err = -ENOMEM;
1271 goto out_unmap_hdr;
1272 }
1273
1274 meta->dmaaddr = map_descbuffer(ring, priv_info->bouncebuffer, skb->len, 1);
1275 if (b43_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) {
1276 kfree(priv_info->bouncebuffer);
1277 priv_info->bouncebuffer = NULL;
1278 ring->current_slot = old_top_slot;
1279 ring->used_slots = old_used_slots;
1280 err = -EIO;
1281 goto out_unmap_hdr;
1282 }
1283 }
1284
1285 ops->fill_descriptor(ring, desc, meta->dmaaddr, skb->len, 0, 1, 1);
1286
1287 if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
1288 /* Tell the firmware about the cookie of the last
1289 * mcast frame, so it can clear the more-data bit in it. */
1290 b43_shm_write16(ring->dev, B43_SHM_SHARED,
1291 B43_SHM_SH_MCASTCOOKIE, cookie);
1292 }
1293 /* Now transfer the whole frame. */
1294 wmb();
1295 ops->poke_tx(ring, next_slot(ring, slot));
1296 return 0;
1297
1298out_unmap_hdr:
1299 unmap_descbuffer(ring, meta_hdr->dmaaddr,
1300 hdrsize, 1);
1301 return err;
1302}
1303
1304static inline int should_inject_overflow(struct b43_dmaring *ring)
1305{
1306#ifdef CONFIG_B43_DEBUG
1307 if (unlikely(b43_debug(ring->dev, B43_DBG_DMAOVERFLOW))) {
1308 /* Check if we should inject another ringbuffer overflow
1309 * to test handling of this situation in the stack. */
1310 unsigned long next_overflow;
1311
1312 next_overflow = ring->last_injected_overflow + HZ;
1313 if (time_after(jiffies, next_overflow)) {
1314 ring->last_injected_overflow = jiffies;
1315 b43dbg(ring->dev->wl,
1316 "Injecting TX ring overflow on "
1317 "DMA controller %d\n", ring->index);
1318 return 1;
1319 }
1320 }
1321#endif /* CONFIG_B43_DEBUG */
1322 return 0;
1323}
1324
1325/* Static mapping of mac80211's queues (priorities) to b43 DMA rings. */
1326static struct b43_dmaring *select_ring_by_priority(struct b43_wldev *dev,
1327 u8 queue_prio)
1328{
1329 struct b43_dmaring *ring;
1330
1331 if (dev->qos_enabled) {
1332 /* 0 = highest priority */
1333 switch (queue_prio) {
1334 default:
1335 B43_WARN_ON(1);
1336 /* fallthrough */
1337 case 0:
1338 ring = dev->dma.tx_ring_AC_VO;
1339 break;
1340 case 1:
1341 ring = dev->dma.tx_ring_AC_VI;
1342 break;
1343 case 2:
1344 ring = dev->dma.tx_ring_AC_BE;
1345 break;
1346 case 3:
1347 ring = dev->dma.tx_ring_AC_BK;
1348 break;
1349 }
1350 } else
1351 ring = dev->dma.tx_ring_AC_BE;
1352
1353 return ring;
1354}
1355
1356int b43_dma_tx(struct b43_wldev *dev, struct sk_buff *skb)
1357{
1358 struct b43_dmaring *ring;
1359 struct ieee80211_hdr *hdr;
1360 int err = 0;
1361 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1362
1363 hdr = (struct ieee80211_hdr *)skb->data;
1364 if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
1365 /* The multicast ring will be sent after the DTIM */
1366 ring = dev->dma.tx_ring_mcast;
1367 /* Set the more-data bit. Ucode will clear it on
1368 * the last frame for us. */
1369 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_MOREDATA);
1370 } else {
1371 /* Decide by priority where to put this frame. */
1372 ring = select_ring_by_priority(
1373 dev, skb_get_queue_mapping(skb));
1374 }
1375
1376 B43_WARN_ON(!ring->tx);
1377
1378 if (unlikely(ring->stopped)) {
1379 /* We get here only because of a bug in mac80211.
1380 * Because of a race, one packet may be queued after
1381 * the queue is stopped, thus we got called when we shouldn't.
1382 * For now, just refuse the transmit. */
1383 if (b43_debug(dev, B43_DBG_DMAVERBOSE))
1384 b43err(dev->wl, "Packet after queue stopped\n");
1385 err = -ENOSPC;
1386 goto out;
1387 }
1388
1389 if (unlikely(WARN_ON(free_slots(ring) < TX_SLOTS_PER_FRAME))) {
1390 /* If we get here, we have a real error with the queue
1391 * full, but queues not stopped. */
1392 b43err(dev->wl, "DMA queue overflow\n");
1393 err = -ENOSPC;
1394 goto out;
1395 }
1396
1397 /* Assign the queue number to the ring (if not already done before)
1398 * so TX status handling can use it. The queue to ring mapping is
1399 * static, so we don't need to store it per frame. */
1400 ring->queue_prio = skb_get_queue_mapping(skb);
1401
1402 err = dma_tx_fragment(ring, skb);
1403 if (unlikely(err == -ENOKEY)) {
1404 /* Drop this packet, as we don't have the encryption key
1405 * anymore and must not transmit it unencrypted. */
1406 dev_kfree_skb_any(skb);
1407 err = 0;
1408 goto out;
1409 }
1410 if (unlikely(err)) {
1411 b43err(dev->wl, "DMA tx mapping failure\n");
1412 goto out;
1413 }
1414 if ((free_slots(ring) < TX_SLOTS_PER_FRAME) ||
1415 should_inject_overflow(ring)) {
1416 /* This TX ring is full. */
1417 ieee80211_stop_queue(dev->wl->hw, skb_get_queue_mapping(skb));
1418 ring->stopped = 1;
1419 if (b43_debug(dev, B43_DBG_DMAVERBOSE)) {
1420 b43dbg(dev->wl, "Stopped TX ring %d\n", ring->index);
1421 }
1422 }
1423out:
1424
1425 return err;
1426}
1427
1428void b43_dma_handle_txstatus(struct b43_wldev *dev,
1429 const struct b43_txstatus *status)
1430{
1431 const struct b43_dma_ops *ops;
1432 struct b43_dmaring *ring;
1433 struct b43_dmadesc_meta *meta;
1434 int slot, firstused;
1435 bool frame_succeed;
1436
1437 ring = parse_cookie(dev, status->cookie, &slot);
1438 if (unlikely(!ring))
1439 return;
1440 B43_WARN_ON(!ring->tx);
1441
1442 /* Sanity check: TX packets are processed in-order on one ring.
1443 * Check if the slot deduced from the cookie really is the first
1444 * used slot. */
1445 firstused = ring->current_slot - ring->used_slots + 1;
1446 if (firstused < 0)
1447 firstused = ring->nr_slots + firstused;
1448 if (unlikely(slot != firstused)) {
1449 /* This possibly is a firmware bug and will result in
1450 * malfunction, memory leaks and/or stall of DMA functionality. */
1451 b43dbg(dev->wl, "Out of order TX status report on DMA ring %d. "
1452 "Expected %d, but got %d\n",
1453 ring->index, firstused, slot);
1454 return;
1455 }
1456
1457 ops = ring->ops;
1458 while (1) {
1459 B43_WARN_ON(slot < 0 || slot >= ring->nr_slots);
1460 /* get meta - ignore returned value */
1461 ops->idx2desc(ring, slot, &meta);
1462
1463 if (b43_dma_ptr_is_poisoned(meta->skb)) {
1464 b43dbg(dev->wl, "Poisoned TX slot %d (first=%d) "
1465 "on ring %d\n",
1466 slot, firstused, ring->index);
1467 break;
1468 }
1469 if (meta->skb) {
1470 struct b43_private_tx_info *priv_info =
1471 b43_get_priv_tx_info(IEEE80211_SKB_CB(meta->skb));
1472
1473 unmap_descbuffer(ring, meta->dmaaddr, meta->skb->len, 1);
1474 kfree(priv_info->bouncebuffer);
1475 priv_info->bouncebuffer = NULL;
1476 } else {
1477 unmap_descbuffer(ring, meta->dmaaddr,
1478 b43_txhdr_size(dev), 1);
1479 }
1480
1481 if (meta->is_last_fragment) {
1482 struct ieee80211_tx_info *info;
1483
1484 if (unlikely(!meta->skb)) {
1485 /* This is a scatter-gather fragment of a frame, so
1486 * the skb pointer must not be NULL. */
1487 b43dbg(dev->wl, "TX status unexpected NULL skb "
1488 "at slot %d (first=%d) on ring %d\n",
1489 slot, firstused, ring->index);
1490 break;
1491 }
1492
1493 info = IEEE80211_SKB_CB(meta->skb);
1494
1495 /*
1496 * Call back to inform the ieee80211 subsystem about
1497 * the status of the transmission.
1498 */
1499 frame_succeed = b43_fill_txstatus_report(dev, info, status);
1500#ifdef CONFIG_B43_DEBUG
1501 if (frame_succeed)
1502 ring->nr_succeed_tx_packets++;
1503 else
1504 ring->nr_failed_tx_packets++;
1505 ring->nr_total_packet_tries += status->frame_count;
1506#endif /* DEBUG */
1507 ieee80211_tx_status(dev->wl->hw, meta->skb);
1508
1509 /* skb will be freed by ieee80211_tx_status().
1510 * Poison our pointer. */
1511 meta->skb = B43_DMA_PTR_POISON;
1512 } else {
1513 /* No need to call free_descriptor_buffer here, as
1514 * this is only the txhdr, which is not allocated.
1515 */
1516 if (unlikely(meta->skb)) {
1517 b43dbg(dev->wl, "TX status unexpected non-NULL skb "
1518 "at slot %d (first=%d) on ring %d\n",
1519 slot, firstused, ring->index);
1520 break;
1521 }
1522 }
1523
1524 /* Everything unmapped and free'd. So it's not used anymore. */
1525 ring->used_slots--;
1526
1527 if (meta->is_last_fragment) {
1528 /* This is the last scatter-gather
1529 * fragment of the frame. We are done. */
1530 break;
1531 }
1532 slot = next_slot(ring, slot);
1533 }
1534 if (ring->stopped) {
1535 B43_WARN_ON(free_slots(ring) < TX_SLOTS_PER_FRAME);
1536 ieee80211_wake_queue(dev->wl->hw, ring->queue_prio);
1537 ring->stopped = 0;
1538 if (b43_debug(dev, B43_DBG_DMAVERBOSE)) {
1539 b43dbg(dev->wl, "Woke up TX ring %d\n", ring->index);
1540 }
1541 }
1542}
1543
1544static void dma_rx(struct b43_dmaring *ring, int *slot)
1545{
1546 const struct b43_dma_ops *ops = ring->ops;
1547 struct b43_dmadesc_generic *desc;
1548 struct b43_dmadesc_meta *meta;
1549 struct b43_rxhdr_fw4 *rxhdr;
1550 struct sk_buff *skb;
1551 u16 len;
1552 int err;
1553 dma_addr_t dmaaddr;
1554
1555 desc = ops->idx2desc(ring, *slot, &meta);
1556
1557 sync_descbuffer_for_cpu(ring, meta->dmaaddr, ring->rx_buffersize);
1558 skb = meta->skb;
1559
1560 rxhdr = (struct b43_rxhdr_fw4 *)skb->data;
1561 len = le16_to_cpu(rxhdr->frame_len);
1562 if (len == 0) {
1563 int i = 0;
1564
1565 do {
1566 udelay(2);
1567 barrier();
1568 len = le16_to_cpu(rxhdr->frame_len);
1569 } while (len == 0 && i++ < 5);
1570 if (unlikely(len == 0)) {
1571 dmaaddr = meta->dmaaddr;
1572 goto drop_recycle_buffer;
1573 }
1574 }
1575 if (unlikely(b43_rx_buffer_is_poisoned(ring, skb))) {
1576 /* Something went wrong with the DMA.
1577 * The device did not touch the buffer and did not overwrite the poison. */
1578 b43dbg(ring->dev->wl, "DMA RX: Dropping poisoned buffer.\n");
1579 dmaaddr = meta->dmaaddr;
1580 goto drop_recycle_buffer;
1581 }
1582 if (unlikely(len + ring->frameoffset > ring->rx_buffersize)) {
1583 /* The data did not fit into one descriptor buffer
1584 * and is split over multiple buffers.
1585 * This should never happen, as we try to allocate buffers
1586 * big enough. So simply ignore this packet.
1587 */
1588 int cnt = 0;
1589 s32 tmp = len;
1590
1591 while (1) {
1592 desc = ops->idx2desc(ring, *slot, &meta);
1593 /* recycle the descriptor buffer. */
1594 b43_poison_rx_buffer(ring, meta->skb);
1595 sync_descbuffer_for_device(ring, meta->dmaaddr,
1596 ring->rx_buffersize);
1597 *slot = next_slot(ring, *slot);
1598 cnt++;
1599 tmp -= ring->rx_buffersize;
1600 if (tmp <= 0)
1601 break;
1602 }
1603 b43err(ring->dev->wl, "DMA RX buffer too small "
1604 "(len: %u, buffer: %u, nr-dropped: %d)\n",
1605 len, ring->rx_buffersize, cnt);
1606 goto drop;
1607 }
1608
1609 dmaaddr = meta->dmaaddr;
1610 err = setup_rx_descbuffer(ring, desc, meta, GFP_ATOMIC);
1611 if (unlikely(err)) {
1612 b43dbg(ring->dev->wl, "DMA RX: setup_rx_descbuffer() failed\n");
1613 goto drop_recycle_buffer;
1614 }
1615
1616 unmap_descbuffer(ring, dmaaddr, ring->rx_buffersize, 0);
1617 skb_put(skb, len + ring->frameoffset);
1618 skb_pull(skb, ring->frameoffset);
1619
1620 b43_rx(ring->dev, skb, rxhdr);
1621drop:
1622 return;
1623
1624drop_recycle_buffer:
1625 /* Poison and recycle the RX buffer. */
1626 b43_poison_rx_buffer(ring, skb);
1627 sync_descbuffer_for_device(ring, dmaaddr, ring->rx_buffersize);
1628}
1629
1630void b43_dma_rx(struct b43_dmaring *ring)
1631{
1632 const struct b43_dma_ops *ops = ring->ops;
1633 int slot, current_slot;
1634 int used_slots = 0;
1635
1636 B43_WARN_ON(ring->tx);
1637 current_slot = ops->get_current_rxslot(ring);
1638 B43_WARN_ON(!(current_slot >= 0 && current_slot < ring->nr_slots));
1639
1640 slot = ring->current_slot;
1641 for (; slot != current_slot; slot = next_slot(ring, slot)) {
1642 dma_rx(ring, &slot);
1643 update_max_used_slots(ring, ++used_slots);
1644 }
1645 wmb();
1646 ops->set_current_rxslot(ring, slot);
1647 ring->current_slot = slot;
1648}
1649
1650static void b43_dma_tx_suspend_ring(struct b43_dmaring *ring)
1651{
1652 B43_WARN_ON(!ring->tx);
1653 ring->ops->tx_suspend(ring);
1654}
1655
1656static void b43_dma_tx_resume_ring(struct b43_dmaring *ring)
1657{
1658 B43_WARN_ON(!ring->tx);
1659 ring->ops->tx_resume(ring);
1660}
1661
1662void b43_dma_tx_suspend(struct b43_wldev *dev)
1663{
1664 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
1665 b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_BK);
1666 b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_BE);
1667 b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_VI);
1668 b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_VO);
1669 b43_dma_tx_suspend_ring(dev->dma.tx_ring_mcast);
1670}
1671
1672void b43_dma_tx_resume(struct b43_wldev *dev)
1673{
1674 b43_dma_tx_resume_ring(dev->dma.tx_ring_mcast);
1675 b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_VO);
1676 b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_VI);
1677 b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_BE);
1678 b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_BK);
1679 b43_power_saving_ctl_bits(dev, 0);
1680}
1681
1682static void direct_fifo_rx(struct b43_wldev *dev, enum b43_dmatype type,
1683 u16 mmio_base, bool enable)
1684{
1685 u32 ctl;
1686
1687 if (type == B43_DMA_64BIT) {
1688 ctl = b43_read32(dev, mmio_base + B43_DMA64_RXCTL);
1689 ctl &= ~B43_DMA64_RXDIRECTFIFO;
1690 if (enable)
1691 ctl |= B43_DMA64_RXDIRECTFIFO;
1692 b43_write32(dev, mmio_base + B43_DMA64_RXCTL, ctl);
1693 } else {
1694 ctl = b43_read32(dev, mmio_base + B43_DMA32_RXCTL);
1695 ctl &= ~B43_DMA32_RXDIRECTFIFO;
1696 if (enable)
1697 ctl |= B43_DMA32_RXDIRECTFIFO;
1698 b43_write32(dev, mmio_base + B43_DMA32_RXCTL, ctl);
1699 }
1700}
1701
1702/* Enable/Disable Direct FIFO Receive Mode (PIO) on a RX engine.
1703 * This is called from PIO code, so DMA structures are not available. */
1704void b43_dma_direct_fifo_rx(struct b43_wldev *dev,
1705 unsigned int engine_index, bool enable)
1706{
1707 enum b43_dmatype type;
1708 u16 mmio_base;
1709
1710 type = dma_mask_to_engine_type(supported_dma_mask(dev));
1711
1712 mmio_base = b43_dmacontroller_base(type, engine_index);
1713 direct_fifo_rx(dev, type, mmio_base, enable);
1714}
1/*
2
3 Broadcom B43 wireless driver
4
5 DMA ringbuffer and descriptor allocation/management
6
7 Copyright (c) 2005, 2006 Michael Buesch <m@bues.ch>
8
9 Some code in this file is derived from the b44.c driver
10 Copyright (C) 2002 David S. Miller
11 Copyright (C) Pekka Pietikainen
12
13 This program is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2 of the License, or
16 (at your option) any later version.
17
18 This program is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
22
23 You should have received a copy of the GNU General Public License
24 along with this program; see the file COPYING. If not, write to
25 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
26 Boston, MA 02110-1301, USA.
27
28*/
29
30#include "b43.h"
31#include "dma.h"
32#include "main.h"
33#include "debugfs.h"
34#include "xmit.h"
35
36#include <linux/dma-mapping.h>
37#include <linux/pci.h>
38#include <linux/delay.h>
39#include <linux/skbuff.h>
40#include <linux/etherdevice.h>
41#include <linux/slab.h>
42#include <asm/div64.h>
43
44
45/* Required number of TX DMA slots per TX frame.
46 * This currently is 2, because we put the header and the ieee80211 frame
47 * into separate slots. */
48#define TX_SLOTS_PER_FRAME 2
49
50static u32 b43_dma_address(struct b43_dma *dma, dma_addr_t dmaaddr,
51 enum b43_addrtype addrtype)
52{
53 u32 uninitialized_var(addr);
54
55 switch (addrtype) {
56 case B43_DMA_ADDR_LOW:
57 addr = lower_32_bits(dmaaddr);
58 if (dma->translation_in_low) {
59 addr &= ~SSB_DMA_TRANSLATION_MASK;
60 addr |= dma->translation;
61 }
62 break;
63 case B43_DMA_ADDR_HIGH:
64 addr = upper_32_bits(dmaaddr);
65 if (!dma->translation_in_low) {
66 addr &= ~SSB_DMA_TRANSLATION_MASK;
67 addr |= dma->translation;
68 }
69 break;
70 case B43_DMA_ADDR_EXT:
71 if (dma->translation_in_low)
72 addr = lower_32_bits(dmaaddr);
73 else
74 addr = upper_32_bits(dmaaddr);
75 addr &= SSB_DMA_TRANSLATION_MASK;
76 addr >>= SSB_DMA_TRANSLATION_SHIFT;
77 break;
78 }
79
80 return addr;
81}
82
83/* 32bit DMA ops. */
84static
85struct b43_dmadesc_generic *op32_idx2desc(struct b43_dmaring *ring,
86 int slot,
87 struct b43_dmadesc_meta **meta)
88{
89 struct b43_dmadesc32 *desc;
90
91 *meta = &(ring->meta[slot]);
92 desc = ring->descbase;
93 desc = &(desc[slot]);
94
95 return (struct b43_dmadesc_generic *)desc;
96}
97
98static void op32_fill_descriptor(struct b43_dmaring *ring,
99 struct b43_dmadesc_generic *desc,
100 dma_addr_t dmaaddr, u16 bufsize,
101 int start, int end, int irq)
102{
103 struct b43_dmadesc32 *descbase = ring->descbase;
104 int slot;
105 u32 ctl;
106 u32 addr;
107 u32 addrext;
108
109 slot = (int)(&(desc->dma32) - descbase);
110 B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
111
112 addr = b43_dma_address(&ring->dev->dma, dmaaddr, B43_DMA_ADDR_LOW);
113 addrext = b43_dma_address(&ring->dev->dma, dmaaddr, B43_DMA_ADDR_EXT);
114
115 ctl = bufsize & B43_DMA32_DCTL_BYTECNT;
116 if (slot == ring->nr_slots - 1)
117 ctl |= B43_DMA32_DCTL_DTABLEEND;
118 if (start)
119 ctl |= B43_DMA32_DCTL_FRAMESTART;
120 if (end)
121 ctl |= B43_DMA32_DCTL_FRAMEEND;
122 if (irq)
123 ctl |= B43_DMA32_DCTL_IRQ;
124 ctl |= (addrext << B43_DMA32_DCTL_ADDREXT_SHIFT)
125 & B43_DMA32_DCTL_ADDREXT_MASK;
126
127 desc->dma32.control = cpu_to_le32(ctl);
128 desc->dma32.address = cpu_to_le32(addr);
129}
130
131static void op32_poke_tx(struct b43_dmaring *ring, int slot)
132{
133 b43_dma_write(ring, B43_DMA32_TXINDEX,
134 (u32) (slot * sizeof(struct b43_dmadesc32)));
135}
136
137static void op32_tx_suspend(struct b43_dmaring *ring)
138{
139 b43_dma_write(ring, B43_DMA32_TXCTL, b43_dma_read(ring, B43_DMA32_TXCTL)
140 | B43_DMA32_TXSUSPEND);
141}
142
143static void op32_tx_resume(struct b43_dmaring *ring)
144{
145 b43_dma_write(ring, B43_DMA32_TXCTL, b43_dma_read(ring, B43_DMA32_TXCTL)
146 & ~B43_DMA32_TXSUSPEND);
147}
148
149static int op32_get_current_rxslot(struct b43_dmaring *ring)
150{
151 u32 val;
152
153 val = b43_dma_read(ring, B43_DMA32_RXSTATUS);
154 val &= B43_DMA32_RXDPTR;
155
156 return (val / sizeof(struct b43_dmadesc32));
157}
158
159static void op32_set_current_rxslot(struct b43_dmaring *ring, int slot)
160{
161 b43_dma_write(ring, B43_DMA32_RXINDEX,
162 (u32) (slot * sizeof(struct b43_dmadesc32)));
163}
164
165static const struct b43_dma_ops dma32_ops = {
166 .idx2desc = op32_idx2desc,
167 .fill_descriptor = op32_fill_descriptor,
168 .poke_tx = op32_poke_tx,
169 .tx_suspend = op32_tx_suspend,
170 .tx_resume = op32_tx_resume,
171 .get_current_rxslot = op32_get_current_rxslot,
172 .set_current_rxslot = op32_set_current_rxslot,
173};
174
175/* 64bit DMA ops. */
176static
177struct b43_dmadesc_generic *op64_idx2desc(struct b43_dmaring *ring,
178 int slot,
179 struct b43_dmadesc_meta **meta)
180{
181 struct b43_dmadesc64 *desc;
182
183 *meta = &(ring->meta[slot]);
184 desc = ring->descbase;
185 desc = &(desc[slot]);
186
187 return (struct b43_dmadesc_generic *)desc;
188}
189
190static void op64_fill_descriptor(struct b43_dmaring *ring,
191 struct b43_dmadesc_generic *desc,
192 dma_addr_t dmaaddr, u16 bufsize,
193 int start, int end, int irq)
194{
195 struct b43_dmadesc64 *descbase = ring->descbase;
196 int slot;
197 u32 ctl0 = 0, ctl1 = 0;
198 u32 addrlo, addrhi;
199 u32 addrext;
200
201 slot = (int)(&(desc->dma64) - descbase);
202 B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
203
204 addrlo = b43_dma_address(&ring->dev->dma, dmaaddr, B43_DMA_ADDR_LOW);
205 addrhi = b43_dma_address(&ring->dev->dma, dmaaddr, B43_DMA_ADDR_HIGH);
206 addrext = b43_dma_address(&ring->dev->dma, dmaaddr, B43_DMA_ADDR_EXT);
207
208 if (slot == ring->nr_slots - 1)
209 ctl0 |= B43_DMA64_DCTL0_DTABLEEND;
210 if (start)
211 ctl0 |= B43_DMA64_DCTL0_FRAMESTART;
212 if (end)
213 ctl0 |= B43_DMA64_DCTL0_FRAMEEND;
214 if (irq)
215 ctl0 |= B43_DMA64_DCTL0_IRQ;
216 ctl1 |= bufsize & B43_DMA64_DCTL1_BYTECNT;
217 ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT)
218 & B43_DMA64_DCTL1_ADDREXT_MASK;
219
220 desc->dma64.control0 = cpu_to_le32(ctl0);
221 desc->dma64.control1 = cpu_to_le32(ctl1);
222 desc->dma64.address_low = cpu_to_le32(addrlo);
223 desc->dma64.address_high = cpu_to_le32(addrhi);
224}
225
226static void op64_poke_tx(struct b43_dmaring *ring, int slot)
227{
228 b43_dma_write(ring, B43_DMA64_TXINDEX,
229 (u32) (slot * sizeof(struct b43_dmadesc64)));
230}
231
232static void op64_tx_suspend(struct b43_dmaring *ring)
233{
234 b43_dma_write(ring, B43_DMA64_TXCTL, b43_dma_read(ring, B43_DMA64_TXCTL)
235 | B43_DMA64_TXSUSPEND);
236}
237
238static void op64_tx_resume(struct b43_dmaring *ring)
239{
240 b43_dma_write(ring, B43_DMA64_TXCTL, b43_dma_read(ring, B43_DMA64_TXCTL)
241 & ~B43_DMA64_TXSUSPEND);
242}
243
244static int op64_get_current_rxslot(struct b43_dmaring *ring)
245{
246 u32 val;
247
248 val = b43_dma_read(ring, B43_DMA64_RXSTATUS);
249 val &= B43_DMA64_RXSTATDPTR;
250
251 return (val / sizeof(struct b43_dmadesc64));
252}
253
254static void op64_set_current_rxslot(struct b43_dmaring *ring, int slot)
255{
256 b43_dma_write(ring, B43_DMA64_RXINDEX,
257 (u32) (slot * sizeof(struct b43_dmadesc64)));
258}
259
260static const struct b43_dma_ops dma64_ops = {
261 .idx2desc = op64_idx2desc,
262 .fill_descriptor = op64_fill_descriptor,
263 .poke_tx = op64_poke_tx,
264 .tx_suspend = op64_tx_suspend,
265 .tx_resume = op64_tx_resume,
266 .get_current_rxslot = op64_get_current_rxslot,
267 .set_current_rxslot = op64_set_current_rxslot,
268};
269
270static inline int free_slots(struct b43_dmaring *ring)
271{
272 return (ring->nr_slots - ring->used_slots);
273}
274
275static inline int next_slot(struct b43_dmaring *ring, int slot)
276{
277 B43_WARN_ON(!(slot >= -1 && slot <= ring->nr_slots - 1));
278 if (slot == ring->nr_slots - 1)
279 return 0;
280 return slot + 1;
281}
282
283static inline int prev_slot(struct b43_dmaring *ring, int slot)
284{
285 B43_WARN_ON(!(slot >= 0 && slot <= ring->nr_slots - 1));
286 if (slot == 0)
287 return ring->nr_slots - 1;
288 return slot - 1;
289}
290
291#ifdef CONFIG_B43_DEBUG
292static void update_max_used_slots(struct b43_dmaring *ring,
293 int current_used_slots)
294{
295 if (current_used_slots <= ring->max_used_slots)
296 return;
297 ring->max_used_slots = current_used_slots;
298 if (b43_debug(ring->dev, B43_DBG_DMAVERBOSE)) {
299 b43dbg(ring->dev->wl,
300 "max_used_slots increased to %d on %s ring %d\n",
301 ring->max_used_slots,
302 ring->tx ? "TX" : "RX", ring->index);
303 }
304}
305#else
306static inline
307 void update_max_used_slots(struct b43_dmaring *ring, int current_used_slots)
308{
309}
310#endif /* DEBUG */
311
312/* Request a slot for usage. */
313static inline int request_slot(struct b43_dmaring *ring)
314{
315 int slot;
316
317 B43_WARN_ON(!ring->tx);
318 B43_WARN_ON(ring->stopped);
319 B43_WARN_ON(free_slots(ring) == 0);
320
321 slot = next_slot(ring, ring->current_slot);
322 ring->current_slot = slot;
323 ring->used_slots++;
324
325 update_max_used_slots(ring, ring->used_slots);
326
327 return slot;
328}
329
330static u16 b43_dmacontroller_base(enum b43_dmatype type, int controller_idx)
331{
332 static const u16 map64[] = {
333 B43_MMIO_DMA64_BASE0,
334 B43_MMIO_DMA64_BASE1,
335 B43_MMIO_DMA64_BASE2,
336 B43_MMIO_DMA64_BASE3,
337 B43_MMIO_DMA64_BASE4,
338 B43_MMIO_DMA64_BASE5,
339 };
340 static const u16 map32[] = {
341 B43_MMIO_DMA32_BASE0,
342 B43_MMIO_DMA32_BASE1,
343 B43_MMIO_DMA32_BASE2,
344 B43_MMIO_DMA32_BASE3,
345 B43_MMIO_DMA32_BASE4,
346 B43_MMIO_DMA32_BASE5,
347 };
348
349 if (type == B43_DMA_64BIT) {
350 B43_WARN_ON(!(controller_idx >= 0 &&
351 controller_idx < ARRAY_SIZE(map64)));
352 return map64[controller_idx];
353 }
354 B43_WARN_ON(!(controller_idx >= 0 &&
355 controller_idx < ARRAY_SIZE(map32)));
356 return map32[controller_idx];
357}
358
359static inline
360 dma_addr_t map_descbuffer(struct b43_dmaring *ring,
361 unsigned char *buf, size_t len, int tx)
362{
363 dma_addr_t dmaaddr;
364
365 if (tx) {
366 dmaaddr = dma_map_single(ring->dev->dev->dma_dev,
367 buf, len, DMA_TO_DEVICE);
368 } else {
369 dmaaddr = dma_map_single(ring->dev->dev->dma_dev,
370 buf, len, DMA_FROM_DEVICE);
371 }
372
373 return dmaaddr;
374}
375
376static inline
377 void unmap_descbuffer(struct b43_dmaring *ring,
378 dma_addr_t addr, size_t len, int tx)
379{
380 if (tx) {
381 dma_unmap_single(ring->dev->dev->dma_dev,
382 addr, len, DMA_TO_DEVICE);
383 } else {
384 dma_unmap_single(ring->dev->dev->dma_dev,
385 addr, len, DMA_FROM_DEVICE);
386 }
387}
388
389static inline
390 void sync_descbuffer_for_cpu(struct b43_dmaring *ring,
391 dma_addr_t addr, size_t len)
392{
393 B43_WARN_ON(ring->tx);
394 dma_sync_single_for_cpu(ring->dev->dev->dma_dev,
395 addr, len, DMA_FROM_DEVICE);
396}
397
398static inline
399 void sync_descbuffer_for_device(struct b43_dmaring *ring,
400 dma_addr_t addr, size_t len)
401{
402 B43_WARN_ON(ring->tx);
403 dma_sync_single_for_device(ring->dev->dev->dma_dev,
404 addr, len, DMA_FROM_DEVICE);
405}
406
407static inline
408 void free_descriptor_buffer(struct b43_dmaring *ring,
409 struct b43_dmadesc_meta *meta)
410{
411 if (meta->skb) {
412 if (ring->tx)
413 ieee80211_free_txskb(ring->dev->wl->hw, meta->skb);
414 else
415 dev_kfree_skb_any(meta->skb);
416 meta->skb = NULL;
417 }
418}
419
420static int alloc_ringmemory(struct b43_dmaring *ring)
421{
422 /* The specs call for 4K buffers for 30- and 32-bit DMA with 4K
423 * alignment and 8K buffers for 64-bit DMA with 8K alignment.
424 * In practice we could use smaller buffers for the latter, but the
425 * alignment is really important because of the hardware bug. If bit
426 * 0x00001000 is used in DMA address, some hardware (like BCM4331)
427 * copies that bit into B43_DMA64_RXSTATUS and we get false values from
428 * B43_DMA64_RXSTATDPTR. Let's just use 8K buffers even if we don't use
429 * more than 256 slots for ring.
430 */
431 u16 ring_mem_size = (ring->type == B43_DMA_64BIT) ?
432 B43_DMA64_RINGMEMSIZE : B43_DMA32_RINGMEMSIZE;
433
434 ring->descbase = dma_zalloc_coherent(ring->dev->dev->dma_dev,
435 ring_mem_size, &(ring->dmabase),
436 GFP_KERNEL);
437 if (!ring->descbase)
438 return -ENOMEM;
439
440 return 0;
441}
442
443static void free_ringmemory(struct b43_dmaring *ring)
444{
445 u16 ring_mem_size = (ring->type == B43_DMA_64BIT) ?
446 B43_DMA64_RINGMEMSIZE : B43_DMA32_RINGMEMSIZE;
447 dma_free_coherent(ring->dev->dev->dma_dev, ring_mem_size,
448 ring->descbase, ring->dmabase);
449}
450
451/* Reset the RX DMA channel */
452static int b43_dmacontroller_rx_reset(struct b43_wldev *dev, u16 mmio_base,
453 enum b43_dmatype type)
454{
455 int i;
456 u32 value;
457 u16 offset;
458
459 might_sleep();
460
461 offset = (type == B43_DMA_64BIT) ? B43_DMA64_RXCTL : B43_DMA32_RXCTL;
462 b43_write32(dev, mmio_base + offset, 0);
463 for (i = 0; i < 10; i++) {
464 offset = (type == B43_DMA_64BIT) ? B43_DMA64_RXSTATUS :
465 B43_DMA32_RXSTATUS;
466 value = b43_read32(dev, mmio_base + offset);
467 if (type == B43_DMA_64BIT) {
468 value &= B43_DMA64_RXSTAT;
469 if (value == B43_DMA64_RXSTAT_DISABLED) {
470 i = -1;
471 break;
472 }
473 } else {
474 value &= B43_DMA32_RXSTATE;
475 if (value == B43_DMA32_RXSTAT_DISABLED) {
476 i = -1;
477 break;
478 }
479 }
480 msleep(1);
481 }
482 if (i != -1) {
483 b43err(dev->wl, "DMA RX reset timed out\n");
484 return -ENODEV;
485 }
486
487 return 0;
488}
489
490/* Reset the TX DMA channel */
491static int b43_dmacontroller_tx_reset(struct b43_wldev *dev, u16 mmio_base,
492 enum b43_dmatype type)
493{
494 int i;
495 u32 value;
496 u16 offset;
497
498 might_sleep();
499
500 for (i = 0; i < 10; i++) {
501 offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXSTATUS :
502 B43_DMA32_TXSTATUS;
503 value = b43_read32(dev, mmio_base + offset);
504 if (type == B43_DMA_64BIT) {
505 value &= B43_DMA64_TXSTAT;
506 if (value == B43_DMA64_TXSTAT_DISABLED ||
507 value == B43_DMA64_TXSTAT_IDLEWAIT ||
508 value == B43_DMA64_TXSTAT_STOPPED)
509 break;
510 } else {
511 value &= B43_DMA32_TXSTATE;
512 if (value == B43_DMA32_TXSTAT_DISABLED ||
513 value == B43_DMA32_TXSTAT_IDLEWAIT ||
514 value == B43_DMA32_TXSTAT_STOPPED)
515 break;
516 }
517 msleep(1);
518 }
519 offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXCTL : B43_DMA32_TXCTL;
520 b43_write32(dev, mmio_base + offset, 0);
521 for (i = 0; i < 10; i++) {
522 offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXSTATUS :
523 B43_DMA32_TXSTATUS;
524 value = b43_read32(dev, mmio_base + offset);
525 if (type == B43_DMA_64BIT) {
526 value &= B43_DMA64_TXSTAT;
527 if (value == B43_DMA64_TXSTAT_DISABLED) {
528 i = -1;
529 break;
530 }
531 } else {
532 value &= B43_DMA32_TXSTATE;
533 if (value == B43_DMA32_TXSTAT_DISABLED) {
534 i = -1;
535 break;
536 }
537 }
538 msleep(1);
539 }
540 if (i != -1) {
541 b43err(dev->wl, "DMA TX reset timed out\n");
542 return -ENODEV;
543 }
544 /* ensure the reset is completed. */
545 msleep(1);
546
547 return 0;
548}
549
550/* Check if a DMA mapping address is invalid. */
551static bool b43_dma_mapping_error(struct b43_dmaring *ring,
552 dma_addr_t addr,
553 size_t buffersize, bool dma_to_device)
554{
555 if (unlikely(dma_mapping_error(ring->dev->dev->dma_dev, addr)))
556 return 1;
557
558 switch (ring->type) {
559 case B43_DMA_30BIT:
560 if ((u64)addr + buffersize > (1ULL << 30))
561 goto address_error;
562 break;
563 case B43_DMA_32BIT:
564 if ((u64)addr + buffersize > (1ULL << 32))
565 goto address_error;
566 break;
567 case B43_DMA_64BIT:
568 /* Currently we can't have addresses beyond
569 * 64bit in the kernel. */
570 break;
571 }
572
573 /* The address is OK. */
574 return 0;
575
576address_error:
577 /* We can't support this address. Unmap it again. */
578 unmap_descbuffer(ring, addr, buffersize, dma_to_device);
579
580 return 1;
581}
582
583static bool b43_rx_buffer_is_poisoned(struct b43_dmaring *ring, struct sk_buff *skb)
584{
585 unsigned char *f = skb->data + ring->frameoffset;
586
587 return ((f[0] & f[1] & f[2] & f[3] & f[4] & f[5] & f[6] & f[7]) == 0xFF);
588}
589
590static void b43_poison_rx_buffer(struct b43_dmaring *ring, struct sk_buff *skb)
591{
592 struct b43_rxhdr_fw4 *rxhdr;
593 unsigned char *frame;
594
595 /* This poisons the RX buffer to detect DMA failures. */
596
597 rxhdr = (struct b43_rxhdr_fw4 *)(skb->data);
598 rxhdr->frame_len = 0;
599
600 B43_WARN_ON(ring->rx_buffersize < ring->frameoffset + sizeof(struct b43_plcp_hdr6) + 2);
601 frame = skb->data + ring->frameoffset;
602 memset(frame, 0xFF, sizeof(struct b43_plcp_hdr6) + 2 /* padding */);
603}
604
605static int setup_rx_descbuffer(struct b43_dmaring *ring,
606 struct b43_dmadesc_generic *desc,
607 struct b43_dmadesc_meta *meta, gfp_t gfp_flags)
608{
609 dma_addr_t dmaaddr;
610 struct sk_buff *skb;
611
612 B43_WARN_ON(ring->tx);
613
614 skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
615 if (unlikely(!skb))
616 return -ENOMEM;
617 b43_poison_rx_buffer(ring, skb);
618 dmaaddr = map_descbuffer(ring, skb->data, ring->rx_buffersize, 0);
619 if (b43_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) {
620 /* ugh. try to realloc in zone_dma */
621 gfp_flags |= GFP_DMA;
622
623 dev_kfree_skb_any(skb);
624
625 skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
626 if (unlikely(!skb))
627 return -ENOMEM;
628 b43_poison_rx_buffer(ring, skb);
629 dmaaddr = map_descbuffer(ring, skb->data,
630 ring->rx_buffersize, 0);
631 if (b43_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) {
632 b43err(ring->dev->wl, "RX DMA buffer allocation failed\n");
633 dev_kfree_skb_any(skb);
634 return -EIO;
635 }
636 }
637
638 meta->skb = skb;
639 meta->dmaaddr = dmaaddr;
640 ring->ops->fill_descriptor(ring, desc, dmaaddr,
641 ring->rx_buffersize, 0, 0, 0);
642
643 return 0;
644}
645
646/* Allocate the initial descbuffers.
647 * This is used for an RX ring only.
648 */
649static int alloc_initial_descbuffers(struct b43_dmaring *ring)
650{
651 int i, err = -ENOMEM;
652 struct b43_dmadesc_generic *desc;
653 struct b43_dmadesc_meta *meta;
654
655 for (i = 0; i < ring->nr_slots; i++) {
656 desc = ring->ops->idx2desc(ring, i, &meta);
657
658 err = setup_rx_descbuffer(ring, desc, meta, GFP_KERNEL);
659 if (err) {
660 b43err(ring->dev->wl,
661 "Failed to allocate initial descbuffers\n");
662 goto err_unwind;
663 }
664 }
665 mb();
666 ring->used_slots = ring->nr_slots;
667 err = 0;
668 out:
669 return err;
670
671 err_unwind:
672 for (i--; i >= 0; i--) {
673 desc = ring->ops->idx2desc(ring, i, &meta);
674
675 unmap_descbuffer(ring, meta->dmaaddr, ring->rx_buffersize, 0);
676 dev_kfree_skb(meta->skb);
677 }
678 goto out;
679}
680
681/* Do initial setup of the DMA controller.
682 * Reset the controller, write the ring busaddress
683 * and switch the "enable" bit on.
684 */
685static int dmacontroller_setup(struct b43_dmaring *ring)
686{
687 int err = 0;
688 u32 value;
689 u32 addrext;
690 bool parity = ring->dev->dma.parity;
691 u32 addrlo;
692 u32 addrhi;
693
694 if (ring->tx) {
695 if (ring->type == B43_DMA_64BIT) {
696 u64 ringbase = (u64) (ring->dmabase);
697 addrext = b43_dma_address(&ring->dev->dma, ringbase, B43_DMA_ADDR_EXT);
698 addrlo = b43_dma_address(&ring->dev->dma, ringbase, B43_DMA_ADDR_LOW);
699 addrhi = b43_dma_address(&ring->dev->dma, ringbase, B43_DMA_ADDR_HIGH);
700
701 value = B43_DMA64_TXENABLE;
702 value |= (addrext << B43_DMA64_TXADDREXT_SHIFT)
703 & B43_DMA64_TXADDREXT_MASK;
704 if (!parity)
705 value |= B43_DMA64_TXPARITYDISABLE;
706 b43_dma_write(ring, B43_DMA64_TXCTL, value);
707 b43_dma_write(ring, B43_DMA64_TXRINGLO, addrlo);
708 b43_dma_write(ring, B43_DMA64_TXRINGHI, addrhi);
709 } else {
710 u32 ringbase = (u32) (ring->dmabase);
711 addrext = b43_dma_address(&ring->dev->dma, ringbase, B43_DMA_ADDR_EXT);
712 addrlo = b43_dma_address(&ring->dev->dma, ringbase, B43_DMA_ADDR_LOW);
713
714 value = B43_DMA32_TXENABLE;
715 value |= (addrext << B43_DMA32_TXADDREXT_SHIFT)
716 & B43_DMA32_TXADDREXT_MASK;
717 if (!parity)
718 value |= B43_DMA32_TXPARITYDISABLE;
719 b43_dma_write(ring, B43_DMA32_TXCTL, value);
720 b43_dma_write(ring, B43_DMA32_TXRING, addrlo);
721 }
722 } else {
723 err = alloc_initial_descbuffers(ring);
724 if (err)
725 goto out;
726 if (ring->type == B43_DMA_64BIT) {
727 u64 ringbase = (u64) (ring->dmabase);
728 addrext = b43_dma_address(&ring->dev->dma, ringbase, B43_DMA_ADDR_EXT);
729 addrlo = b43_dma_address(&ring->dev->dma, ringbase, B43_DMA_ADDR_LOW);
730 addrhi = b43_dma_address(&ring->dev->dma, ringbase, B43_DMA_ADDR_HIGH);
731
732 value = (ring->frameoffset << B43_DMA64_RXFROFF_SHIFT);
733 value |= B43_DMA64_RXENABLE;
734 value |= (addrext << B43_DMA64_RXADDREXT_SHIFT)
735 & B43_DMA64_RXADDREXT_MASK;
736 if (!parity)
737 value |= B43_DMA64_RXPARITYDISABLE;
738 b43_dma_write(ring, B43_DMA64_RXCTL, value);
739 b43_dma_write(ring, B43_DMA64_RXRINGLO, addrlo);
740 b43_dma_write(ring, B43_DMA64_RXRINGHI, addrhi);
741 b43_dma_write(ring, B43_DMA64_RXINDEX, ring->nr_slots *
742 sizeof(struct b43_dmadesc64));
743 } else {
744 u32 ringbase = (u32) (ring->dmabase);
745 addrext = b43_dma_address(&ring->dev->dma, ringbase, B43_DMA_ADDR_EXT);
746 addrlo = b43_dma_address(&ring->dev->dma, ringbase, B43_DMA_ADDR_LOW);
747
748 value = (ring->frameoffset << B43_DMA32_RXFROFF_SHIFT);
749 value |= B43_DMA32_RXENABLE;
750 value |= (addrext << B43_DMA32_RXADDREXT_SHIFT)
751 & B43_DMA32_RXADDREXT_MASK;
752 if (!parity)
753 value |= B43_DMA32_RXPARITYDISABLE;
754 b43_dma_write(ring, B43_DMA32_RXCTL, value);
755 b43_dma_write(ring, B43_DMA32_RXRING, addrlo);
756 b43_dma_write(ring, B43_DMA32_RXINDEX, ring->nr_slots *
757 sizeof(struct b43_dmadesc32));
758 }
759 }
760
761out:
762 return err;
763}
764
765/* Shutdown the DMA controller. */
766static void dmacontroller_cleanup(struct b43_dmaring *ring)
767{
768 if (ring->tx) {
769 b43_dmacontroller_tx_reset(ring->dev, ring->mmio_base,
770 ring->type);
771 if (ring->type == B43_DMA_64BIT) {
772 b43_dma_write(ring, B43_DMA64_TXRINGLO, 0);
773 b43_dma_write(ring, B43_DMA64_TXRINGHI, 0);
774 } else
775 b43_dma_write(ring, B43_DMA32_TXRING, 0);
776 } else {
777 b43_dmacontroller_rx_reset(ring->dev, ring->mmio_base,
778 ring->type);
779 if (ring->type == B43_DMA_64BIT) {
780 b43_dma_write(ring, B43_DMA64_RXRINGLO, 0);
781 b43_dma_write(ring, B43_DMA64_RXRINGHI, 0);
782 } else
783 b43_dma_write(ring, B43_DMA32_RXRING, 0);
784 }
785}
786
787static void free_all_descbuffers(struct b43_dmaring *ring)
788{
789 struct b43_dmadesc_meta *meta;
790 int i;
791
792 if (!ring->used_slots)
793 return;
794 for (i = 0; i < ring->nr_slots; i++) {
795 /* get meta - ignore returned value */
796 ring->ops->idx2desc(ring, i, &meta);
797
798 if (!meta->skb || b43_dma_ptr_is_poisoned(meta->skb)) {
799 B43_WARN_ON(!ring->tx);
800 continue;
801 }
802 if (ring->tx) {
803 unmap_descbuffer(ring, meta->dmaaddr,
804 meta->skb->len, 1);
805 } else {
806 unmap_descbuffer(ring, meta->dmaaddr,
807 ring->rx_buffersize, 0);
808 }
809 free_descriptor_buffer(ring, meta);
810 }
811}
812
813static u64 supported_dma_mask(struct b43_wldev *dev)
814{
815 u32 tmp;
816 u16 mmio_base;
817
818 switch (dev->dev->bus_type) {
819#ifdef CONFIG_B43_BCMA
820 case B43_BUS_BCMA:
821 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOST);
822 if (tmp & BCMA_IOST_DMA64)
823 return DMA_BIT_MASK(64);
824 break;
825#endif
826#ifdef CONFIG_B43_SSB
827 case B43_BUS_SSB:
828 tmp = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
829 if (tmp & SSB_TMSHIGH_DMA64)
830 return DMA_BIT_MASK(64);
831 break;
832#endif
833 }
834
835 mmio_base = b43_dmacontroller_base(0, 0);
836 b43_write32(dev, mmio_base + B43_DMA32_TXCTL, B43_DMA32_TXADDREXT_MASK);
837 tmp = b43_read32(dev, mmio_base + B43_DMA32_TXCTL);
838 if (tmp & B43_DMA32_TXADDREXT_MASK)
839 return DMA_BIT_MASK(32);
840
841 return DMA_BIT_MASK(30);
842}
843
844static enum b43_dmatype dma_mask_to_engine_type(u64 dmamask)
845{
846 if (dmamask == DMA_BIT_MASK(30))
847 return B43_DMA_30BIT;
848 if (dmamask == DMA_BIT_MASK(32))
849 return B43_DMA_32BIT;
850 if (dmamask == DMA_BIT_MASK(64))
851 return B43_DMA_64BIT;
852 B43_WARN_ON(1);
853 return B43_DMA_30BIT;
854}
855
856/* Main initialization function. */
857static
858struct b43_dmaring *b43_setup_dmaring(struct b43_wldev *dev,
859 int controller_index,
860 int for_tx,
861 enum b43_dmatype type)
862{
863 struct b43_dmaring *ring;
864 int i, err;
865 dma_addr_t dma_test;
866
867 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
868 if (!ring)
869 goto out;
870
871 ring->nr_slots = B43_RXRING_SLOTS;
872 if (for_tx)
873 ring->nr_slots = B43_TXRING_SLOTS;
874
875 ring->meta = kcalloc(ring->nr_slots, sizeof(struct b43_dmadesc_meta),
876 GFP_KERNEL);
877 if (!ring->meta)
878 goto err_kfree_ring;
879 for (i = 0; i < ring->nr_slots; i++)
880 ring->meta->skb = B43_DMA_PTR_POISON;
881
882 ring->type = type;
883 ring->dev = dev;
884 ring->mmio_base = b43_dmacontroller_base(type, controller_index);
885 ring->index = controller_index;
886 if (type == B43_DMA_64BIT)
887 ring->ops = &dma64_ops;
888 else
889 ring->ops = &dma32_ops;
890 if (for_tx) {
891 ring->tx = true;
892 ring->current_slot = -1;
893 } else {
894 if (ring->index == 0) {
895 switch (dev->fw.hdr_format) {
896 case B43_FW_HDR_598:
897 ring->rx_buffersize = B43_DMA0_RX_FW598_BUFSIZE;
898 ring->frameoffset = B43_DMA0_RX_FW598_FO;
899 break;
900 case B43_FW_HDR_410:
901 case B43_FW_HDR_351:
902 ring->rx_buffersize = B43_DMA0_RX_FW351_BUFSIZE;
903 ring->frameoffset = B43_DMA0_RX_FW351_FO;
904 break;
905 }
906 } else
907 B43_WARN_ON(1);
908 }
909#ifdef CONFIG_B43_DEBUG
910 ring->last_injected_overflow = jiffies;
911#endif
912
913 if (for_tx) {
914 /* Assumption: B43_TXRING_SLOTS can be divided by TX_SLOTS_PER_FRAME */
915 BUILD_BUG_ON(B43_TXRING_SLOTS % TX_SLOTS_PER_FRAME != 0);
916
917 ring->txhdr_cache = kcalloc(ring->nr_slots / TX_SLOTS_PER_FRAME,
918 b43_txhdr_size(dev),
919 GFP_KERNEL);
920 if (!ring->txhdr_cache)
921 goto err_kfree_meta;
922
923 /* test for ability to dma to txhdr_cache */
924 dma_test = dma_map_single(dev->dev->dma_dev,
925 ring->txhdr_cache,
926 b43_txhdr_size(dev),
927 DMA_TO_DEVICE);
928
929 if (b43_dma_mapping_error(ring, dma_test,
930 b43_txhdr_size(dev), 1)) {
931 /* ugh realloc */
932 kfree(ring->txhdr_cache);
933 ring->txhdr_cache = kcalloc(ring->nr_slots / TX_SLOTS_PER_FRAME,
934 b43_txhdr_size(dev),
935 GFP_KERNEL | GFP_DMA);
936 if (!ring->txhdr_cache)
937 goto err_kfree_meta;
938
939 dma_test = dma_map_single(dev->dev->dma_dev,
940 ring->txhdr_cache,
941 b43_txhdr_size(dev),
942 DMA_TO_DEVICE);
943
944 if (b43_dma_mapping_error(ring, dma_test,
945 b43_txhdr_size(dev), 1)) {
946
947 b43err(dev->wl,
948 "TXHDR DMA allocation failed\n");
949 goto err_kfree_txhdr_cache;
950 }
951 }
952
953 dma_unmap_single(dev->dev->dma_dev,
954 dma_test, b43_txhdr_size(dev),
955 DMA_TO_DEVICE);
956 }
957
958 err = alloc_ringmemory(ring);
959 if (err)
960 goto err_kfree_txhdr_cache;
961 err = dmacontroller_setup(ring);
962 if (err)
963 goto err_free_ringmemory;
964
965 out:
966 return ring;
967
968 err_free_ringmemory:
969 free_ringmemory(ring);
970 err_kfree_txhdr_cache:
971 kfree(ring->txhdr_cache);
972 err_kfree_meta:
973 kfree(ring->meta);
974 err_kfree_ring:
975 kfree(ring);
976 ring = NULL;
977 goto out;
978}
979
980#define divide(a, b) ({ \
981 typeof(a) __a = a; \
982 do_div(__a, b); \
983 __a; \
984 })
985
986#define modulo(a, b) ({ \
987 typeof(a) __a = a; \
988 do_div(__a, b); \
989 })
990
991/* Main cleanup function. */
992static void b43_destroy_dmaring(struct b43_dmaring *ring,
993 const char *ringname)
994{
995 if (!ring)
996 return;
997
998#ifdef CONFIG_B43_DEBUG
999 {
1000 /* Print some statistics. */
1001 u64 failed_packets = ring->nr_failed_tx_packets;
1002 u64 succeed_packets = ring->nr_succeed_tx_packets;
1003 u64 nr_packets = failed_packets + succeed_packets;
1004 u64 permille_failed = 0, average_tries = 0;
1005
1006 if (nr_packets)
1007 permille_failed = divide(failed_packets * 1000, nr_packets);
1008 if (nr_packets)
1009 average_tries = divide(ring->nr_total_packet_tries * 100, nr_packets);
1010
1011 b43dbg(ring->dev->wl, "DMA-%u %s: "
1012 "Used slots %d/%d, Failed frames %llu/%llu = %llu.%01llu%%, "
1013 "Average tries %llu.%02llu\n",
1014 (unsigned int)(ring->type), ringname,
1015 ring->max_used_slots,
1016 ring->nr_slots,
1017 (unsigned long long)failed_packets,
1018 (unsigned long long)nr_packets,
1019 (unsigned long long)divide(permille_failed, 10),
1020 (unsigned long long)modulo(permille_failed, 10),
1021 (unsigned long long)divide(average_tries, 100),
1022 (unsigned long long)modulo(average_tries, 100));
1023 }
1024#endif /* DEBUG */
1025
1026 /* Device IRQs are disabled prior entering this function,
1027 * so no need to take care of concurrency with rx handler stuff.
1028 */
1029 dmacontroller_cleanup(ring);
1030 free_all_descbuffers(ring);
1031 free_ringmemory(ring);
1032
1033 kfree(ring->txhdr_cache);
1034 kfree(ring->meta);
1035 kfree(ring);
1036}
1037
1038#define destroy_ring(dma, ring) do { \
1039 b43_destroy_dmaring((dma)->ring, __stringify(ring)); \
1040 (dma)->ring = NULL; \
1041 } while (0)
1042
1043void b43_dma_free(struct b43_wldev *dev)
1044{
1045 struct b43_dma *dma;
1046
1047 if (b43_using_pio_transfers(dev))
1048 return;
1049 dma = &dev->dma;
1050
1051 destroy_ring(dma, rx_ring);
1052 destroy_ring(dma, tx_ring_AC_BK);
1053 destroy_ring(dma, tx_ring_AC_BE);
1054 destroy_ring(dma, tx_ring_AC_VI);
1055 destroy_ring(dma, tx_ring_AC_VO);
1056 destroy_ring(dma, tx_ring_mcast);
1057}
1058
1059static int b43_dma_set_mask(struct b43_wldev *dev, u64 mask)
1060{
1061 u64 orig_mask = mask;
1062 bool fallback = false;
1063 int err;
1064
1065 /* Try to set the DMA mask. If it fails, try falling back to a
1066 * lower mask, as we can always also support a lower one. */
1067 while (1) {
1068 err = dma_set_mask_and_coherent(dev->dev->dma_dev, mask);
1069 if (!err)
1070 break;
1071 if (mask == DMA_BIT_MASK(64)) {
1072 mask = DMA_BIT_MASK(32);
1073 fallback = true;
1074 continue;
1075 }
1076 if (mask == DMA_BIT_MASK(32)) {
1077 mask = DMA_BIT_MASK(30);
1078 fallback = true;
1079 continue;
1080 }
1081 b43err(dev->wl, "The machine/kernel does not support "
1082 "the required %u-bit DMA mask\n",
1083 (unsigned int)dma_mask_to_engine_type(orig_mask));
1084 return -EOPNOTSUPP;
1085 }
1086 if (fallback) {
1087 b43info(dev->wl, "DMA mask fallback from %u-bit to %u-bit\n",
1088 (unsigned int)dma_mask_to_engine_type(orig_mask),
1089 (unsigned int)dma_mask_to_engine_type(mask));
1090 }
1091
1092 return 0;
1093}
1094
1095/* Some hardware with 64-bit DMA seems to be bugged and looks for translation
1096 * bit in low address word instead of high one.
1097 */
1098static bool b43_dma_translation_in_low_word(struct b43_wldev *dev,
1099 enum b43_dmatype type)
1100{
1101 if (type != B43_DMA_64BIT)
1102 return 1;
1103
1104#ifdef CONFIG_B43_SSB
1105 if (dev->dev->bus_type == B43_BUS_SSB &&
1106 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI &&
1107 !(pci_is_pcie(dev->dev->sdev->bus->host_pci) &&
1108 ssb_read32(dev->dev->sdev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64))
1109 return 1;
1110#endif
1111 return 0;
1112}
1113
1114int b43_dma_init(struct b43_wldev *dev)
1115{
1116 struct b43_dma *dma = &dev->dma;
1117 int err;
1118 u64 dmamask;
1119 enum b43_dmatype type;
1120
1121 dmamask = supported_dma_mask(dev);
1122 type = dma_mask_to_engine_type(dmamask);
1123 err = b43_dma_set_mask(dev, dmamask);
1124 if (err)
1125 return err;
1126
1127 switch (dev->dev->bus_type) {
1128#ifdef CONFIG_B43_BCMA
1129 case B43_BUS_BCMA:
1130 dma->translation = bcma_core_dma_translation(dev->dev->bdev);
1131 break;
1132#endif
1133#ifdef CONFIG_B43_SSB
1134 case B43_BUS_SSB:
1135 dma->translation = ssb_dma_translation(dev->dev->sdev);
1136 break;
1137#endif
1138 }
1139 dma->translation_in_low = b43_dma_translation_in_low_word(dev, type);
1140
1141 dma->parity = true;
1142#ifdef CONFIG_B43_BCMA
1143 /* TODO: find out which SSB devices need disabling parity */
1144 if (dev->dev->bus_type == B43_BUS_BCMA)
1145 dma->parity = false;
1146#endif
1147
1148 err = -ENOMEM;
1149 /* setup TX DMA channels. */
1150 dma->tx_ring_AC_BK = b43_setup_dmaring(dev, 0, 1, type);
1151 if (!dma->tx_ring_AC_BK)
1152 goto out;
1153
1154 dma->tx_ring_AC_BE = b43_setup_dmaring(dev, 1, 1, type);
1155 if (!dma->tx_ring_AC_BE)
1156 goto err_destroy_bk;
1157
1158 dma->tx_ring_AC_VI = b43_setup_dmaring(dev, 2, 1, type);
1159 if (!dma->tx_ring_AC_VI)
1160 goto err_destroy_be;
1161
1162 dma->tx_ring_AC_VO = b43_setup_dmaring(dev, 3, 1, type);
1163 if (!dma->tx_ring_AC_VO)
1164 goto err_destroy_vi;
1165
1166 dma->tx_ring_mcast = b43_setup_dmaring(dev, 4, 1, type);
1167 if (!dma->tx_ring_mcast)
1168 goto err_destroy_vo;
1169
1170 /* setup RX DMA channel. */
1171 dma->rx_ring = b43_setup_dmaring(dev, 0, 0, type);
1172 if (!dma->rx_ring)
1173 goto err_destroy_mcast;
1174
1175 /* No support for the TX status DMA ring. */
1176 B43_WARN_ON(dev->dev->core_rev < 5);
1177
1178 b43dbg(dev->wl, "%u-bit DMA initialized\n",
1179 (unsigned int)type);
1180 err = 0;
1181out:
1182 return err;
1183
1184err_destroy_mcast:
1185 destroy_ring(dma, tx_ring_mcast);
1186err_destroy_vo:
1187 destroy_ring(dma, tx_ring_AC_VO);
1188err_destroy_vi:
1189 destroy_ring(dma, tx_ring_AC_VI);
1190err_destroy_be:
1191 destroy_ring(dma, tx_ring_AC_BE);
1192err_destroy_bk:
1193 destroy_ring(dma, tx_ring_AC_BK);
1194 return err;
1195}
1196
1197/* Generate a cookie for the TX header. */
1198static u16 generate_cookie(struct b43_dmaring *ring, int slot)
1199{
1200 u16 cookie;
1201
1202 /* Use the upper 4 bits of the cookie as
1203 * DMA controller ID and store the slot number
1204 * in the lower 12 bits.
1205 * Note that the cookie must never be 0, as this
1206 * is a special value used in RX path.
1207 * It can also not be 0xFFFF because that is special
1208 * for multicast frames.
1209 */
1210 cookie = (((u16)ring->index + 1) << 12);
1211 B43_WARN_ON(slot & ~0x0FFF);
1212 cookie |= (u16)slot;
1213
1214 return cookie;
1215}
1216
1217/* Inspect a cookie and find out to which controller/slot it belongs. */
1218static
1219struct b43_dmaring *parse_cookie(struct b43_wldev *dev, u16 cookie, int *slot)
1220{
1221 struct b43_dma *dma = &dev->dma;
1222 struct b43_dmaring *ring = NULL;
1223
1224 switch (cookie & 0xF000) {
1225 case 0x1000:
1226 ring = dma->tx_ring_AC_BK;
1227 break;
1228 case 0x2000:
1229 ring = dma->tx_ring_AC_BE;
1230 break;
1231 case 0x3000:
1232 ring = dma->tx_ring_AC_VI;
1233 break;
1234 case 0x4000:
1235 ring = dma->tx_ring_AC_VO;
1236 break;
1237 case 0x5000:
1238 ring = dma->tx_ring_mcast;
1239 break;
1240 }
1241 *slot = (cookie & 0x0FFF);
1242 if (unlikely(!ring || *slot < 0 || *slot >= ring->nr_slots)) {
1243 b43dbg(dev->wl, "TX-status contains "
1244 "invalid cookie: 0x%04X\n", cookie);
1245 return NULL;
1246 }
1247
1248 return ring;
1249}
1250
1251static int dma_tx_fragment(struct b43_dmaring *ring,
1252 struct sk_buff *skb)
1253{
1254 const struct b43_dma_ops *ops = ring->ops;
1255 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1256 struct b43_private_tx_info *priv_info = b43_get_priv_tx_info(info);
1257 u8 *header;
1258 int slot, old_top_slot, old_used_slots;
1259 int err;
1260 struct b43_dmadesc_generic *desc;
1261 struct b43_dmadesc_meta *meta;
1262 struct b43_dmadesc_meta *meta_hdr;
1263 u16 cookie;
1264 size_t hdrsize = b43_txhdr_size(ring->dev);
1265
1266 /* Important note: If the number of used DMA slots per TX frame
1267 * is changed here, the TX_SLOTS_PER_FRAME definition at the top of
1268 * the file has to be updated, too!
1269 */
1270
1271 old_top_slot = ring->current_slot;
1272 old_used_slots = ring->used_slots;
1273
1274 /* Get a slot for the header. */
1275 slot = request_slot(ring);
1276 desc = ops->idx2desc(ring, slot, &meta_hdr);
1277 memset(meta_hdr, 0, sizeof(*meta_hdr));
1278
1279 header = &(ring->txhdr_cache[(slot / TX_SLOTS_PER_FRAME) * hdrsize]);
1280 cookie = generate_cookie(ring, slot);
1281 err = b43_generate_txhdr(ring->dev, header,
1282 skb, info, cookie);
1283 if (unlikely(err)) {
1284 ring->current_slot = old_top_slot;
1285 ring->used_slots = old_used_slots;
1286 return err;
1287 }
1288
1289 meta_hdr->dmaaddr = map_descbuffer(ring, (unsigned char *)header,
1290 hdrsize, 1);
1291 if (b43_dma_mapping_error(ring, meta_hdr->dmaaddr, hdrsize, 1)) {
1292 ring->current_slot = old_top_slot;
1293 ring->used_slots = old_used_slots;
1294 return -EIO;
1295 }
1296 ops->fill_descriptor(ring, desc, meta_hdr->dmaaddr,
1297 hdrsize, 1, 0, 0);
1298
1299 /* Get a slot for the payload. */
1300 slot = request_slot(ring);
1301 desc = ops->idx2desc(ring, slot, &meta);
1302 memset(meta, 0, sizeof(*meta));
1303
1304 meta->skb = skb;
1305 meta->is_last_fragment = true;
1306 priv_info->bouncebuffer = NULL;
1307
1308 meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
1309 /* create a bounce buffer in zone_dma on mapping failure. */
1310 if (b43_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) {
1311 priv_info->bouncebuffer = kmemdup(skb->data, skb->len,
1312 GFP_ATOMIC | GFP_DMA);
1313 if (!priv_info->bouncebuffer) {
1314 ring->current_slot = old_top_slot;
1315 ring->used_slots = old_used_slots;
1316 err = -ENOMEM;
1317 goto out_unmap_hdr;
1318 }
1319
1320 meta->dmaaddr = map_descbuffer(ring, priv_info->bouncebuffer, skb->len, 1);
1321 if (b43_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) {
1322 kfree(priv_info->bouncebuffer);
1323 priv_info->bouncebuffer = NULL;
1324 ring->current_slot = old_top_slot;
1325 ring->used_slots = old_used_slots;
1326 err = -EIO;
1327 goto out_unmap_hdr;
1328 }
1329 }
1330
1331 ops->fill_descriptor(ring, desc, meta->dmaaddr, skb->len, 0, 1, 1);
1332
1333 if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
1334 /* Tell the firmware about the cookie of the last
1335 * mcast frame, so it can clear the more-data bit in it. */
1336 b43_shm_write16(ring->dev, B43_SHM_SHARED,
1337 B43_SHM_SH_MCASTCOOKIE, cookie);
1338 }
1339 /* Now transfer the whole frame. */
1340 wmb();
1341 ops->poke_tx(ring, next_slot(ring, slot));
1342 return 0;
1343
1344out_unmap_hdr:
1345 unmap_descbuffer(ring, meta_hdr->dmaaddr,
1346 hdrsize, 1);
1347 return err;
1348}
1349
1350static inline int should_inject_overflow(struct b43_dmaring *ring)
1351{
1352#ifdef CONFIG_B43_DEBUG
1353 if (unlikely(b43_debug(ring->dev, B43_DBG_DMAOVERFLOW))) {
1354 /* Check if we should inject another ringbuffer overflow
1355 * to test handling of this situation in the stack. */
1356 unsigned long next_overflow;
1357
1358 next_overflow = ring->last_injected_overflow + HZ;
1359 if (time_after(jiffies, next_overflow)) {
1360 ring->last_injected_overflow = jiffies;
1361 b43dbg(ring->dev->wl,
1362 "Injecting TX ring overflow on "
1363 "DMA controller %d\n", ring->index);
1364 return 1;
1365 }
1366 }
1367#endif /* CONFIG_B43_DEBUG */
1368 return 0;
1369}
1370
1371/* Static mapping of mac80211's queues (priorities) to b43 DMA rings. */
1372static struct b43_dmaring *select_ring_by_priority(struct b43_wldev *dev,
1373 u8 queue_prio)
1374{
1375 struct b43_dmaring *ring;
1376
1377 if (dev->qos_enabled) {
1378 /* 0 = highest priority */
1379 switch (queue_prio) {
1380 default:
1381 B43_WARN_ON(1);
1382 /* fallthrough */
1383 case 0:
1384 ring = dev->dma.tx_ring_AC_VO;
1385 break;
1386 case 1:
1387 ring = dev->dma.tx_ring_AC_VI;
1388 break;
1389 case 2:
1390 ring = dev->dma.tx_ring_AC_BE;
1391 break;
1392 case 3:
1393 ring = dev->dma.tx_ring_AC_BK;
1394 break;
1395 }
1396 } else
1397 ring = dev->dma.tx_ring_AC_BE;
1398
1399 return ring;
1400}
1401
1402int b43_dma_tx(struct b43_wldev *dev, struct sk_buff *skb)
1403{
1404 struct b43_dmaring *ring;
1405 struct ieee80211_hdr *hdr;
1406 int err = 0;
1407 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1408
1409 hdr = (struct ieee80211_hdr *)skb->data;
1410 if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
1411 /* The multicast ring will be sent after the DTIM */
1412 ring = dev->dma.tx_ring_mcast;
1413 /* Set the more-data bit. Ucode will clear it on
1414 * the last frame for us. */
1415 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_MOREDATA);
1416 } else {
1417 /* Decide by priority where to put this frame. */
1418 ring = select_ring_by_priority(
1419 dev, skb_get_queue_mapping(skb));
1420 }
1421
1422 B43_WARN_ON(!ring->tx);
1423
1424 if (unlikely(ring->stopped)) {
1425 /* We get here only because of a bug in mac80211.
1426 * Because of a race, one packet may be queued after
1427 * the queue is stopped, thus we got called when we shouldn't.
1428 * For now, just refuse the transmit. */
1429 if (b43_debug(dev, B43_DBG_DMAVERBOSE))
1430 b43err(dev->wl, "Packet after queue stopped\n");
1431 err = -ENOSPC;
1432 goto out;
1433 }
1434
1435 if (unlikely(WARN_ON(free_slots(ring) < TX_SLOTS_PER_FRAME))) {
1436 /* If we get here, we have a real error with the queue
1437 * full, but queues not stopped. */
1438 b43err(dev->wl, "DMA queue overflow\n");
1439 err = -ENOSPC;
1440 goto out;
1441 }
1442
1443 /* Assign the queue number to the ring (if not already done before)
1444 * so TX status handling can use it. The queue to ring mapping is
1445 * static, so we don't need to store it per frame. */
1446 ring->queue_prio = skb_get_queue_mapping(skb);
1447
1448 err = dma_tx_fragment(ring, skb);
1449 if (unlikely(err == -ENOKEY)) {
1450 /* Drop this packet, as we don't have the encryption key
1451 * anymore and must not transmit it unencrypted. */
1452 ieee80211_free_txskb(dev->wl->hw, skb);
1453 err = 0;
1454 goto out;
1455 }
1456 if (unlikely(err)) {
1457 b43err(dev->wl, "DMA tx mapping failure\n");
1458 goto out;
1459 }
1460 if ((free_slots(ring) < TX_SLOTS_PER_FRAME) ||
1461 should_inject_overflow(ring)) {
1462 /* This TX ring is full. */
1463 unsigned int skb_mapping = skb_get_queue_mapping(skb);
1464 ieee80211_stop_queue(dev->wl->hw, skb_mapping);
1465 dev->wl->tx_queue_stopped[skb_mapping] = 1;
1466 ring->stopped = true;
1467 if (b43_debug(dev, B43_DBG_DMAVERBOSE)) {
1468 b43dbg(dev->wl, "Stopped TX ring %d\n", ring->index);
1469 }
1470 }
1471out:
1472
1473 return err;
1474}
1475
1476void b43_dma_handle_txstatus(struct b43_wldev *dev,
1477 const struct b43_txstatus *status)
1478{
1479 const struct b43_dma_ops *ops;
1480 struct b43_dmaring *ring;
1481 struct b43_dmadesc_meta *meta;
1482 static const struct b43_txstatus fake; /* filled with 0 */
1483 const struct b43_txstatus *txstat;
1484 int slot, firstused;
1485 bool frame_succeed;
1486 int skip;
1487 static u8 err_out1, err_out2;
1488
1489 ring = parse_cookie(dev, status->cookie, &slot);
1490 if (unlikely(!ring))
1491 return;
1492 B43_WARN_ON(!ring->tx);
1493
1494 /* Sanity check: TX packets are processed in-order on one ring.
1495 * Check if the slot deduced from the cookie really is the first
1496 * used slot. */
1497 firstused = ring->current_slot - ring->used_slots + 1;
1498 if (firstused < 0)
1499 firstused = ring->nr_slots + firstused;
1500
1501 skip = 0;
1502 if (unlikely(slot != firstused)) {
1503 /* This possibly is a firmware bug and will result in
1504 * malfunction, memory leaks and/or stall of DMA functionality.
1505 */
1506 if (slot == next_slot(ring, next_slot(ring, firstused))) {
1507 /* If a single header/data pair was missed, skip over
1508 * the first two slots in an attempt to recover.
1509 */
1510 slot = firstused;
1511 skip = 2;
1512 if (!err_out1) {
1513 /* Report the error once. */
1514 b43dbg(dev->wl,
1515 "Skip on DMA ring %d slot %d.\n",
1516 ring->index, slot);
1517 err_out1 = 1;
1518 }
1519 } else {
1520 /* More than a single header/data pair were missed.
1521 * Report this error once.
1522 */
1523 if (!err_out2)
1524 b43dbg(dev->wl,
1525 "Out of order TX status report on DMA ring %d. Expected %d, but got %d\n",
1526 ring->index, firstused, slot);
1527 err_out2 = 1;
1528 return;
1529 }
1530 }
1531
1532 ops = ring->ops;
1533 while (1) {
1534 B43_WARN_ON(slot < 0 || slot >= ring->nr_slots);
1535 /* get meta - ignore returned value */
1536 ops->idx2desc(ring, slot, &meta);
1537
1538 if (b43_dma_ptr_is_poisoned(meta->skb)) {
1539 b43dbg(dev->wl, "Poisoned TX slot %d (first=%d) "
1540 "on ring %d\n",
1541 slot, firstused, ring->index);
1542 break;
1543 }
1544
1545 if (meta->skb) {
1546 struct b43_private_tx_info *priv_info =
1547 b43_get_priv_tx_info(IEEE80211_SKB_CB(meta->skb));
1548
1549 unmap_descbuffer(ring, meta->dmaaddr,
1550 meta->skb->len, 1);
1551 kfree(priv_info->bouncebuffer);
1552 priv_info->bouncebuffer = NULL;
1553 } else {
1554 unmap_descbuffer(ring, meta->dmaaddr,
1555 b43_txhdr_size(dev), 1);
1556 }
1557
1558 if (meta->is_last_fragment) {
1559 struct ieee80211_tx_info *info;
1560
1561 if (unlikely(!meta->skb)) {
1562 /* This is a scatter-gather fragment of a frame,
1563 * so the skb pointer must not be NULL.
1564 */
1565 b43dbg(dev->wl, "TX status unexpected NULL skb "
1566 "at slot %d (first=%d) on ring %d\n",
1567 slot, firstused, ring->index);
1568 break;
1569 }
1570
1571 info = IEEE80211_SKB_CB(meta->skb);
1572
1573 /*
1574 * Call back to inform the ieee80211 subsystem about
1575 * the status of the transmission. When skipping over
1576 * a missed TX status report, use a status structure
1577 * filled with zeros to indicate that the frame was not
1578 * sent (frame_count 0) and not acknowledged
1579 */
1580 if (unlikely(skip))
1581 txstat = &fake;
1582 else
1583 txstat = status;
1584
1585 frame_succeed = b43_fill_txstatus_report(dev, info,
1586 txstat);
1587#ifdef CONFIG_B43_DEBUG
1588 if (frame_succeed)
1589 ring->nr_succeed_tx_packets++;
1590 else
1591 ring->nr_failed_tx_packets++;
1592 ring->nr_total_packet_tries += status->frame_count;
1593#endif /* DEBUG */
1594 ieee80211_tx_status(dev->wl->hw, meta->skb);
1595
1596 /* skb will be freed by ieee80211_tx_status().
1597 * Poison our pointer. */
1598 meta->skb = B43_DMA_PTR_POISON;
1599 } else {
1600 /* No need to call free_descriptor_buffer here, as
1601 * this is only the txhdr, which is not allocated.
1602 */
1603 if (unlikely(meta->skb)) {
1604 b43dbg(dev->wl, "TX status unexpected non-NULL skb "
1605 "at slot %d (first=%d) on ring %d\n",
1606 slot, firstused, ring->index);
1607 break;
1608 }
1609 }
1610
1611 /* Everything unmapped and free'd. So it's not used anymore. */
1612 ring->used_slots--;
1613
1614 if (meta->is_last_fragment && !skip) {
1615 /* This is the last scatter-gather
1616 * fragment of the frame. We are done. */
1617 break;
1618 }
1619 slot = next_slot(ring, slot);
1620 if (skip > 0)
1621 --skip;
1622 }
1623 if (ring->stopped) {
1624 B43_WARN_ON(free_slots(ring) < TX_SLOTS_PER_FRAME);
1625 ring->stopped = false;
1626 }
1627
1628 if (dev->wl->tx_queue_stopped[ring->queue_prio]) {
1629 dev->wl->tx_queue_stopped[ring->queue_prio] = 0;
1630 } else {
1631 /* If the driver queue is running wake the corresponding
1632 * mac80211 queue. */
1633 ieee80211_wake_queue(dev->wl->hw, ring->queue_prio);
1634 if (b43_debug(dev, B43_DBG_DMAVERBOSE)) {
1635 b43dbg(dev->wl, "Woke up TX ring %d\n", ring->index);
1636 }
1637 }
1638 /* Add work to the queue. */
1639 ieee80211_queue_work(dev->wl->hw, &dev->wl->tx_work);
1640}
1641
1642static void dma_rx(struct b43_dmaring *ring, int *slot)
1643{
1644 const struct b43_dma_ops *ops = ring->ops;
1645 struct b43_dmadesc_generic *desc;
1646 struct b43_dmadesc_meta *meta;
1647 struct b43_rxhdr_fw4 *rxhdr;
1648 struct sk_buff *skb;
1649 u16 len;
1650 int err;
1651 dma_addr_t dmaaddr;
1652
1653 desc = ops->idx2desc(ring, *slot, &meta);
1654
1655 sync_descbuffer_for_cpu(ring, meta->dmaaddr, ring->rx_buffersize);
1656 skb = meta->skb;
1657
1658 rxhdr = (struct b43_rxhdr_fw4 *)skb->data;
1659 len = le16_to_cpu(rxhdr->frame_len);
1660 if (len == 0) {
1661 int i = 0;
1662
1663 do {
1664 udelay(2);
1665 barrier();
1666 len = le16_to_cpu(rxhdr->frame_len);
1667 } while (len == 0 && i++ < 5);
1668 if (unlikely(len == 0)) {
1669 dmaaddr = meta->dmaaddr;
1670 goto drop_recycle_buffer;
1671 }
1672 }
1673 if (unlikely(b43_rx_buffer_is_poisoned(ring, skb))) {
1674 /* Something went wrong with the DMA.
1675 * The device did not touch the buffer and did not overwrite the poison. */
1676 b43dbg(ring->dev->wl, "DMA RX: Dropping poisoned buffer.\n");
1677 dmaaddr = meta->dmaaddr;
1678 goto drop_recycle_buffer;
1679 }
1680 if (unlikely(len + ring->frameoffset > ring->rx_buffersize)) {
1681 /* The data did not fit into one descriptor buffer
1682 * and is split over multiple buffers.
1683 * This should never happen, as we try to allocate buffers
1684 * big enough. So simply ignore this packet.
1685 */
1686 int cnt = 0;
1687 s32 tmp = len;
1688
1689 while (1) {
1690 desc = ops->idx2desc(ring, *slot, &meta);
1691 /* recycle the descriptor buffer. */
1692 b43_poison_rx_buffer(ring, meta->skb);
1693 sync_descbuffer_for_device(ring, meta->dmaaddr,
1694 ring->rx_buffersize);
1695 *slot = next_slot(ring, *slot);
1696 cnt++;
1697 tmp -= ring->rx_buffersize;
1698 if (tmp <= 0)
1699 break;
1700 }
1701 b43err(ring->dev->wl, "DMA RX buffer too small "
1702 "(len: %u, buffer: %u, nr-dropped: %d)\n",
1703 len, ring->rx_buffersize, cnt);
1704 goto drop;
1705 }
1706
1707 dmaaddr = meta->dmaaddr;
1708 err = setup_rx_descbuffer(ring, desc, meta, GFP_ATOMIC);
1709 if (unlikely(err)) {
1710 b43dbg(ring->dev->wl, "DMA RX: setup_rx_descbuffer() failed\n");
1711 goto drop_recycle_buffer;
1712 }
1713
1714 unmap_descbuffer(ring, dmaaddr, ring->rx_buffersize, 0);
1715 skb_put(skb, len + ring->frameoffset);
1716 skb_pull(skb, ring->frameoffset);
1717
1718 b43_rx(ring->dev, skb, rxhdr);
1719drop:
1720 return;
1721
1722drop_recycle_buffer:
1723 /* Poison and recycle the RX buffer. */
1724 b43_poison_rx_buffer(ring, skb);
1725 sync_descbuffer_for_device(ring, dmaaddr, ring->rx_buffersize);
1726}
1727
1728void b43_dma_handle_rx_overflow(struct b43_dmaring *ring)
1729{
1730 int current_slot, previous_slot;
1731
1732 B43_WARN_ON(ring->tx);
1733
1734 /* Device has filled all buffers, drop all packets and let TCP
1735 * decrease speed.
1736 * Decrement RX index by one will let the device to see all slots
1737 * as free again
1738 */
1739 /*
1740 *TODO: How to increase rx_drop in mac80211?
1741 */
1742 current_slot = ring->ops->get_current_rxslot(ring);
1743 previous_slot = prev_slot(ring, current_slot);
1744 ring->ops->set_current_rxslot(ring, previous_slot);
1745}
1746
1747void b43_dma_rx(struct b43_dmaring *ring)
1748{
1749 const struct b43_dma_ops *ops = ring->ops;
1750 int slot, current_slot;
1751 int used_slots = 0;
1752
1753 B43_WARN_ON(ring->tx);
1754 current_slot = ops->get_current_rxslot(ring);
1755 B43_WARN_ON(!(current_slot >= 0 && current_slot < ring->nr_slots));
1756
1757 slot = ring->current_slot;
1758 for (; slot != current_slot; slot = next_slot(ring, slot)) {
1759 dma_rx(ring, &slot);
1760 update_max_used_slots(ring, ++used_slots);
1761 }
1762 wmb();
1763 ops->set_current_rxslot(ring, slot);
1764 ring->current_slot = slot;
1765}
1766
1767static void b43_dma_tx_suspend_ring(struct b43_dmaring *ring)
1768{
1769 B43_WARN_ON(!ring->tx);
1770 ring->ops->tx_suspend(ring);
1771}
1772
1773static void b43_dma_tx_resume_ring(struct b43_dmaring *ring)
1774{
1775 B43_WARN_ON(!ring->tx);
1776 ring->ops->tx_resume(ring);
1777}
1778
1779void b43_dma_tx_suspend(struct b43_wldev *dev)
1780{
1781 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
1782 b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_BK);
1783 b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_BE);
1784 b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_VI);
1785 b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_VO);
1786 b43_dma_tx_suspend_ring(dev->dma.tx_ring_mcast);
1787}
1788
1789void b43_dma_tx_resume(struct b43_wldev *dev)
1790{
1791 b43_dma_tx_resume_ring(dev->dma.tx_ring_mcast);
1792 b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_VO);
1793 b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_VI);
1794 b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_BE);
1795 b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_BK);
1796 b43_power_saving_ctl_bits(dev, 0);
1797}
1798
1799static void direct_fifo_rx(struct b43_wldev *dev, enum b43_dmatype type,
1800 u16 mmio_base, bool enable)
1801{
1802 u32 ctl;
1803
1804 if (type == B43_DMA_64BIT) {
1805 ctl = b43_read32(dev, mmio_base + B43_DMA64_RXCTL);
1806 ctl &= ~B43_DMA64_RXDIRECTFIFO;
1807 if (enable)
1808 ctl |= B43_DMA64_RXDIRECTFIFO;
1809 b43_write32(dev, mmio_base + B43_DMA64_RXCTL, ctl);
1810 } else {
1811 ctl = b43_read32(dev, mmio_base + B43_DMA32_RXCTL);
1812 ctl &= ~B43_DMA32_RXDIRECTFIFO;
1813 if (enable)
1814 ctl |= B43_DMA32_RXDIRECTFIFO;
1815 b43_write32(dev, mmio_base + B43_DMA32_RXCTL, ctl);
1816 }
1817}
1818
1819/* Enable/Disable Direct FIFO Receive Mode (PIO) on a RX engine.
1820 * This is called from PIO code, so DMA structures are not available. */
1821void b43_dma_direct_fifo_rx(struct b43_wldev *dev,
1822 unsigned int engine_index, bool enable)
1823{
1824 enum b43_dmatype type;
1825 u16 mmio_base;
1826
1827 type = dma_mask_to_engine_type(supported_dma_mask(dev));
1828
1829 mmio_base = b43_dmacontroller_base(type, engine_index);
1830 direct_fifo_rx(dev, type, mmio_base, enable);
1831}