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1/*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/nl80211.h>
18#include <linux/pci.h>
19#include <linux/pci-aspm.h>
20#include <linux/ath9k_platform.h>
21#include "ath9k.h"
22
23static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
24 { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */
25 { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
26 { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */
27 { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */
28 { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
29 { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
30 { PCI_VDEVICE(ATHEROS, 0x002C) }, /* PCI-E 802.11n bonded out */
31 { PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI */
32 { PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */
33 { PCI_VDEVICE(ATHEROS, 0x0030) }, /* PCI-E AR9300 */
34 { PCI_VDEVICE(ATHEROS, 0x0032) }, /* PCI-E AR9485 */
35 { 0 }
36};
37
38/* return bus cachesize in 4B word units */
39static void ath_pci_read_cachesize(struct ath_common *common, int *csz)
40{
41 struct ath_softc *sc = (struct ath_softc *) common->priv;
42 u8 u8tmp;
43
44 pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE, &u8tmp);
45 *csz = (int)u8tmp;
46
47 /*
48 * This check was put in to avoid "unpleasant" consequences if
49 * the bootrom has not fully initialized all PCI devices.
50 * Sometimes the cache line size register is not set
51 */
52
53 if (*csz == 0)
54 *csz = DEFAULT_CACHELINE >> 2; /* Use the default size */
55}
56
57static bool ath_pci_eeprom_read(struct ath_common *common, u32 off, u16 *data)
58{
59 struct ath_softc *sc = (struct ath_softc *) common->priv;
60 struct ath9k_platform_data *pdata = sc->dev->platform_data;
61
62 if (pdata) {
63 if (off >= (ARRAY_SIZE(pdata->eeprom_data))) {
64 ath_err(common,
65 "%s: eeprom read failed, offset %08x is out of range\n",
66 __func__, off);
67 }
68
69 *data = pdata->eeprom_data[off];
70 } else {
71 struct ath_hw *ah = (struct ath_hw *) common->ah;
72
73 common->ops->read(ah, AR5416_EEPROM_OFFSET +
74 (off << AR5416_EEPROM_S));
75
76 if (!ath9k_hw_wait(ah,
77 AR_EEPROM_STATUS_DATA,
78 AR_EEPROM_STATUS_DATA_BUSY |
79 AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
80 AH_WAIT_TIMEOUT)) {
81 return false;
82 }
83
84 *data = MS(common->ops->read(ah, AR_EEPROM_STATUS_DATA),
85 AR_EEPROM_STATUS_DATA_VAL);
86 }
87
88 return true;
89}
90
91/*
92 * Bluetooth coexistance requires disabling ASPM.
93 */
94static void ath_pci_bt_coex_prep(struct ath_common *common)
95{
96 struct ath_softc *sc = (struct ath_softc *) common->priv;
97 struct pci_dev *pdev = to_pci_dev(sc->dev);
98 u8 aspm;
99
100 if (!pci_is_pcie(pdev))
101 return;
102
103 pci_read_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, &aspm);
104 aspm &= ~(ATH_PCIE_CAP_LINK_L0S | ATH_PCIE_CAP_LINK_L1);
105 pci_write_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, aspm);
106}
107
108static void ath_pci_extn_synch_enable(struct ath_common *common)
109{
110 struct ath_softc *sc = (struct ath_softc *) common->priv;
111 struct pci_dev *pdev = to_pci_dev(sc->dev);
112 u8 lnkctl;
113
114 pci_read_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, &lnkctl);
115 lnkctl |= PCI_EXP_LNKCTL_ES;
116 pci_write_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, lnkctl);
117}
118
119static void ath_pci_aspm_init(struct ath_common *common)
120{
121 struct ath_softc *sc = (struct ath_softc *) common->priv;
122 struct ath_hw *ah = sc->sc_ah;
123 struct pci_dev *pdev = to_pci_dev(sc->dev);
124 struct pci_dev *parent;
125 int pos;
126 u8 aspm;
127
128 if (!pci_is_pcie(pdev))
129 return;
130
131 parent = pdev->bus->self;
132 if (WARN_ON(!parent))
133 return;
134
135 pos = pci_pcie_cap(parent);
136 pci_read_config_byte(parent, pos + PCI_EXP_LNKCTL, &aspm);
137 if (aspm & (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1)) {
138 ah->aspm_enabled = true;
139 /* Initialize PCIe PM and SERDES registers. */
140 ath9k_hw_configpcipowersave(ah, 0, 0);
141 }
142}
143
144static const struct ath_bus_ops ath_pci_bus_ops = {
145 .ath_bus_type = ATH_PCI,
146 .read_cachesize = ath_pci_read_cachesize,
147 .eeprom_read = ath_pci_eeprom_read,
148 .bt_coex_prep = ath_pci_bt_coex_prep,
149 .extn_synch_en = ath_pci_extn_synch_enable,
150 .aspm_init = ath_pci_aspm_init,
151};
152
153static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
154{
155 void __iomem *mem;
156 struct ath_softc *sc;
157 struct ieee80211_hw *hw;
158 u8 csz;
159 u16 subsysid;
160 u32 val;
161 int ret = 0;
162 char hw_name[64];
163
164 if (pci_enable_device(pdev))
165 return -EIO;
166
167 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
168 if (ret) {
169 printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
170 goto err_dma;
171 }
172
173 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
174 if (ret) {
175 printk(KERN_ERR "ath9k: 32-bit DMA consistent "
176 "DMA enable failed\n");
177 goto err_dma;
178 }
179
180 /*
181 * Cache line size is used to size and align various
182 * structures used to communicate with the hardware.
183 */
184 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
185 if (csz == 0) {
186 /*
187 * Linux 2.4.18 (at least) writes the cache line size
188 * register as a 16-bit wide register which is wrong.
189 * We must have this setup properly for rx buffer
190 * DMA to work so force a reasonable value here if it
191 * comes up zero.
192 */
193 csz = L1_CACHE_BYTES / sizeof(u32);
194 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
195 }
196 /*
197 * The default setting of latency timer yields poor results,
198 * set it to the value used by other systems. It may be worth
199 * tweaking this setting more.
200 */
201 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
202
203 pci_set_master(pdev);
204
205 /*
206 * Disable the RETRY_TIMEOUT register (0x41) to keep
207 * PCI Tx retries from interfering with C3 CPU state.
208 */
209 pci_read_config_dword(pdev, 0x40, &val);
210 if ((val & 0x0000ff00) != 0)
211 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
212
213 ret = pci_request_region(pdev, 0, "ath9k");
214 if (ret) {
215 dev_err(&pdev->dev, "PCI memory region reserve error\n");
216 ret = -ENODEV;
217 goto err_region;
218 }
219
220 mem = pci_iomap(pdev, 0, 0);
221 if (!mem) {
222 printk(KERN_ERR "PCI memory map error\n") ;
223 ret = -EIO;
224 goto err_iomap;
225 }
226
227 hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
228 if (!hw) {
229 dev_err(&pdev->dev, "No memory for ieee80211_hw\n");
230 ret = -ENOMEM;
231 goto err_alloc_hw;
232 }
233
234 SET_IEEE80211_DEV(hw, &pdev->dev);
235 pci_set_drvdata(pdev, hw);
236
237 sc = hw->priv;
238 sc->hw = hw;
239 sc->dev = &pdev->dev;
240 sc->mem = mem;
241
242 /* Will be cleared in ath9k_start() */
243 sc->sc_flags |= SC_OP_INVALID;
244
245 ret = request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath9k", sc);
246 if (ret) {
247 dev_err(&pdev->dev, "request_irq failed\n");
248 goto err_irq;
249 }
250
251 sc->irq = pdev->irq;
252
253 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &subsysid);
254 ret = ath9k_init_device(id->device, sc, subsysid, &ath_pci_bus_ops);
255 if (ret) {
256 dev_err(&pdev->dev, "Failed to initialize device\n");
257 goto err_init;
258 }
259
260 ath9k_hw_name(sc->sc_ah, hw_name, sizeof(hw_name));
261 wiphy_info(hw->wiphy, "%s mem=0x%lx, irq=%d\n",
262 hw_name, (unsigned long)mem, pdev->irq);
263
264 return 0;
265
266err_init:
267 free_irq(sc->irq, sc);
268err_irq:
269 ieee80211_free_hw(hw);
270err_alloc_hw:
271 pci_iounmap(pdev, mem);
272err_iomap:
273 pci_release_region(pdev, 0);
274err_region:
275 /* Nothing */
276err_dma:
277 pci_disable_device(pdev);
278 return ret;
279}
280
281static void ath_pci_remove(struct pci_dev *pdev)
282{
283 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
284 struct ath_softc *sc = hw->priv;
285 void __iomem *mem = sc->mem;
286
287 if (!is_ath9k_unloaded)
288 sc->sc_ah->ah_flags |= AH_UNPLUGGED;
289 ath9k_deinit_device(sc);
290 free_irq(sc->irq, sc);
291 ieee80211_free_hw(sc->hw);
292
293 pci_iounmap(pdev, mem);
294 pci_disable_device(pdev);
295 pci_release_region(pdev, 0);
296}
297
298#ifdef CONFIG_PM
299
300static int ath_pci_suspend(struct device *device)
301{
302 struct pci_dev *pdev = to_pci_dev(device);
303 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
304 struct ath_softc *sc = hw->priv;
305
306 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
307
308 /* The device has to be moved to FULLSLEEP forcibly.
309 * Otherwise the chip never moved to full sleep,
310 * when no interface is up.
311 */
312 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
313
314 return 0;
315}
316
317static int ath_pci_resume(struct device *device)
318{
319 struct pci_dev *pdev = to_pci_dev(device);
320 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
321 struct ath_softc *sc = hw->priv;
322 u32 val;
323
324 /*
325 * Suspend/Resume resets the PCI configuration space, so we have to
326 * re-disable the RETRY_TIMEOUT register (0x41) to keep
327 * PCI Tx retries from interfering with C3 CPU state
328 */
329 pci_read_config_dword(pdev, 0x40, &val);
330 if ((val & 0x0000ff00) != 0)
331 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
332
333 /* Enable LED */
334 ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
335 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
336 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
337
338 /*
339 * Reset key cache to sane defaults (all entries cleared) instead of
340 * semi-random values after suspend/resume.
341 */
342 ath9k_ps_wakeup(sc);
343 ath9k_init_crypto(sc);
344 ath9k_ps_restore(sc);
345
346 sc->ps_idle = true;
347 ath_radio_disable(sc, hw);
348
349 return 0;
350}
351
352static const struct dev_pm_ops ath9k_pm_ops = {
353 .suspend = ath_pci_suspend,
354 .resume = ath_pci_resume,
355 .freeze = ath_pci_suspend,
356 .thaw = ath_pci_resume,
357 .poweroff = ath_pci_suspend,
358 .restore = ath_pci_resume,
359};
360
361#define ATH9K_PM_OPS (&ath9k_pm_ops)
362
363#else /* !CONFIG_PM */
364
365#define ATH9K_PM_OPS NULL
366
367#endif /* !CONFIG_PM */
368
369
370MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
371
372static struct pci_driver ath_pci_driver = {
373 .name = "ath9k",
374 .id_table = ath_pci_id_table,
375 .probe = ath_pci_probe,
376 .remove = ath_pci_remove,
377 .driver.pm = ATH9K_PM_OPS,
378};
379
380int ath_pci_init(void)
381{
382 return pci_register_driver(&ath_pci_driver);
383}
384
385void ath_pci_exit(void)
386{
387 pci_unregister_driver(&ath_pci_driver);
388}
1/*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18
19#include <linux/nl80211.h>
20#include <linux/pci.h>
21#include <linux/pci-aspm.h>
22#include <linux/ath9k_platform.h>
23#include <linux/module.h>
24#include "ath9k.h"
25
26static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
27 { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */
28 { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
29 { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */
30 { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */
31 { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
32
33 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
34 0x002A,
35 PCI_VENDOR_ID_AZWAVE,
36 0x1C71),
37 .driver_data = ATH9K_PCI_D3_L1_WAR },
38 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
39 0x002A,
40 PCI_VENDOR_ID_FOXCONN,
41 0xE01F),
42 .driver_data = ATH9K_PCI_D3_L1_WAR },
43 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
44 0x002A,
45 0x11AD, /* LITEON */
46 0x6632),
47 .driver_data = ATH9K_PCI_D3_L1_WAR },
48 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
49 0x002A,
50 0x11AD, /* LITEON */
51 0x6642),
52 .driver_data = ATH9K_PCI_D3_L1_WAR },
53 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
54 0x002A,
55 PCI_VENDOR_ID_QMI,
56 0x0306),
57 .driver_data = ATH9K_PCI_D3_L1_WAR },
58 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
59 0x002A,
60 0x185F, /* WNC */
61 0x309D),
62 .driver_data = ATH9K_PCI_D3_L1_WAR },
63 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
64 0x002A,
65 0x10CF, /* Fujitsu */
66 0x147C),
67 .driver_data = ATH9K_PCI_D3_L1_WAR },
68 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
69 0x002A,
70 0x10CF, /* Fujitsu */
71 0x147D),
72 .driver_data = ATH9K_PCI_D3_L1_WAR },
73 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
74 0x002A,
75 0x10CF, /* Fujitsu */
76 0x1536),
77 .driver_data = ATH9K_PCI_D3_L1_WAR },
78
79 /* AR9285 card for Asus */
80 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
81 0x002B,
82 PCI_VENDOR_ID_AZWAVE,
83 0x2C37),
84 .driver_data = ATH9K_PCI_BT_ANT_DIV },
85
86 { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
87 { PCI_VDEVICE(ATHEROS, 0x002C) }, /* PCI-E 802.11n bonded out */
88 { PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI */
89 { PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */
90
91 /* Killer Wireless (3x3) */
92 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
93 0x0030,
94 0x1A56,
95 0x2000),
96 .driver_data = ATH9K_PCI_KILLER },
97 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
98 0x0030,
99 0x1A56,
100 0x2001),
101 .driver_data = ATH9K_PCI_KILLER },
102
103 { PCI_VDEVICE(ATHEROS, 0x0030) }, /* PCI-E AR9300 */
104
105 /* PCI-E CUS198 */
106 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
107 0x0032,
108 PCI_VENDOR_ID_AZWAVE,
109 0x2086),
110 .driver_data = ATH9K_PCI_CUS198 | ATH9K_PCI_BT_ANT_DIV },
111 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
112 0x0032,
113 PCI_VENDOR_ID_AZWAVE,
114 0x1237),
115 .driver_data = ATH9K_PCI_CUS198 | ATH9K_PCI_BT_ANT_DIV },
116 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
117 0x0032,
118 PCI_VENDOR_ID_AZWAVE,
119 0x2126),
120 .driver_data = ATH9K_PCI_CUS198 | ATH9K_PCI_BT_ANT_DIV },
121 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
122 0x0032,
123 PCI_VENDOR_ID_AZWAVE,
124 0x126A),
125 .driver_data = ATH9K_PCI_CUS198 | ATH9K_PCI_BT_ANT_DIV },
126
127 /* PCI-E CUS230 */
128 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
129 0x0032,
130 PCI_VENDOR_ID_AZWAVE,
131 0x2152),
132 .driver_data = ATH9K_PCI_CUS230 | ATH9K_PCI_BT_ANT_DIV },
133 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
134 0x0032,
135 PCI_VENDOR_ID_FOXCONN,
136 0xE075),
137 .driver_data = ATH9K_PCI_CUS230 | ATH9K_PCI_BT_ANT_DIV },
138
139 /* WB225 */
140 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
141 0x0032,
142 PCI_VENDOR_ID_ATHEROS,
143 0x3119),
144 .driver_data = ATH9K_PCI_BT_ANT_DIV },
145 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
146 0x0032,
147 PCI_VENDOR_ID_ATHEROS,
148 0x3122),
149 .driver_data = ATH9K_PCI_BT_ANT_DIV },
150 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
151 0x0032,
152 0x185F, /* WNC */
153 0x3119),
154 .driver_data = ATH9K_PCI_BT_ANT_DIV },
155 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
156 0x0032,
157 0x185F, /* WNC */
158 0x3027),
159 .driver_data = ATH9K_PCI_BT_ANT_DIV },
160 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
161 0x0032,
162 PCI_VENDOR_ID_SAMSUNG,
163 0x4105),
164 .driver_data = ATH9K_PCI_BT_ANT_DIV },
165 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
166 0x0032,
167 PCI_VENDOR_ID_SAMSUNG,
168 0x4106),
169 .driver_data = ATH9K_PCI_BT_ANT_DIV },
170 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
171 0x0032,
172 PCI_VENDOR_ID_SAMSUNG,
173 0x410D),
174 .driver_data = ATH9K_PCI_BT_ANT_DIV },
175 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
176 0x0032,
177 PCI_VENDOR_ID_SAMSUNG,
178 0x410E),
179 .driver_data = ATH9K_PCI_BT_ANT_DIV },
180 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
181 0x0032,
182 PCI_VENDOR_ID_SAMSUNG,
183 0x410F),
184 .driver_data = ATH9K_PCI_BT_ANT_DIV },
185 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
186 0x0032,
187 PCI_VENDOR_ID_SAMSUNG,
188 0xC706),
189 .driver_data = ATH9K_PCI_BT_ANT_DIV },
190 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
191 0x0032,
192 PCI_VENDOR_ID_SAMSUNG,
193 0xC680),
194 .driver_data = ATH9K_PCI_BT_ANT_DIV },
195 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
196 0x0032,
197 PCI_VENDOR_ID_SAMSUNG,
198 0xC708),
199 .driver_data = ATH9K_PCI_BT_ANT_DIV },
200 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
201 0x0032,
202 PCI_VENDOR_ID_LENOVO,
203 0x3218),
204 .driver_data = ATH9K_PCI_BT_ANT_DIV },
205 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
206 0x0032,
207 PCI_VENDOR_ID_LENOVO,
208 0x3219),
209 .driver_data = ATH9K_PCI_BT_ANT_DIV },
210
211 /* AR9485 cards with PLL power-save disabled by default. */
212 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
213 0x0032,
214 PCI_VENDOR_ID_AZWAVE,
215 0x2C97),
216 .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
217 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
218 0x0032,
219 PCI_VENDOR_ID_AZWAVE,
220 0x2100),
221 .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
222 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
223 0x0032,
224 0x1C56, /* ASKEY */
225 0x4001),
226 .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
227 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
228 0x0032,
229 0x11AD, /* LITEON */
230 0x6627),
231 .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
232 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
233 0x0032,
234 0x11AD, /* LITEON */
235 0x6628),
236 .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
237 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
238 0x0032,
239 PCI_VENDOR_ID_FOXCONN,
240 0xE04E),
241 .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
242 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
243 0x0032,
244 PCI_VENDOR_ID_FOXCONN,
245 0xE04F),
246 .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
247 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
248 0x0032,
249 0x144F, /* ASKEY */
250 0x7197),
251 .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
252 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
253 0x0032,
254 0x1B9A, /* XAVI */
255 0x2000),
256 .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
257 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
258 0x0032,
259 0x1B9A, /* XAVI */
260 0x2001),
261 .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
262 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
263 0x0032,
264 PCI_VENDOR_ID_AZWAVE,
265 0x1186),
266 .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
267 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
268 0x0032,
269 PCI_VENDOR_ID_AZWAVE,
270 0x1F86),
271 .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
272 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
273 0x0032,
274 PCI_VENDOR_ID_AZWAVE,
275 0x1195),
276 .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
277 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
278 0x0032,
279 PCI_VENDOR_ID_AZWAVE,
280 0x1F95),
281 .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
282 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
283 0x0032,
284 0x1B9A, /* XAVI */
285 0x1C00),
286 .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
287 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
288 0x0032,
289 0x1B9A, /* XAVI */
290 0x1C01),
291 .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
292 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
293 0x0032,
294 PCI_VENDOR_ID_ASUSTEK,
295 0x850D),
296 .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
297
298 { PCI_VDEVICE(ATHEROS, 0x0032) }, /* PCI-E AR9485 */
299 { PCI_VDEVICE(ATHEROS, 0x0033) }, /* PCI-E AR9580 */
300
301 /* PCI-E CUS217 */
302 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
303 0x0034,
304 PCI_VENDOR_ID_AZWAVE,
305 0x2116),
306 .driver_data = ATH9K_PCI_CUS217 },
307 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
308 0x0034,
309 0x11AD, /* LITEON */
310 0x6661),
311 .driver_data = ATH9K_PCI_CUS217 },
312
313 /* AR9462 with WoW support */
314 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
315 0x0034,
316 PCI_VENDOR_ID_ATHEROS,
317 0x3117),
318 .driver_data = ATH9K_PCI_WOW },
319 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
320 0x0034,
321 PCI_VENDOR_ID_LENOVO,
322 0x3214),
323 .driver_data = ATH9K_PCI_WOW },
324 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
325 0x0034,
326 PCI_VENDOR_ID_ATTANSIC,
327 0x0091),
328 .driver_data = ATH9K_PCI_WOW },
329 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
330 0x0034,
331 PCI_VENDOR_ID_AZWAVE,
332 0x2110),
333 .driver_data = ATH9K_PCI_WOW },
334 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
335 0x0034,
336 PCI_VENDOR_ID_ASUSTEK,
337 0x850E),
338 .driver_data = ATH9K_PCI_WOW },
339 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
340 0x0034,
341 0x11AD, /* LITEON */
342 0x6631),
343 .driver_data = ATH9K_PCI_WOW },
344 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
345 0x0034,
346 0x11AD, /* LITEON */
347 0x6641),
348 .driver_data = ATH9K_PCI_WOW },
349 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
350 0x0034,
351 PCI_VENDOR_ID_HP,
352 0x1864),
353 .driver_data = ATH9K_PCI_WOW },
354 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
355 0x0034,
356 0x14CD, /* USI */
357 0x0063),
358 .driver_data = ATH9K_PCI_WOW },
359 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
360 0x0034,
361 0x14CD, /* USI */
362 0x0064),
363 .driver_data = ATH9K_PCI_WOW },
364 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
365 0x0034,
366 0x10CF, /* Fujitsu */
367 0x1783),
368 .driver_data = ATH9K_PCI_WOW },
369
370 /* Killer Wireless (2x2) */
371 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
372 0x0030,
373 0x1A56,
374 0x2003),
375 .driver_data = ATH9K_PCI_KILLER },
376
377 { PCI_VDEVICE(ATHEROS, 0x0034) }, /* PCI-E AR9462 */
378 { PCI_VDEVICE(ATHEROS, 0x0037) }, /* PCI-E AR1111/AR9485 */
379
380 /* CUS252 */
381 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
382 0x0036,
383 PCI_VENDOR_ID_ATHEROS,
384 0x3028),
385 .driver_data = ATH9K_PCI_CUS252 |
386 ATH9K_PCI_AR9565_2ANT |
387 ATH9K_PCI_BT_ANT_DIV },
388 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
389 0x0036,
390 PCI_VENDOR_ID_AZWAVE,
391 0x2176),
392 .driver_data = ATH9K_PCI_CUS252 |
393 ATH9K_PCI_AR9565_2ANT |
394 ATH9K_PCI_BT_ANT_DIV },
395
396 /* WB335 1-ANT */
397 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
398 0x0036,
399 PCI_VENDOR_ID_FOXCONN,
400 0xE068),
401 .driver_data = ATH9K_PCI_AR9565_1ANT },
402 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
403 0x0036,
404 0x185F, /* WNC */
405 0xA119),
406 .driver_data = ATH9K_PCI_AR9565_1ANT },
407 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
408 0x0036,
409 0x11AD, /* LITEON */
410 0x0632),
411 .driver_data = ATH9K_PCI_AR9565_1ANT },
412 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
413 0x0036,
414 0x11AD, /* LITEON */
415 0x06B2),
416 .driver_data = ATH9K_PCI_AR9565_1ANT },
417 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
418 0x0036,
419 0x11AD, /* LITEON */
420 0x0842),
421 .driver_data = ATH9K_PCI_AR9565_1ANT },
422 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
423 0x0036,
424 0x11AD, /* LITEON */
425 0x6671),
426 .driver_data = ATH9K_PCI_AR9565_1ANT },
427 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
428 0x0036,
429 0x1B9A, /* XAVI */
430 0x2811),
431 .driver_data = ATH9K_PCI_AR9565_1ANT },
432 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
433 0x0036,
434 0x1B9A, /* XAVI */
435 0x2812),
436 .driver_data = ATH9K_PCI_AR9565_1ANT },
437 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
438 0x0036,
439 0x1B9A, /* XAVI */
440 0x28A1),
441 .driver_data = ATH9K_PCI_AR9565_1ANT },
442 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
443 0x0036,
444 PCI_VENDOR_ID_AZWAVE,
445 0x218A),
446 .driver_data = ATH9K_PCI_AR9565_1ANT },
447
448 /* WB335 1-ANT / Antenna Diversity */
449 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
450 0x0036,
451 PCI_VENDOR_ID_ATHEROS,
452 0x3025),
453 .driver_data = ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_BT_ANT_DIV },
454 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
455 0x0036,
456 PCI_VENDOR_ID_ATHEROS,
457 0x3026),
458 .driver_data = ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_BT_ANT_DIV },
459 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
460 0x0036,
461 PCI_VENDOR_ID_ATHEROS,
462 0x302B),
463 .driver_data = ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_BT_ANT_DIV },
464 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
465 0x0036,
466 PCI_VENDOR_ID_FOXCONN,
467 0xE069),
468 .driver_data = ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_BT_ANT_DIV },
469 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
470 0x0036,
471 0x185F, /* WNC */
472 0x3028),
473 .driver_data = ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_BT_ANT_DIV },
474 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
475 0x0036,
476 0x11AD, /* LITEON */
477 0x0622),
478 .driver_data = ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_BT_ANT_DIV },
479 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
480 0x0036,
481 0x11AD, /* LITEON */
482 0x0672),
483 .driver_data = ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_BT_ANT_DIV },
484 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
485 0x0036,
486 0x11AD, /* LITEON */
487 0x0662),
488 .driver_data = ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_BT_ANT_DIV },
489 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
490 0x0036,
491 0x11AD, /* LITEON */
492 0x06A2),
493 .driver_data = ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_BT_ANT_DIV },
494 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
495 0x0036,
496 0x11AD, /* LITEON */
497 0x0682),
498 .driver_data = ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_BT_ANT_DIV },
499 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
500 0x0036,
501 PCI_VENDOR_ID_AZWAVE,
502 0x213A),
503 .driver_data = ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_BT_ANT_DIV },
504 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
505 0x0036,
506 PCI_VENDOR_ID_HP,
507 0x18E3),
508 .driver_data = ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_BT_ANT_DIV },
509 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
510 0x0036,
511 PCI_VENDOR_ID_HP,
512 0x217F),
513 .driver_data = ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_BT_ANT_DIV },
514 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
515 0x0036,
516 PCI_VENDOR_ID_HP,
517 0x2005),
518 .driver_data = ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_BT_ANT_DIV },
519 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
520 0x0036,
521 PCI_VENDOR_ID_DELL,
522 0x020C),
523 .driver_data = ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_BT_ANT_DIV },
524
525 /* WB335 2-ANT / Antenna-Diversity */
526 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
527 0x0036,
528 PCI_VENDOR_ID_SAMSUNG,
529 0x411A),
530 .driver_data = ATH9K_PCI_AR9565_2ANT | ATH9K_PCI_BT_ANT_DIV },
531 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
532 0x0036,
533 PCI_VENDOR_ID_SAMSUNG,
534 0x411B),
535 .driver_data = ATH9K_PCI_AR9565_2ANT | ATH9K_PCI_BT_ANT_DIV },
536 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
537 0x0036,
538 PCI_VENDOR_ID_SAMSUNG,
539 0x411C),
540 .driver_data = ATH9K_PCI_AR9565_2ANT | ATH9K_PCI_BT_ANT_DIV },
541 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
542 0x0036,
543 PCI_VENDOR_ID_SAMSUNG,
544 0x411D),
545 .driver_data = ATH9K_PCI_AR9565_2ANT | ATH9K_PCI_BT_ANT_DIV },
546 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
547 0x0036,
548 PCI_VENDOR_ID_SAMSUNG,
549 0x411E),
550 .driver_data = ATH9K_PCI_AR9565_2ANT | ATH9K_PCI_BT_ANT_DIV },
551 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
552 0x0036,
553 PCI_VENDOR_ID_ATHEROS,
554 0x3027),
555 .driver_data = ATH9K_PCI_AR9565_2ANT | ATH9K_PCI_BT_ANT_DIV },
556 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
557 0x0036,
558 PCI_VENDOR_ID_ATHEROS,
559 0x302C),
560 .driver_data = ATH9K_PCI_AR9565_2ANT | ATH9K_PCI_BT_ANT_DIV },
561 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
562 0x0036,
563 0x11AD, /* LITEON */
564 0x0642),
565 .driver_data = ATH9K_PCI_AR9565_2ANT | ATH9K_PCI_BT_ANT_DIV },
566 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
567 0x0036,
568 0x11AD, /* LITEON */
569 0x0652),
570 .driver_data = ATH9K_PCI_AR9565_2ANT | ATH9K_PCI_BT_ANT_DIV },
571 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
572 0x0036,
573 0x11AD, /* LITEON */
574 0x0612),
575 .driver_data = ATH9K_PCI_AR9565_2ANT | ATH9K_PCI_BT_ANT_DIV },
576 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
577 0x0036,
578 0x11AD, /* LITEON */
579 0x0832),
580 .driver_data = ATH9K_PCI_AR9565_2ANT | ATH9K_PCI_BT_ANT_DIV },
581 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
582 0x0036,
583 0x11AD, /* LITEON */
584 0x0692),
585 .driver_data = ATH9K_PCI_AR9565_2ANT | ATH9K_PCI_BT_ANT_DIV },
586 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
587 0x0036,
588 PCI_VENDOR_ID_AZWAVE,
589 0x2130),
590 .driver_data = ATH9K_PCI_AR9565_2ANT | ATH9K_PCI_BT_ANT_DIV },
591 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
592 0x0036,
593 PCI_VENDOR_ID_AZWAVE,
594 0x213B),
595 .driver_data = ATH9K_PCI_AR9565_2ANT | ATH9K_PCI_BT_ANT_DIV },
596 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
597 0x0036,
598 PCI_VENDOR_ID_AZWAVE,
599 0x2182),
600 .driver_data = ATH9K_PCI_AR9565_2ANT | ATH9K_PCI_BT_ANT_DIV },
601 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
602 0x0036,
603 0x144F, /* ASKEY */
604 0x7202),
605 .driver_data = ATH9K_PCI_AR9565_2ANT | ATH9K_PCI_BT_ANT_DIV },
606 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
607 0x0036,
608 0x1B9A, /* XAVI */
609 0x2810),
610 .driver_data = ATH9K_PCI_AR9565_2ANT | ATH9K_PCI_BT_ANT_DIV },
611 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
612 0x0036,
613 0x1B9A, /* XAVI */
614 0x28A2),
615 .driver_data = ATH9K_PCI_AR9565_2ANT | ATH9K_PCI_BT_ANT_DIV },
616 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
617 0x0036,
618 0x185F, /* WNC */
619 0x3027),
620 .driver_data = ATH9K_PCI_AR9565_2ANT | ATH9K_PCI_BT_ANT_DIV },
621 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
622 0x0036,
623 0x185F, /* WNC */
624 0xA120),
625 .driver_data = ATH9K_PCI_AR9565_2ANT | ATH9K_PCI_BT_ANT_DIV },
626 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
627 0x0036,
628 PCI_VENDOR_ID_FOXCONN,
629 0xE07F),
630 .driver_data = ATH9K_PCI_AR9565_2ANT | ATH9K_PCI_BT_ANT_DIV },
631 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
632 0x0036,
633 PCI_VENDOR_ID_FOXCONN,
634 0xE081),
635 .driver_data = ATH9K_PCI_AR9565_2ANT | ATH9K_PCI_BT_ANT_DIV },
636 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
637 0x0036,
638 PCI_VENDOR_ID_LENOVO,
639 0x3026),
640 .driver_data = ATH9K_PCI_AR9565_2ANT | ATH9K_PCI_BT_ANT_DIV },
641 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
642 0x0036,
643 PCI_VENDOR_ID_LENOVO,
644 0x4026),
645 .driver_data = ATH9K_PCI_AR9565_2ANT | ATH9K_PCI_BT_ANT_DIV },
646 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
647 0x0036,
648 PCI_VENDOR_ID_ASUSTEK,
649 0x85F2),
650 .driver_data = ATH9K_PCI_AR9565_2ANT | ATH9K_PCI_BT_ANT_DIV },
651 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
652 0x0036,
653 PCI_VENDOR_ID_DELL,
654 0x020E),
655 .driver_data = ATH9K_PCI_AR9565_2ANT | ATH9K_PCI_BT_ANT_DIV },
656
657 /* PCI-E AR9565 (WB335) */
658 { PCI_VDEVICE(ATHEROS, 0x0036),
659 .driver_data = ATH9K_PCI_BT_ANT_DIV },
660
661 { 0 }
662};
663
664
665/* return bus cachesize in 4B word units */
666static void ath_pci_read_cachesize(struct ath_common *common, int *csz)
667{
668 struct ath_softc *sc = (struct ath_softc *) common->priv;
669 u8 u8tmp;
670
671 pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE, &u8tmp);
672 *csz = (int)u8tmp;
673
674 /*
675 * This check was put in to avoid "unpleasant" consequences if
676 * the bootrom has not fully initialized all PCI devices.
677 * Sometimes the cache line size register is not set
678 */
679
680 if (*csz == 0)
681 *csz = DEFAULT_CACHELINE >> 2; /* Use the default size */
682}
683
684static bool ath_pci_eeprom_read(struct ath_common *common, u32 off, u16 *data)
685{
686 struct ath_softc *sc = (struct ath_softc *) common->priv;
687 struct ath9k_platform_data *pdata = sc->dev->platform_data;
688
689 if (pdata) {
690 if (off >= (ARRAY_SIZE(pdata->eeprom_data))) {
691 ath_err(common,
692 "%s: eeprom read failed, offset %08x is out of range\n",
693 __func__, off);
694 }
695
696 *data = pdata->eeprom_data[off];
697 } else {
698 struct ath_hw *ah = (struct ath_hw *) common->ah;
699
700 common->ops->read(ah, AR5416_EEPROM_OFFSET +
701 (off << AR5416_EEPROM_S));
702
703 if (!ath9k_hw_wait(ah,
704 AR_EEPROM_STATUS_DATA,
705 AR_EEPROM_STATUS_DATA_BUSY |
706 AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
707 AH_WAIT_TIMEOUT)) {
708 return false;
709 }
710
711 *data = MS(common->ops->read(ah, AR_EEPROM_STATUS_DATA),
712 AR_EEPROM_STATUS_DATA_VAL);
713 }
714
715 return true;
716}
717
718/* Need to be called after we discover btcoex capabilities */
719static void ath_pci_aspm_init(struct ath_common *common)
720{
721 struct ath_softc *sc = (struct ath_softc *) common->priv;
722 struct ath_hw *ah = sc->sc_ah;
723 struct pci_dev *pdev = to_pci_dev(sc->dev);
724 struct pci_dev *parent;
725 u16 aspm;
726
727 if (!ah->is_pciexpress)
728 return;
729
730 parent = pdev->bus->self;
731 if (!parent)
732 return;
733
734 if ((ath9k_hw_get_btcoex_scheme(ah) != ATH_BTCOEX_CFG_NONE) &&
735 (AR_SREV_9285(ah))) {
736 /* Bluetooth coexistence requires disabling ASPM. */
737 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
738 PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1);
739
740 /*
741 * Both upstream and downstream PCIe components should
742 * have the same ASPM settings.
743 */
744 pcie_capability_clear_word(parent, PCI_EXP_LNKCTL,
745 PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1);
746
747 ath_info(common, "Disabling ASPM since BTCOEX is enabled\n");
748 return;
749 }
750
751 /*
752 * 0x70c - Ack Frequency Register.
753 *
754 * Bits 27:29 - DEFAULT_L1_ENTRANCE_LATENCY.
755 *
756 * 000 : 1 us
757 * 001 : 2 us
758 * 010 : 4 us
759 * 011 : 8 us
760 * 100 : 16 us
761 * 101 : 32 us
762 * 110/111 : 64 us
763 */
764 if (AR_SREV_9462(ah))
765 pci_read_config_dword(pdev, 0x70c, &ah->config.aspm_l1_fix);
766
767 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &aspm);
768 if (aspm & (PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1)) {
769 ah->aspm_enabled = true;
770 /* Initialize PCIe PM and SERDES registers. */
771 ath9k_hw_configpcipowersave(ah, false);
772 ath_info(common, "ASPM enabled: 0x%x\n", aspm);
773 }
774}
775
776static const struct ath_bus_ops ath_pci_bus_ops = {
777 .ath_bus_type = ATH_PCI,
778 .read_cachesize = ath_pci_read_cachesize,
779 .eeprom_read = ath_pci_eeprom_read,
780 .aspm_init = ath_pci_aspm_init,
781};
782
783static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
784{
785 struct ath_softc *sc;
786 struct ieee80211_hw *hw;
787 u8 csz;
788 u32 val;
789 int ret = 0;
790 char hw_name[64];
791
792 if (pcim_enable_device(pdev))
793 return -EIO;
794
795 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
796 if (ret) {
797 pr_err("32-bit DMA not available\n");
798 return ret;
799 }
800
801 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
802 if (ret) {
803 pr_err("32-bit DMA consistent DMA enable failed\n");
804 return ret;
805 }
806
807 /*
808 * Cache line size is used to size and align various
809 * structures used to communicate with the hardware.
810 */
811 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
812 if (csz == 0) {
813 /*
814 * Linux 2.4.18 (at least) writes the cache line size
815 * register as a 16-bit wide register which is wrong.
816 * We must have this setup properly for rx buffer
817 * DMA to work so force a reasonable value here if it
818 * comes up zero.
819 */
820 csz = L1_CACHE_BYTES / sizeof(u32);
821 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
822 }
823 /*
824 * The default setting of latency timer yields poor results,
825 * set it to the value used by other systems. It may be worth
826 * tweaking this setting more.
827 */
828 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
829
830 pci_set_master(pdev);
831
832 /*
833 * Disable the RETRY_TIMEOUT register (0x41) to keep
834 * PCI Tx retries from interfering with C3 CPU state.
835 */
836 pci_read_config_dword(pdev, 0x40, &val);
837 if ((val & 0x0000ff00) != 0)
838 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
839
840 ret = pcim_iomap_regions(pdev, BIT(0), "ath9k");
841 if (ret) {
842 dev_err(&pdev->dev, "PCI memory region reserve error\n");
843 return -ENODEV;
844 }
845
846 hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
847 if (!hw) {
848 dev_err(&pdev->dev, "No memory for ieee80211_hw\n");
849 return -ENOMEM;
850 }
851
852 SET_IEEE80211_DEV(hw, &pdev->dev);
853 pci_set_drvdata(pdev, hw);
854
855 sc = hw->priv;
856 sc->hw = hw;
857 sc->dev = &pdev->dev;
858 sc->mem = pcim_iomap_table(pdev)[0];
859 sc->driver_data = id->driver_data;
860
861 ret = request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath9k", sc);
862 if (ret) {
863 dev_err(&pdev->dev, "request_irq failed\n");
864 goto err_irq;
865 }
866
867 sc->irq = pdev->irq;
868
869 ret = ath9k_init_device(id->device, sc, &ath_pci_bus_ops);
870 if (ret) {
871 dev_err(&pdev->dev, "Failed to initialize device\n");
872 goto err_init;
873 }
874
875 ath9k_hw_name(sc->sc_ah, hw_name, sizeof(hw_name));
876 wiphy_info(hw->wiphy, "%s mem=0x%lx, irq=%d\n",
877 hw_name, (unsigned long)sc->mem, pdev->irq);
878
879 return 0;
880
881err_init:
882 free_irq(sc->irq, sc);
883err_irq:
884 ieee80211_free_hw(hw);
885 return ret;
886}
887
888static void ath_pci_remove(struct pci_dev *pdev)
889{
890 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
891 struct ath_softc *sc = hw->priv;
892
893 if (!is_ath9k_unloaded)
894 sc->sc_ah->ah_flags |= AH_UNPLUGGED;
895 ath9k_deinit_device(sc);
896 free_irq(sc->irq, sc);
897 ieee80211_free_hw(sc->hw);
898}
899
900#ifdef CONFIG_PM_SLEEP
901
902static int ath_pci_suspend(struct device *device)
903{
904 struct pci_dev *pdev = to_pci_dev(device);
905 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
906 struct ath_softc *sc = hw->priv;
907
908 if (sc->wow_enabled)
909 return 0;
910
911 /* The device has to be moved to FULLSLEEP forcibly.
912 * Otherwise the chip never moved to full sleep,
913 * when no interface is up.
914 */
915 ath9k_stop_btcoex(sc);
916 ath9k_hw_disable(sc->sc_ah);
917 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
918
919 return 0;
920}
921
922static int ath_pci_resume(struct device *device)
923{
924 struct pci_dev *pdev = to_pci_dev(device);
925 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
926 struct ath_softc *sc = hw->priv;
927 struct ath_hw *ah = sc->sc_ah;
928 struct ath_common *common = ath9k_hw_common(ah);
929 u32 val;
930
931 /*
932 * Suspend/Resume resets the PCI configuration space, so we have to
933 * re-disable the RETRY_TIMEOUT register (0x41) to keep
934 * PCI Tx retries from interfering with C3 CPU state
935 */
936 pci_read_config_dword(pdev, 0x40, &val);
937 if ((val & 0x0000ff00) != 0)
938 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
939
940 ath_pci_aspm_init(common);
941 ah->reset_power_on = false;
942
943 return 0;
944}
945
946static SIMPLE_DEV_PM_OPS(ath9k_pm_ops, ath_pci_suspend, ath_pci_resume);
947
948#define ATH9K_PM_OPS (&ath9k_pm_ops)
949
950#else /* !CONFIG_PM_SLEEP */
951
952#define ATH9K_PM_OPS NULL
953
954#endif /* !CONFIG_PM_SLEEP */
955
956
957MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
958
959static struct pci_driver ath_pci_driver = {
960 .name = "ath9k",
961 .id_table = ath_pci_id_table,
962 .probe = ath_pci_probe,
963 .remove = ath_pci_remove,
964 .driver.pm = ATH9K_PM_OPS,
965};
966
967int ath_pci_init(void)
968{
969 return pci_register_driver(&ath_pci_driver);
970}
971
972void ath_pci_exit(void)
973{
974 pci_unregister_driver(&ath_pci_driver);
975}