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v3.1
  1/*
  2 * Copyright (c) 2009-2011 Atheros Communications Inc.
  3 *
  4 * Permission to use, copy, modify, and/or distribute this software for any
  5 * purpose with or without fee is hereby granted, provided that the above
  6 * copyright notice and this permission notice appear in all copies.
  7 *
  8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 15 */
 16
 
 17#include "hw.h"
 18
 19enum ath_bt_mode {
 20	ATH_BT_COEX_MODE_LEGACY,        /* legacy rx_clear mode */
 21	ATH_BT_COEX_MODE_UNSLOTTED,     /* untimed/unslotted mode */
 22	ATH_BT_COEX_MODE_SLOTTED,       /* slotted mode */
 23	ATH_BT_COEX_MODE_DISALBED,      /* coexistence disabled */
 24};
 25
 26struct ath_btcoex_config {
 27	u8 bt_time_extend;
 28	bool bt_txstate_extend;
 29	bool bt_txframe_extend;
 30	enum ath_bt_mode bt_mode; /* coexistence mode */
 31	bool bt_quiet_collision;
 32	bool bt_rxclear_polarity; /* invert rx_clear as WLAN_ACTIVE*/
 33	u8 bt_priority_time;
 34	u8 bt_first_slot_time;
 35	bool bt_hold_rx_clear;
 36};
 37
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 38
 39void ath9k_hw_init_btcoex_hw(struct ath_hw *ah, int qnum)
 40{
 41	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
 42	const struct ath_btcoex_config ath_bt_config = {
 43		.bt_time_extend = 0,
 44		.bt_txstate_extend = true,
 45		.bt_txframe_extend = true,
 46		.bt_mode = ATH_BT_COEX_MODE_SLOTTED,
 47		.bt_quiet_collision = true,
 48		.bt_rxclear_polarity = true,
 49		.bt_priority_time = 2,
 50		.bt_first_slot_time = 5,
 51		.bt_hold_rx_clear = true,
 52	};
 53	u32 i, idx;
 54	bool rxclear_polarity = ath_bt_config.bt_rxclear_polarity;
 55
 56	if (AR_SREV_9300_20_OR_LATER(ah))
 57		rxclear_polarity = !ath_bt_config.bt_rxclear_polarity;
 58
 59	btcoex_hw->bt_coex_mode =
 60		(btcoex_hw->bt_coex_mode & AR_BT_QCU_THRESH) |
 61		SM(ath_bt_config.bt_time_extend, AR_BT_TIME_EXTEND) |
 62		SM(ath_bt_config.bt_txstate_extend, AR_BT_TXSTATE_EXTEND) |
 63		SM(ath_bt_config.bt_txframe_extend, AR_BT_TX_FRAME_EXTEND) |
 64		SM(ath_bt_config.bt_mode, AR_BT_MODE) |
 65		SM(ath_bt_config.bt_quiet_collision, AR_BT_QUIET) |
 66		SM(rxclear_polarity, AR_BT_RX_CLEAR_POLARITY) |
 67		SM(ath_bt_config.bt_priority_time, AR_BT_PRIORITY_TIME) |
 68		SM(ath_bt_config.bt_first_slot_time, AR_BT_FIRST_SLOT_TIME) |
 69		SM(qnum, AR_BT_QCU_THRESH);
 70
 71	btcoex_hw->bt_coex_mode2 =
 72		SM(ath_bt_config.bt_hold_rx_clear, AR_BT_HOLD_RX_CLEAR) |
 73		SM(ATH_BTCOEX_BMISS_THRESH, AR_BT_BCN_MISS_THRESH) |
 74		AR_BT_DISABLE_BT_ANT;
 
 
 
 
 
 
 
 75
 76	for (i = 0; i < 32; i++) {
 77		idx = (debruijn32 << i) >> 27;
 78		ah->hw_gen_timers.gen_timer_index[idx] = i;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 79	}
 80}
 81EXPORT_SYMBOL(ath9k_hw_init_btcoex_hw);
 82
 83void ath9k_hw_btcoex_init_2wire(struct ath_hw *ah)
 84{
 85	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
 86
 87	/* connect bt_active to baseband */
 88	REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
 89		    (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
 90		     AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
 91
 92	REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
 93		    AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
 94
 95	/* Set input mux for bt_active to gpio pin */
 96	REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
 97		      AR_GPIO_INPUT_MUX1_BT_ACTIVE,
 98		      btcoex_hw->btactive_gpio);
 99
100	/* Configure the desired gpio port for input */
101	ath9k_hw_cfg_gpio_input(ah, btcoex_hw->btactive_gpio);
102}
103EXPORT_SYMBOL(ath9k_hw_btcoex_init_2wire);
104
105void ath9k_hw_btcoex_init_3wire(struct ath_hw *ah)
106{
107	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
108
109	/* btcoex 3-wire */
110	REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
111			(AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB |
112			 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB));
113
114	/* Set input mux for bt_prority_async and
115	 *                  bt_active_async to GPIO pins */
116	REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
117			AR_GPIO_INPUT_MUX1_BT_ACTIVE,
118			btcoex_hw->btactive_gpio);
119
120	REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
121			AR_GPIO_INPUT_MUX1_BT_PRIORITY,
122			btcoex_hw->btpriority_gpio);
123
124	/* Configure the desired GPIO ports for input */
125
126	ath9k_hw_cfg_gpio_input(ah, btcoex_hw->btactive_gpio);
127	ath9k_hw_cfg_gpio_input(ah, btcoex_hw->btpriority_gpio);
128}
129EXPORT_SYMBOL(ath9k_hw_btcoex_init_3wire);
130
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
131static void ath9k_hw_btcoex_enable_2wire(struct ath_hw *ah)
132{
133	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
134
135	/* Configure the desired GPIO port for TX_FRAME output */
136	ath9k_hw_cfg_output(ah, btcoex_hw->wlanactive_gpio,
137			    AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
138}
139
 
 
 
 
140void ath9k_hw_btcoex_set_weight(struct ath_hw *ah,
141				u32 bt_weight,
142				u32 wlan_weight)
 
143{
144	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
145
146	btcoex_hw->bt_coex_weights = SM(bt_weight, AR_BTCOEX_BT_WGHT) |
147				     SM(wlan_weight, AR_BTCOEX_WL_WGHT);
148}
149EXPORT_SYMBOL(ath9k_hw_btcoex_set_weight);
150
151
152static void ath9k_hw_btcoex_enable_3wire(struct ath_hw *ah)
153{
154	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
155	u32  val;
 
156
157	/*
158	 * Program coex mode and weight registers to
159	 * enable coex 3-wire
160	 */
161	REG_WRITE(ah, AR_BT_COEX_MODE, btcoex_hw->bt_coex_mode);
162	REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex_hw->bt_coex_mode2);
163
164
165	if (AR_SREV_9300_20_OR_LATER(ah)) {
166		REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, ah->bt_coex_wlan_weight[0]);
167		REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, ah->bt_coex_wlan_weight[1]);
168		REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS0, ah->bt_coex_bt_weight[0]);
169		REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS1, ah->bt_coex_bt_weight[1]);
170		REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS2, ah->bt_coex_bt_weight[2]);
171		REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS3, ah->bt_coex_bt_weight[3]);
172
173	} else
174		REG_WRITE(ah, AR_BT_COEX_WEIGHT, btcoex_hw->bt_coex_weights);
175
176
177
178	if (AR_SREV_9271(ah)) {
179		val = REG_READ(ah, 0x50040);
180		val &= 0xFFFFFEFF;
181		REG_WRITE(ah, 0x50040, val);
182	}
183
184	REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
185	REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0);
186
187	ath9k_hw_cfg_output(ah, btcoex_hw->wlanactive_gpio,
188			    AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL);
189}
190
 
 
 
 
 
 
 
 
 
 
 
 
 
191void ath9k_hw_btcoex_enable(struct ath_hw *ah)
192{
193	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
194
195	switch (btcoex_hw->scheme) {
196	case ATH_BTCOEX_CFG_NONE:
197		break;
198	case ATH_BTCOEX_CFG_2WIRE:
199		ath9k_hw_btcoex_enable_2wire(ah);
200		break;
201	case ATH_BTCOEX_CFG_3WIRE:
 
 
 
 
202		ath9k_hw_btcoex_enable_3wire(ah);
203		break;
204	}
205
206	REG_RMW(ah, AR_GPIO_PDPU,
207		(0x2 << (btcoex_hw->btactive_gpio * 2)),
208		(0x3 << (btcoex_hw->btactive_gpio * 2)));
209
210	ah->btcoex_hw.enabled = true;
211}
212EXPORT_SYMBOL(ath9k_hw_btcoex_enable);
213
214void ath9k_hw_btcoex_disable(struct ath_hw *ah)
215{
216	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
 
217
 
 
 
 
 
 
 
 
218	ath9k_hw_set_gpio(ah, btcoex_hw->wlanactive_gpio, 0);
219
220	ath9k_hw_cfg_output(ah, btcoex_hw->wlanactive_gpio,
221			AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
222
223	if (btcoex_hw->scheme == ATH_BTCOEX_CFG_3WIRE) {
224		REG_WRITE(ah, AR_BT_COEX_MODE, AR_BT_QUIET | AR_BT_MODE);
225		REG_WRITE(ah, AR_BT_COEX_MODE2, 0);
226
227		if (AR_SREV_9300_20_OR_LATER(ah)) {
228			REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, 0);
229			REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, 0);
230			REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS0, 0);
231			REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS1, 0);
232			REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS2, 0);
233			REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS3, 0);
234		} else
235			REG_WRITE(ah, AR_BT_COEX_WEIGHT, 0);
236
237	}
238
239	ah->btcoex_hw.enabled = false;
240}
241EXPORT_SYMBOL(ath9k_hw_btcoex_disable);
242
243static void ar9003_btcoex_bt_stomp(struct ath_hw *ah,
244			 enum ath_stomp_type stomp_type)
245{
246	ah->bt_coex_bt_weight[0] = AR9300_BT_WGHT;
247	ah->bt_coex_bt_weight[1] = AR9300_BT_WGHT;
248	ah->bt_coex_bt_weight[2] = AR9300_BT_WGHT;
249	ah->bt_coex_bt_weight[3] = AR9300_BT_WGHT;
250
251
252	switch (stomp_type) {
253	case ATH_BTCOEX_STOMP_ALL:
254		ah->bt_coex_wlan_weight[0] = AR9300_STOMP_ALL_WLAN_WGHT0;
255		ah->bt_coex_wlan_weight[1] = AR9300_STOMP_ALL_WLAN_WGHT1;
256		break;
257	case ATH_BTCOEX_STOMP_LOW:
258		ah->bt_coex_wlan_weight[0] = AR9300_STOMP_LOW_WLAN_WGHT0;
259		ah->bt_coex_wlan_weight[1] = AR9300_STOMP_LOW_WLAN_WGHT1;
260		break;
261	case ATH_BTCOEX_STOMP_NONE:
262		ah->bt_coex_wlan_weight[0] = AR9300_STOMP_NONE_WLAN_WGHT0;
263		ah->bt_coex_wlan_weight[1] = AR9300_STOMP_NONE_WLAN_WGHT1;
264		break;
265
266	default:
267		ath_dbg(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
268				"Invalid Stomptype\n");
269		break;
270	}
271
272	ath9k_hw_btcoex_enable(ah);
273}
274
275/*
276 * Configures appropriate weight based on stomp type.
277 */
278void ath9k_hw_btcoex_bt_stomp(struct ath_hw *ah,
279			      enum ath_stomp_type stomp_type)
280{
281	if (AR_SREV_9300_20_OR_LATER(ah)) {
282		ar9003_btcoex_bt_stomp(ah, stomp_type);
283		return;
284	}
285
286	switch (stomp_type) {
287	case ATH_BTCOEX_STOMP_ALL:
288		ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
289				AR_STOMP_ALL_WLAN_WGHT);
290		break;
291	case ATH_BTCOEX_STOMP_LOW:
292		ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
293				AR_STOMP_LOW_WLAN_WGHT);
294		break;
295	case ATH_BTCOEX_STOMP_NONE:
296		ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
297				AR_STOMP_NONE_WLAN_WGHT);
298		break;
299	default:
300		ath_dbg(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
301				"Invalid Stomptype\n");
302		break;
303	}
304
305	ath9k_hw_btcoex_enable(ah);
306}
307EXPORT_SYMBOL(ath9k_hw_btcoex_bt_stomp);
v3.15
  1/*
  2 * Copyright (c) 2009-2011 Atheros Communications Inc.
  3 *
  4 * Permission to use, copy, modify, and/or distribute this software for any
  5 * purpose with or without fee is hereby granted, provided that the above
  6 * copyright notice and this permission notice appear in all copies.
  7 *
  8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 15 */
 16
 17#include <linux/export.h>
 18#include "hw.h"
 19
 20enum ath_bt_mode {
 21	ATH_BT_COEX_MODE_LEGACY,        /* legacy rx_clear mode */
 22	ATH_BT_COEX_MODE_UNSLOTTED,     /* untimed/unslotted mode */
 23	ATH_BT_COEX_MODE_SLOTTED,       /* slotted mode */
 24	ATH_BT_COEX_MODE_DISABLED,      /* coexistence disabled */
 25};
 26
 27struct ath_btcoex_config {
 28	u8 bt_time_extend;
 29	bool bt_txstate_extend;
 30	bool bt_txframe_extend;
 31	enum ath_bt_mode bt_mode; /* coexistence mode */
 32	bool bt_quiet_collision;
 33	bool bt_rxclear_polarity; /* invert rx_clear as WLAN_ACTIVE*/
 34	u8 bt_priority_time;
 35	u8 bt_first_slot_time;
 36	bool bt_hold_rx_clear;
 37};
 38
 39static const u32 ar9003_wlan_weights[ATH_BTCOEX_STOMP_MAX]
 40				    [AR9300_NUM_WLAN_WEIGHTS] = {
 41	{ 0xfffffff0, 0xfffffff0, 0xfffffff0, 0xfffffff0 }, /* STOMP_ALL */
 42	{ 0x88888880, 0x88888880, 0x88888880, 0x88888880 }, /* STOMP_LOW */
 43	{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* STOMP_NONE */
 44};
 45
 46static const u32 mci_wlan_weights[ATH_BTCOEX_STOMP_MAX]
 47				 [AR9300_NUM_WLAN_WEIGHTS] = {
 48	{ 0x01017d01, 0x41414101, 0x41414101, 0x41414141 }, /* STOMP_ALL */
 49	{ 0x01017d01, 0x3b3b3b01, 0x3b3b3b01, 0x3b3b3b3b }, /* STOMP_LOW */
 50	{ 0x01017d01, 0x01010101, 0x01010101, 0x01010101 }, /* STOMP_NONE */
 51	{ 0x01017d01, 0x013b0101, 0x3b3b0101, 0x3b3b013b }, /* STOMP_LOW_FTP */
 52	{ 0xffffff01, 0xffffffff, 0xffffff01, 0xffffffff }, /* STOMP_AUDIO */
 53};
 54
 55void ath9k_hw_init_btcoex_hw(struct ath_hw *ah, int qnum)
 56{
 57	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
 58	const struct ath_btcoex_config ath_bt_config = {
 59		.bt_time_extend = 0,
 60		.bt_txstate_extend = true,
 61		.bt_txframe_extend = true,
 62		.bt_mode = ATH_BT_COEX_MODE_SLOTTED,
 63		.bt_quiet_collision = true,
 64		.bt_rxclear_polarity = true,
 65		.bt_priority_time = 2,
 66		.bt_first_slot_time = 5,
 67		.bt_hold_rx_clear = true,
 68	};
 
 69	bool rxclear_polarity = ath_bt_config.bt_rxclear_polarity;
 70
 71	if (AR_SREV_9300_20_OR_LATER(ah))
 72		rxclear_polarity = !ath_bt_config.bt_rxclear_polarity;
 73
 74	btcoex_hw->bt_coex_mode =
 75		(btcoex_hw->bt_coex_mode & AR_BT_QCU_THRESH) |
 76		SM(ath_bt_config.bt_time_extend, AR_BT_TIME_EXTEND) |
 77		SM(ath_bt_config.bt_txstate_extend, AR_BT_TXSTATE_EXTEND) |
 78		SM(ath_bt_config.bt_txframe_extend, AR_BT_TX_FRAME_EXTEND) |
 79		SM(ath_bt_config.bt_mode, AR_BT_MODE) |
 80		SM(ath_bt_config.bt_quiet_collision, AR_BT_QUIET) |
 81		SM(rxclear_polarity, AR_BT_RX_CLEAR_POLARITY) |
 82		SM(ath_bt_config.bt_priority_time, AR_BT_PRIORITY_TIME) |
 83		SM(ath_bt_config.bt_first_slot_time, AR_BT_FIRST_SLOT_TIME) |
 84		SM(qnum, AR_BT_QCU_THRESH);
 85
 86	btcoex_hw->bt_coex_mode2 =
 87		SM(ath_bt_config.bt_hold_rx_clear, AR_BT_HOLD_RX_CLEAR) |
 88		SM(ATH_BTCOEX_BMISS_THRESH, AR_BT_BCN_MISS_THRESH) |
 89		AR_BT_DISABLE_BT_ANT;
 90}
 91EXPORT_SYMBOL(ath9k_hw_init_btcoex_hw);
 92
 93void ath9k_hw_btcoex_init_scheme(struct ath_hw *ah)
 94{
 95	struct ath_common *common = ath9k_hw_common(ah);
 96	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
 97
 98	/*
 99	 * Check if BTCOEX is globally disabled.
100	 */
101	if (!common->btcoex_enabled) {
102		btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
103		return;
104	}
105
106	if (AR_SREV_9300_20_OR_LATER(ah)) {
107		btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
108		btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO_9300;
109		btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO_9300;
110		btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO_9300;
111	} else if (AR_SREV_9280_20_OR_LATER(ah)) {
112		btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO_9280;
113		btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO_9280;
114
115		if (AR_SREV_9285(ah)) {
116			btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
117			btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO_9285;
118		} else {
119			btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
120		}
121	}
122}
123EXPORT_SYMBOL(ath9k_hw_btcoex_init_scheme);
124
125void ath9k_hw_btcoex_init_2wire(struct ath_hw *ah)
126{
127	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
128
129	/* connect bt_active to baseband */
130	REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
131		    (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
132		     AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
133
134	REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
135		    AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
136
137	/* Set input mux for bt_active to gpio pin */
138	REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
139		      AR_GPIO_INPUT_MUX1_BT_ACTIVE,
140		      btcoex_hw->btactive_gpio);
141
142	/* Configure the desired gpio port for input */
143	ath9k_hw_cfg_gpio_input(ah, btcoex_hw->btactive_gpio);
144}
145EXPORT_SYMBOL(ath9k_hw_btcoex_init_2wire);
146
147void ath9k_hw_btcoex_init_3wire(struct ath_hw *ah)
148{
149	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
150
151	/* btcoex 3-wire */
152	REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
153			(AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB |
154			 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB));
155
156	/* Set input mux for bt_prority_async and
157	 *                  bt_active_async to GPIO pins */
158	REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
159			AR_GPIO_INPUT_MUX1_BT_ACTIVE,
160			btcoex_hw->btactive_gpio);
161
162	REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
163			AR_GPIO_INPUT_MUX1_BT_PRIORITY,
164			btcoex_hw->btpriority_gpio);
165
166	/* Configure the desired GPIO ports for input */
167
168	ath9k_hw_cfg_gpio_input(ah, btcoex_hw->btactive_gpio);
169	ath9k_hw_cfg_gpio_input(ah, btcoex_hw->btpriority_gpio);
170}
171EXPORT_SYMBOL(ath9k_hw_btcoex_init_3wire);
172
173void ath9k_hw_btcoex_init_mci(struct ath_hw *ah)
174{
175	ah->btcoex_hw.mci.ready = false;
176	ah->btcoex_hw.mci.bt_state = 0;
177	ah->btcoex_hw.mci.bt_ver_major = 3;
178	ah->btcoex_hw.mci.bt_ver_minor = 0;
179	ah->btcoex_hw.mci.bt_version_known = false;
180	ah->btcoex_hw.mci.update_2g5g = true;
181	ah->btcoex_hw.mci.is_2g = true;
182	ah->btcoex_hw.mci.wlan_channels_update = false;
183	ah->btcoex_hw.mci.wlan_channels[0] = 0x00000000;
184	ah->btcoex_hw.mci.wlan_channels[1] = 0xffffffff;
185	ah->btcoex_hw.mci.wlan_channels[2] = 0xffffffff;
186	ah->btcoex_hw.mci.wlan_channels[3] = 0x7fffffff;
187	ah->btcoex_hw.mci.query_bt = true;
188	ah->btcoex_hw.mci.unhalt_bt_gpm = true;
189	ah->btcoex_hw.mci.halted_bt_gpm = false;
190	ah->btcoex_hw.mci.need_flush_btinfo = false;
191	ah->btcoex_hw.mci.wlan_cal_seq = 0;
192	ah->btcoex_hw.mci.wlan_cal_done = 0;
193	ah->btcoex_hw.mci.config = (AR_SREV_9462(ah)) ? 0x2201 : 0xa4c1;
194}
195EXPORT_SYMBOL(ath9k_hw_btcoex_init_mci);
196
197static void ath9k_hw_btcoex_enable_2wire(struct ath_hw *ah)
198{
199	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
200
201	/* Configure the desired GPIO port for TX_FRAME output */
202	ath9k_hw_cfg_output(ah, btcoex_hw->wlanactive_gpio,
203			    AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
204}
205
206/*
207 * For AR9002, bt_weight/wlan_weight are used.
208 * For AR9003 and above, stomp_type is used.
209 */
210void ath9k_hw_btcoex_set_weight(struct ath_hw *ah,
211				u32 bt_weight,
212				u32 wlan_weight,
213				enum ath_stomp_type stomp_type)
214{
215	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
216	struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;
217	u8 txprio_shift[] = { 24, 16, 16, 0 }; /* tx priority weight */
218	bool concur_tx = (mci_hw->concur_tx && btcoex_hw->tx_prio[stomp_type]);
219	const u32 *weight = ar9003_wlan_weights[stomp_type];
220	int i;
221
222	if (!AR_SREV_9300_20_OR_LATER(ah)) {
223		btcoex_hw->bt_coex_weights =
224			SM(bt_weight, AR_BTCOEX_BT_WGHT) |
225			SM(wlan_weight, AR_BTCOEX_WL_WGHT);
226		return;
227	}
228
229	if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
230		enum ath_stomp_type stype =
231			((stomp_type == ATH_BTCOEX_STOMP_LOW) &&
232			 btcoex_hw->mci.stomp_ftp) ?
233			ATH_BTCOEX_STOMP_LOW_FTP : stomp_type;
234		weight = mci_wlan_weights[stype];
235	}
236
237	for (i = 0; i < AR9300_NUM_WLAN_WEIGHTS; i++) {
238		btcoex_hw->bt_weight[i] = AR9300_BT_WGHT;
239		btcoex_hw->wlan_weight[i] = weight[i];
240		if (concur_tx && i) {
241			btcoex_hw->wlan_weight[i] &=
242				~(0xff << txprio_shift[i-1]);
243			btcoex_hw->wlan_weight[i] |=
244				(btcoex_hw->tx_prio[stomp_type] <<
245				 txprio_shift[i-1]);
246		}
247	}
248	/* Last WLAN weight has to be adjusted wrt tx priority */
249	if (concur_tx) {
250		btcoex_hw->wlan_weight[i-1] &= ~(0xff << txprio_shift[i-1]);
251		btcoex_hw->wlan_weight[i-1] |= (btcoex_hw->tx_prio[stomp_type]
252						      << txprio_shift[i-1]);
253	}
254
 
 
255}
256EXPORT_SYMBOL(ath9k_hw_btcoex_set_weight);
257
258
259static void ath9k_hw_btcoex_enable_3wire(struct ath_hw *ah)
260{
261	struct ath_btcoex_hw *btcoex = &ah->btcoex_hw;
262	u32  val;
263	int i;
264
265	/*
266	 * Program coex mode and weight registers to
267	 * enable coex 3-wire
268	 */
269	REG_WRITE(ah, AR_BT_COEX_MODE, btcoex->bt_coex_mode);
270	REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex->bt_coex_mode2);
271
272
273	if (AR_SREV_9300_20_OR_LATER(ah)) {
274		REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, btcoex->wlan_weight[0]);
275		REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, btcoex->wlan_weight[1]);
276		for (i = 0; i < AR9300_NUM_BT_WEIGHTS; i++)
277			REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS(i),
278				  btcoex->bt_weight[i]);
 
 
279	} else
280		REG_WRITE(ah, AR_BT_COEX_WEIGHT, btcoex->bt_coex_weights);
281
282
283
284	if (AR_SREV_9271(ah)) {
285		val = REG_READ(ah, 0x50040);
286		val &= 0xFFFFFEFF;
287		REG_WRITE(ah, 0x50040, val);
288	}
289
290	REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
291	REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0);
292
293	ath9k_hw_cfg_output(ah, btcoex->wlanactive_gpio,
294			    AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL);
295}
296
297static void ath9k_hw_btcoex_enable_mci(struct ath_hw *ah)
298{
299	struct ath_btcoex_hw *btcoex = &ah->btcoex_hw;
300	int i;
301
302	for (i = 0; i < AR9300_NUM_BT_WEIGHTS; i++)
303		REG_WRITE(ah, AR_MCI_COEX_WL_WEIGHTS(i),
304			  btcoex->wlan_weight[i]);
305
306	REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
307	btcoex->enabled = true;
308}
309
310void ath9k_hw_btcoex_enable(struct ath_hw *ah)
311{
312	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
313
314	switch (ath9k_hw_get_btcoex_scheme(ah)) {
315	case ATH_BTCOEX_CFG_NONE:
316		return;
317	case ATH_BTCOEX_CFG_2WIRE:
318		ath9k_hw_btcoex_enable_2wire(ah);
319		break;
320	case ATH_BTCOEX_CFG_3WIRE:
321		if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
322			ath9k_hw_btcoex_enable_mci(ah);
323			return;
324		}
325		ath9k_hw_btcoex_enable_3wire(ah);
326		break;
327	}
328
329	REG_RMW(ah, AR_GPIO_PDPU,
330		(0x2 << (btcoex_hw->btactive_gpio * 2)),
331		(0x3 << (btcoex_hw->btactive_gpio * 2)));
332
333	ah->btcoex_hw.enabled = true;
334}
335EXPORT_SYMBOL(ath9k_hw_btcoex_enable);
336
337void ath9k_hw_btcoex_disable(struct ath_hw *ah)
338{
339	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
340	int i;
341
342	btcoex_hw->enabled = false;
343	if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
344		ath9k_hw_btcoex_bt_stomp(ah, ATH_BTCOEX_STOMP_NONE);
345		for (i = 0; i < AR9300_NUM_BT_WEIGHTS; i++)
346			REG_WRITE(ah, AR_MCI_COEX_WL_WEIGHTS(i),
347				  btcoex_hw->wlan_weight[i]);
348		return;
349	}
350	ath9k_hw_set_gpio(ah, btcoex_hw->wlanactive_gpio, 0);
351
352	ath9k_hw_cfg_output(ah, btcoex_hw->wlanactive_gpio,
353			AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
354
355	if (btcoex_hw->scheme == ATH_BTCOEX_CFG_3WIRE) {
356		REG_WRITE(ah, AR_BT_COEX_MODE, AR_BT_QUIET | AR_BT_MODE);
357		REG_WRITE(ah, AR_BT_COEX_MODE2, 0);
358
359		if (AR_SREV_9300_20_OR_LATER(ah)) {
360			REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, 0);
361			REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, 0);
362			for (i = 0; i < AR9300_NUM_BT_WEIGHTS; i++)
363				REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS(i), 0);
 
 
364		} else
365			REG_WRITE(ah, AR_BT_COEX_WEIGHT, 0);
366
367	}
 
 
368}
369EXPORT_SYMBOL(ath9k_hw_btcoex_disable);
370
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
371/*
372 * Configures appropriate weight based on stomp type.
373 */
374void ath9k_hw_btcoex_bt_stomp(struct ath_hw *ah,
375			      enum ath_stomp_type stomp_type)
376{
377	if (AR_SREV_9300_20_OR_LATER(ah)) {
378		ath9k_hw_btcoex_set_weight(ah, 0, 0, stomp_type);
379		return;
380	}
381
382	switch (stomp_type) {
383	case ATH_BTCOEX_STOMP_ALL:
384		ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
385					   AR_STOMP_ALL_WLAN_WGHT, 0);
386		break;
387	case ATH_BTCOEX_STOMP_LOW:
388		ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
389					   AR_STOMP_LOW_WLAN_WGHT, 0);
390		break;
391	case ATH_BTCOEX_STOMP_NONE:
392		ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
393					   AR_STOMP_NONE_WLAN_WGHT, 0);
394		break;
395	default:
396		ath_dbg(ath9k_hw_common(ah), BTCOEX, "Invalid Stomptype\n");
 
397		break;
398	}
 
 
399}
400EXPORT_SYMBOL(ath9k_hw_btcoex_bt_stomp);
401
402void ath9k_hw_btcoex_set_concur_txprio(struct ath_hw *ah, u8 *stomp_txprio)
403{
404	struct ath_btcoex_hw *btcoex = &ah->btcoex_hw;
405	int i;
406
407	for (i = 0; i < ATH_BTCOEX_STOMP_MAX; i++)
408		btcoex->tx_prio[i] = stomp_txprio[i];
409}
410EXPORT_SYMBOL(ath9k_hw_btcoex_set_concur_txprio);