1/*
  2 * Copyright (c) 2005-2011 Atheros Communications Inc.
  3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
  4 *
  5 * Permission to use, copy, modify, and/or distribute this software for any
  6 * purpose with or without fee is hereby granted, provided that the above
  7 * copyright notice and this permission notice appear in all copies.
  8 *
  9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 16 */
 17
 18#ifndef _CORE_H_
 19#define _CORE_H_
 20
 21#include <linux/completion.h>
 22#include <linux/if_ether.h>
 23#include <linux/types.h>
 24#include <linux/pci.h>
 25
 26#include "htt.h"
 27#include "htc.h"
 28#include "hw.h"
 29#include "targaddrs.h"
 30#include "wmi.h"
 31#include "../ath.h"
 32#include "../regd.h"
 33#include "../dfs_pattern_detector.h"
 34
 35#define MS(_v, _f) (((_v) & _f##_MASK) >> _f##_LSB)
 36#define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK)
 37#define WO(_f)      ((_f##_OFFSET) >> 2)
 38
 39#define ATH10K_SCAN_ID 0
 40#define WMI_READY_TIMEOUT (5 * HZ)
 41#define ATH10K_FLUSH_TIMEOUT_HZ (5*HZ)
 42#define ATH10K_NUM_CHANS 38
 43
 44/* Antenna noise floor */
 45#define ATH10K_DEFAULT_NOISE_FLOOR -95
 46
 47#define ATH10K_MAX_NUM_MGMT_PENDING 128
 48
 49/* number of failed packets */
 50#define ATH10K_KICKOUT_THRESHOLD 50
 51
 52/*
 53 * Use insanely high numbers to make sure that the firmware implementation
 54 * won't start, we have the same functionality already in hostapd. Unit
 55 * is seconds.
 56 */
 57#define ATH10K_KEEPALIVE_MIN_IDLE 3747
 58#define ATH10K_KEEPALIVE_MAX_IDLE 3895
 59#define ATH10K_KEEPALIVE_MAX_UNRESPONSIVE 3900
 60
 61struct ath10k;
 62
 63struct ath10k_skb_cb {
 64	dma_addr_t paddr;
 65	u8 vdev_id;
 66
 67	struct {
 68		u8 tid;
 69		bool is_offchan;
 70		struct ath10k_htt_txbuf *txbuf;
 71		u32 txbuf_paddr;
 72	} __packed htt;
 73
 74	struct {
 75		bool dtim_zero;
 76		bool deliver_cab;
 77	} bcn;
 78} __packed;
 79
 80static inline struct ath10k_skb_cb *ATH10K_SKB_CB(struct sk_buff *skb)
 81{
 82	BUILD_BUG_ON(sizeof(struct ath10k_skb_cb) >
 83		     IEEE80211_TX_INFO_DRIVER_DATA_SIZE);
 84	return (struct ath10k_skb_cb *)&IEEE80211_SKB_CB(skb)->driver_data;
 85}
 86
 87static inline u32 host_interest_item_address(u32 item_offset)
 88{
 89	return QCA988X_HOST_INTEREST_ADDRESS + item_offset;
 90}
 91
 92struct ath10k_bmi {
 93	bool done_sent;
 94};
 95
 96#define ATH10K_MAX_MEM_REQS 16
 97
 98struct ath10k_mem_chunk {
 99	void *vaddr;
100	dma_addr_t paddr;
101	u32 len;
102	u32 req_id;
103};
104
105struct ath10k_wmi {
106	enum ath10k_htc_ep_id eid;
107	struct completion service_ready;
108	struct completion unified_ready;
109	wait_queue_head_t tx_credits_wq;
110	struct wmi_cmd_map *cmd;
111	struct wmi_vdev_param_map *vdev_param;
112	struct wmi_pdev_param_map *pdev_param;
113
114	u32 num_mem_chunks;
115	struct ath10k_mem_chunk mem_chunks[ATH10K_MAX_MEM_REQS];
116};
117
118struct ath10k_peer_stat {
119	u8 peer_macaddr[ETH_ALEN];
120	u32 peer_rssi;
121	u32 peer_tx_rate;
122};
123
124struct ath10k_target_stats {
125	/* PDEV stats */
126	s32 ch_noise_floor;
127	u32 tx_frame_count;
128	u32 rx_frame_count;
129	u32 rx_clear_count;
130	u32 cycle_count;
131	u32 phy_err_count;
132	u32 chan_tx_power;
133
134	/* PDEV TX stats */
135	s32 comp_queued;
136	s32 comp_delivered;
137	s32 msdu_enqued;
138	s32 mpdu_enqued;
139	s32 wmm_drop;
140	s32 local_enqued;
141	s32 local_freed;
142	s32 hw_queued;
143	s32 hw_reaped;
144	s32 underrun;
145	s32 tx_abort;
146	s32 mpdus_requed;
147	u32 tx_ko;
148	u32 data_rc;
149	u32 self_triggers;
150	u32 sw_retry_failure;
151	u32 illgl_rate_phy_err;
152	u32 pdev_cont_xretry;
153	u32 pdev_tx_timeout;
154	u32 pdev_resets;
155	u32 phy_underrun;
156	u32 txop_ovf;
157
158	/* PDEV RX stats */
159	s32 mid_ppdu_route_change;
160	s32 status_rcvd;
161	s32 r0_frags;
162	s32 r1_frags;
163	s32 r2_frags;
164	s32 r3_frags;
165	s32 htt_msdus;
166	s32 htt_mpdus;
167	s32 loc_msdus;
168	s32 loc_mpdus;
169	s32 oversize_amsdu;
170	s32 phy_errs;
171	s32 phy_err_drop;
172	s32 mpdu_errs;
173
174	/* VDEV STATS */
175
176	/* PEER STATS */
177	u8 peers;
178	struct ath10k_peer_stat peer_stat[TARGET_NUM_PEERS];
179
180	/* TODO: Beacon filter stats */
181
182};
183
184struct ath10k_dfs_stats {
185	u32 phy_errors;
186	u32 pulses_total;
187	u32 pulses_detected;
188	u32 pulses_discarded;
189	u32 radar_detected;
190};
191
192#define ATH10K_MAX_NUM_PEER_IDS (1 << 11) /* htt rx_desc limit */
193
194struct ath10k_peer {
195	struct list_head list;
196	int vdev_id;
197	u8 addr[ETH_ALEN];
198	DECLARE_BITMAP(peer_ids, ATH10K_MAX_NUM_PEER_IDS);
199	struct ieee80211_key_conf *keys[WMI_MAX_KEY_INDEX + 1];
200};
201
202struct ath10k_sta {
203	struct ath10k_vif *arvif;
204
205	/* the following are protected by ar->data_lock */
206	u32 changed; /* IEEE80211_RC_* */
207	u32 bw;
208	u32 nss;
209	u32 smps;
210
211	struct work_struct update_wk;
212};
213
214#define ATH10K_VDEV_SETUP_TIMEOUT_HZ (5*HZ)
215
216struct ath10k_vif {
217	struct list_head list;
218
219	u32 vdev_id;
220	enum wmi_vdev_type vdev_type;
221	enum wmi_vdev_subtype vdev_subtype;
222	u32 beacon_interval;
223	u32 dtim_period;
224	struct sk_buff *beacon;
225	/* protected by data_lock */
226	bool beacon_sent;
227
228	struct ath10k *ar;
229	struct ieee80211_vif *vif;
230
231	bool is_started;
232	bool is_up;
233	u32 aid;
234	u8 bssid[ETH_ALEN];
235
236	struct work_struct wep_key_work;
237	struct ieee80211_key_conf *wep_keys[WMI_MAX_KEY_INDEX + 1];
238	u8 def_wep_key_idx;
239	u8 def_wep_key_newidx;
240
241	u16 tx_seq_no;
242
243	union {
244		struct {
245			u32 uapsd;
246		} sta;
247		struct {
248			/* 127 stations; wmi limit */
249			u8 tim_bitmap[16];
250			u8 tim_len;
251			u32 ssid_len;
252			u8 ssid[IEEE80211_MAX_SSID_LEN];
253			bool hidden_ssid;
254			/* P2P_IE with NoA attribute for P2P_GO case */
255			u32 noa_len;
256			u8 *noa_data;
257		} ap;
258	} u;
259
260	u8 fixed_rate;
261	u8 fixed_nss;
262	u8 force_sgi;
263};
264
265struct ath10k_vif_iter {
266	u32 vdev_id;
267	struct ath10k_vif *arvif;
268};
269
270struct ath10k_debug {
271	struct dentry *debugfs_phy;
272
273	struct ath10k_target_stats target_stats;
274	u32 wmi_service_bitmap[WMI_SERVICE_BM_SIZE];
275
276	struct completion event_stats_compl;
277
278	unsigned long htt_stats_mask;
279	struct delayed_work htt_stats_dwork;
280	struct ath10k_dfs_stats dfs_stats;
281	struct ath_dfs_pool_stats dfs_pool_stats;
282
283	u32 fw_dbglog_mask;
284};
285
286enum ath10k_state {
287	ATH10K_STATE_OFF = 0,
288	ATH10K_STATE_ON,
289
290	/* When doing firmware recovery the device is first powered down.
291	 * mac80211 is supposed to call in to start() hook later on. It is
292	 * however possible that driver unloading and firmware crash overlap.
293	 * mac80211 can wait on conf_mutex in stop() while the device is
294	 * stopped in ath10k_core_restart() work holding conf_mutex. The state
295	 * RESTARTED means that the device is up and mac80211 has started hw
296	 * reconfiguration. Once mac80211 is done with the reconfiguration we
297	 * set the state to STATE_ON in restart_complete(). */
298	ATH10K_STATE_RESTARTING,
299	ATH10K_STATE_RESTARTED,
300
301	/* The device has crashed while restarting hw. This state is like ON
302	 * but commands are blocked in HTC and -ECOMM response is given. This
303	 * prevents completion timeouts and makes the driver more responsive to
304	 * userspace commands. This is also prevents recursive recovery. */
305	ATH10K_STATE_WEDGED,
306};
307
308enum ath10k_fw_features {
309	/* wmi_mgmt_rx_hdr contains extra RSSI information */
310	ATH10K_FW_FEATURE_EXT_WMI_MGMT_RX = 0,
311
312	/* firmware from 10X branch */
313	ATH10K_FW_FEATURE_WMI_10X = 1,
314
315	/* firmware support tx frame management over WMI, otherwise it's HTT */
316	ATH10K_FW_FEATURE_HAS_WMI_MGMT_TX = 2,
317
318	/* Firmware does not support P2P */
319	ATH10K_FW_FEATURE_NO_P2P = 3,
320
321	/* keep last */
322	ATH10K_FW_FEATURE_COUNT,
323};
324
325enum ath10k_dev_flags {
326	/* Indicates that ath10k device is during CAC phase of DFS */
327	ATH10K_CAC_RUNNING,
328	ATH10K_FLAG_FIRST_BOOT_DONE,
329};
330
331struct ath10k {
332	struct ath_common ath_common;
333	struct ieee80211_hw *hw;
334	struct device *dev;
335	u8 mac_addr[ETH_ALEN];
336
337	u32 chip_id;
338	u32 target_version;
339	u8 fw_version_major;
340	u32 fw_version_minor;
341	u16 fw_version_release;
342	u16 fw_version_build;
343	u32 phy_capability;
344	u32 hw_min_tx_power;
345	u32 hw_max_tx_power;
346	u32 ht_cap_info;
347	u32 vht_cap_info;
348	u32 num_rf_chains;
349
350	DECLARE_BITMAP(fw_features, ATH10K_FW_FEATURE_COUNT);
351
352	struct targetdef *targetdef;
353	struct hostdef *hostdef;
354
355	bool p2p;
356
357	struct {
358		void *priv;
359		const struct ath10k_hif_ops *ops;
360	} hif;
361
362	struct completion target_suspend;
363
364	struct ath10k_bmi bmi;
365	struct ath10k_wmi wmi;
366	struct ath10k_htc htc;
367	struct ath10k_htt htt;
368
369	struct ath10k_hw_params {
370		u32 id;
371		const char *name;
372		u32 patch_load_addr;
373
374		struct ath10k_hw_params_fw {
375			const char *dir;
376			const char *fw;
377			const char *otp;
378			const char *board;
379		} fw;
380	} hw_params;
381
382	const struct firmware *board;
383	const void *board_data;
384	size_t board_len;
385
386	const struct firmware *otp;
387	const void *otp_data;
388	size_t otp_len;
389
390	const struct firmware *firmware;
391	const void *firmware_data;
392	size_t firmware_len;
393
394	int fw_api;
395
396	struct {
397		struct completion started;
398		struct completion completed;
399		struct completion on_channel;
400		struct timer_list timeout;
401		bool is_roc;
402		bool in_progress;
403		bool aborting;
404		int vdev_id;
405		int roc_freq;
406	} scan;
407
408	struct {
409		struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
410	} mac;
411
412	/* should never be NULL; needed for regular htt rx */
413	struct ieee80211_channel *rx_channel;
414
415	/* valid during scan; needed for mgmt rx during scan */
416	struct ieee80211_channel *scan_channel;
417
418	/* current operating channel definition */
419	struct cfg80211_chan_def chandef;
420
421	int free_vdev_map;
422	int monitor_vdev_id;
423	bool monitor_enabled;
424	bool monitor_present;
425	unsigned int filter_flags;
426	unsigned long dev_flags;
427	u32 dfs_block_radar_events;
428
429	struct wmi_pdev_set_wmm_params_arg wmm_params;
430	struct completion install_key_done;
431
432	struct completion vdev_setup_done;
433
434	struct workqueue_struct *workqueue;
435
436	/* prevents concurrent FW reconfiguration */
437	struct mutex conf_mutex;
438
439	/* protects shared structure data */
440	spinlock_t data_lock;
441
442	struct list_head arvifs;
443	struct list_head peers;
444	wait_queue_head_t peer_mapping_wq;
445
446	/* number of created peers; protected by data_lock */
447	int num_peers;
448
449	struct work_struct offchan_tx_work;
450	struct sk_buff_head offchan_tx_queue;
451	struct completion offchan_tx_completed;
452	struct sk_buff *offchan_tx_skb;
453
454	struct work_struct wmi_mgmt_tx_work;
455	struct sk_buff_head wmi_mgmt_tx_queue;
456
457	enum ath10k_state state;
458
459	struct work_struct restart_work;
460
461	/* cycle count is reported twice for each visited channel during scan.
462	 * access protected by data_lock */
463	u32 survey_last_rx_clear_count;
464	u32 survey_last_cycle_count;
465	struct survey_info survey[ATH10K_NUM_CHANS];
466
467	struct dfs_pattern_detector *dfs_detector;
468
469#ifdef CONFIG_ATH10K_DEBUGFS
470	struct ath10k_debug debug;
471#endif
472};
473
474struct ath10k *ath10k_core_create(void *hif_priv, struct device *dev,
475				  const struct ath10k_hif_ops *hif_ops);
476void ath10k_core_destroy(struct ath10k *ar);
477
478int ath10k_core_start(struct ath10k *ar);
479int ath10k_wait_for_suspend(struct ath10k *ar, u32 suspend_opt);
480void ath10k_core_stop(struct ath10k *ar);
481int ath10k_core_register(struct ath10k *ar, u32 chip_id);
482void ath10k_core_unregister(struct ath10k *ar);
483
484#endif /* _CORE_H_ */