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1/*
2 * Copyright (C) 2005 - 2014 Emulex
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
11 * linux-drivers@emulex.com
12 *
13 * Emulex
14 * 3333 Susan Street
15 * Costa Mesa, CA 92626
16 */
17
18/*
19 * The driver sends configuration and managements command requests to the
20 * firmware in the BE. These requests are communicated to the processor
21 * using Work Request Blocks (WRBs) submitted to the MCC-WRB ring or via one
22 * WRB inside a MAILBOX.
23 * The commands are serviced by the ARM processor in the BladeEngine's MPU.
24 */
25
26struct be_sge {
27 u32 pa_lo;
28 u32 pa_hi;
29 u32 len;
30};
31
32#define MCC_WRB_EMBEDDED_MASK 1 /* bit 0 of dword 0*/
33#define MCC_WRB_SGE_CNT_SHIFT 3 /* bits 3 - 7 of dword 0 */
34#define MCC_WRB_SGE_CNT_MASK 0x1F /* bits 3 - 7 of dword 0 */
35struct be_mcc_wrb {
36 u32 embedded; /* dword 0 */
37 u32 payload_length; /* dword 1 */
38 u32 tag0; /* dword 2 */
39 u32 tag1; /* dword 3 */
40 u32 rsvd; /* dword 4 */
41 union {
42 u8 embedded_payload[236]; /* used by embedded cmds */
43 struct be_sge sgl[19]; /* used by non-embedded cmds */
44 } payload;
45};
46
47#define CQE_FLAGS_VALID_MASK (1 << 31)
48#define CQE_FLAGS_ASYNC_MASK (1 << 30)
49#define CQE_FLAGS_COMPLETED_MASK (1 << 28)
50#define CQE_FLAGS_CONSUMED_MASK (1 << 27)
51
52/* Completion Status */
53enum {
54 MCC_STATUS_SUCCESS = 0,
55 MCC_STATUS_FAILED = 1,
56 MCC_STATUS_ILLEGAL_REQUEST = 2,
57 MCC_STATUS_ILLEGAL_FIELD = 3,
58 MCC_STATUS_INSUFFICIENT_BUFFER = 4,
59 MCC_STATUS_UNAUTHORIZED_REQUEST = 5,
60 MCC_STATUS_NOT_SUPPORTED = 66
61};
62
63#define MCC_ADDL_STS_INSUFFICIENT_RESOURCES 0x16
64
65#define CQE_STATUS_COMPL_MASK 0xFFFF
66#define CQE_STATUS_COMPL_SHIFT 0 /* bits 0 - 15 */
67#define CQE_STATUS_EXTD_MASK 0xFFFF
68#define CQE_STATUS_EXTD_SHIFT 16 /* bits 16 - 31 */
69
70struct be_mcc_compl {
71 u32 status; /* dword 0 */
72 u32 tag0; /* dword 1 */
73 u32 tag1; /* dword 2 */
74 u32 flags; /* dword 3 */
75};
76
77/* When the async bit of mcc_compl is set, the last 4 bytes of
78 * mcc_compl is interpreted as follows:
79 */
80#define ASYNC_TRAILER_EVENT_CODE_SHIFT 8 /* bits 8 - 15 */
81#define ASYNC_TRAILER_EVENT_CODE_MASK 0xFF
82#define ASYNC_TRAILER_EVENT_TYPE_SHIFT 16
83#define ASYNC_TRAILER_EVENT_TYPE_MASK 0xFF
84#define ASYNC_EVENT_CODE_LINK_STATE 0x1
85#define ASYNC_EVENT_CODE_GRP_5 0x5
86#define ASYNC_EVENT_QOS_SPEED 0x1
87#define ASYNC_EVENT_COS_PRIORITY 0x2
88#define ASYNC_EVENT_PVID_STATE 0x3
89#define ASYNC_EVENT_CODE_QNQ 0x6
90#define ASYNC_DEBUG_EVENT_TYPE_QNQ 1
91
92struct be_async_event_trailer {
93 u32 code;
94};
95
96enum {
97 LINK_DOWN = 0x0,
98 LINK_UP = 0x1
99};
100#define LINK_STATUS_MASK 0x1
101#define LOGICAL_LINK_STATUS_MASK 0x2
102
103/* When the event code of an async trailer is link-state, the mcc_compl
104 * must be interpreted as follows
105 */
106struct be_async_event_link_state {
107 u8 physical_port;
108 u8 port_link_status;
109 u8 port_duplex;
110 u8 port_speed;
111 u8 port_fault;
112 u8 rsvd0[7];
113 struct be_async_event_trailer trailer;
114} __packed;
115
116/* When the event code of an async trailer is GRP-5 and event_type is QOS_SPEED
117 * the mcc_compl must be interpreted as follows
118 */
119struct be_async_event_grp5_qos_link_speed {
120 u8 physical_port;
121 u8 rsvd[5];
122 u16 qos_link_speed;
123 u32 event_tag;
124 struct be_async_event_trailer trailer;
125} __packed;
126
127/* When the event code of an async trailer is GRP5 and event type is
128 * CoS-Priority, the mcc_compl must be interpreted as follows
129 */
130struct be_async_event_grp5_cos_priority {
131 u8 physical_port;
132 u8 available_priority_bmap;
133 u8 reco_default_priority;
134 u8 valid;
135 u8 rsvd0;
136 u8 event_tag;
137 struct be_async_event_trailer trailer;
138} __packed;
139
140/* When the event code of an async trailer is GRP5 and event type is
141 * PVID state, the mcc_compl must be interpreted as follows
142 */
143struct be_async_event_grp5_pvid_state {
144 u8 enabled;
145 u8 rsvd0;
146 u16 tag;
147 u32 event_tag;
148 u32 rsvd1;
149 struct be_async_event_trailer trailer;
150} __packed;
151
152/* async event indicating outer VLAN tag in QnQ */
153struct be_async_event_qnq {
154 u8 valid; /* Indicates if outer VLAN is valid */
155 u8 rsvd0;
156 u16 vlan_tag;
157 u32 event_tag;
158 u8 rsvd1[4];
159 struct be_async_event_trailer trailer;
160} __packed;
161
162struct be_mcc_mailbox {
163 struct be_mcc_wrb wrb;
164 struct be_mcc_compl compl;
165};
166
167#define CMD_SUBSYSTEM_COMMON 0x1
168#define CMD_SUBSYSTEM_ETH 0x3
169#define CMD_SUBSYSTEM_LOWLEVEL 0xb
170
171#define OPCODE_COMMON_NTWK_MAC_QUERY 1
172#define OPCODE_COMMON_NTWK_MAC_SET 2
173#define OPCODE_COMMON_NTWK_MULTICAST_SET 3
174#define OPCODE_COMMON_NTWK_VLAN_CONFIG 4
175#define OPCODE_COMMON_NTWK_LINK_STATUS_QUERY 5
176#define OPCODE_COMMON_READ_FLASHROM 6
177#define OPCODE_COMMON_WRITE_FLASHROM 7
178#define OPCODE_COMMON_CQ_CREATE 12
179#define OPCODE_COMMON_EQ_CREATE 13
180#define OPCODE_COMMON_MCC_CREATE 21
181#define OPCODE_COMMON_SET_QOS 28
182#define OPCODE_COMMON_MCC_CREATE_EXT 90
183#define OPCODE_COMMON_SEEPROM_READ 30
184#define OPCODE_COMMON_GET_CNTL_ATTRIBUTES 32
185#define OPCODE_COMMON_NTWK_RX_FILTER 34
186#define OPCODE_COMMON_GET_FW_VERSION 35
187#define OPCODE_COMMON_SET_FLOW_CONTROL 36
188#define OPCODE_COMMON_GET_FLOW_CONTROL 37
189#define OPCODE_COMMON_SET_FRAME_SIZE 39
190#define OPCODE_COMMON_MODIFY_EQ_DELAY 41
191#define OPCODE_COMMON_FIRMWARE_CONFIG 42
192#define OPCODE_COMMON_NTWK_INTERFACE_CREATE 50
193#define OPCODE_COMMON_NTWK_INTERFACE_DESTROY 51
194#define OPCODE_COMMON_MCC_DESTROY 53
195#define OPCODE_COMMON_CQ_DESTROY 54
196#define OPCODE_COMMON_EQ_DESTROY 55
197#define OPCODE_COMMON_QUERY_FIRMWARE_CONFIG 58
198#define OPCODE_COMMON_NTWK_PMAC_ADD 59
199#define OPCODE_COMMON_NTWK_PMAC_DEL 60
200#define OPCODE_COMMON_FUNCTION_RESET 61
201#define OPCODE_COMMON_MANAGE_FAT 68
202#define OPCODE_COMMON_ENABLE_DISABLE_BEACON 69
203#define OPCODE_COMMON_GET_BEACON_STATE 70
204#define OPCODE_COMMON_READ_TRANSRECV_DATA 73
205#define OPCODE_COMMON_GET_PORT_NAME 77
206#define OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG 80
207#define OPCODE_COMMON_SET_INTERRUPT_ENABLE 89
208#define OPCODE_COMMON_SET_FN_PRIVILEGES 100
209#define OPCODE_COMMON_GET_PHY_DETAILS 102
210#define OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP 103
211#define OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES 121
212#define OPCODE_COMMON_GET_EXT_FAT_CAPABILITES 125
213#define OPCODE_COMMON_SET_EXT_FAT_CAPABILITES 126
214#define OPCODE_COMMON_GET_MAC_LIST 147
215#define OPCODE_COMMON_SET_MAC_LIST 148
216#define OPCODE_COMMON_GET_HSW_CONFIG 152
217#define OPCODE_COMMON_GET_FUNC_CONFIG 160
218#define OPCODE_COMMON_GET_PROFILE_CONFIG 164
219#define OPCODE_COMMON_SET_PROFILE_CONFIG 165
220#define OPCODE_COMMON_GET_ACTIVE_PROFILE 167
221#define OPCODE_COMMON_SET_HSW_CONFIG 153
222#define OPCODE_COMMON_GET_FN_PRIVILEGES 170
223#define OPCODE_COMMON_READ_OBJECT 171
224#define OPCODE_COMMON_WRITE_OBJECT 172
225#define OPCODE_COMMON_MANAGE_IFACE_FILTERS 193
226#define OPCODE_COMMON_GET_IFACE_LIST 194
227#define OPCODE_COMMON_ENABLE_DISABLE_VF 196
228
229#define OPCODE_ETH_RSS_CONFIG 1
230#define OPCODE_ETH_ACPI_CONFIG 2
231#define OPCODE_ETH_PROMISCUOUS 3
232#define OPCODE_ETH_GET_STATISTICS 4
233#define OPCODE_ETH_TX_CREATE 7
234#define OPCODE_ETH_RX_CREATE 8
235#define OPCODE_ETH_TX_DESTROY 9
236#define OPCODE_ETH_RX_DESTROY 10
237#define OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG 12
238#define OPCODE_ETH_GET_PPORT_STATS 18
239
240#define OPCODE_LOWLEVEL_HOST_DDR_DMA 17
241#define OPCODE_LOWLEVEL_LOOPBACK_TEST 18
242#define OPCODE_LOWLEVEL_SET_LOOPBACK_MODE 19
243
244struct be_cmd_req_hdr {
245 u8 opcode; /* dword 0 */
246 u8 subsystem; /* dword 0 */
247 u8 port_number; /* dword 0 */
248 u8 domain; /* dword 0 */
249 u32 timeout; /* dword 1 */
250 u32 request_length; /* dword 2 */
251 u8 version; /* dword 3 */
252 u8 rsvd[3]; /* dword 3 */
253};
254
255#define RESP_HDR_INFO_OPCODE_SHIFT 0 /* bits 0 - 7 */
256#define RESP_HDR_INFO_SUBSYS_SHIFT 8 /* bits 8 - 15 */
257struct be_cmd_resp_hdr {
258 u8 opcode; /* dword 0 */
259 u8 subsystem; /* dword 0 */
260 u8 rsvd[2]; /* dword 0 */
261 u8 status; /* dword 1 */
262 u8 add_status; /* dword 1 */
263 u8 rsvd1[2]; /* dword 1 */
264 u32 response_length; /* dword 2 */
265 u32 actual_resp_len; /* dword 3 */
266};
267
268struct phys_addr {
269 u32 lo;
270 u32 hi;
271};
272
273/**************************
274 * BE Command definitions *
275 **************************/
276
277/* Pseudo amap definition in which each bit of the actual structure is defined
278 * as a byte: used to calculate offset/shift/mask of each field */
279struct amap_eq_context {
280 u8 cidx[13]; /* dword 0*/
281 u8 rsvd0[3]; /* dword 0*/
282 u8 epidx[13]; /* dword 0*/
283 u8 valid; /* dword 0*/
284 u8 rsvd1; /* dword 0*/
285 u8 size; /* dword 0*/
286 u8 pidx[13]; /* dword 1*/
287 u8 rsvd2[3]; /* dword 1*/
288 u8 pd[10]; /* dword 1*/
289 u8 count[3]; /* dword 1*/
290 u8 solevent; /* dword 1*/
291 u8 stalled; /* dword 1*/
292 u8 armed; /* dword 1*/
293 u8 rsvd3[4]; /* dword 2*/
294 u8 func[8]; /* dword 2*/
295 u8 rsvd4; /* dword 2*/
296 u8 delaymult[10]; /* dword 2*/
297 u8 rsvd5[2]; /* dword 2*/
298 u8 phase[2]; /* dword 2*/
299 u8 nodelay; /* dword 2*/
300 u8 rsvd6[4]; /* dword 2*/
301 u8 rsvd7[32]; /* dword 3*/
302} __packed;
303
304struct be_cmd_req_eq_create {
305 struct be_cmd_req_hdr hdr;
306 u16 num_pages; /* sword */
307 u16 rsvd0; /* sword */
308 u8 context[sizeof(struct amap_eq_context) / 8];
309 struct phys_addr pages[8];
310} __packed;
311
312struct be_cmd_resp_eq_create {
313 struct be_cmd_resp_hdr resp_hdr;
314 u16 eq_id; /* sword */
315 u16 msix_idx; /* available only in v2 */
316} __packed;
317
318/******************** Mac query ***************************/
319enum {
320 MAC_ADDRESS_TYPE_STORAGE = 0x0,
321 MAC_ADDRESS_TYPE_NETWORK = 0x1,
322 MAC_ADDRESS_TYPE_PD = 0x2,
323 MAC_ADDRESS_TYPE_MANAGEMENT = 0x3
324};
325
326struct mac_addr {
327 u16 size_of_struct;
328 u8 addr[ETH_ALEN];
329} __packed;
330
331struct be_cmd_req_mac_query {
332 struct be_cmd_req_hdr hdr;
333 u8 type;
334 u8 permanent;
335 u16 if_id;
336 u32 pmac_id;
337} __packed;
338
339struct be_cmd_resp_mac_query {
340 struct be_cmd_resp_hdr hdr;
341 struct mac_addr mac;
342};
343
344/******************** PMac Add ***************************/
345struct be_cmd_req_pmac_add {
346 struct be_cmd_req_hdr hdr;
347 u32 if_id;
348 u8 mac_address[ETH_ALEN];
349 u8 rsvd0[2];
350} __packed;
351
352struct be_cmd_resp_pmac_add {
353 struct be_cmd_resp_hdr hdr;
354 u32 pmac_id;
355};
356
357/******************** PMac Del ***************************/
358struct be_cmd_req_pmac_del {
359 struct be_cmd_req_hdr hdr;
360 u32 if_id;
361 u32 pmac_id;
362};
363
364/******************** Create CQ ***************************/
365/* Pseudo amap definition in which each bit of the actual structure is defined
366 * as a byte: used to calculate offset/shift/mask of each field */
367struct amap_cq_context_be {
368 u8 cidx[11]; /* dword 0*/
369 u8 rsvd0; /* dword 0*/
370 u8 coalescwm[2]; /* dword 0*/
371 u8 nodelay; /* dword 0*/
372 u8 epidx[11]; /* dword 0*/
373 u8 rsvd1; /* dword 0*/
374 u8 count[2]; /* dword 0*/
375 u8 valid; /* dword 0*/
376 u8 solevent; /* dword 0*/
377 u8 eventable; /* dword 0*/
378 u8 pidx[11]; /* dword 1*/
379 u8 rsvd2; /* dword 1*/
380 u8 pd[10]; /* dword 1*/
381 u8 eqid[8]; /* dword 1*/
382 u8 stalled; /* dword 1*/
383 u8 armed; /* dword 1*/
384 u8 rsvd3[4]; /* dword 2*/
385 u8 func[8]; /* dword 2*/
386 u8 rsvd4[20]; /* dword 2*/
387 u8 rsvd5[32]; /* dword 3*/
388} __packed;
389
390struct amap_cq_context_v2 {
391 u8 rsvd0[12]; /* dword 0*/
392 u8 coalescwm[2]; /* dword 0*/
393 u8 nodelay; /* dword 0*/
394 u8 rsvd1[12]; /* dword 0*/
395 u8 count[2]; /* dword 0*/
396 u8 valid; /* dword 0*/
397 u8 rsvd2; /* dword 0*/
398 u8 eventable; /* dword 0*/
399 u8 eqid[16]; /* dword 1*/
400 u8 rsvd3[15]; /* dword 1*/
401 u8 armed; /* dword 1*/
402 u8 rsvd4[32]; /* dword 2*/
403 u8 rsvd5[32]; /* dword 3*/
404} __packed;
405
406struct be_cmd_req_cq_create {
407 struct be_cmd_req_hdr hdr;
408 u16 num_pages;
409 u8 page_size;
410 u8 rsvd0;
411 u8 context[sizeof(struct amap_cq_context_be) / 8];
412 struct phys_addr pages[8];
413} __packed;
414
415
416struct be_cmd_resp_cq_create {
417 struct be_cmd_resp_hdr hdr;
418 u16 cq_id;
419 u16 rsvd0;
420} __packed;
421
422struct be_cmd_req_get_fat {
423 struct be_cmd_req_hdr hdr;
424 u32 fat_operation;
425 u32 read_log_offset;
426 u32 read_log_length;
427 u32 data_buffer_size;
428 u32 data_buffer[1];
429} __packed;
430
431struct be_cmd_resp_get_fat {
432 struct be_cmd_resp_hdr hdr;
433 u32 log_size;
434 u32 read_log_length;
435 u32 rsvd[2];
436 u32 data_buffer[1];
437} __packed;
438
439
440/******************** Create MCCQ ***************************/
441/* Pseudo amap definition in which each bit of the actual structure is defined
442 * as a byte: used to calculate offset/shift/mask of each field */
443struct amap_mcc_context_be {
444 u8 con_index[14];
445 u8 rsvd0[2];
446 u8 ring_size[4];
447 u8 fetch_wrb;
448 u8 fetch_r2t;
449 u8 cq_id[10];
450 u8 prod_index[14];
451 u8 fid[8];
452 u8 pdid[9];
453 u8 valid;
454 u8 rsvd1[32];
455 u8 rsvd2[32];
456} __packed;
457
458struct amap_mcc_context_v1 {
459 u8 async_cq_id[16];
460 u8 ring_size[4];
461 u8 rsvd0[12];
462 u8 rsvd1[31];
463 u8 valid;
464 u8 async_cq_valid[1];
465 u8 rsvd2[31];
466 u8 rsvd3[32];
467} __packed;
468
469struct be_cmd_req_mcc_create {
470 struct be_cmd_req_hdr hdr;
471 u16 num_pages;
472 u16 cq_id;
473 u8 context[sizeof(struct amap_mcc_context_be) / 8];
474 struct phys_addr pages[8];
475} __packed;
476
477struct be_cmd_req_mcc_ext_create {
478 struct be_cmd_req_hdr hdr;
479 u16 num_pages;
480 u16 cq_id;
481 u32 async_event_bitmap[1];
482 u8 context[sizeof(struct amap_mcc_context_v1) / 8];
483 struct phys_addr pages[8];
484} __packed;
485
486struct be_cmd_resp_mcc_create {
487 struct be_cmd_resp_hdr hdr;
488 u16 id;
489 u16 rsvd0;
490} __packed;
491
492/******************** Create TxQ ***************************/
493#define BE_ETH_TX_RING_TYPE_STANDARD 2
494#define BE_ULP1_NUM 1
495
496struct be_cmd_req_eth_tx_create {
497 struct be_cmd_req_hdr hdr;
498 u8 num_pages;
499 u8 ulp_num;
500 u16 type;
501 u16 if_id;
502 u8 queue_size;
503 u8 rsvd0;
504 u32 rsvd1;
505 u16 cq_id;
506 u16 rsvd2;
507 u32 rsvd3[13];
508 struct phys_addr pages[8];
509} __packed;
510
511struct be_cmd_resp_eth_tx_create {
512 struct be_cmd_resp_hdr hdr;
513 u16 cid;
514 u16 rid;
515 u32 db_offset;
516 u32 rsvd0[4];
517} __packed;
518
519/******************** Create RxQ ***************************/
520struct be_cmd_req_eth_rx_create {
521 struct be_cmd_req_hdr hdr;
522 u16 cq_id;
523 u8 frag_size;
524 u8 num_pages;
525 struct phys_addr pages[2];
526 u32 interface_id;
527 u16 max_frame_size;
528 u16 rsvd0;
529 u32 rss_queue;
530} __packed;
531
532struct be_cmd_resp_eth_rx_create {
533 struct be_cmd_resp_hdr hdr;
534 u16 id;
535 u8 rss_id;
536 u8 rsvd0;
537} __packed;
538
539/******************** Q Destroy ***************************/
540/* Type of Queue to be destroyed */
541enum {
542 QTYPE_EQ = 1,
543 QTYPE_CQ,
544 QTYPE_TXQ,
545 QTYPE_RXQ,
546 QTYPE_MCCQ
547};
548
549struct be_cmd_req_q_destroy {
550 struct be_cmd_req_hdr hdr;
551 u16 id;
552 u16 bypass_flush; /* valid only for rx q destroy */
553} __packed;
554
555/************ I/f Create (it's actually I/f Config Create)**********/
556
557/* Capability flags for the i/f */
558enum be_if_flags {
559 BE_IF_FLAGS_RSS = 0x4,
560 BE_IF_FLAGS_PROMISCUOUS = 0x8,
561 BE_IF_FLAGS_BROADCAST = 0x10,
562 BE_IF_FLAGS_UNTAGGED = 0x20,
563 BE_IF_FLAGS_ULP = 0x40,
564 BE_IF_FLAGS_VLAN_PROMISCUOUS = 0x80,
565 BE_IF_FLAGS_VLAN = 0x100,
566 BE_IF_FLAGS_MCAST_PROMISCUOUS = 0x200,
567 BE_IF_FLAGS_PASS_L2_ERRORS = 0x400,
568 BE_IF_FLAGS_PASS_L3L4_ERRORS = 0x800,
569 BE_IF_FLAGS_MULTICAST = 0x1000
570};
571
572#define BE_IF_CAP_FLAGS_WANT (BE_IF_FLAGS_RSS | BE_IF_FLAGS_PROMISCUOUS |\
573 BE_IF_FLAGS_BROADCAST | BE_IF_FLAGS_VLAN_PROMISCUOUS |\
574 BE_IF_FLAGS_VLAN | BE_IF_FLAGS_MCAST_PROMISCUOUS |\
575 BE_IF_FLAGS_PASS_L3L4_ERRORS | BE_IF_FLAGS_MULTICAST |\
576 BE_IF_FLAGS_UNTAGGED)
577
578/* An RX interface is an object with one or more MAC addresses and
579 * filtering capabilities. */
580struct be_cmd_req_if_create {
581 struct be_cmd_req_hdr hdr;
582 u32 version; /* ignore currently */
583 u32 capability_flags;
584 u32 enable_flags;
585 u8 mac_addr[ETH_ALEN];
586 u8 rsvd0;
587 u8 pmac_invalid; /* if set, don't attach the mac addr to the i/f */
588 u32 vlan_tag; /* not used currently */
589} __packed;
590
591struct be_cmd_resp_if_create {
592 struct be_cmd_resp_hdr hdr;
593 u32 interface_id;
594 u32 pmac_id;
595};
596
597/****** I/f Destroy(it's actually I/f Config Destroy )**********/
598struct be_cmd_req_if_destroy {
599 struct be_cmd_req_hdr hdr;
600 u32 interface_id;
601};
602
603/*************** HW Stats Get **********************************/
604struct be_port_rxf_stats_v0 {
605 u32 rx_bytes_lsd; /* dword 0*/
606 u32 rx_bytes_msd; /* dword 1*/
607 u32 rx_total_frames; /* dword 2*/
608 u32 rx_unicast_frames; /* dword 3*/
609 u32 rx_multicast_frames; /* dword 4*/
610 u32 rx_broadcast_frames; /* dword 5*/
611 u32 rx_crc_errors; /* dword 6*/
612 u32 rx_alignment_symbol_errors; /* dword 7*/
613 u32 rx_pause_frames; /* dword 8*/
614 u32 rx_control_frames; /* dword 9*/
615 u32 rx_in_range_errors; /* dword 10*/
616 u32 rx_out_range_errors; /* dword 11*/
617 u32 rx_frame_too_long; /* dword 12*/
618 u32 rx_address_filtered; /* dword 13*/
619 u32 rx_vlan_filtered; /* dword 14*/
620 u32 rx_dropped_too_small; /* dword 15*/
621 u32 rx_dropped_too_short; /* dword 16*/
622 u32 rx_dropped_header_too_small; /* dword 17*/
623 u32 rx_dropped_tcp_length; /* dword 18*/
624 u32 rx_dropped_runt; /* dword 19*/
625 u32 rx_64_byte_packets; /* dword 20*/
626 u32 rx_65_127_byte_packets; /* dword 21*/
627 u32 rx_128_256_byte_packets; /* dword 22*/
628 u32 rx_256_511_byte_packets; /* dword 23*/
629 u32 rx_512_1023_byte_packets; /* dword 24*/
630 u32 rx_1024_1518_byte_packets; /* dword 25*/
631 u32 rx_1519_2047_byte_packets; /* dword 26*/
632 u32 rx_2048_4095_byte_packets; /* dword 27*/
633 u32 rx_4096_8191_byte_packets; /* dword 28*/
634 u32 rx_8192_9216_byte_packets; /* dword 29*/
635 u32 rx_ip_checksum_errs; /* dword 30*/
636 u32 rx_tcp_checksum_errs; /* dword 31*/
637 u32 rx_udp_checksum_errs; /* dword 32*/
638 u32 rx_non_rss_packets; /* dword 33*/
639 u32 rx_ipv4_packets; /* dword 34*/
640 u32 rx_ipv6_packets; /* dword 35*/
641 u32 rx_ipv4_bytes_lsd; /* dword 36*/
642 u32 rx_ipv4_bytes_msd; /* dword 37*/
643 u32 rx_ipv6_bytes_lsd; /* dword 38*/
644 u32 rx_ipv6_bytes_msd; /* dword 39*/
645 u32 rx_chute1_packets; /* dword 40*/
646 u32 rx_chute2_packets; /* dword 41*/
647 u32 rx_chute3_packets; /* dword 42*/
648 u32 rx_management_packets; /* dword 43*/
649 u32 rx_switched_unicast_packets; /* dword 44*/
650 u32 rx_switched_multicast_packets; /* dword 45*/
651 u32 rx_switched_broadcast_packets; /* dword 46*/
652 u32 tx_bytes_lsd; /* dword 47*/
653 u32 tx_bytes_msd; /* dword 48*/
654 u32 tx_unicastframes; /* dword 49*/
655 u32 tx_multicastframes; /* dword 50*/
656 u32 tx_broadcastframes; /* dword 51*/
657 u32 tx_pauseframes; /* dword 52*/
658 u32 tx_controlframes; /* dword 53*/
659 u32 tx_64_byte_packets; /* dword 54*/
660 u32 tx_65_127_byte_packets; /* dword 55*/
661 u32 tx_128_256_byte_packets; /* dword 56*/
662 u32 tx_256_511_byte_packets; /* dword 57*/
663 u32 tx_512_1023_byte_packets; /* dword 58*/
664 u32 tx_1024_1518_byte_packets; /* dword 59*/
665 u32 tx_1519_2047_byte_packets; /* dword 60*/
666 u32 tx_2048_4095_byte_packets; /* dword 61*/
667 u32 tx_4096_8191_byte_packets; /* dword 62*/
668 u32 tx_8192_9216_byte_packets; /* dword 63*/
669 u32 rx_fifo_overflow; /* dword 64*/
670 u32 rx_input_fifo_overflow; /* dword 65*/
671};
672
673struct be_rxf_stats_v0 {
674 struct be_port_rxf_stats_v0 port[2];
675 u32 rx_drops_no_pbuf; /* dword 132*/
676 u32 rx_drops_no_txpb; /* dword 133*/
677 u32 rx_drops_no_erx_descr; /* dword 134*/
678 u32 rx_drops_no_tpre_descr; /* dword 135*/
679 u32 management_rx_port_packets; /* dword 136*/
680 u32 management_rx_port_bytes; /* dword 137*/
681 u32 management_rx_port_pause_frames; /* dword 138*/
682 u32 management_rx_port_errors; /* dword 139*/
683 u32 management_tx_port_packets; /* dword 140*/
684 u32 management_tx_port_bytes; /* dword 141*/
685 u32 management_tx_port_pause; /* dword 142*/
686 u32 management_rx_port_rxfifo_overflow; /* dword 143*/
687 u32 rx_drops_too_many_frags; /* dword 144*/
688 u32 rx_drops_invalid_ring; /* dword 145*/
689 u32 forwarded_packets; /* dword 146*/
690 u32 rx_drops_mtu; /* dword 147*/
691 u32 rsvd0[7];
692 u32 port0_jabber_events;
693 u32 port1_jabber_events;
694 u32 rsvd1[6];
695};
696
697struct be_erx_stats_v0 {
698 u32 rx_drops_no_fragments[44]; /* dwordS 0 to 43*/
699 u32 rsvd[4];
700};
701
702struct be_pmem_stats {
703 u32 eth_red_drops;
704 u32 rsvd[5];
705};
706
707struct be_hw_stats_v0 {
708 struct be_rxf_stats_v0 rxf;
709 u32 rsvd[48];
710 struct be_erx_stats_v0 erx;
711 struct be_pmem_stats pmem;
712};
713
714struct be_cmd_req_get_stats_v0 {
715 struct be_cmd_req_hdr hdr;
716 u8 rsvd[sizeof(struct be_hw_stats_v0)];
717};
718
719struct be_cmd_resp_get_stats_v0 {
720 struct be_cmd_resp_hdr hdr;
721 struct be_hw_stats_v0 hw_stats;
722};
723
724struct lancer_pport_stats {
725 u32 tx_packets_lo;
726 u32 tx_packets_hi;
727 u32 tx_unicast_packets_lo;
728 u32 tx_unicast_packets_hi;
729 u32 tx_multicast_packets_lo;
730 u32 tx_multicast_packets_hi;
731 u32 tx_broadcast_packets_lo;
732 u32 tx_broadcast_packets_hi;
733 u32 tx_bytes_lo;
734 u32 tx_bytes_hi;
735 u32 tx_unicast_bytes_lo;
736 u32 tx_unicast_bytes_hi;
737 u32 tx_multicast_bytes_lo;
738 u32 tx_multicast_bytes_hi;
739 u32 tx_broadcast_bytes_lo;
740 u32 tx_broadcast_bytes_hi;
741 u32 tx_discards_lo;
742 u32 tx_discards_hi;
743 u32 tx_errors_lo;
744 u32 tx_errors_hi;
745 u32 tx_pause_frames_lo;
746 u32 tx_pause_frames_hi;
747 u32 tx_pause_on_frames_lo;
748 u32 tx_pause_on_frames_hi;
749 u32 tx_pause_off_frames_lo;
750 u32 tx_pause_off_frames_hi;
751 u32 tx_internal_mac_errors_lo;
752 u32 tx_internal_mac_errors_hi;
753 u32 tx_control_frames_lo;
754 u32 tx_control_frames_hi;
755 u32 tx_packets_64_bytes_lo;
756 u32 tx_packets_64_bytes_hi;
757 u32 tx_packets_65_to_127_bytes_lo;
758 u32 tx_packets_65_to_127_bytes_hi;
759 u32 tx_packets_128_to_255_bytes_lo;
760 u32 tx_packets_128_to_255_bytes_hi;
761 u32 tx_packets_256_to_511_bytes_lo;
762 u32 tx_packets_256_to_511_bytes_hi;
763 u32 tx_packets_512_to_1023_bytes_lo;
764 u32 tx_packets_512_to_1023_bytes_hi;
765 u32 tx_packets_1024_to_1518_bytes_lo;
766 u32 tx_packets_1024_to_1518_bytes_hi;
767 u32 tx_packets_1519_to_2047_bytes_lo;
768 u32 tx_packets_1519_to_2047_bytes_hi;
769 u32 tx_packets_2048_to_4095_bytes_lo;
770 u32 tx_packets_2048_to_4095_bytes_hi;
771 u32 tx_packets_4096_to_8191_bytes_lo;
772 u32 tx_packets_4096_to_8191_bytes_hi;
773 u32 tx_packets_8192_to_9216_bytes_lo;
774 u32 tx_packets_8192_to_9216_bytes_hi;
775 u32 tx_lso_packets_lo;
776 u32 tx_lso_packets_hi;
777 u32 rx_packets_lo;
778 u32 rx_packets_hi;
779 u32 rx_unicast_packets_lo;
780 u32 rx_unicast_packets_hi;
781 u32 rx_multicast_packets_lo;
782 u32 rx_multicast_packets_hi;
783 u32 rx_broadcast_packets_lo;
784 u32 rx_broadcast_packets_hi;
785 u32 rx_bytes_lo;
786 u32 rx_bytes_hi;
787 u32 rx_unicast_bytes_lo;
788 u32 rx_unicast_bytes_hi;
789 u32 rx_multicast_bytes_lo;
790 u32 rx_multicast_bytes_hi;
791 u32 rx_broadcast_bytes_lo;
792 u32 rx_broadcast_bytes_hi;
793 u32 rx_unknown_protos;
794 u32 rsvd_69; /* Word 69 is reserved */
795 u32 rx_discards_lo;
796 u32 rx_discards_hi;
797 u32 rx_errors_lo;
798 u32 rx_errors_hi;
799 u32 rx_crc_errors_lo;
800 u32 rx_crc_errors_hi;
801 u32 rx_alignment_errors_lo;
802 u32 rx_alignment_errors_hi;
803 u32 rx_symbol_errors_lo;
804 u32 rx_symbol_errors_hi;
805 u32 rx_pause_frames_lo;
806 u32 rx_pause_frames_hi;
807 u32 rx_pause_on_frames_lo;
808 u32 rx_pause_on_frames_hi;
809 u32 rx_pause_off_frames_lo;
810 u32 rx_pause_off_frames_hi;
811 u32 rx_frames_too_long_lo;
812 u32 rx_frames_too_long_hi;
813 u32 rx_internal_mac_errors_lo;
814 u32 rx_internal_mac_errors_hi;
815 u32 rx_undersize_packets;
816 u32 rx_oversize_packets;
817 u32 rx_fragment_packets;
818 u32 rx_jabbers;
819 u32 rx_control_frames_lo;
820 u32 rx_control_frames_hi;
821 u32 rx_control_frames_unknown_opcode_lo;
822 u32 rx_control_frames_unknown_opcode_hi;
823 u32 rx_in_range_errors;
824 u32 rx_out_of_range_errors;
825 u32 rx_address_filtered;
826 u32 rx_vlan_filtered;
827 u32 rx_dropped_too_small;
828 u32 rx_dropped_too_short;
829 u32 rx_dropped_header_too_small;
830 u32 rx_dropped_invalid_tcp_length;
831 u32 rx_dropped_runt;
832 u32 rx_ip_checksum_errors;
833 u32 rx_tcp_checksum_errors;
834 u32 rx_udp_checksum_errors;
835 u32 rx_non_rss_packets;
836 u32 rsvd_111;
837 u32 rx_ipv4_packets_lo;
838 u32 rx_ipv4_packets_hi;
839 u32 rx_ipv6_packets_lo;
840 u32 rx_ipv6_packets_hi;
841 u32 rx_ipv4_bytes_lo;
842 u32 rx_ipv4_bytes_hi;
843 u32 rx_ipv6_bytes_lo;
844 u32 rx_ipv6_bytes_hi;
845 u32 rx_nic_packets_lo;
846 u32 rx_nic_packets_hi;
847 u32 rx_tcp_packets_lo;
848 u32 rx_tcp_packets_hi;
849 u32 rx_iscsi_packets_lo;
850 u32 rx_iscsi_packets_hi;
851 u32 rx_management_packets_lo;
852 u32 rx_management_packets_hi;
853 u32 rx_switched_unicast_packets_lo;
854 u32 rx_switched_unicast_packets_hi;
855 u32 rx_switched_multicast_packets_lo;
856 u32 rx_switched_multicast_packets_hi;
857 u32 rx_switched_broadcast_packets_lo;
858 u32 rx_switched_broadcast_packets_hi;
859 u32 num_forwards_lo;
860 u32 num_forwards_hi;
861 u32 rx_fifo_overflow;
862 u32 rx_input_fifo_overflow;
863 u32 rx_drops_too_many_frags_lo;
864 u32 rx_drops_too_many_frags_hi;
865 u32 rx_drops_invalid_queue;
866 u32 rsvd_141;
867 u32 rx_drops_mtu_lo;
868 u32 rx_drops_mtu_hi;
869 u32 rx_packets_64_bytes_lo;
870 u32 rx_packets_64_bytes_hi;
871 u32 rx_packets_65_to_127_bytes_lo;
872 u32 rx_packets_65_to_127_bytes_hi;
873 u32 rx_packets_128_to_255_bytes_lo;
874 u32 rx_packets_128_to_255_bytes_hi;
875 u32 rx_packets_256_to_511_bytes_lo;
876 u32 rx_packets_256_to_511_bytes_hi;
877 u32 rx_packets_512_to_1023_bytes_lo;
878 u32 rx_packets_512_to_1023_bytes_hi;
879 u32 rx_packets_1024_to_1518_bytes_lo;
880 u32 rx_packets_1024_to_1518_bytes_hi;
881 u32 rx_packets_1519_to_2047_bytes_lo;
882 u32 rx_packets_1519_to_2047_bytes_hi;
883 u32 rx_packets_2048_to_4095_bytes_lo;
884 u32 rx_packets_2048_to_4095_bytes_hi;
885 u32 rx_packets_4096_to_8191_bytes_lo;
886 u32 rx_packets_4096_to_8191_bytes_hi;
887 u32 rx_packets_8192_to_9216_bytes_lo;
888 u32 rx_packets_8192_to_9216_bytes_hi;
889};
890
891struct pport_stats_params {
892 u16 pport_num;
893 u8 rsvd;
894 u8 reset_stats;
895};
896
897struct lancer_cmd_req_pport_stats {
898 struct be_cmd_req_hdr hdr;
899 union {
900 struct pport_stats_params params;
901 u8 rsvd[sizeof(struct lancer_pport_stats)];
902 } cmd_params;
903};
904
905struct lancer_cmd_resp_pport_stats {
906 struct be_cmd_resp_hdr hdr;
907 struct lancer_pport_stats pport_stats;
908};
909
910static inline struct lancer_pport_stats*
911 pport_stats_from_cmd(struct be_adapter *adapter)
912{
913 struct lancer_cmd_resp_pport_stats *cmd = adapter->stats_cmd.va;
914 return &cmd->pport_stats;
915}
916
917struct be_cmd_req_get_cntl_addnl_attribs {
918 struct be_cmd_req_hdr hdr;
919 u8 rsvd[8];
920};
921
922struct be_cmd_resp_get_cntl_addnl_attribs {
923 struct be_cmd_resp_hdr hdr;
924 u16 ipl_file_number;
925 u8 ipl_file_version;
926 u8 rsvd0;
927 u8 on_die_temperature; /* in degrees centigrade*/
928 u8 rsvd1[3];
929};
930
931struct be_cmd_req_vlan_config {
932 struct be_cmd_req_hdr hdr;
933 u8 interface_id;
934 u8 promiscuous;
935 u8 untagged;
936 u8 num_vlan;
937 u16 normal_vlan[64];
938} __packed;
939
940/******************* RX FILTER ******************************/
941#define BE_MAX_MC 64 /* set mcast promisc if > 64 */
942struct macaddr {
943 u8 byte[ETH_ALEN];
944};
945
946struct be_cmd_req_rx_filter {
947 struct be_cmd_req_hdr hdr;
948 u32 global_flags_mask;
949 u32 global_flags;
950 u32 if_flags_mask;
951 u32 if_flags;
952 u32 if_id;
953 u32 mcast_num;
954 struct macaddr mcast_mac[BE_MAX_MC];
955};
956
957/******************** Link Status Query *******************/
958struct be_cmd_req_link_status {
959 struct be_cmd_req_hdr hdr;
960 u32 rsvd;
961};
962
963enum {
964 PHY_LINK_DUPLEX_NONE = 0x0,
965 PHY_LINK_DUPLEX_HALF = 0x1,
966 PHY_LINK_DUPLEX_FULL = 0x2
967};
968
969enum {
970 PHY_LINK_SPEED_ZERO = 0x0, /* => No link */
971 PHY_LINK_SPEED_10MBPS = 0x1,
972 PHY_LINK_SPEED_100MBPS = 0x2,
973 PHY_LINK_SPEED_1GBPS = 0x3,
974 PHY_LINK_SPEED_10GBPS = 0x4,
975 PHY_LINK_SPEED_20GBPS = 0x5,
976 PHY_LINK_SPEED_25GBPS = 0x6,
977 PHY_LINK_SPEED_40GBPS = 0x7
978};
979
980struct be_cmd_resp_link_status {
981 struct be_cmd_resp_hdr hdr;
982 u8 physical_port;
983 u8 mac_duplex;
984 u8 mac_speed;
985 u8 mac_fault;
986 u8 mgmt_mac_duplex;
987 u8 mgmt_mac_speed;
988 u16 link_speed;
989 u8 logical_link_status;
990 u8 rsvd1[3];
991} __packed;
992
993/******************** Port Identification ***************************/
994/* Identifies the type of port attached to NIC */
995struct be_cmd_req_port_type {
996 struct be_cmd_req_hdr hdr;
997 u32 page_num;
998 u32 port;
999};
1000
1001enum {
1002 TR_PAGE_A0 = 0xa0,
1003 TR_PAGE_A2 = 0xa2
1004};
1005
1006struct be_cmd_resp_port_type {
1007 struct be_cmd_resp_hdr hdr;
1008 u32 page_num;
1009 u32 port;
1010 struct data {
1011 u8 identifier;
1012 u8 identifier_ext;
1013 u8 connector;
1014 u8 transceiver[8];
1015 u8 rsvd0[3];
1016 u8 length_km;
1017 u8 length_hm;
1018 u8 length_om1;
1019 u8 length_om2;
1020 u8 length_cu;
1021 u8 length_cu_m;
1022 u8 vendor_name[16];
1023 u8 rsvd;
1024 u8 vendor_oui[3];
1025 u8 vendor_pn[16];
1026 u8 vendor_rev[4];
1027 } data;
1028};
1029
1030/******************** Get FW Version *******************/
1031struct be_cmd_req_get_fw_version {
1032 struct be_cmd_req_hdr hdr;
1033 u8 rsvd0[FW_VER_LEN];
1034 u8 rsvd1[FW_VER_LEN];
1035} __packed;
1036
1037struct be_cmd_resp_get_fw_version {
1038 struct be_cmd_resp_hdr hdr;
1039 u8 firmware_version_string[FW_VER_LEN];
1040 u8 fw_on_flash_version_string[FW_VER_LEN];
1041} __packed;
1042
1043/******************** Set Flow Contrl *******************/
1044struct be_cmd_req_set_flow_control {
1045 struct be_cmd_req_hdr hdr;
1046 u16 tx_flow_control;
1047 u16 rx_flow_control;
1048} __packed;
1049
1050/******************** Get Flow Contrl *******************/
1051struct be_cmd_req_get_flow_control {
1052 struct be_cmd_req_hdr hdr;
1053 u32 rsvd;
1054};
1055
1056struct be_cmd_resp_get_flow_control {
1057 struct be_cmd_resp_hdr hdr;
1058 u16 tx_flow_control;
1059 u16 rx_flow_control;
1060} __packed;
1061
1062/******************** Modify EQ Delay *******************/
1063struct be_set_eqd {
1064 u32 eq_id;
1065 u32 phase;
1066 u32 delay_multiplier;
1067};
1068
1069struct be_cmd_req_modify_eq_delay {
1070 struct be_cmd_req_hdr hdr;
1071 u32 num_eq;
1072 struct be_set_eqd set_eqd[MAX_EVT_QS];
1073} __packed;
1074
1075struct be_cmd_resp_modify_eq_delay {
1076 struct be_cmd_resp_hdr hdr;
1077 u32 rsvd0;
1078} __packed;
1079
1080/******************** Get FW Config *******************/
1081/* The HW can come up in either of the following multi-channel modes
1082 * based on the skew/IPL.
1083 */
1084#define RDMA_ENABLED 0x4
1085#define FLEX10_MODE 0x400
1086#define VNIC_MODE 0x20000
1087#define UMC_ENABLED 0x1000000
1088struct be_cmd_req_query_fw_cfg {
1089 struct be_cmd_req_hdr hdr;
1090 u32 rsvd[31];
1091};
1092
1093struct be_cmd_resp_query_fw_cfg {
1094 struct be_cmd_resp_hdr hdr;
1095 u32 be_config_number;
1096 u32 asic_revision;
1097 u32 phys_port;
1098 u32 function_mode;
1099 u32 rsvd[26];
1100 u32 function_caps;
1101};
1102
1103/******************** RSS Config ****************************************/
1104/* RSS type Input parameters used to compute RX hash
1105 * RSS_ENABLE_IPV4 SRC IPv4, DST IPv4
1106 * RSS_ENABLE_TCP_IPV4 SRC IPv4, DST IPv4, TCP SRC PORT, TCP DST PORT
1107 * RSS_ENABLE_IPV6 SRC IPv6, DST IPv6
1108 * RSS_ENABLE_TCP_IPV6 SRC IPv6, DST IPv6, TCP SRC PORT, TCP DST PORT
1109 * RSS_ENABLE_UDP_IPV4 SRC IPv4, DST IPv4, UDP SRC PORT, UDP DST PORT
1110 * RSS_ENABLE_UDP_IPV6 SRC IPv6, DST IPv6, UDP SRC PORT, UDP DST PORT
1111 *
1112 * When multiple RSS types are enabled, HW picks the best hash policy
1113 * based on the type of the received packet.
1114 */
1115#define RSS_ENABLE_NONE 0x0
1116#define RSS_ENABLE_IPV4 0x1
1117#define RSS_ENABLE_TCP_IPV4 0x2
1118#define RSS_ENABLE_IPV6 0x4
1119#define RSS_ENABLE_TCP_IPV6 0x8
1120#define RSS_ENABLE_UDP_IPV4 0x10
1121#define RSS_ENABLE_UDP_IPV6 0x20
1122
1123#define L3_RSS_FLAGS (RXH_IP_DST | RXH_IP_SRC)
1124#define L4_RSS_FLAGS (RXH_L4_B_0_1 | RXH_L4_B_2_3)
1125
1126struct be_cmd_req_rss_config {
1127 struct be_cmd_req_hdr hdr;
1128 u32 if_id;
1129 u16 enable_rss;
1130 u16 cpu_table_size_log2;
1131 u32 hash[10];
1132 u8 cpu_table[128];
1133 u8 flush;
1134 u8 rsvd0[3];
1135};
1136
1137/******************** Port Beacon ***************************/
1138
1139#define BEACON_STATE_ENABLED 0x1
1140#define BEACON_STATE_DISABLED 0x0
1141
1142struct be_cmd_req_enable_disable_beacon {
1143 struct be_cmd_req_hdr hdr;
1144 u8 port_num;
1145 u8 beacon_state;
1146 u8 beacon_duration;
1147 u8 status_duration;
1148} __packed;
1149
1150struct be_cmd_resp_enable_disable_beacon {
1151 struct be_cmd_resp_hdr resp_hdr;
1152 u32 rsvd0;
1153} __packed;
1154
1155struct be_cmd_req_get_beacon_state {
1156 struct be_cmd_req_hdr hdr;
1157 u8 port_num;
1158 u8 rsvd0;
1159 u16 rsvd1;
1160} __packed;
1161
1162struct be_cmd_resp_get_beacon_state {
1163 struct be_cmd_resp_hdr resp_hdr;
1164 u8 beacon_state;
1165 u8 rsvd0[3];
1166} __packed;
1167
1168/****************** Firmware Flash ******************/
1169struct flashrom_params {
1170 u32 op_code;
1171 u32 op_type;
1172 u32 data_buf_size;
1173 u32 offset;
1174};
1175
1176struct be_cmd_write_flashrom {
1177 struct be_cmd_req_hdr hdr;
1178 struct flashrom_params params;
1179 u8 data_buf[32768];
1180 u8 rsvd[4];
1181} __packed;
1182
1183/* cmd to read flash crc */
1184struct be_cmd_read_flash_crc {
1185 struct be_cmd_req_hdr hdr;
1186 struct flashrom_params params;
1187 u8 crc[4];
1188 u8 rsvd[4];
1189};
1190/**************** Lancer Firmware Flash ************/
1191struct amap_lancer_write_obj_context {
1192 u8 write_length[24];
1193 u8 reserved1[7];
1194 u8 eof;
1195} __packed;
1196
1197struct lancer_cmd_req_write_object {
1198 struct be_cmd_req_hdr hdr;
1199 u8 context[sizeof(struct amap_lancer_write_obj_context) / 8];
1200 u32 write_offset;
1201 u8 object_name[104];
1202 u32 descriptor_count;
1203 u32 buf_len;
1204 u32 addr_low;
1205 u32 addr_high;
1206};
1207
1208#define LANCER_NO_RESET_NEEDED 0x00
1209#define LANCER_FW_RESET_NEEDED 0x02
1210struct lancer_cmd_resp_write_object {
1211 u8 opcode;
1212 u8 subsystem;
1213 u8 rsvd1[2];
1214 u8 status;
1215 u8 additional_status;
1216 u8 rsvd2[2];
1217 u32 resp_len;
1218 u32 actual_resp_len;
1219 u32 actual_write_len;
1220 u8 change_status;
1221 u8 rsvd3[3];
1222};
1223
1224/************************ Lancer Read FW info **************/
1225#define LANCER_READ_FILE_CHUNK (32*1024)
1226#define LANCER_READ_FILE_EOF_MASK 0x80000000
1227
1228#define LANCER_FW_DUMP_FILE "/dbg/dump.bin"
1229#define LANCER_VPD_PF_FILE "/vpd/ntr_pf.vpd"
1230#define LANCER_VPD_VF_FILE "/vpd/ntr_vf.vpd"
1231
1232struct lancer_cmd_req_read_object {
1233 struct be_cmd_req_hdr hdr;
1234 u32 desired_read_len;
1235 u32 read_offset;
1236 u8 object_name[104];
1237 u32 descriptor_count;
1238 u32 buf_len;
1239 u32 addr_low;
1240 u32 addr_high;
1241};
1242
1243struct lancer_cmd_resp_read_object {
1244 u8 opcode;
1245 u8 subsystem;
1246 u8 rsvd1[2];
1247 u8 status;
1248 u8 additional_status;
1249 u8 rsvd2[2];
1250 u32 resp_len;
1251 u32 actual_resp_len;
1252 u32 actual_read_len;
1253 u32 eof;
1254};
1255
1256/************************ WOL *******************************/
1257struct be_cmd_req_acpi_wol_magic_config{
1258 struct be_cmd_req_hdr hdr;
1259 u32 rsvd0[145];
1260 u8 magic_mac[6];
1261 u8 rsvd2[2];
1262} __packed;
1263
1264struct be_cmd_req_acpi_wol_magic_config_v1 {
1265 struct be_cmd_req_hdr hdr;
1266 u8 rsvd0[2];
1267 u8 query_options;
1268 u8 rsvd1[5];
1269 u32 rsvd2[288];
1270 u8 magic_mac[6];
1271 u8 rsvd3[22];
1272} __packed;
1273
1274struct be_cmd_resp_acpi_wol_magic_config_v1 {
1275 struct be_cmd_resp_hdr hdr;
1276 u8 rsvd0[2];
1277 u8 wol_settings;
1278 u8 rsvd1[5];
1279 u32 rsvd2[295];
1280} __packed;
1281
1282#define BE_GET_WOL_CAP 2
1283
1284#define BE_WOL_CAP 0x1
1285#define BE_PME_D0_CAP 0x8
1286#define BE_PME_D1_CAP 0x10
1287#define BE_PME_D2_CAP 0x20
1288#define BE_PME_D3HOT_CAP 0x40
1289#define BE_PME_D3COLD_CAP 0x80
1290
1291/********************** LoopBack test *********************/
1292struct be_cmd_req_loopback_test {
1293 struct be_cmd_req_hdr hdr;
1294 u32 loopback_type;
1295 u32 num_pkts;
1296 u64 pattern;
1297 u32 src_port;
1298 u32 dest_port;
1299 u32 pkt_size;
1300};
1301
1302struct be_cmd_resp_loopback_test {
1303 struct be_cmd_resp_hdr resp_hdr;
1304 u32 status;
1305 u32 num_txfer;
1306 u32 num_rx;
1307 u32 miscomp_off;
1308 u32 ticks_compl;
1309};
1310
1311struct be_cmd_req_set_lmode {
1312 struct be_cmd_req_hdr hdr;
1313 u8 src_port;
1314 u8 dest_port;
1315 u8 loopback_type;
1316 u8 loopback_state;
1317};
1318
1319struct be_cmd_resp_set_lmode {
1320 struct be_cmd_resp_hdr resp_hdr;
1321 u8 rsvd0[4];
1322};
1323
1324/********************** DDR DMA test *********************/
1325struct be_cmd_req_ddrdma_test {
1326 struct be_cmd_req_hdr hdr;
1327 u64 pattern;
1328 u32 byte_count;
1329 u32 rsvd0;
1330 u8 snd_buff[4096];
1331 u8 rsvd1[4096];
1332};
1333
1334struct be_cmd_resp_ddrdma_test {
1335 struct be_cmd_resp_hdr hdr;
1336 u64 pattern;
1337 u32 byte_cnt;
1338 u32 snd_err;
1339 u8 rsvd0[4096];
1340 u8 rcv_buff[4096];
1341};
1342
1343/*********************** SEEPROM Read ***********************/
1344
1345#define BE_READ_SEEPROM_LEN 1024
1346struct be_cmd_req_seeprom_read {
1347 struct be_cmd_req_hdr hdr;
1348 u8 rsvd0[BE_READ_SEEPROM_LEN];
1349};
1350
1351struct be_cmd_resp_seeprom_read {
1352 struct be_cmd_req_hdr hdr;
1353 u8 seeprom_data[BE_READ_SEEPROM_LEN];
1354};
1355
1356enum {
1357 PHY_TYPE_CX4_10GB = 0,
1358 PHY_TYPE_XFP_10GB,
1359 PHY_TYPE_SFP_1GB,
1360 PHY_TYPE_SFP_PLUS_10GB,
1361 PHY_TYPE_KR_10GB,
1362 PHY_TYPE_KX4_10GB,
1363 PHY_TYPE_BASET_10GB,
1364 PHY_TYPE_BASET_1GB,
1365 PHY_TYPE_BASEX_1GB,
1366 PHY_TYPE_SGMII,
1367 PHY_TYPE_DISABLED = 255
1368};
1369
1370#define BE_SUPPORTED_SPEED_NONE 0
1371#define BE_SUPPORTED_SPEED_10MBPS 1
1372#define BE_SUPPORTED_SPEED_100MBPS 2
1373#define BE_SUPPORTED_SPEED_1GBPS 4
1374#define BE_SUPPORTED_SPEED_10GBPS 8
1375
1376#define BE_AN_EN 0x2
1377#define BE_PAUSE_SYM_EN 0x80
1378
1379/* MAC speed valid values */
1380#define SPEED_DEFAULT 0x0
1381#define SPEED_FORCED_10GB 0x1
1382#define SPEED_FORCED_1GB 0x2
1383#define SPEED_AUTONEG_10GB 0x3
1384#define SPEED_AUTONEG_1GB 0x4
1385#define SPEED_AUTONEG_100MB 0x5
1386#define SPEED_AUTONEG_10GB_1GB 0x6
1387#define SPEED_AUTONEG_10GB_1GB_100MB 0x7
1388#define SPEED_AUTONEG_1GB_100MB 0x8
1389#define SPEED_AUTONEG_10MB 0x9
1390#define SPEED_AUTONEG_1GB_100MB_10MB 0xa
1391#define SPEED_AUTONEG_100MB_10MB 0xb
1392#define SPEED_FORCED_100MB 0xc
1393#define SPEED_FORCED_10MB 0xd
1394
1395struct be_cmd_req_get_phy_info {
1396 struct be_cmd_req_hdr hdr;
1397 u8 rsvd0[24];
1398};
1399
1400struct be_phy_info {
1401 u16 phy_type;
1402 u16 interface_type;
1403 u32 misc_params;
1404 u16 ext_phy_details;
1405 u16 rsvd;
1406 u16 auto_speeds_supported;
1407 u16 fixed_speeds_supported;
1408 u32 future_use[2];
1409};
1410
1411struct be_cmd_resp_get_phy_info {
1412 struct be_cmd_req_hdr hdr;
1413 struct be_phy_info phy_info;
1414};
1415
1416/*********************** Set QOS ***********************/
1417
1418#define BE_QOS_BITS_NIC 1
1419
1420struct be_cmd_req_set_qos {
1421 struct be_cmd_req_hdr hdr;
1422 u32 valid_bits;
1423 u32 max_bps_nic;
1424 u32 rsvd[7];
1425};
1426
1427struct be_cmd_resp_set_qos {
1428 struct be_cmd_resp_hdr hdr;
1429 u32 rsvd;
1430};
1431
1432/*********************** Controller Attributes ***********************/
1433struct be_cmd_req_cntl_attribs {
1434 struct be_cmd_req_hdr hdr;
1435};
1436
1437struct be_cmd_resp_cntl_attribs {
1438 struct be_cmd_resp_hdr hdr;
1439 struct mgmt_controller_attrib attribs;
1440};
1441
1442/*********************** Set driver function ***********************/
1443#define CAPABILITY_SW_TIMESTAMPS 2
1444#define CAPABILITY_BE3_NATIVE_ERX_API 4
1445
1446struct be_cmd_req_set_func_cap {
1447 struct be_cmd_req_hdr hdr;
1448 u32 valid_cap_flags;
1449 u32 cap_flags;
1450 u8 rsvd[212];
1451};
1452
1453struct be_cmd_resp_set_func_cap {
1454 struct be_cmd_resp_hdr hdr;
1455 u32 valid_cap_flags;
1456 u32 cap_flags;
1457 u8 rsvd[212];
1458};
1459
1460/*********************** Function Privileges ***********************/
1461enum {
1462 BE_PRIV_DEFAULT = 0x1,
1463 BE_PRIV_LNKQUERY = 0x2,
1464 BE_PRIV_LNKSTATS = 0x4,
1465 BE_PRIV_LNKMGMT = 0x8,
1466 BE_PRIV_LNKDIAG = 0x10,
1467 BE_PRIV_UTILQUERY = 0x20,
1468 BE_PRIV_FILTMGMT = 0x40,
1469 BE_PRIV_IFACEMGMT = 0x80,
1470 BE_PRIV_VHADM = 0x100,
1471 BE_PRIV_DEVCFG = 0x200,
1472 BE_PRIV_DEVSEC = 0x400
1473};
1474#define MAX_PRIVILEGES (BE_PRIV_VHADM | BE_PRIV_DEVCFG | \
1475 BE_PRIV_DEVSEC)
1476#define MIN_PRIVILEGES BE_PRIV_DEFAULT
1477
1478struct be_cmd_priv_map {
1479 u8 opcode;
1480 u8 subsystem;
1481 u32 priv_mask;
1482};
1483
1484struct be_cmd_req_get_fn_privileges {
1485 struct be_cmd_req_hdr hdr;
1486 u32 rsvd;
1487};
1488
1489struct be_cmd_resp_get_fn_privileges {
1490 struct be_cmd_resp_hdr hdr;
1491 u32 privilege_mask;
1492};
1493
1494struct be_cmd_req_set_fn_privileges {
1495 struct be_cmd_req_hdr hdr;
1496 u32 privileges; /* Used by BE3, SH-R */
1497 u32 privileges_lancer; /* Used by Lancer */
1498};
1499
1500/******************** GET/SET_MACLIST **************************/
1501#define BE_MAX_MAC 64
1502struct be_cmd_req_get_mac_list {
1503 struct be_cmd_req_hdr hdr;
1504 u8 mac_type;
1505 u8 perm_override;
1506 u16 iface_id;
1507 u32 mac_id;
1508 u32 rsvd[3];
1509} __packed;
1510
1511struct get_list_macaddr {
1512 u16 mac_addr_size;
1513 union {
1514 u8 macaddr[6];
1515 struct {
1516 u8 rsvd[2];
1517 u32 mac_id;
1518 } __packed s_mac_id;
1519 } __packed mac_addr_id;
1520} __packed;
1521
1522struct be_cmd_resp_get_mac_list {
1523 struct be_cmd_resp_hdr hdr;
1524 struct get_list_macaddr fd_macaddr; /* Factory default mac */
1525 struct get_list_macaddr macid_macaddr; /* soft mac */
1526 u8 true_mac_count;
1527 u8 pseudo_mac_count;
1528 u8 mac_list_size;
1529 u8 rsvd;
1530 /* perm override mac */
1531 struct get_list_macaddr macaddr_list[BE_MAX_MAC];
1532} __packed;
1533
1534struct be_cmd_req_set_mac_list {
1535 struct be_cmd_req_hdr hdr;
1536 u8 mac_count;
1537 u8 rsvd1;
1538 u16 rsvd2;
1539 struct macaddr mac[BE_MAX_MAC];
1540} __packed;
1541
1542/*********************** HSW Config ***********************/
1543#define PORT_FWD_TYPE_VEPA 0x3
1544#define PORT_FWD_TYPE_VEB 0x2
1545
1546struct amap_set_hsw_context {
1547 u8 interface_id[16];
1548 u8 rsvd0[14];
1549 u8 pvid_valid;
1550 u8 pport;
1551 u8 rsvd1[6];
1552 u8 port_fwd_type[3];
1553 u8 rsvd2[7];
1554 u8 pvid[16];
1555 u8 rsvd3[32];
1556 u8 rsvd4[32];
1557 u8 rsvd5[32];
1558} __packed;
1559
1560struct be_cmd_req_set_hsw_config {
1561 struct be_cmd_req_hdr hdr;
1562 u8 context[sizeof(struct amap_set_hsw_context) / 8];
1563} __packed;
1564
1565struct be_cmd_resp_set_hsw_config {
1566 struct be_cmd_resp_hdr hdr;
1567 u32 rsvd;
1568};
1569
1570struct amap_get_hsw_req_context {
1571 u8 interface_id[16];
1572 u8 rsvd0[14];
1573 u8 pvid_valid;
1574 u8 pport;
1575} __packed;
1576
1577struct amap_get_hsw_resp_context {
1578 u8 rsvd0[6];
1579 u8 port_fwd_type[3];
1580 u8 rsvd1[7];
1581 u8 pvid[16];
1582 u8 rsvd2[32];
1583 u8 rsvd3[32];
1584 u8 rsvd4[32];
1585} __packed;
1586
1587struct be_cmd_req_get_hsw_config {
1588 struct be_cmd_req_hdr hdr;
1589 u8 context[sizeof(struct amap_get_hsw_req_context) / 8];
1590} __packed;
1591
1592struct be_cmd_resp_get_hsw_config {
1593 struct be_cmd_resp_hdr hdr;
1594 u8 context[sizeof(struct amap_get_hsw_resp_context) / 8];
1595 u32 rsvd;
1596};
1597
1598/******************* get port names ***************/
1599struct be_cmd_req_get_port_name {
1600 struct be_cmd_req_hdr hdr;
1601 u32 rsvd0;
1602};
1603
1604struct be_cmd_resp_get_port_name {
1605 struct be_cmd_req_hdr hdr;
1606 u8 port_name[4];
1607};
1608
1609/*************** HW Stats Get v1 **********************************/
1610#define BE_TXP_SW_SZ 48
1611struct be_port_rxf_stats_v1 {
1612 u32 rsvd0[12];
1613 u32 rx_crc_errors;
1614 u32 rx_alignment_symbol_errors;
1615 u32 rx_pause_frames;
1616 u32 rx_priority_pause_frames;
1617 u32 rx_control_frames;
1618 u32 rx_in_range_errors;
1619 u32 rx_out_range_errors;
1620 u32 rx_frame_too_long;
1621 u32 rx_address_filtered;
1622 u32 rx_dropped_too_small;
1623 u32 rx_dropped_too_short;
1624 u32 rx_dropped_header_too_small;
1625 u32 rx_dropped_tcp_length;
1626 u32 rx_dropped_runt;
1627 u32 rsvd1[10];
1628 u32 rx_ip_checksum_errs;
1629 u32 rx_tcp_checksum_errs;
1630 u32 rx_udp_checksum_errs;
1631 u32 rsvd2[7];
1632 u32 rx_switched_unicast_packets;
1633 u32 rx_switched_multicast_packets;
1634 u32 rx_switched_broadcast_packets;
1635 u32 rsvd3[3];
1636 u32 tx_pauseframes;
1637 u32 tx_priority_pauseframes;
1638 u32 tx_controlframes;
1639 u32 rsvd4[10];
1640 u32 rxpp_fifo_overflow_drop;
1641 u32 rx_input_fifo_overflow_drop;
1642 u32 pmem_fifo_overflow_drop;
1643 u32 jabber_events;
1644 u32 rsvd5[3];
1645};
1646
1647
1648struct be_rxf_stats_v1 {
1649 struct be_port_rxf_stats_v1 port[4];
1650 u32 rsvd0[2];
1651 u32 rx_drops_no_pbuf;
1652 u32 rx_drops_no_txpb;
1653 u32 rx_drops_no_erx_descr;
1654 u32 rx_drops_no_tpre_descr;
1655 u32 rsvd1[6];
1656 u32 rx_drops_too_many_frags;
1657 u32 rx_drops_invalid_ring;
1658 u32 forwarded_packets;
1659 u32 rx_drops_mtu;
1660 u32 rsvd2[14];
1661};
1662
1663struct be_erx_stats_v1 {
1664 u32 rx_drops_no_fragments[68]; /* dwordS 0 to 67*/
1665 u32 rsvd[4];
1666};
1667
1668struct be_port_rxf_stats_v2 {
1669 u32 rsvd0[10];
1670 u32 roce_bytes_received_lsd;
1671 u32 roce_bytes_received_msd;
1672 u32 rsvd1[5];
1673 u32 roce_frames_received;
1674 u32 rx_crc_errors;
1675 u32 rx_alignment_symbol_errors;
1676 u32 rx_pause_frames;
1677 u32 rx_priority_pause_frames;
1678 u32 rx_control_frames;
1679 u32 rx_in_range_errors;
1680 u32 rx_out_range_errors;
1681 u32 rx_frame_too_long;
1682 u32 rx_address_filtered;
1683 u32 rx_dropped_too_small;
1684 u32 rx_dropped_too_short;
1685 u32 rx_dropped_header_too_small;
1686 u32 rx_dropped_tcp_length;
1687 u32 rx_dropped_runt;
1688 u32 rsvd2[10];
1689 u32 rx_ip_checksum_errs;
1690 u32 rx_tcp_checksum_errs;
1691 u32 rx_udp_checksum_errs;
1692 u32 rsvd3[7];
1693 u32 rx_switched_unicast_packets;
1694 u32 rx_switched_multicast_packets;
1695 u32 rx_switched_broadcast_packets;
1696 u32 rsvd4[3];
1697 u32 tx_pauseframes;
1698 u32 tx_priority_pauseframes;
1699 u32 tx_controlframes;
1700 u32 rsvd5[10];
1701 u32 rxpp_fifo_overflow_drop;
1702 u32 rx_input_fifo_overflow_drop;
1703 u32 pmem_fifo_overflow_drop;
1704 u32 jabber_events;
1705 u32 rsvd6[3];
1706 u32 rx_drops_payload_size;
1707 u32 rx_drops_clipped_header;
1708 u32 rx_drops_crc;
1709 u32 roce_drops_payload_len;
1710 u32 roce_drops_crc;
1711 u32 rsvd7[19];
1712};
1713
1714struct be_rxf_stats_v2 {
1715 struct be_port_rxf_stats_v2 port[4];
1716 u32 rsvd0[2];
1717 u32 rx_drops_no_pbuf;
1718 u32 rx_drops_no_txpb;
1719 u32 rx_drops_no_erx_descr;
1720 u32 rx_drops_no_tpre_descr;
1721 u32 rsvd1[6];
1722 u32 rx_drops_too_many_frags;
1723 u32 rx_drops_invalid_ring;
1724 u32 forwarded_packets;
1725 u32 rx_drops_mtu;
1726 u32 rsvd2[35];
1727};
1728
1729struct be_hw_stats_v1 {
1730 struct be_rxf_stats_v1 rxf;
1731 u32 rsvd0[BE_TXP_SW_SZ];
1732 struct be_erx_stats_v1 erx;
1733 struct be_pmem_stats pmem;
1734 u32 rsvd1[18];
1735};
1736
1737struct be_cmd_req_get_stats_v1 {
1738 struct be_cmd_req_hdr hdr;
1739 u8 rsvd[sizeof(struct be_hw_stats_v1)];
1740};
1741
1742struct be_cmd_resp_get_stats_v1 {
1743 struct be_cmd_resp_hdr hdr;
1744 struct be_hw_stats_v1 hw_stats;
1745};
1746
1747struct be_erx_stats_v2 {
1748 u32 rx_drops_no_fragments[136]; /* dwordS 0 to 135*/
1749 u32 rsvd[3];
1750};
1751
1752struct be_hw_stats_v2 {
1753 struct be_rxf_stats_v2 rxf;
1754 u32 rsvd0[BE_TXP_SW_SZ];
1755 struct be_erx_stats_v2 erx;
1756 struct be_pmem_stats pmem;
1757 u32 rsvd1[18];
1758};
1759
1760struct be_cmd_req_get_stats_v2 {
1761 struct be_cmd_req_hdr hdr;
1762 u8 rsvd[sizeof(struct be_hw_stats_v2)];
1763};
1764
1765struct be_cmd_resp_get_stats_v2 {
1766 struct be_cmd_resp_hdr hdr;
1767 struct be_hw_stats_v2 hw_stats;
1768};
1769
1770/************** get fat capabilites *******************/
1771#define MAX_MODULES 27
1772#define MAX_MODES 4
1773#define MODE_UART 0
1774#define FW_LOG_LEVEL_DEFAULT 48
1775#define FW_LOG_LEVEL_FATAL 64
1776
1777struct ext_fat_mode {
1778 u8 mode;
1779 u8 rsvd0;
1780 u16 port_mask;
1781 u32 dbg_lvl;
1782 u64 fun_mask;
1783} __packed;
1784
1785struct ext_fat_modules {
1786 u8 modules_str[32];
1787 u32 modules_id;
1788 u32 num_modes;
1789 struct ext_fat_mode trace_lvl[MAX_MODES];
1790} __packed;
1791
1792struct be_fat_conf_params {
1793 u32 max_log_entries;
1794 u32 log_entry_size;
1795 u8 log_type;
1796 u8 max_log_funs;
1797 u8 max_log_ports;
1798 u8 rsvd0;
1799 u32 supp_modes;
1800 u32 num_modules;
1801 struct ext_fat_modules module[MAX_MODULES];
1802} __packed;
1803
1804struct be_cmd_req_get_ext_fat_caps {
1805 struct be_cmd_req_hdr hdr;
1806 u32 parameter_type;
1807};
1808
1809struct be_cmd_resp_get_ext_fat_caps {
1810 struct be_cmd_resp_hdr hdr;
1811 struct be_fat_conf_params get_params;
1812};
1813
1814struct be_cmd_req_set_ext_fat_caps {
1815 struct be_cmd_req_hdr hdr;
1816 struct be_fat_conf_params set_params;
1817};
1818
1819#define RESOURCE_DESC_SIZE_V0 72
1820#define RESOURCE_DESC_SIZE_V1 88
1821#define PCIE_RESOURCE_DESC_TYPE_V0 0x40
1822#define NIC_RESOURCE_DESC_TYPE_V0 0x41
1823#define PCIE_RESOURCE_DESC_TYPE_V1 0x50
1824#define NIC_RESOURCE_DESC_TYPE_V1 0x51
1825#define PORT_RESOURCE_DESC_TYPE_V1 0x55
1826#define MAX_RESOURCE_DESC 264
1827
1828#define IMM_SHIFT 6 /* Immediate */
1829#define NOSV_SHIFT 7 /* No save */
1830
1831struct be_res_desc_hdr {
1832 u8 desc_type;
1833 u8 desc_len;
1834} __packed;
1835
1836struct be_port_res_desc {
1837 struct be_res_desc_hdr hdr;
1838 u8 rsvd0;
1839 u8 flags;
1840 u8 link_num;
1841 u8 mc_type;
1842 u16 rsvd1;
1843
1844#define NV_TYPE_MASK 0x3 /* bits 0-1 */
1845#define NV_TYPE_DISABLED 1
1846#define NV_TYPE_VXLAN 3
1847#define SOCVID_SHIFT 2 /* Strip outer vlan */
1848#define RCVID_SHIFT 4 /* Report vlan */
1849 u8 nv_flags;
1850 u8 rsvd2;
1851 __le16 nv_port; /* vxlan/gre port */
1852 u32 rsvd3[19];
1853} __packed;
1854
1855struct be_pcie_res_desc {
1856 struct be_res_desc_hdr hdr;
1857 u8 rsvd0;
1858 u8 flags;
1859 u16 rsvd1;
1860 u8 pf_num;
1861 u8 rsvd2;
1862 u32 rsvd3;
1863 u8 sriov_state;
1864 u8 pf_state;
1865 u8 pf_type;
1866 u8 rsvd4;
1867 u16 num_vfs;
1868 u16 rsvd5;
1869 u32 rsvd6[17];
1870} __packed;
1871
1872struct be_nic_res_desc {
1873 struct be_res_desc_hdr hdr;
1874 u8 rsvd1;
1875
1876#define QUN_SHIFT 4 /* QoS is in absolute units */
1877 u8 flags;
1878 u8 vf_num;
1879 u8 rsvd2;
1880 u8 pf_num;
1881 u8 rsvd3;
1882 u16 unicast_mac_count;
1883 u8 rsvd4[6];
1884 u16 mcc_count;
1885 u16 vlan_count;
1886 u16 mcast_mac_count;
1887 u16 txq_count;
1888 u16 rq_count;
1889 u16 rssq_count;
1890 u16 lro_count;
1891 u16 cq_count;
1892 u16 toe_conn_count;
1893 u16 eq_count;
1894 u32 rsvd5;
1895 u32 cap_flags;
1896 u8 link_param;
1897 u8 rsvd6[3];
1898 u32 bw_min;
1899 u32 bw_max;
1900 u8 acpi_params;
1901 u8 wol_param;
1902 u16 rsvd7;
1903 u32 rsvd8[7];
1904} __packed;
1905
1906/************ Multi-Channel type ***********/
1907enum mc_type {
1908 MC_NONE = 0x01,
1909 UMC = 0x02,
1910 FLEX10 = 0x03,
1911 vNIC1 = 0x04,
1912 nPAR = 0x05,
1913 UFP = 0x06,
1914 vNIC2 = 0x07
1915};
1916
1917/* Is BE in a multi-channel mode */
1918static inline bool be_is_mc(struct be_adapter *adapter)
1919{
1920 return adapter->mc_type > MC_NONE;
1921}
1922
1923struct be_cmd_req_get_func_config {
1924 struct be_cmd_req_hdr hdr;
1925};
1926
1927struct be_cmd_resp_get_func_config {
1928 struct be_cmd_resp_hdr hdr;
1929 u32 desc_count;
1930 u8 func_param[MAX_RESOURCE_DESC * RESOURCE_DESC_SIZE_V1];
1931};
1932
1933#define ACTIVE_PROFILE_TYPE 0x2
1934struct be_cmd_req_get_profile_config {
1935 struct be_cmd_req_hdr hdr;
1936 u8 rsvd;
1937 u8 type;
1938 u16 rsvd1;
1939};
1940
1941struct be_cmd_resp_get_profile_config {
1942 struct be_cmd_resp_hdr hdr;
1943 u32 desc_count;
1944 u8 func_param[MAX_RESOURCE_DESC * RESOURCE_DESC_SIZE_V1];
1945};
1946
1947struct be_cmd_req_set_profile_config {
1948 struct be_cmd_req_hdr hdr;
1949 u32 rsvd;
1950 u32 desc_count;
1951 u8 desc[RESOURCE_DESC_SIZE_V1];
1952};
1953
1954struct be_cmd_resp_set_profile_config {
1955 struct be_cmd_resp_hdr hdr;
1956};
1957
1958struct be_cmd_req_get_active_profile {
1959 struct be_cmd_req_hdr hdr;
1960 u32 rsvd;
1961} __packed;
1962
1963struct be_cmd_resp_get_active_profile {
1964 struct be_cmd_resp_hdr hdr;
1965 u16 active_profile_id;
1966 u16 next_profile_id;
1967} __packed;
1968
1969struct be_cmd_enable_disable_vf {
1970 struct be_cmd_req_hdr hdr;
1971 u8 enable;
1972 u8 rsvd[3];
1973};
1974
1975struct be_cmd_req_intr_set {
1976 struct be_cmd_req_hdr hdr;
1977 u8 intr_enabled;
1978 u8 rsvd[3];
1979};
1980
1981static inline bool check_privilege(struct be_adapter *adapter, u32 flags)
1982{
1983 return flags & adapter->cmd_privileges ? true : false;
1984}
1985
1986/************** Get IFACE LIST *******************/
1987struct be_if_desc {
1988 u32 if_id;
1989 u32 cap_flags;
1990 u32 en_flags;
1991};
1992
1993struct be_cmd_req_get_iface_list {
1994 struct be_cmd_req_hdr hdr;
1995};
1996
1997struct be_cmd_resp_get_iface_list {
1998 struct be_cmd_req_hdr hdr;
1999 u32 if_cnt;
2000 struct be_if_desc if_desc;
2001};
2002
2003/*************** Set logical link ********************/
2004#define PLINK_TRACK_SHIFT 8
2005struct be_cmd_req_set_ll_link {
2006 struct be_cmd_req_hdr hdr;
2007 u32 link_config; /* Bit 0: UP_DOWN, Bit 9: PLINK */
2008};
2009
2010/************** Manage IFACE Filters *******************/
2011#define OP_CONVERT_NORMAL_TO_TUNNEL 0
2012#define OP_CONVERT_TUNNEL_TO_NORMAL 1
2013
2014struct be_cmd_req_manage_iface_filters {
2015 struct be_cmd_req_hdr hdr;
2016 u8 op;
2017 u8 rsvd0;
2018 u8 flags;
2019 u8 rsvd1;
2020 u32 tunnel_iface_id;
2021 u32 target_iface_id;
2022 u8 mac[6];
2023 u16 vlan_tag;
2024 u32 tenant_id;
2025 u32 filter_id;
2026 u32 cap_flags;
2027 u32 cap_control_flags;
2028} __packed;
2029
2030int be_pci_fnum_get(struct be_adapter *adapter);
2031int be_fw_wait_ready(struct be_adapter *adapter);
2032int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
2033 bool permanent, u32 if_handle, u32 pmac_id);
2034int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr, u32 if_id,
2035 u32 *pmac_id, u32 domain);
2036int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id,
2037 u32 domain);
2038int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
2039 u32 *if_handle, u32 domain);
2040int be_cmd_if_destroy(struct be_adapter *adapter, int if_handle, u32 domain);
2041int be_cmd_eq_create(struct be_adapter *adapter, struct be_eq_obj *eqo);
2042int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
2043 struct be_queue_info *eq, bool no_delay,
2044 int num_cqe_dma_coalesce);
2045int be_cmd_mccq_create(struct be_adapter *adapter, struct be_queue_info *mccq,
2046 struct be_queue_info *cq);
2047int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo);
2048int be_cmd_rxq_create(struct be_adapter *adapter, struct be_queue_info *rxq,
2049 u16 cq_id, u16 frag_size, u32 if_id, u32 rss, u8 *rss_id);
2050int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
2051 int type);
2052int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q);
2053int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed,
2054 u8 *link_status, u32 dom);
2055int be_cmd_reset(struct be_adapter *adapter);
2056int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd);
2057int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
2058 struct be_dma_mem *nonemb_cmd);
2059int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver,
2060 char *fw_on_flash);
2061int be_cmd_modify_eqd(struct be_adapter *adapter, struct be_set_eqd *, int num);
2062int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
2063 u32 num, bool promiscuous);
2064int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 status);
2065int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc);
2066int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc);
2067int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num,
2068 u32 *function_mode, u32 *function_caps, u16 *asic_rev);
2069int be_cmd_reset_function(struct be_adapter *adapter);
2070int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
2071 u32 rss_hash_opts, u16 table_size);
2072int be_process_mcc(struct be_adapter *adapter);
2073int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num, u8 beacon,
2074 u8 status, u8 state);
2075int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num,
2076 u32 *state);
2077int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
2078 u32 flash_oper, u32 flash_opcode, u32 buf_size);
2079int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2080 u32 data_size, u32 data_offset,
2081 const char *obj_name, u32 *data_written,
2082 u8 *change_status, u8 *addn_status);
2083int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2084 u32 data_size, u32 data_offset, const char *obj_name,
2085 u32 *data_read, u32 *eof, u8 *addn_status);
2086int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
2087 int offset);
2088int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
2089 struct be_dma_mem *nonemb_cmd);
2090int be_cmd_fw_init(struct be_adapter *adapter);
2091int be_cmd_fw_clean(struct be_adapter *adapter);
2092void be_async_mcc_enable(struct be_adapter *adapter);
2093void be_async_mcc_disable(struct be_adapter *adapter);
2094int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
2095 u32 loopback_type, u32 pkt_size, u32 num_pkts,
2096 u64 pattern);
2097int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern, u32 byte_cnt,
2098 struct be_dma_mem *cmd);
2099int be_cmd_get_seeprom_data(struct be_adapter *adapter,
2100 struct be_dma_mem *nonemb_cmd);
2101int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
2102 u8 loopback_type, u8 enable);
2103int be_cmd_get_phy_info(struct be_adapter *adapter);
2104int be_cmd_config_qos(struct be_adapter *adapter, u32 bps, u8 domain);
2105void be_detect_error(struct be_adapter *adapter);
2106int be_cmd_get_die_temperature(struct be_adapter *adapter);
2107int be_cmd_get_cntl_attributes(struct be_adapter *adapter);
2108int be_cmd_req_native_mode(struct be_adapter *adapter);
2109int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size);
2110void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf);
2111int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege,
2112 u32 domain);
2113int be_cmd_set_fn_privileges(struct be_adapter *adapter, u32 privileges,
2114 u32 vf_num);
2115int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
2116 bool *pmac_id_active, u32 *pmac_id,
2117 u32 if_handle, u8 domain);
2118int be_cmd_get_active_mac(struct be_adapter *adapter, u32 pmac_id, u8 *mac,
2119 u32 if_handle, bool active, u32 domain);
2120int be_cmd_get_perm_mac(struct be_adapter *adapter, u8 *mac);
2121int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array, u8 mac_count,
2122 u32 domain);
2123int be_cmd_set_mac(struct be_adapter *adapter, u8 *mac, int if_id, u32 dom);
2124int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid, u32 domain,
2125 u16 intf_id, u16 hsw_mode);
2126int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid, u32 domain,
2127 u16 intf_id, u8 *mode);
2128int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter);
2129int be_cmd_set_fw_log_level(struct be_adapter *adapter, u32 level);
2130int be_cmd_get_fw_log_level(struct be_adapter *adapter);
2131int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
2132 struct be_dma_mem *cmd);
2133int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
2134 struct be_dma_mem *cmd,
2135 struct be_fat_conf_params *cfgs);
2136int lancer_physdev_ctrl(struct be_adapter *adapter, u32 mask);
2137int lancer_initiate_dump(struct be_adapter *adapter);
2138bool dump_present(struct be_adapter *adapter);
2139int lancer_test_and_set_rdy_state(struct be_adapter *adapter);
2140int be_cmd_query_port_name(struct be_adapter *adapter, u8 *port_name);
2141int be_cmd_get_func_config(struct be_adapter *adapter,
2142 struct be_resources *res);
2143int be_cmd_get_profile_config(struct be_adapter *adapter,
2144 struct be_resources *res, u8 domain);
2145int be_cmd_set_profile_config(struct be_adapter *adapter, void *desc,
2146 int size, u8 version, u8 domain);
2147int be_cmd_get_active_profile(struct be_adapter *adapter, u16 *profile);
2148int be_cmd_get_if_id(struct be_adapter *adapter, struct be_vf_cfg *vf_cfg,
2149 int vf_num);
2150int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain);
2151int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable);
2152int be_cmd_set_logical_link_config(struct be_adapter *adapter,
2153 int link_state, u8 domain);
2154int be_cmd_set_vxlan_port(struct be_adapter *adapter, __be16 port);
2155int be_cmd_manage_iface(struct be_adapter *adapter, u32 iface, u8 op);